diff --git a/.gitignore b/.gitignore index e76aab9..ad9a130 100644 --- a/.gitignore +++ b/.gitignore @@ -2,6 +2,10 @@ FPGA/db/* FPGA/output_files/* FPGA/greybox_tmp/* FPGA/incremental_db/* +FPGA_61.440/db/* +FPGA_61.440/output_files/* +FPGA_61.440/greybox_tmp/* +FPGA_61.440/incremental_db/* STM32/MDK-ARM/WOLF-Lite/*.htm STM32/MDK-ARM/WOLF-Lite/*.hex STM32/Debug/* diff --git a/FPGA_61.440/DEBUG.sopcinfo b/FPGA_61.440/DEBUG.sopcinfo index 1942e23..1eb23ab 100644 --- a/FPGA_61.440/DEBUG.sopcinfo +++ b/FPGA_61.440/DEBUG.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1617214592 + 1644138403 false true false diff --git a/FPGA_61.440/DEBUG2.sopcinfo b/FPGA_61.440/DEBUG2.sopcinfo index 518ae3b..5aee1a5 100644 --- a/FPGA_61.440/DEBUG2.sopcinfo +++ b/FPGA_61.440/DEBUG2.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1617214606 + 1644138415 false true false diff --git a/FPGA_61.440/WOLF-LITE.bdf b/FPGA_61.440/WOLF-LITE.bdf index addbaeb..dbabfe1 100644 --- a/FPGA_61.440/WOLF-LITE.bdf +++ b/FPGA_61.440/WOLF-LITE.bdf @@ -512,6 +512,22 @@ refer to the applicable agreement for further details. ) (annotation_block (location)(rect 3688 48 3744 72)) ) +(pin + (output) + (rect 3416 1168 3592 1184) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "VCXO_PWM" (rect 90 0 151 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) (pin (bidir) (rect 3456 168 3632 184) @@ -1620,314 +1636,6 @@ refer to the applicable agreement for further details. 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0 30 12)(font "Arial" )) + (text "ATT_2" (rect 242 347 267 359)(font "Arial" )) + (line (pt 288 352)(pt 272 352)) + ) + (port + (pt 288 368) + (output) + (text "ATT_4" (rect 0 0 30 12)(font "Arial" )) + (text "ATT_4" (rect 242 363 267 375)(font "Arial" )) + (line (pt 288 368)(pt 272 368)) + ) + (port + (pt 288 384) + (output) + (text "ATT_8" (rect 0 0 30 12)(font "Arial" )) + (text "ATT_8" (rect 242 379 267 391)(font "Arial" )) + (line (pt 288 384)(pt 272 384)) + ) + (port + (pt 288 400) + (output) + (text "ATT_16" (rect 0 0 36 12)(font "Arial" )) + (text "ATT_16" (rect 237 395 267 407)(font "Arial" )) + (line (pt 288 400)(pt 272 400)) + ) + (port + (pt 288 416) + (output) + (text "BPF_A" (rect 0 0 35 12)(font "Arial" )) + (text "BPF_A" (rect 238 411 267 423)(font "Arial" )) + (line (pt 288 416)(pt 272 416)) + ) + (port + (pt 288 432) + (output) + (text "BPF_B" (rect 0 0 34 12)(font "Arial" )) + (text "BPF_B" (rect 239 427 267 439)(font "Arial" )) + (line (pt 288 432)(pt 272 432)) + ) + (port + (pt 288 448) + (output) + (text "BPF_OE1" (rect 0 0 48 12)(font "Arial" )) + (text "BPF_OE1" (rect 227 443 267 455)(font "Arial" )) + (line (pt 288 448)(pt 272 448)) + ) + (port + (pt 288 464) + (output) + (text "BPF_OE2" (rect 0 0 48 12)(font "Arial" )) + (text "BPF_OE2" (rect 227 459 267 471)(font "Arial" )) + (line (pt 288 464)(pt 272 464)) + ) + (port + (pt 288 480) + (output) + (text "LPF_1" (rect 0 0 31 12)(font "Arial" )) + (text "LPF_1" (rect 241 475 267 487)(font "Arial" )) + (line (pt 288 480)(pt 272 480)) + ) + (port + (pt 288 496) + (output) + (text "LPF_2" (rect 0 0 31 12)(font "Arial" )) + (text "LPF_2" (rect 241 491 267 503)(font "Arial" )) + (line (pt 288 496)(pt 272 496)) + ) + (port + (pt 288 512) + (output) + (text "LPF_3" (rect 0 0 31 12)(font "Arial" )) + (text "LPF_3" (rect 241 507 267 519)(font "Arial" )) + (line (pt 288 512)(pt 272 512)) + ) + (port + (pt 288 528) + (output) + (text "VCXO_correction[15..0]" (rect 0 0 115 12)(font "Arial" )) + (text "VCXO_correction[15..0]" (rect 170 523 267 535)(font "Arial" )) + (line (pt 288 528)(pt 272 528)(line_width 3)) + ) + (port + (pt 288 32) + (bidir) + (text "DATA_BUS[7..0]" (rect 0 0 82 12)(font "Arial" )) + (text "DATA_BUS[7..0]" (rect 193 27 275 39)(font "Arial" )) + (line (pt 288 32)(pt 272 32)(line_width 3)) + ) + (parameter + "rx_buffer_length" + "7" + "" + (type "PARAMETER_SIGNED_DEC") ) + (drawing + (rectangle (rect 16 16 272 544)) + ) + (annotation_block (parameter)(rect 3088 96 3296 136)) +) +(symbol + (rect 3080 1144 3304 1224) + (text "vcxo_controller" (rect 5 0 80 12)(font "Arial" )) + (text "VCXO_PWM_CONTROLLER" (rect 8 64 144 81)(font "Intel Clear" )) + (port + (pt 0 32) + (input) + (text "pwm_clk_in" (rect 0 0 56 12)(font "Arial" )) + (text "pwm_clk_in" (rect 21 27 77 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "VCXO_correction[15..0]" (rect 0 0 115 12)(font "Arial" )) + (text "VCXO_correction[15..0]" (rect 21 43 136 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 224 32) + (output) + (text "pump" (rect 0 0 27 12)(font "Arial" )) + (text "pump" (rect 181 27 208 39)(font "Arial" )) + (line (pt 224 32)(pt 208 32)) + ) + (drawing + (rectangle (rect 16 16 208 64)) + ) +) (connector (pt 528 32) (pt 440 32) @@ -4117,10 +4169,6 @@ refer to the applicable agreement for further details. (pt 3048 784) (pt 3048 904) ) -(connector - (pt 3048 904) - (pt 3048 1008) -) (connector (pt 440 -104) (pt 520 -104) @@ -4263,6 +4311,34 @@ refer to the applicable agreement for further details. (pt 1216 192) (bus) ) +(connector + (pt 3080 1176) + (pt 3048 1176) +) +(connector + (pt 3048 904) + (pt 3048 1008) +) +(connector + (pt 3048 1008) + (pt 3048 1176) +) +(connector + (text "VCXO_correction[15..0]" (rect 2954 1176 3064 1193)(font "Intel Clear" )) + (pt 3080 1192) + (pt 2944 1192) + (bus) +) +(connector + (pt 3304 1176) + (pt 3416 1176) +) +(connector + (text "VCXO_correction[15..0]" (rect 3498 672 3608 689)(font "Intel Clear" )) + (pt 3376 672) + (pt 3536 672) + (bus) +) (junction (pt 376 120)) (junction (pt 440 32)) (junction (pt 440 448)) @@ -4289,4 +4365,5 @@ refer to the applicable agreement for further details. (junction (pt 3472 104)) (junction (pt 3048 904)) (junction (pt 440 -32)) +(junction (pt 3048 1008)) (text "153.6mhz" (rect 3328 760 3388 779)(font "Intel Clear" (font_size 8))) diff --git a/FPGA_61.440/WOLF-LITE.qsf b/FPGA_61.440/WOLF-LITE.qsf index db37c19..0cdccb9 100644 --- a/FPGA_61.440/WOLF-LITE.qsf +++ b/FPGA_61.440/WOLF-LITE.qsf @@ -321,4 +321,6 @@ set_global_assignment -name SIP_FILE tx_ciccomp.sip set_global_assignment -name QIP_FILE diffclock_buff.qip set_global_assignment -name QIP_FILE dcdc_pll.qip set_global_assignment -name QIP_FILE tx_pll.qip +set_location_assignment PIN_143 -to VCXO_PWM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VCXO_PWM set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_61.440/WOLF-LITE.qws b/FPGA_61.440/WOLF-LITE.qws index 0eb7078..9bab9f5 100644 Binary files a/FPGA_61.440/WOLF-LITE.qws and b/FPGA_61.440/WOLF-LITE.qws differ diff --git a/FPGA_61.440/clock_buffer.sopcinfo b/FPGA_61.440/clock_buffer.sopcinfo index c350629..6909a29 100644 --- a/FPGA_61.440/clock_buffer.sopcinfo +++ b/FPGA_61.440/clock_buffer.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1617214510 + 1644138337 false true false diff --git a/FPGA_61.440/db/.cmp.kpt b/FPGA_61.440/db/.cmp.kpt deleted file mode 100644 index c0b1cc4..0000000 Binary files a/FPGA_61.440/db/.cmp.kpt and /dev/null differ diff --git a/FPGA_61.440/db/MAIN_PLL_altpll.v b/FPGA_61.440/db/MAIN_PLL_altpll.v deleted file mode 100644 index a9994b0..0000000 --- a/FPGA_61.440/db/MAIN_PLL_altpll.v +++ /dev/null @@ -1,96 +0,0 @@ -//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=5 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" clk1_divide_by=1280 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=16276 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=MAIN_PLL" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 -//VERSION_BEGIN 18.1 cbx_altclkbuf 2018:09:12:13:04:24:SJ cbx_altiobuf_bidir 2018:09:12:13:04:24:SJ cbx_altiobuf_in 2018:09:12:13:04:24:SJ cbx_altiobuf_out 2018:09:12:13:04:24:SJ cbx_altpll 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END -//CBXI_INSTANCE_NAME="WOLF_LITE_MAIN_PLL_MAIN_PLL_altpll_altpll_component" -// synthesis VERILOG_INPUT_VERSION VERILOG_2001 -// altera message_off 10463 - - - -// Copyright (C) 2018 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License -// Subscription Agreement, the Intel Quartus Prime License Agreement, -// the Intel FPGA IP License Agreement, or other applicable license -// agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by -// Intel and sold by Intel or its authorized distributors. Please -// refer to the applicable agreement for further details. - - - -//synthesis_resources = cycloneive_pll 1 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module MAIN_PLL_altpll - ( - clk, - inclk) /* synthesis synthesis_clearbox=1 */; - output [4:0] clk; - input [1:0] inclk; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri0 [1:0] inclk; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [4:0] wire_pll1_clk; - wire wire_pll1_fbout; - - cycloneive_pll pll1 - ( - .activeclock(), - .clk(wire_pll1_clk), - .clkbad(), - .fbin(wire_pll1_fbout), - .fbout(wire_pll1_fbout), - .inclk(inclk), - .locked(), - .phasedone(), - .scandataout(), - .scandone(), - .vcooverrange(), - .vcounderrange() - `ifndef FORMAL_VERIFICATION - // synopsys translate_off - `endif - , - .areset(1'b0), - .clkswitch(1'b0), - .configupdate(1'b0), - .pfdena(1'b1), - .phasecounterselect({3{1'b0}}), - .phasestep(1'b0), - .phaseupdown(1'b0), - .scanclk(1'b0), - .scanclkena(1'b1), - .scandata(1'b0) - `ifndef FORMAL_VERIFICATION - // synopsys translate_on - `endif - ); - defparam - pll1.bandwidth_type = "auto", - pll1.clk0_divide_by = 5, - pll1.clk0_duty_cycle = 50, - pll1.clk0_multiply_by = 1, - pll1.clk0_phase_shift = "0", - pll1.clk1_divide_by = 1280, - pll1.clk1_duty_cycle = 50, - pll1.clk1_multiply_by = 1, - pll1.clk1_phase_shift = "0", - pll1.compensate_clock = "clk0", - pll1.inclk0_input_frequency = 16276, - pll1.operation_mode = "normal", - pll1.pll_type = "auto", - pll1.lpm_type = "cycloneive_pll"; - assign - clk = {wire_pll1_clk[4:0]}; -endmodule //MAIN_PLL_altpll -//VALID FILE diff --git a/FPGA_61.440/db/WOLF-LITE.(0).cnf.cdb b/FPGA_61.440/db/WOLF-LITE.(0).cnf.cdb deleted file mode 100644 index 00bc242..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.(0).cnf.cdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.(0).cnf.hdb b/FPGA_61.440/db/WOLF-LITE.(0).cnf.hdb deleted file mode 100644 index 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b/FPGA_61.440/db/WOLF-LITE.0.cmp.rdb deleted file mode 100644 index f5853b3..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.0.cmp.rdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.1.cmp.rdb b/FPGA_61.440/db/WOLF-LITE.1.cmp.rdb deleted file mode 100644 index a0b0a45..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.1.cmp.rdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.asm.qmsg b/FPGA_61.440/db/WOLF-LITE.asm.qmsg deleted file mode 100644 index 9e17f9a..0000000 --- a/FPGA_61.440/db/WOLF-LITE.asm.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1620759531493 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1620759531512 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 11 21:58:50 2021 " "Processing started: Tue May 11 21:58:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1620759531512 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1620759531512 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off WOLF-LITE -c WOLF-LITE " "Command: quartus_asm --read_settings_files=off --write_settings_files=off WOLF-LITE -c WOLF-LITE" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1620759531512 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1620759537132 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1620759537172 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4725 " "Peak virtual memory: 4725 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1620759538106 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 11 21:58:58 2021 " "Processing ended: Tue May 11 21:58:58 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1620759538106 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1620759538106 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1620759538106 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1620759538106 ""} diff --git a/FPGA_61.440/db/WOLF-LITE.asm.rdb b/FPGA_61.440/db/WOLF-LITE.asm.rdb deleted file mode 100644 index 2a346f1..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.asm.rdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.asm_labs.ddb b/FPGA_61.440/db/WOLF-LITE.asm_labs.ddb deleted file mode 100644 index 4808e7e..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.asm_labs.ddb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.autoh_e40e1.map.reg_db.cdb b/FPGA_61.440/db/WOLF-LITE.autoh_e40e1.map.reg_db.cdb deleted file mode 100644 index 2b7262a..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.autoh_e40e1.map.reg_db.cdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.autoh_e40e1.qmsg b/FPGA_61.440/db/WOLF-LITE.autoh_e40e1.qmsg deleted file mode 100644 index ed8640b..0000000 --- a/FPGA_61.440/db/WOLF-LITE.autoh_e40e1.qmsg +++ /dev/null @@ -1,14 +0,0 @@ -{ "Info" "IQSYN_SYNTHESIZE_PARTITION" "sld_hub:auto_hub " "Starting Logic Optimization and Technology Mapping for Partition sld_hub:auto_hub" { } { } 0 281019 "Starting Logic Optimization and Technology Mapping for Partition %1!s!" 0 0 "Analysis & Synthesis" 0 1 1617214732400 ""} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 speed 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"speed\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 1 1617214732892 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "sld_jtag_hub.vhd" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 386 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 1 1617214732913 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 1 1617214732913 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_hub:auto_hub " "Timing-Driven Synthesis is running on partition \"sld_hub:auto_hub\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 1 1617214733211 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" { } { } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Analysis & Synthesis" 0 1 1617214734699 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Analysis & Synthesis" 0 1 1617214735119 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1617214735121 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1617214735121 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 16.276 clk_sys " " 16.276 clk_sys" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1617214735121 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 clock_stm32 " " 40.000 clock_stm32" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1617214735121 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 81.380 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 81.380 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1617214735121 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "20833.280 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\] " "20833.280 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1617214735121 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 6.510 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 6.510 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1617214735121 ""} } { } 0 332111 "%1!s!" 0 0 "Analysis & Synthesis" 0 1 1617214735121 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" { } { } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Analysis & Synthesis" 0 1 1617214735145 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" { } { } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Analysis & Synthesis" 0 1 1617214735298 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:01 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:01" { } { } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Analysis & Synthesis" 0 1 1617214735301 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "239 " "Implemented 239 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "39 " "Implemented 39 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 1 1617214735405 ""} { "Info" "ICUT_CUT_TM_OPINS" "56 " "Implemented 56 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 1 1617214735405 ""} { "Info" "ICUT_CUT_TM_LCELLS" "144 " "Implemented 144 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 1 1617214735405 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 1 1617214735405 ""} -{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DEBUG2 16 " "Ignored 16 assignments for entity \"DEBUG2\" -- entity does not exist in design" { } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 1 1617214735438 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4817 " "Peak virtual memory: 4817 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 1 1617214735530 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 31 21:18:55 2021 " "Processing ended: Wed Mar 31 21:18:55 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 1 1617214735530 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 1 1617214735530 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 1 1617214735530 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 1 1617214735530 ""} diff --git a/FPGA_61.440/db/WOLF-LITE.cbx.xml b/FPGA_61.440/db/WOLF-LITE.cbx.xml deleted file mode 100644 index 82478bb..0000000 --- a/FPGA_61.440/db/WOLF-LITE.cbx.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/FPGA_61.440/db/WOLF-LITE.cmp.bpm b/FPGA_61.440/db/WOLF-LITE.cmp.bpm deleted file mode 100644 index b114ea7..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.cmp.bpm and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.cmp.cdb b/FPGA_61.440/db/WOLF-LITE.cmp.cdb deleted file mode 100644 index 7a983fb..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.cmp.cdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.cmp.hdb b/FPGA_61.440/db/WOLF-LITE.cmp.hdb deleted file mode 100644 index 792840c..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.cmp.hdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.cmp.idb b/FPGA_61.440/db/WOLF-LITE.cmp.idb deleted file mode 100644 index b87dbae..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.cmp.idb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.cmp.logdb b/FPGA_61.440/db/WOLF-LITE.cmp.logdb deleted file mode 100644 index bd49897..0000000 --- a/FPGA_61.440/db/WOLF-LITE.cmp.logdb +++ /dev/null @@ -1,3563 +0,0 @@ -v1 -PORT_SWAPPING,PORT_SWAP_TYPE_DSPMULT,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1, -PORT_SWAPPING,PORT_SWAP_TYPE_DSPMULT,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1, -GLOBAL_SIGNAL_SINGLE_POINT_ASSIGNMENT,,, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[2][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[1][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_aseq_eq,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16|delay_signals[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16|delay_signals[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16|delay_signals[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16|delay_signals[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_aseq_q_16|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16|delay_signals[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16|delay_signals[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16|delay_signals[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16|delay_signals[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17|delay_signals[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_enableQ[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_count[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_count[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_q[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute|delay_signals[1][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14|delay_signals[1][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_14|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_oseq_eq,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_16|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_oseq_gated_reg_q[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~11,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~10,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~9,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~8,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT15,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT14,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT13,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT12,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT11,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT10,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT9,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT8,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~11,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~10,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~9,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~8,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT15,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT14,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT13,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT12,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT11,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT10,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT9,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT8,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|result[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p1_of_2_o[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_p2_of_2_o[5],Global Clock, -GLOBAL_SIGNAL_SINGLE_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|tx,Off, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_accum_o[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~12,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~11,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~10,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~9,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~8,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT14,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT13,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT12,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT11,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT10,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT9,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT8,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~9,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~8,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT17,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT16,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT15,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT14,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT13,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT12,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT11,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT10,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT9,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT8,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~12,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~11,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~10,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~9,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~8,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT14,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT13,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT12,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT11,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT10,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT9,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT8,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~9,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~8,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAB_REGOUT0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT17,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT16,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT15,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT14,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT13,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT12,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT11,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT10,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT9,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT8,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT7,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT6,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT5,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT4,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT3,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT2,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT1,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_mult1~OBSERVABLEDATAA_REGOUT0,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|result[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|result[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_enableQ[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_count[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|\u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_count[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_enableQ[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_count[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff|auk_dspip_delay:\glogic:u0|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_q[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_count[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[2][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_run_q[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute|delay_signals[1][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[1][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_memread|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[2][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[2][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute|delay_signals[1][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count1_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_ra0_count0_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[1][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[1][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15|delay_signals[2][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:u0_m0_wo0_compute|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_ca0_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_wa0_i[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_xIn_0_13|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15|delay_signals[1][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15|delay_signals[2][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_cm0_q[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_aseq_eq,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_oseq_eq,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15|delay_signals[1][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_16|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_15|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_aseq_eq,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_oseq_gated_reg_q[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|dspba_delay:d_u0_m0_wo0_compute_q_16|delay_signals[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid,Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_out[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_altqmcpipe:ux000|lpm_add_sub:acc|add_sub_u4i:auto_generated|pipeline_dffe[11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[0].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[1].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[2].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[3].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[4].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][84],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][83],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][82],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][81],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][80],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][79],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][78],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][77],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][76],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][75],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][74],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][73],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][72],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][71],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][70],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][69],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][68],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][67],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][66],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][65],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][64],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][63],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][62],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][61],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][60],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][59],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][58],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][57],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][56],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][55],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][54],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][0],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][1],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][2],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][3],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][4],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][5],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][6],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][7],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][8],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][9],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][10],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][11],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][12],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][13],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][14],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][15],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][16],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][17],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][18],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][19],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][20],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][21],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][22],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][23],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][24],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][25],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][26],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][27],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][28],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][29],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][30],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][31],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][32],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][33],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][34],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][35],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][36],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][37],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][38],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][39],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][40],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][41],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][42],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][43],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][44],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][45],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][46],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][47],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][48],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][49],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][50],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][51],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][52],Global Clock, -GLOBAL_SIGNAL_POINT_TO_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_integrator:integrator[5].integration|auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1|\register_fifo:fifo_data[0][53],Global Clock, -GLOBAL_SIGNAL_SINGLE_POINT_ASSIGNMENT,stm32_interface:STM32_INTERFACE|reset_n,Off, -GLOBAL_SIGNAL_SINGLE_POINT_ASSIGNMENT,data_shifter:RX_CICFIR_GAINER|data_valid_out_Q,Global Clock, -GLOBAL_SIGNAL_SINGLE_POINT_ASSIGNMENT,clk_sys,Global Clock, -GLOBAL_SIGNAL_SINGLE_POINT_ASSIGNMENT,MAIN_PLL:MAIN_PLL|altpll:altpll_component|MAIN_PLL_altpll:auto_generated|wire_pll1_clk[0],Global Clock, -GLOBAL_SIGNAL_SINGLE_POINT_ASSIGNMENT,MAIN_PLL:MAIN_PLL|altpll:altpll_component|MAIN_PLL_altpll:auto_generated|wire_pll1_clk[1],Global Clock, -GLOBAL_SIGNAL_SINGLE_POINT_ASSIGNMENT,tx_pll:TX_PLL|altpll:altpll_component|tx_pll_altpll:auto_generated|wire_pll1_clk[0],Global Clock, -GLOBAL_SIGNAL_SINGLE_POINT_ASSIGNMENT,altera_internal_jtag~TCKUTAP,Global Clock, -IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, -IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, -IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, -IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, -IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, -IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, -IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, -IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, -IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, -IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, -IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, -IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, -IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,PASS,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,0 such failures found.,,I/O,, -IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,PASS,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, -IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, -IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,, -IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, -IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, -IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, -IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, -IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, -IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, -IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, -IO_RULES_MATRIX,Total Pass,61;0;61;0;0;65;61;0;65;65;0;0;0;41;24;0;0;24;41;0;0;0;0;0;0;0;0;65;0;0, -IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,Total Inapplicable,4;65;4;65;65;0;4;65;0;0;65;65;65;24;41;65;65;41;24;65;65;65;65;65;65;65;65;0;65;65, -IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,PREAMP,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,AUDIO_I2S_CLOCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,AUDIO_48K_CLOCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,FLASH_C,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,FLASH_S,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,FLASH_MOSI,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_PD,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_CLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ATT_05,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ATT_1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ATT_2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ATT_4,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ATT_8,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ATT_16,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,BPF_A,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,BPF_B,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,BPF_OE1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,BPF_OE2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LPF_1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LPF_2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LPF_3,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,TXRX_OUT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_OUTPUT[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_OUTPUT[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_OUTPUT[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_OUTPUT[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_OUTPUT[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_OUTPUT[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_OUTPUT[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_OUTPUT[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_OUTPUT[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_OUTPUT[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_OUTPUT[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_OUTPUT[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_OUTPUT[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,DAC_OUTPUT[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,STM32_DATA_BUS[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,STM32_DATA_BUS[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,STM32_DATA_BUS[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,STM32_DATA_BUS[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,STM32_DATA_BUS[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,STM32_DATA_BUS[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,STM32_DATA_BUS[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,STM32_DATA_BUS[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,STM32_CLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,STM32_SYNC,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,clk_sys,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ADC_INPUT[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ADC_INPUT[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ADC_OTR,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ADC_INPUT[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,FLASH_MISO,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ADC_INPUT[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ADC_INPUT[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ADC_INPUT[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ADC_INPUT[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ADC_INPUT[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ADC_INPUT[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ADC_INPUT[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ADC_INPUT[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,ADC_INPUT[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,altera_reserved_tms,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,altera_reserved_tck,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,altera_reserved_tdi,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,altera_reserved_tdo,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_SUMMARY,Total I/O Rules,30, -IO_RULES_SUMMARY,Number of I/O Rules Passed,11, -IO_RULES_SUMMARY,Number of I/O Rules Failed,0, -IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, -IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,19, diff --git a/FPGA_61.440/db/WOLF-LITE.cmp.rdb b/FPGA_61.440/db/WOLF-LITE.cmp.rdb deleted file mode 100644 index f666a7e..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.cmp.rdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.cmp_merge.kpt b/FPGA_61.440/db/WOLF-LITE.cmp_merge.kpt deleted file mode 100644 index e5c5729..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.cmp_merge.kpt and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/FPGA_61.440/db/WOLF-LITE.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd deleted file mode 100644 index 85c88ff..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd b/FPGA_61.440/db/WOLF-LITE.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd deleted file mode 100644 index d4bac09..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd b/FPGA_61.440/db/WOLF-LITE.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd deleted file mode 100644 index 49e2997..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.cycloneive_io_sim_cache.45um_tt_1200mv_85c_nom.hsd b/FPGA_61.440/db/WOLF-LITE.cycloneive_io_sim_cache.45um_tt_1200mv_85c_nom.hsd deleted file mode 100644 index ed4553d..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.cycloneive_io_sim_cache.45um_tt_1200mv_85c_nom.hsd and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.db_info b/FPGA_61.440/db/WOLF-LITE.db_info deleted file mode 100644 index d5e3ead..0000000 --- a/FPGA_61.440/db/WOLF-LITE.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition -Version_Index = 486699264 -Creation_Time = Tue Oct 26 20:50:35 2021 diff --git a/FPGA_61.440/db/WOLF-LITE.fit.qmsg b/FPGA_61.440/db/WOLF-LITE.fit.qmsg deleted file mode 100644 index 4415f16..0000000 --- a/FPGA_61.440/db/WOLF-LITE.fit.qmsg +++ /dev/null @@ -1,109 +0,0 @@ -{ "Info" "IQCU_OPT_MODE_DESCRIPTION" "Aggressive Performance timing performance increased logic area and compilation time " "Aggressive Performance optimization mode selected -- timing performance will be prioritized at the potential cost of increased logic area and compilation time" { } { } 0 16303 "%1!s! optimization mode selected -- %2!s! will be prioritized at the potential cost of %3!s!" 0 0 "Fitter" 0 -1 1620759490865 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1620759490886 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "WOLF-LITE EP4CE10E22C8 " "Selected device EP4CE10E22C8 for design \"WOLF-LITE\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1620759491009 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1620759491079 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1620759491079 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] 1 5 0 0 " "Implementing clock multiplication of 1, clock division of 5, and phase shift of 0 degrees (0 ps) for MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1620759491138 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] 1 1280 0 0 " "Implementing clock multiplication of 1, clock division of 1280, and phase shift of 0 degrees (0 ps) for MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 600 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1620759491138 ""} } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1620759491138 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|wire_pll1_clk\[0\] 5 2 0 0 " "Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3170 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1620759491143 ""} } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3170 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1620759491143 ""} -{ "Warning" "WMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a0 " "Atom \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a0\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Design Software" 0 -1 1620759491146 "|WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4k82:auto_generated|ram_block1a0"} } { } 0 18550 "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." 1 0 "Fitter" 0 -1 1620759491146 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1620759491451 ""} -{ "Info" "IFITCC_FITCC_QIC_PARTITION_SUMMARY" "98.76 1 0 3 " "Fitter is preserving placement for 98.76 percent of the design from 1 Post-Fit partition(s) and 0 imported partition(s) of 3 total partition(s)" { } { } 0 171122 "Fitter is preserving placement for %1!s! percent of the design from %2!d! Post-Fit partition(s) and %3!d! imported partition(s) of %4!d! total partition(s)" 0 0 "Fitter" 0 -1 1620759492447 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6E22C8 " "Device EP4CE6E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1620759492992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C8 " "Device EP4CE15E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1620759492992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C8 " "Device EP4CE22E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1620759492992 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1620759492992 ""} -{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1620759493110 ""} -{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1620759493110 ""} -{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1620759493110 ""} -{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1620759493110 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 1 0 "Fitter" 0 -1 1620759493115 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1620759493399 ""} -{ "Info" "IFIOMGR_CONFIGURATION_VOLTAGE_IS_AUTOMATICALLY_ENFORCED" "Cyclone IV E Active Serial " "Configuration voltage level is automatically enforced for the device family 'Cyclone IV E' with the configuration scheme 'Active Serial'" { } { } 0 169197 "Configuration voltage level is automatically enforced for the device family '%1!s!' with the configuration scheme '%2!s!'" 0 0 "Fitter" 0 -1 1620759493722 ""} -{ "Info" "IFIOMGR_IO_BANK_VCCIO_SET_FOR_CONFIGURATION" "2.5V 1 " "Configuration voltage level of 2.5V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 2.5V." { } { } 0 169213 "Configuration voltage level of %1!s! is enforced on the I/O bank %2!s!. The VCCIO of the I/O bank %2!s! is set to %1!s!." 0 0 "Fitter" 0 -1 1620759493722 ""} -{ "Info" "IFIOMGR_IO_BANK_VCCIO_SET_FOR_CONFIGURATION" "2.5V 1 " "Configuration voltage level of 2.5V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 2.5V." { } { } 0 169213 "Configuration voltage level of %1!s! is enforced on the I/O bank %2!s!. The VCCIO of the I/O bank %2!s! is set to %1!s!." 0 0 "Fitter" 0 -1 1620759493722 ""} -{ "Warning" "WAMM_AMM_ATOM_MOD_POST_FIT_ATOM_W_LOCATION_E" "PLL Merging clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk " "Cannot modify or duplicate post-fit node \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk\" with PLL Merging -- node is marked with preserve location" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } } 0 126022 "Cannot modify or duplicate post-fit node \"%2!s!\" with %1!s! -- node is marked with preserve location" 0 0 "Fitter" 0 -1 1620759494160 ""} -{ "Warning" "WAMM_AMM_ATOM_MOD_POST_FIT_ATOM_W_LOCATION_AND_ROUTING_E" "PLL Merging clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk " "Cannot modify or duplicate post-fit node \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk\" with PLL Merging -- node is marked with preserve location and routing" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } } 0 126024 "Cannot modify or duplicate post-fit node \"%2!s!\" with %1!s! -- node is marked with preserve location and routing" 0 0 "Fitter" 0 -1 1620759494160 ""} -{ "Warning" "WAMM_AMM_ATOM_MOD_POST_FIT_ATOM_W_LOCATION_AND_ROUTING_AND_TILE_E" "PLL Merging clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk " "Cannot modify or duplicate post-fit node \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk\" with PLL Merging -- node is marked with preserve location, routing, and tile" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } } 0 126026 "Cannot modify or duplicate post-fit node \"%2!s!\" with %1!s! -- node is marked with preserve location, routing, and tile" 0 0 "Fitter" 0 -1 1620759494160 ""} -{ "Warning" "WAMM_AMM_ATOM_MOD_POST_FIT_ATOM_W_LOCATION_E" "PLL Merging clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1~ena_reg " "Cannot modify or duplicate post-fit node \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1~ena_reg\" with PLL Merging -- node is marked with preserve location" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } } 0 126022 "Cannot modify or duplicate post-fit node \"%2!s!\" with %1!s! -- node is marked with preserve location" 0 0 "Fitter" 0 -1 1620759494161 ""} -{ "Warning" "WAMM_AMM_ATOM_MOD_POST_FIT_ATOM_W_LOCATION_AND_ROUTING_E" "PLL Merging clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1~ena_reg " "Cannot modify or duplicate post-fit node \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1~ena_reg\" with PLL Merging -- node is marked with preserve location and routing" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } } 0 126024 "Cannot modify or duplicate post-fit node \"%2!s!\" with %1!s! -- node is marked with preserve location and routing" 0 0 "Fitter" 0 -1 1620759494161 ""} -{ "Warning" "WAMM_AMM_ATOM_MOD_POST_FIT_ATOM_W_LOCATION_AND_ROUTING_AND_TILE_E" "PLL Merging clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1~ena_reg " "Cannot modify or duplicate post-fit node \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1~ena_reg\" with PLL Merging -- node is marked with preserve location, routing, and tile" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } } 0 126026 "Cannot modify or duplicate post-fit node \"%2!s!\" with %1!s! -- node is marked with preserve location, routing, and tile" 0 0 "Fitter" 0 -1 1620759494161 ""} -{ "Warning" "WAMM_AMM_ATOM_MOD_POST_FIT_ATOM_W_LOCATION_E" "PLL Merging clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk " "Cannot modify or duplicate post-fit node \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk\" with PLL Merging -- node is marked with preserve location" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } } 0 126022 "Cannot modify or duplicate post-fit node \"%2!s!\" with %1!s! -- node is marked with preserve location" 0 0 "Fitter" 0 -1 1620759494161 ""} -{ "Warning" "WAMM_AMM_ATOM_MOD_POST_FIT_ATOM_W_LOCATION_AND_ROUTING_E" "PLL Merging clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk " "Cannot modify or duplicate post-fit node \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk\" with PLL Merging -- node is marked with preserve location and routing" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } } 0 126024 "Cannot modify or duplicate post-fit node \"%2!s!\" with %1!s! -- node is marked with preserve location and routing" 0 0 "Fitter" 0 -1 1620759494161 ""} -{ "Warning" "WAMM_AMM_ATOM_MOD_POST_FIT_ATOM_W_LOCATION_AND_ROUTING_AND_TILE_E" "PLL Merging clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk " "Cannot modify or duplicate post-fit node \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk\" with PLL Merging -- node is marked with preserve location, routing, and tile" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } } 0 126026 "Cannot modify or duplicate post-fit node \"%2!s!\" with %1!s! -- node is marked with preserve location, routing, and tile" 0 0 "Fitter" 0 -1 1620759494161 ""} -{ "Warning" "WAMM_AMM_ATOM_MOD_POST_FIT_ATOM_W_LOCATION_E" "PLL Merging clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1~ena_reg " "Cannot modify or duplicate post-fit node \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1~ena_reg\" with PLL Merging -- node is marked with preserve location" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } } 0 126022 "Cannot modify or duplicate post-fit node \"%2!s!\" with %1!s! -- node is marked with preserve location" 0 0 "Fitter" 0 -1 1620759494161 ""} -{ "Warning" "WAMM_AMM_ATOM_MOD_POST_FIT_ATOM_W_LOCATION_AND_ROUTING_E" "PLL Merging clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1~ena_reg " "Cannot modify or duplicate post-fit node \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1~ena_reg\" with PLL Merging -- node is marked with preserve location and routing" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } } 0 126024 "Cannot modify or duplicate post-fit node \"%2!s!\" with %1!s! -- node is marked with preserve location and routing" 0 0 "Fitter" 0 -1 1620759494161 ""} -{ "Warning" "WAMM_AMM_ATOM_MOD_POST_FIT_ATOM_W_LOCATION_AND_ROUTING_AND_TILE_E" "PLL Merging clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1~ena_reg " "Cannot modify or duplicate post-fit node \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1~ena_reg\" with PLL Merging -- node is marked with preserve location, routing, and tile" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } } 0 126026 "Cannot modify or duplicate post-fit node \"%2!s!\" with %1!s! -- node is marked with preserve location, routing, and tile" 0 0 "Fitter" 0 -1 1620759494161 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1620759496082 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1620759496082 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1620759496082 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1620759496082 ""} -{ "Info" "ISTA_SDC_FOUND" "SDC.sdc " "Reading SDC File: 'SDC.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1620759496206 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 5 rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid port or pin or register or keeper or net or combinational node or node " "Ignored filter at SDC.sdc(5): rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid could not be matched with a port or pin or register or keeper or net or combinational node or node" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1620759496212 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock SDC.sdc 5 Argument is not an object ID " "Ignored create_clock at SDC.sdc(5): Argument is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name \"iq_valid\" -period 48KHz \{rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid\} " "create_clock -name \"iq_valid\" -period 48KHz \{rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid\}" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759496213 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1620759496213 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 7 clock_sys clock " "Ignored filter at SDC.sdc(7): clock_sys could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 7 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1620759496214 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 7 iq_valid clock " "Ignored filter at SDC.sdc(7): iq_valid could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 7 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1620759496214 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1620759496214 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{TX_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{TX_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1620759496224 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1620759496224 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 1280 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 1280 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1620759496224 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1620759496224 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 13 clock_crystal clock " "Ignored filter at SDC.sdc(13): clock_crystal could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1620759496225 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_output_delay SDC.sdc 13 Argument -clock is not an object ID " "Ignored set_output_delay at SDC.sdc(13): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_output_delay -clock clock_crystal -max 36ps \[get_ports \{DAC_OUTPUT\[*\]\}\] " "set_output_delay -clock clock_crystal -max 36ps \[get_ports \{DAC_OUTPUT\[*\]\}\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759496226 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1620759496226 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_output_delay SDC.sdc 14 Argument -clock is not an object ID " "Ignored set_output_delay at SDC.sdc(14): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_output_delay -clock clock_crystal -min 0ps \[get_ports \{DAC_OUTPUT\[*\]\}\] " "set_output_delay -clock clock_crystal -min 0ps \[get_ports \{DAC_OUTPUT\[*\]\}\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 14 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759496226 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 14 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1620759496226 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 18 clock_adc clock " "Ignored filter at SDC.sdc(18): clock_adc could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1620759496226 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 18 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(18): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_INPUT\[*\]\] " "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_INPUT\[*\]\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759496227 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1620759496227 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 19 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(19): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_INPUT\[*\]\] " "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_INPUT\[*\]\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 19 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759496227 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 19 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1620759496227 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 20 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(20): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_OTR\] " "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_OTR\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 20 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759496227 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 20 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1620759496227 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 21 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(21): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_OTR\] " "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_OTR\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759496228 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1620759496228 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 27 iq_valid clock " "Ignored filter at SDC.sdc(27): iq_valid could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1620759496228 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 27 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(27): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759496229 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1620759496229 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 28 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(28): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 28 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759496229 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 28 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1620759496229 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 29 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(29): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 29 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759496229 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 29 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1620759496229 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 30 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(30): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 30 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759496230 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 30 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1620759496230 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 31 clock_sys clock " "Ignored filter at SDC.sdc(31): clock_sys could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1620759496230 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 31 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(31): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759496230 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1620759496230 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 32 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(32): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 32 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759496231 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 32 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1620759496231 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Node: rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_I\[5\]\[15\] rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_I\[5\]\[15\] is being clocked by rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1620759496290 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 1 0 "Fitter" 0 -1 1620759496290 "|WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1620759496422 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1620759496428 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1620759496429 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1620759496429 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1620759496429 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 16.276 clk_sys " " 16.276 clk_sys" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1620759496429 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 clock_stm32 " " 40.000 clock_stm32" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1620759496429 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 81.380 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 81.380 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1620759496429 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "20833.280 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\] " "20833.280 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1620759496429 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 6.510 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 6.510 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1620759496429 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1620759496429 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL_FANOUTS" "altera_internal_jtag~TCKUTAPclkctrl Global Clock " "Promoted altera_internal_jtag~TCKUTAPclkctrl to use location or clock signal Global Clock" { } { { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 24013 14177 15141 0 0 "" 0 "" "" } } } } } 0 176354 "Promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1620759497090 ""} } { { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 23525 14177 15141 0 0 "" 0 "" "" } } } } } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1620759497090 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "clk_sys~input (placed in PIN 89 (CLK6, DIFFCLK_3p)) " "Promoted node clk_sys~input (placed in PIN 89 (CLK6, DIFFCLK_3p))" { { "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL_FANOUTS" "clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1 Global Clock CLKCTRL_G9 " "Promoted clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1 to use location or clock signal Global Clock CLKCTRL_G9" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3168 14177 15141 0 0 "" 0 "" "" } } } } } 0 176354 "Promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1620759497090 ""} } { { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 688 2216 2392 704 "clk_sys" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 23581 14177 15141 0 0 "" 0 "" "" } } } } } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1620759497090 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "data_shifter:RX_CICFIR_GAINER\|data_valid_out_Q " "Promoted node data_shifter:RX_CICFIR_GAINER\|data_valid_out_Q " { { "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL_FANOUTS" "data_shifter:RX_CICFIR_GAINER\|data_valid_out_Q~clkctrl Global Clock " "Promoted data_shifter:RX_CICFIR_GAINER\|data_valid_out_Q~clkctrl to use location or clock signal Global Clock" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 13 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 24014 14177 15141 0 0 "" 0 "" "" } } } } } 0 176354 "Promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1620759497090 ""} } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 13 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 1984 14177 15141 0 0 "" 0 "" "" } } } } } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1620759497090 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_2) " "Promoted node MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL_FANOUTS" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[0\]~clkctrl Global Clock CLKCTRL_G8 " "Promoted MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[0\]~clkctrl to use location or clock signal Global Clock CLKCTRL_G8" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 24016 14177 15141 0 0 "" 0 "" "" } } } } } 0 176354 "Promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1620759497090 ""} } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1620759497090 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_2) " "Promoted node MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL_FANOUTS" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[1\]~clkctrl Global Clock CLKCTRL_G7 " "Promoted MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[1\]~clkctrl to use location or clock signal Global Clock CLKCTRL_G7" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 24018 14177 15141 0 0 "" 0 "" "" } } } } } 0 176354 "Promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1620759497090 ""} } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1620759497090 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "stm32_interface:STM32_INTERFACE\|reset_n " "Promoted node stm32_interface:STM32_INTERFACE\|reset_n " { { "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL_FANOUTS" "stm32_interface:STM32_INTERFACE\|reset_n~clkctrl Global Clock " "Promoted stm32_interface:STM32_INTERFACE\|reset_n~clkctrl to use location or clock signal Global Clock" { } { { "stm32_interface.v" "" { Text "C:/FPGA/stm32_interface.v" 64 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 24010 14177 15141 0 0 "" 0 "" "" } } } } } 0 176354 "Promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1620759497091 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated\|mac_out2 " "Destination node mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated\|mac_out2" { } { { "db/mult_jnp.tdf" "" { Text "C:/FPGA/db/mult_jnp.tdf" 46 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 633 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497091 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mixer:RX_MIXER_Q\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated\|mac_out2 " "Destination node mixer:RX_MIXER_Q\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated\|mac_out2" { } { { "db/mult_jnp.tdf" "" { Text "C:/FPGA/db/mult_jnp.tdf" 46 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3864 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497091 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cntr_r9b:wr_ptr\|counter_reg_bit\[1\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cntr_r9b:wr_ptr\|counter_reg_bit\[1\]" { } { { "db/cntr_r9b.tdf" "" { Text "C:/FPGA/db/cntr_r9b.tdf" 43 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4875 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497091 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cntr_r9b:wr_ptr\|counter_reg_bit\[0\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cntr_r9b:wr_ptr\|counter_reg_bit\[0\]" { } { { "db/cntr_r9b.tdf" "" { Text "C:/FPGA/db/cntr_r9b.tdf" 43 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4876 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497091 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cntr_7a7:usedw_counter\|counter_reg_bit\[1\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cntr_7a7:usedw_counter\|counter_reg_bit\[1\]" { } { { "db/cntr_7a7.tdf" "" { Text "C:/FPGA/db/cntr_7a7.tdf" 44 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4883 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497091 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cntr_7a7:usedw_counter\|counter_reg_bit\[0\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cntr_7a7:usedw_counter\|counter_reg_bit\[0\]" { } { { "db/cntr_7a7.tdf" "" { Text "C:/FPGA/db/cntr_7a7.tdf" 44 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4884 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497091 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cntr_q9b:rd_ptr_msb\|counter_reg_bit\[0\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cntr_q9b:rd_ptr_msb\|counter_reg_bit\[0\]" { } { { "db/cntr_q9b.tdf" "" { Text "C:/FPGA/db/cntr_q9b.tdf" 38 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4891 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497091 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[4\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[4\]" { } { { "db/cntr_u9b.tdf" "" { Text "C:/FPGA/db/cntr_u9b.tdf" 58 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 5480 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497091 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[3\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[3\]" { } { { "db/cntr_u9b.tdf" "" { Text "C:/FPGA/db/cntr_u9b.tdf" 58 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 5481 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497091 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[2\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[2\]" { } { { "db/cntr_u9b.tdf" "" { Text "C:/FPGA/db/cntr_u9b.tdf" 58 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 5482 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497091 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Design Software" 0 -1 1620759497091 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1620759497091 ""} } { { "stm32_interface.v" "" { Text "C:/FPGA/stm32_interface.v" 64 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3837 14177 15141 0 0 "" 0 "" "" } } } } } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1620759497091 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "stm32_interface:STM32_INTERFACE\|tx " "Promoted node stm32_interface:STM32_INTERFACE\|tx " { { "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL_FANOUTS" "stm32_interface:STM32_INTERFACE\|tx~clkctrl Global Clock " "Promoted stm32_interface:STM32_INTERFACE\|tx~clkctrl to use location or clock signal Global Clock" { } { { "stm32_interface.v" "" { Text "C:/FPGA/stm32_interface.v" 63 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 24015 14177 15141 0 0 "" 0 "" "" } } } } } 0 176354 "Promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1620759497092 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_abt:auto_generated\|mac_out2 " "Destination node tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_abt:auto_generated\|mac_out2" { } { { "db/mult_abt.tdf" "" { Text "C:/FPGA/db/mult_abt.tdf" 46 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3102 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497092 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a0 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a0" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 39 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2200 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497092 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a4 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a4" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 187 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2204 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497092 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a8 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a8" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 335 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2208 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497092 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a12 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a12" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 483 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2212 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497092 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_u8a1:auto_generated\|ram_block1a0 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_u8a1:auto_generated\|ram_block1a0" { } { { "db/altsyncram_u8a1.tdf" "" { Text "C:/FPGA/db/altsyncram_u8a1.tdf" 35 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2165 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497092 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_u8a1:auto_generated\|ram_block1a4 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_u8a1:auto_generated\|ram_block1a4" { } { { "db/altsyncram_u8a1.tdf" "" { Text "C:/FPGA/db/altsyncram_u8a1.tdf" 123 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2169 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497092 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_u8a1:auto_generated\|ram_block1a8 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_u8a1:auto_generated\|ram_block1a8" { } { { "db/altsyncram_u8a1.tdf" "" { Text "C:/FPGA/db/altsyncram_u8a1.tdf" 211 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2173 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497092 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_u8a1:auto_generated\|ram_block1a12 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_u8a1:auto_generated\|ram_block1a12" { } { { "db/altsyncram_u8a1.tdf" "" { Text "C:/FPGA/db/altsyncram_u8a1.tdf" 299 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2177 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497092 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\|altsyncram_p8a1:auto_generated\|ram_block1a0 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\|altsyncram_p8a1:auto_generated\|ram_block1a0" { } { { "db/altsyncram_p8a1.tdf" "" { Text "C:/FPGA/db/altsyncram_p8a1.tdf" 35 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2131 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1620759497092 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Design Software" 0 -1 1620759497092 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1620759497092 ""} } { { "stm32_interface.v" "" { Text "C:/FPGA/stm32_interface.v" 63 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3827 14177 15141 0 0 "" 0 "" "" } } } } } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1620759497092 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1) " "Promoted node tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL_FANOUTS" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|wire_pll1_clk\[0\]~clkctrl Global Clock CLKCTRL_G3 " "Promoted tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|wire_pll1_clk\[0\]~clkctrl to use location or clock signal Global Clock CLKCTRL_G3" { } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 24011 14177 15141 0 0 "" 0 "" "" } } } } } 0 176354 "Promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1620759497093 ""} } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3170 14177 15141 0 0 "" 0 "" "" } } } } } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1620759497093 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1620759502637 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1620759502676 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1620759502678 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1620759502720 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1620759502755 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1620759502825 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1620759502826 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1620759502861 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1620759502861 ""} -{ "Warning" "WCUT_PLL_INCLK_NOT_FROM_DEDICATED_INPUT" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 0 " "PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input" { { "Info" "ICUT_CUT_INPUT_PORT_SIGNAL_SOURCE" "INCLK\[0\] MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 driven by clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1 " "Input port INCLK\[0\] of node \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" is driven by clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 45 -1 0 } } { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 112 0 0 } } { "db/ip/clock_buffer/clock_buffer.v" "" { Text "C:/FPGA/db/ip/clock_buffer/clock_buffer.v" 14 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 624 2416 2688 728 "SYSCLK_BUFFER" "" } } } } } 0 15024 "Input port %1!s! of node \"%2!s!\" is %3!s!" 0 0 "Design Software" 0 -1 1620759503101 ""} } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } } 0 15055 "PLL \"%1!s!\" input clock inclk\[%2!d!\] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input" 0 0 "Fitter" 0 -1 1620759503101 ""} -{ "Warning" "WCUT_PLL_NON_ZDB_COMP_CLK_FEEDING_IO" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 compensate_clock 0 " "PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" is in normal or source synchronous mode with output clock \"compensate_clock\" set to clk\[0\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } } 0 15058 "PLL \"%1!s!\" is in normal or source synchronous mode with output clock \"%2!s!\" set to clk\[%3!d!\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" 0 0 "Fitter" 0 -1 1620759503105 ""} -{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 clk\[0\] AUDIO_I2S_CLOCK~output " "PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" output port clk\[0\] feeds output pin \"AUDIO_I2S_CLOCK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 1000 3408 3584 1016 "AUDIO_I2S_CLOCK" "" } } } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "Fitter" 0 -1 1620759503105 ""} -{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 clk\[1\] AUDIO_48K_CLOCK~output " "PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"AUDIO_48K_CLOCK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 1016 3408 3584 1032 "AUDIO_48K_CLOCK" "" } } } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "Fitter" 0 -1 1620759503105 ""} -{ "Warning" "WCUT_PLL_INCLK_NOT_FROM_DEDICATED_INPUT" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 0 " "PLL \"tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input" { { "Info" "ICUT_CUT_INPUT_PORT_SIGNAL_SOURCE" "INCLK\[0\] tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 driven by clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1 " "Input port INCLK\[0\] of node \"tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1\" is driven by clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1" { } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 720 3080 3320 872 "TX_PLL" "" } } } } { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 45 -1 0 } } { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 112 0 0 } } { "db/ip/clock_buffer/clock_buffer.v" "" { Text "C:/FPGA/db/ip/clock_buffer/clock_buffer.v" 14 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 624 2416 2688 728 "SYSCLK_BUFFER" "" } } } } } 0 15024 "Input port %1!s! of node \"%2!s!\" is %3!s!" 0 0 "Design Software" 0 -1 1620759503112 ""} } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 720 3080 3320 872 "TX_PLL" "" } } } } } 0 15055 "PLL \"%1!s!\" input clock inclk\[%2!d!\] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input" 0 0 "Fitter" 0 -1 1620759503112 ""} -{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 clk\[0\] DAC_CLK~output " "PLL \"tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1\" output port clk\[0\] feeds output pin \"DAC_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 720 3080 3320 872 "TX_PLL" "" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 80 6288 6464 96 "DAC_CLK" "" } } } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "Fitter" 0 -1 1620759503113 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" { } { } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Fitter" 0 -1 1620759503405 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:04 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:04" { } { } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Fitter" 0 -1 1620759507415 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:15 " "Fitter preparation operations ending: elapsed time is 00:00:15" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1620759507650 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1620759509496 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1620759510078 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1620759510390 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1620759510427 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1620759512559 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1620759512559 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1620759512983 ""} -{ "Info" "IFITAPI_FITAPI_VPR_RCF_NUM_ROUTES_CONSTRAINED" "99.34 " "Router is attempting to preserve 99.34 percent of routes from an earlier compilation, a user specified Routing Constraints File, or internal routing requirements." { } { } 0 170239 "Router is attempting to preserve %1!s! percent of routes from an earlier compilation, a user specified Routing Constraints File, or internal routing requirements." 0 0 "Fitter" 0 -1 1620759513611 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Router estimated average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "6 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 6% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "C:/FPGA/" { { 1 { 0 "Router estimated peak interconnect usage is 6% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1620759513920 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1620759513920 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1620759514970 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.77 " "Total time spent on timing analysis during the Fitter is 0.77 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1620759515145 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1620759516291 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1620759517497 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1620759517505 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1620759519242 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:06 " "Fitter post-fit operations ending: elapsed time is 00:00:06" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1620759522269 ""} -{ "Info" "IFIOMGR_CONFIGURATION_VOLTAGE_IS_AUTOMATICALLY_ENFORCED" "Cyclone IV E Active Serial " "Configuration voltage level is automatically enforced for the device family 'Cyclone IV E' with the configuration scheme 'Active Serial'" { } { } 0 169197 "Configuration voltage level is automatically enforced for the device family '%1!s!' with the configuration scheme '%2!s!'" 0 0 "Fitter" 0 -1 1620759522997 ""} -{ "Info" "IFIOMGR_IO_BANK_VCCIO_SET_FOR_CONFIGURATION" "2.5V 1 " "Configuration voltage level of 2.5V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 2.5V." { } { } 0 169213 "Configuration voltage level of %1!s! is enforced on the I/O bank %2!s!. The VCCIO of the I/O bank %2!s! is set to %1!s!." 0 0 "Fitter" 0 -1 1620759522997 ""} -{ "Info" "IFIOMGR_IO_BANK_VCCIO_SET_FOR_CONFIGURATION" "2.5V 1 " "Configuration voltage level of 2.5V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 2.5V." { } { } 0 169213 "Configuration voltage level of %1!s! is enforced on the I/O bank %2!s!. The VCCIO of the I/O bank %2!s! is set to %1!s!." 0 0 "Fitter" 0 -1 1620759522997 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 1 0 "Fitter" 0 -1 1620759523172 ""} -{ "Warning" "WFIOMGR_FIOMGR_MUST_USE_EXTERNAL_CLAMPING_DIODE_TOP_LEVEL" "1 " "Following 1 pins must use external clamping diodes." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "FLASH_MISO 2.5 V 13 " "Pin FLASH_MISO uses I/O standard 2.5 V at 13" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { FLASH_MISO } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FLASH_MISO" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 1000 3744 3920 1016 "FLASH_MISO" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 468 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} } { } 0 169180 "Following %1!d! pins must use external clamping diodes." 1 0 "Fitter" 0 -1 1620759523264 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "24 Cyclone IV E " "24 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[7\] 3.3-V LVTTL 46 " "Pin STM32_DATA_BUS\[7\] uses I/O standard 3.3-V LVTTL at 46" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[7] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[7\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 441 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[6\] 3.3-V LVTTL 43 " "Pin STM32_DATA_BUS\[6\] uses I/O standard 3.3-V LVTTL at 43" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[6] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[6\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 442 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[5\] 3.3-V LVTTL 42 " "Pin STM32_DATA_BUS\[5\] uses I/O standard 3.3-V LVTTL at 42" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[5] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[5\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 443 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[4\] 3.3-V LVTTL 39 " "Pin STM32_DATA_BUS\[4\] uses I/O standard 3.3-V LVTTL at 39" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[4] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[4\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 444 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[3\] 3.3-V LVTTL 38 " "Pin STM32_DATA_BUS\[3\] uses I/O standard 3.3-V LVTTL at 38" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[3] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[3\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 445 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[2\] 3.3-V LVTTL 51 " "Pin STM32_DATA_BUS\[2\] uses I/O standard 3.3-V LVTTL at 51" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[2] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[2\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 446 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[1\] 3.3-V LVTTL 50 " "Pin STM32_DATA_BUS\[1\] uses I/O standard 3.3-V LVTTL at 50" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[1] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[1\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 447 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[0\] 3.3-V LVTTL 49 " "Pin STM32_DATA_BUS\[0\] uses I/O standard 3.3-V LVTTL at 49" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[0] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[0\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 448 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_CLK 3.3-V LVTTL 33 " "Pin STM32_CLK uses I/O standard 3.3-V LVTTL at 33" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_CLK } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_CLK" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 2840 3016 184 "STM32_CLK" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 464 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_SYNC 3.3-V LVTTL 32 " "Pin STM32_SYNC uses I/O standard 3.3-V LVTTL at 32" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_SYNC } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_SYNC" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 216 2840 3016 232 "STM32_SYNC" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 465 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "clk_sys 3.3-V LVTTL 89 " "Pin clk_sys uses I/O standard 3.3-V LVTTL at 89" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { clk_sys } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk_sys" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 688 2216 2392 704 "clk_sys" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 467 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[0\] 3.3-V LVTTL 68 " "Pin ADC_INPUT\[0\] uses I/O standard 3.3-V LVTTL at 68" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[0] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[0\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 440 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[1\] 3.3-V LVTTL 67 " "Pin ADC_INPUT\[1\] uses I/O standard 3.3-V LVTTL at 67" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[1] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[1\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 439 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_OTR 3.3-V LVTTL 44 " "Pin ADC_OTR uses I/O standard 3.3-V LVTTL at 44" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_OTR } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_OTR" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 232 2840 3016 248 "ADC_OTR" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 466 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[2\] 3.3-V LVTTL 66 " "Pin ADC_INPUT\[2\] uses I/O standard 3.3-V LVTTL at 66" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[2] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[2\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 438 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[3\] 3.3-V LVTTL 65 " "Pin ADC_INPUT\[3\] uses I/O standard 3.3-V LVTTL at 65" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[3] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[3\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 437 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[7\] 3.3-V LVTTL 58 " "Pin ADC_INPUT\[7\] uses I/O standard 3.3-V LVTTL at 58" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[7] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[7\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 433 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[6\] 3.3-V LVTTL 59 " "Pin ADC_INPUT\[6\] uses I/O standard 3.3-V LVTTL at 59" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[6] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[6\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 434 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[5\] 3.3-V LVTTL 60 " "Pin ADC_INPUT\[5\] uses I/O standard 3.3-V LVTTL at 60" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[5] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[5\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 435 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[4\] 3.3-V LVTTL 64 " "Pin ADC_INPUT\[4\] uses I/O standard 3.3-V LVTTL at 64" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[4] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[4\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 436 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[11\] 3.3-V LVTTL 52 " "Pin ADC_INPUT\[11\] uses I/O standard 3.3-V LVTTL at 52" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[11] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[11\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 429 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[10\] 3.3-V LVTTL 53 " "Pin ADC_INPUT\[10\] uses I/O standard 3.3-V LVTTL at 53" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[10] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[10\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 430 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[9\] 3.3-V LVTTL 54 " "Pin ADC_INPUT\[9\] uses I/O standard 3.3-V LVTTL at 54" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[9] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[9\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 431 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[8\] 3.3-V LVTTL 55 " "Pin ADC_INPUT\[8\] uses I/O standard 3.3-V LVTTL at 55" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[8] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[8\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 432 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1620759523264 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 1 0 "Fitter" 0 -1 1620759523264 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/FPGA/output_files/WOLF-LITE.fit.smsg " "Generated suppressed messages file C:/FPGA/output_files/WOLF-LITE.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1620759524301 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 38 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 38 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5977 " "Peak virtual memory: 5977 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1620759528964 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 11 21:58:48 2021 " "Processing ended: Tue May 11 21:58:48 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1620759528964 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:40 " "Elapsed time: 00:00:40" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1620759528964 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:50 " "Total CPU time (on all processors): 00:00:50" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1620759528964 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1620759528964 ""} diff --git a/FPGA_61.440/db/WOLF-LITE.hier_info b/FPGA_61.440/db/WOLF-LITE.hier_info deleted file mode 100644 index 7746816..0000000 --- a/FPGA_61.440/db/WOLF-LITE.hier_info +++ /dev/null @@ -1,1353 +0,0 @@ -|WOLF-LITE -PREAMP <= preamp_enable.DB_MAX_OUTPUT_PORT_TYPE -STM32_CLK => FLASH_data_out[0].CLK -STM32_CLK => FLASH_data_out[1].CLK -STM32_CLK => FLASH_data_out[2].CLK -STM32_CLK => FLASH_data_out[3].CLK -STM32_CLK => FLASH_data_out[4].CLK -STM32_CLK => FLASH_data_out[5].CLK -STM32_CLK => FLASH_data_out[6].CLK -STM32_CLK => FLASH_data_out[7].CLK -STM32_CLK => TX_Q[0].CLK -STM32_CLK => TX_Q[1].CLK -STM32_CLK => TX_Q[2].CLK -STM32_CLK => TX_Q[3].CLK -STM32_CLK => TX_Q[4].CLK -STM32_CLK => TX_Q[5].CLK -STM32_CLK => TX_Q[6].CLK -STM32_CLK => TX_Q[7].CLK -STM32_CLK => TX_Q[8].CLK -STM32_CLK => TX_Q[9].CLK -STM32_CLK => TX_Q[10].CLK -STM32_CLK => TX_Q[11].CLK -STM32_CLK => TX_Q[12].CLK -STM32_CLK => TX_Q[13].CLK -STM32_CLK => TX_Q[14].CLK -STM32_CLK => TX_Q[15].CLK -STM32_CLK => TX_I[0].CLK -STM32_CLK => TX_I[1].CLK -STM32_CLK => TX_I[2].CLK -STM32_CLK => TX_I[3].CLK -STM32_CLK => TX_I[4].CLK -STM32_CLK => TX_I[5].CLK -STM32_CLK => TX_I[6].CLK -STM32_CLK => TX_I[7].CLK -STM32_CLK => TX_I[8].CLK -STM32_CLK => TX_I[9].CLK -STM32_CLK => TX_I[10].CLK -STM32_CLK => TX_I[11].CLK -STM32_CLK => TX_I[12].CLK -STM32_CLK => TX_I[13].CLK -STM32_CLK => TX_I[14].CLK -STM32_CLK => TX_I[15].CLK -STM32_CLK => I_HOLD[0].CLK -STM32_CLK => I_HOLD[1].CLK -STM32_CLK => I_HOLD[2].CLK -STM32_CLK => I_HOLD[3].CLK -STM32_CLK => I_HOLD[4].CLK -STM32_CLK => I_HOLD[5].CLK -STM32_CLK => I_HOLD[6].CLK -STM32_CLK => I_HOLD[7].CLK -STM32_CLK => I_HOLD[8].CLK -STM32_CLK => I_HOLD[9].CLK -STM32_CLK => I_HOLD[10].CLK -STM32_CLK => I_HOLD[11].CLK -STM32_CLK => I_HOLD[12].CLK -STM32_CLK => I_HOLD[13].CLK -STM32_CLK => I_HOLD[14].CLK -STM32_CLK => I_HOLD[15].CLK -STM32_CLK => Q_HOLD[0].CLK -STM32_CLK => Q_HOLD[1].CLK -STM32_CLK => Q_HOLD[2].CLK -STM32_CLK => Q_HOLD[3].CLK -STM32_CLK => Q_HOLD[4].CLK -STM32_CLK => Q_HOLD[5].CLK -STM32_CLK => Q_HOLD[6].CLK -STM32_CLK => Q_HOLD[7].CLK -STM32_CLK => Q_HOLD[8].CLK -STM32_CLK => Q_HOLD[9].CLK -STM32_CLK => Q_HOLD[10].CLK -STM32_CLK => Q_HOLD[11].CLK -STM32_CLK => Q_HOLD[12].CLK -STM32_CLK => Q_HOLD[13].CLK -STM32_CLK => Q_HOLD[14].CLK -STM32_CLK => Q_HOLD[15].CLK -STM32_CLK => DATA_BUS_OUT[0].CLK -STM32_CLK => DATA_BUS_OUT[1].CLK -STM32_CLK => DATA_BUS_OUT[2].CLK -STM32_CLK => DATA_BUS_OUT[3].CLK -STM32_CLK => LPF_3.CLK -STM32_CLK => LPF_2.CLK -STM32_CLK => LPF_1.CLK -STM32_CLK => BPF_OE2.CLK -STM32_CLK => BPF_OE1.CLK -STM32_CLK => BPF_B.CLK -STM32_CLK => BPF_A.CLK -STM32_CLK => TX_NCO_freq[0].CLK -STM32_CLK => TX_NCO_freq[1].CLK -STM32_CLK => TX_NCO_freq[2].CLK -STM32_CLK => TX_NCO_freq[3].CLK -STM32_CLK => TX_NCO_freq[4].CLK -STM32_CLK => TX_NCO_freq[5].CLK -STM32_CLK => TX_NCO_freq[6].CLK -STM32_CLK => TX_NCO_freq[7].CLK -STM32_CLK => TX_NCO_freq[8].CLK -STM32_CLK => TX_NCO_freq[9].CLK -STM32_CLK => TX_NCO_freq[10].CLK -STM32_CLK => TX_NCO_freq[11].CLK -STM32_CLK => TX_NCO_freq[12].CLK -STM32_CLK => TX_NCO_freq[13].CLK -STM32_CLK => TX_NCO_freq[14].CLK -STM32_CLK => TX_NCO_freq[15].CLK -STM32_CLK => TX_NCO_freq[16].CLK -STM32_CLK => TX_NCO_freq[17].CLK -STM32_CLK => TX_NCO_freq[18].CLK -STM32_CLK => TX_NCO_freq[19].CLK -STM32_CLK => TX_NCO_freq[20].CLK -STM32_CLK => TX_NCO_freq[21].CLK -STM32_CLK => DAC_GAIN[0].CLK -STM32_CLK => DAC_GAIN[1].CLK -STM32_CLK => DAC_GAIN[2].CLK -STM32_CLK => DAC_GAIN[3].CLK -STM32_CLK => DAC_GAIN[4].CLK -STM32_CLK => DAC_GAIN[5].CLK -STM32_CLK => DAC_GAIN[6].CLK -STM32_CLK => DAC_GAIN[7].CLK -STM32_CLK => TX_CICFIR_GAIN[0].CLK -STM32_CLK => TX_CICFIR_GAIN[1].CLK -STM32_CLK => TX_CICFIR_GAIN[2].CLK -STM32_CLK => TX_CICFIR_GAIN[3].CLK -STM32_CLK => TX_CICFIR_GAIN[4].CLK -STM32_CLK => CICFIR_GAIN[0].CLK -STM32_CLK => CICFIR_GAIN[1].CLK -STM32_CLK => CICFIR_GAIN[2].CLK -STM32_CLK => CICFIR_GAIN[3].CLK -STM32_CLK => CICFIR_GAIN[4].CLK -STM32_CLK => CICFIR_GAIN[5].CLK -STM32_CLK => NCO_freq[0].CLK -STM32_CLK => NCO_freq[1].CLK -STM32_CLK => NCO_freq[2].CLK -STM32_CLK => NCO_freq[3].CLK -STM32_CLK => NCO_freq[4].CLK -STM32_CLK => NCO_freq[5].CLK -STM32_CLK => NCO_freq[6].CLK -STM32_CLK => NCO_freq[7].CLK -STM32_CLK => NCO_freq[8].CLK -STM32_CLK => NCO_freq[9].CLK -STM32_CLK => NCO_freq[10].CLK -STM32_CLK => NCO_freq[11].CLK -STM32_CLK => NCO_freq[12].CLK -STM32_CLK => NCO_freq[13].CLK -STM32_CLK => NCO_freq[14].CLK -STM32_CLK => NCO_freq[15].CLK -STM32_CLK => NCO_freq[16].CLK -STM32_CLK => NCO_freq[17].CLK -STM32_CLK => NCO_freq[18].CLK -STM32_CLK => NCO_freq[19].CLK -STM32_CLK => NCO_freq[20].CLK -STM32_CLK => NCO_freq[21].CLK -STM32_CLK => ATT_16.CLK -STM32_CLK => ATT_8.CLK -STM32_CLK => ATT_4.CLK -STM32_CLK => ATT_2.CLK -STM32_CLK => ATT_1.CLK -STM32_CLK => ATT_05.CLK -STM32_CLK => preamp_enable.CLK -STM32_CLK => tx.CLK -STM32_CLK => rx.CLK -STM32_CLK => FLASH_enable.CLK -STM32_CLK => sync_reset_n.CLK -STM32_CLK => tx_iq_valid.CLK -STM32_CLK => k[0].CLK -STM32_CLK => k[1].CLK -STM32_CLK => k[2].CLK -STM32_CLK => k[3].CLK -STM32_CLK => k[4].CLK -STM32_CLK => k[5].CLK -STM32_CLK => k[6].CLK -STM32_CLK => k[7].CLK -STM32_CLK => k[8].CLK -STM32_CLK => k[9].CLK -STM32_CLK => FLASH_continue_read.CLK -STM32_CLK => ADC_MINMAX_RESET.CLK -STM32_CLK => BUFFER_RX_tail[1].CLK -STM32_CLK => BUFFER_RX_tail[0].CLK -STM32_CLK => BUFFER_RX_tail[2].CLK -STM32_CLK => BUFFER_RX_tail[3].CLK -STM32_CLK => BUFFER_RX_tail[4].CLK -STM32_CLK => BUFFER_RX_tail[5].CLK -STM32_CLK => BUFFER_RX_tail[6].CLK -STM32_CLK => BUFFER_RX_tail[7].CLK -STM32_CLK => BUFFER_RX_tail[8].CLK -STM32_CLK => BUFFER_RX_tail[9].CLK -STM32_CLK => BUFFER_RX_tail[10].CLK -STM32_CLK => BUFFER_RX_tail[11].CLK -STM32_CLK => BUFFER_RX_tail[12].CLK -STM32_CLK => BUFFER_RX_tail[13].CLK -STM32_CLK => BUFFER_RX_tail[14].CLK -STM32_CLK => BUFFER_RX_tail[15].CLK -STM32_CLK => DATA_BUS_OUT[7].CLK -STM32_CLK => DATA_BUS_OE.CLK -STM32_CLK => DATA_BUS_OUT[6].CLK -STM32_CLK => DATA_BUS_OUT[5].CLK -STM32_CLK => DATA_BUS_OUT[4].CLK -STM32_SYNC => I_HOLD[9].IN0 -STM32_SYNC => preamp_enable.IN0 -STM32_SYNC => sync_reset_n.IN0 -STM32_SYNC => FLASH_continue_read.SCLR -STM32_SYNC => ADC_MINMAX_RESET.SCLR -STM32_SYNC => tx_iq_valid.OUTPUTSELECT -STM32_SYNC => k.OUTPUTSELECT -STM32_SYNC => k.OUTPUTSELECT -STM32_SYNC => k.OUTPUTSELECT -STM32_SYNC => k.OUTPUTSELECT -STM32_SYNC => k.OUTPUTSELECT -STM32_SYNC => k.OUTPUTSELECT -STM32_SYNC => k.OUTPUTSELECT -STM32_SYNC => k.OUTPUTSELECT -STM32_SYNC => k.OUTPUTSELECT -STM32_SYNC => k.OUTPUTSELECT -STM32_SYNC => FLASH_enable.OUTPUTSELECT -STM32_SYNC => FLASH_enable.DATAB -STM32_SYNC => tx_iq_valid.DATAB -STM32_SYNC => DATA_BUS_OE.SLOAD -ADC_OTR => DATA_BUS_OUT.IN0 -clk_sys => clkctrl1.INCLK -FLASH_MISO => data_out[7].DATAB -FLASH_MISO => data_out[6].DATAB -FLASH_MISO => data_out[5].DATAB -FLASH_MISO => data_out[4].DATAB -FLASH_MISO => data_out[3].DATAB -FLASH_MISO => data_out[2].DATAB -FLASH_MISO => data_out[1].DATAB -FLASH_MISO => data_out[0].DATAB -ADC_INPUT[11] => pipeline_dffe[11].DATAIN -ADC_INPUT[10] => pipeline_dffe[10].DATAIN -ADC_INPUT[9] => pipeline_dffe[9].DATAIN -ADC_INPUT[8] => pipeline_dffe[8].DATAIN -ADC_INPUT[7] => pipeline_dffe[7].DATAIN -ADC_INPUT[6] => pipeline_dffe[6].DATAIN -ADC_INPUT[5] => pipeline_dffe[5].DATAIN -ADC_INPUT[4] => pipeline_dffe[4].DATAIN -ADC_INPUT[3] => pipeline_dffe[3].DATAIN -ADC_INPUT[2] => pipeline_dffe[2].DATAIN -ADC_INPUT[1] => pipeline_dffe[1].DATAIN -ADC_INPUT[0] => pipeline_dffe[0].DATAIN -STM32_DATA_BUS[7] <> DATA_BUS[7] -STM32_DATA_BUS[6] <> DATA_BUS[6] -STM32_DATA_BUS[5] <> DATA_BUS[5] -STM32_DATA_BUS[4] <> DATA_BUS[4] -STM32_DATA_BUS[3] <> DATA_BUS[3] -STM32_DATA_BUS[2] <> DATA_BUS[2] -STM32_DATA_BUS[1] <> DATA_BUS[1] -STM32_DATA_BUS[0] <> DATA_BUS[0] -AUDIO_I2S_CLOCK <= pll1.CLK -AUDIO_48K_CLOCK <= pll1.CLK1 -FLASH_C <= SCK_C.DB_MAX_OUTPUT_PORT_TYPE -FLASH_S <= CS_S.DB_MAX_OUTPUT_PORT_TYPE -FLASH_MOSI <= MOSI_DQ0.DB_MAX_OUTPUT_PORT_TYPE -DAC_PD <= tx.DB_MAX_OUTPUT_PORT_TYPE -DAC_CLK <= pll1.CLK -ATT_05 <= ATT_05.DB_MAX_OUTPUT_PORT_TYPE -ATT_1 <= ATT_1.DB_MAX_OUTPUT_PORT_TYPE -ATT_2 <= ATT_2.DB_MAX_OUTPUT_PORT_TYPE -ATT_4 <= ATT_4.DB_MAX_OUTPUT_PORT_TYPE -ATT_8 <= ATT_8.DB_MAX_OUTPUT_PORT_TYPE -ATT_16 <= ATT_16.DB_MAX_OUTPUT_PORT_TYPE -BPF_A <= BPF_A.DB_MAX_OUTPUT_PORT_TYPE -BPF_B <= BPF_B.DB_MAX_OUTPUT_PORT_TYPE -BPF_OE1 <= BPF_OE1.DB_MAX_OUTPUT_PORT_TYPE -BPF_OE2 <= BPF_OE2.DB_MAX_OUTPUT_PORT_TYPE -LPF_1 <= LPF_1.DB_MAX_OUTPUT_PORT_TYPE -LPF_2 <= LPF_2.DB_MAX_OUTPUT_PORT_TYPE -LPF_3 <= LPF_3.DB_MAX_OUTPUT_PORT_TYPE -TXRX_OUT <= tx.DB_MAX_OUTPUT_PORT_TYPE -DAC_OUTPUT[13] <= result_node[13].DB_MAX_OUTPUT_PORT_TYPE -DAC_OUTPUT[12] <= result_node[12].DB_MAX_OUTPUT_PORT_TYPE -DAC_OUTPUT[11] <= result_node[11].DB_MAX_OUTPUT_PORT_TYPE -DAC_OUTPUT[10] <= result_node[10].DB_MAX_OUTPUT_PORT_TYPE -DAC_OUTPUT[9] <= result_node[9].DB_MAX_OUTPUT_PORT_TYPE -DAC_OUTPUT[8] <= result_node[8].DB_MAX_OUTPUT_PORT_TYPE -DAC_OUTPUT[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE -DAC_OUTPUT[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE -DAC_OUTPUT[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE -DAC_OUTPUT[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE -DAC_OUTPUT[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE -DAC_OUTPUT[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE -DAC_OUTPUT[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE -DAC_OUTPUT[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => hold_reg[0].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => bypass_reg.CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => shift_reg[0].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => shift_reg[1].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => shift_reg[2].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => shift_reg[3].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => shift_reg[4].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => shift_reg[5].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => shift_reg[6].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => shift_reg[7].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => shift_reg[8].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => shift_reg[9].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => shift_reg[10].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => shift_reg[11].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => WORD_SR[0].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => WORD_SR[1].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => WORD_SR[2].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => WORD_SR[3].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => word_counter[0].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => word_counter[1].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => word_counter[2].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_raw_tck => word_counter[3].CLK -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_tdi => bypass_reg.DATAIN -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_tdi => shift_reg.IN1 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_tdi => WORD_SR.DATAB -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_usr1 => dr_scan.IN0 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_usr1 => vjtag_uir_i.IN0 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_cdr => instance_id_gen.IN0 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_cdr => shift_reg.IN1 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_sdr => vjtag_sdr_i.IN1 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_sdr => instance_id_gen.IN1 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_e1dr => hold_reg[0].IN1 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_udr => vjtag_uir_i.IN1 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_cir => ~NO_FANOUT~ -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_uir => ~NO_FANOUT~ -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_tlr => bypass_reg.ACLR -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_tlr => shift_reg[0].ACLR -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_tlr => shift_reg[1].ACLR -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_tlr => shift_reg[2].ACLR -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_tlr => shift_reg[3].ACLR -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_tlr => shift_reg[4].ACLR -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_tlr => shift_reg[5].ACLR -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_tlr => shift_reg[6].ACLR -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_tlr => shift_reg[7].ACLR -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_tlr => shift_reg[8].ACLR -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_tlr => shift_reg[9].ACLR -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_tlr => shift_reg[10].ACLR -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_tlr => shift_reg[11].ACLR -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_jtag_state_tlr => hold_reg[0].IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_clr => ~NO_FANOUT~ -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ena => dr_scan.IN1 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ena => vjtag_uir_i.IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_0_ => tdo.OUTPUTSELECT -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_1_ => process_1.IN0 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_1_ => shift_reg.IN0 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_1_ => shift_reg.IN1 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_1_ => shift_reg.IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_1_ => shift_reg.IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_1_ => shift_reg.IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_1_ => shift_reg.IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_1_ => shift_reg.IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_1_ => shift_reg.IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_1_ => shift_reg.IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_1_ => shift_reg.IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_1_ => shift_reg.IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_1_ => shift_reg.IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_1_ => shift_reg.IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => process_1.IN1 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => shift_reg.IN1 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => shift_reg.IN1 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => shift_reg.IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => shift_reg.IN3 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => shift_reg.IN3 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => shift_reg.IN3 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => shift_reg.IN3 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => shift_reg.IN3 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => shift_reg.IN3 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => shift_reg.IN3 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => shift_reg.IN3 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => shift_reg.IN3 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => shift_reg.IN3 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_2_ => shift_reg.IN3 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_3_ => process_1.IN2 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_in_3_ => hold_reg[0].IN3 -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_out_0_ <= -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_out_1_ <= -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_out_2_ <= -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_ir_out_3_ <= -jtag.bp.DBG_ADC_in_system_sources_probes_0_issp_impl_tdo <= tdo.DB_MAX_OUTPUT_PORT_TYPE - - -|WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult1 -dataa[0] => mult_36t:auto_generated.dataa[0] -dataa[1] => mult_36t:auto_generated.dataa[1] -dataa[2] => mult_36t:auto_generated.dataa[2] -dataa[3] => mult_36t:auto_generated.dataa[3] -dataa[4] => mult_36t:auto_generated.dataa[4] -dataa[5] => mult_36t:auto_generated.dataa[5] -dataa[6] => mult_36t:auto_generated.dataa[6] -dataa[7] => mult_36t:auto_generated.dataa[7] -dataa[8] => mult_36t:auto_generated.dataa[8] -dataa[9] => mult_36t:auto_generated.dataa[9] -dataa[10] => mult_36t:auto_generated.dataa[10] -dataa[11] => mult_36t:auto_generated.dataa[11] -dataa[12] => mult_36t:auto_generated.dataa[12] -dataa[13] => mult_36t:auto_generated.dataa[13] -dataa[14] => mult_36t:auto_generated.dataa[14] -dataa[15] => mult_36t:auto_generated.dataa[15] -datab[0] => mult_36t:auto_generated.datab[0] -datab[1] => mult_36t:auto_generated.datab[1] -datab[2] => mult_36t:auto_generated.datab[2] -datab[3] => mult_36t:auto_generated.datab[3] -datab[4] => mult_36t:auto_generated.datab[4] -datab[5] => mult_36t:auto_generated.datab[5] -datab[6] => mult_36t:auto_generated.datab[6] -datab[7] => mult_36t:auto_generated.datab[7] -datab[8] => mult_36t:auto_generated.datab[8] -datab[9] => mult_36t:auto_generated.datab[9] -datab[10] => mult_36t:auto_generated.datab[10] -datab[11] => mult_36t:auto_generated.datab[11] -datab[12] => mult_36t:auto_generated.datab[12] -datab[13] => mult_36t:auto_generated.datab[13] -datab[14] => mult_36t:auto_generated.datab[14] -datab[15] => mult_36t:auto_generated.datab[15] -sum[0] => ~NO_FANOUT~ -aclr => ~NO_FANOUT~ -sclr => ~NO_FANOUT~ -clock => ~NO_FANOUT~ -clken => ~NO_FANOUT~ -result[0] <= mult_36t:auto_generated.result[0] -result[1] <= mult_36t:auto_generated.result[1] -result[2] <= mult_36t:auto_generated.result[2] -result[3] <= mult_36t:auto_generated.result[3] -result[4] <= mult_36t:auto_generated.result[4] -result[5] <= mult_36t:auto_generated.result[5] -result[6] <= mult_36t:auto_generated.result[6] -result[7] <= mult_36t:auto_generated.result[7] -result[8] <= mult_36t:auto_generated.result[8] -result[9] <= mult_36t:auto_generated.result[9] -result[10] <= mult_36t:auto_generated.result[10] -result[11] <= mult_36t:auto_generated.result[11] -result[12] <= mult_36t:auto_generated.result[12] -result[13] <= mult_36t:auto_generated.result[13] -result[14] <= mult_36t:auto_generated.result[14] -result[15] <= mult_36t:auto_generated.result[15] -result[16] <= mult_36t:auto_generated.result[16] -result[17] <= mult_36t:auto_generated.result[17] -result[18] <= mult_36t:auto_generated.result[18] -result[19] <= mult_36t:auto_generated.result[19] -result[20] <= mult_36t:auto_generated.result[20] -result[21] <= mult_36t:auto_generated.result[21] -result[22] <= mult_36t:auto_generated.result[22] -result[23] <= mult_36t:auto_generated.result[23] -result[24] <= mult_36t:auto_generated.result[24] -result[25] <= mult_36t:auto_generated.result[25] -result[26] <= mult_36t:auto_generated.result[26] -result[27] <= mult_36t:auto_generated.result[27] -result[28] <= mult_36t:auto_generated.result[28] -result[29] <= mult_36t:auto_generated.result[29] -result[30] <= mult_36t:auto_generated.result[30] -result[31] <= mult_36t:auto_generated.result[31] - - -|WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult1|mult_36t:auto_generated -dataa[0] => mac_mult1.DATAA -dataa[1] => mac_mult1.DATAA1 -dataa[2] => mac_mult1.DATAA2 -dataa[3] => mac_mult1.DATAA3 -dataa[4] => mac_mult1.DATAA4 -dataa[5] => mac_mult1.DATAA5 -dataa[6] => mac_mult1.DATAA6 -dataa[7] => mac_mult1.DATAA7 -dataa[8] => mac_mult1.DATAA8 -dataa[9] => mac_mult1.DATAA9 -dataa[10] => mac_mult1.DATAA10 -dataa[11] => mac_mult1.DATAA11 -dataa[12] => mac_mult1.DATAA12 -dataa[13] => mac_mult1.DATAA13 -dataa[14] => mac_mult1.DATAA14 -dataa[15] => mac_mult1.DATAA15 -datab[0] => mac_mult1.DATAB -datab[1] => mac_mult1.DATAB1 -datab[2] => mac_mult1.DATAB2 -datab[3] => mac_mult1.DATAB3 -datab[4] => mac_mult1.DATAB4 -datab[5] => mac_mult1.DATAB5 -datab[6] => mac_mult1.DATAB6 -datab[7] => mac_mult1.DATAB7 -datab[8] => mac_mult1.DATAB8 -datab[9] => mac_mult1.DATAB9 -datab[10] => mac_mult1.DATAB10 -datab[11] => mac_mult1.DATAB11 -datab[12] => mac_mult1.DATAB12 -datab[13] => mac_mult1.DATAB13 -datab[14] => mac_mult1.DATAB14 -datab[15] => mac_mult1.DATAB15 -result[0] <= mac_out2.DATAOUT -result[1] <= mac_out2.DATAOUT1 -result[2] <= mac_out2.DATAOUT2 -result[3] <= mac_out2.DATAOUT3 -result[4] <= mac_out2.DATAOUT4 -result[5] <= mac_out2.DATAOUT5 -result[6] <= mac_out2.DATAOUT6 -result[7] <= mac_out2.DATAOUT7 -result[8] <= mac_out2.DATAOUT8 -result[9] <= mac_out2.DATAOUT9 -result[10] <= mac_out2.DATAOUT10 -result[11] <= mac_out2.DATAOUT11 -result[12] <= mac_out2.DATAOUT12 -result[13] <= mac_out2.DATAOUT13 -result[14] <= mac_out2.DATAOUT14 -result[15] <= mac_out2.DATAOUT15 -result[16] <= mac_out2.DATAOUT16 -result[17] <= mac_out2.DATAOUT17 -result[18] <= mac_out2.DATAOUT18 -result[19] <= mac_out2.DATAOUT19 -result[20] <= mac_out2.DATAOUT20 -result[21] <= mac_out2.DATAOUT21 -result[22] <= mac_out2.DATAOUT22 -result[23] <= mac_out2.DATAOUT23 -result[24] <= mac_out2.DATAOUT24 -result[25] <= mac_out2.DATAOUT25 -result[26] <= mac_out2.DATAOUT26 -result[27] <= mac_out2.DATAOUT27 -result[28] <= mac_out2.DATAOUT28 -result[29] <= mac_out2.DATAOUT29 -result[30] <= mac_out2.DATAOUT30 -result[31] <= mac_out2.DATAOUT31 - - -|WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult0 -dataa[0] => mult_36t:auto_generated.dataa[0] -dataa[1] => mult_36t:auto_generated.dataa[1] -dataa[2] => mult_36t:auto_generated.dataa[2] -dataa[3] => mult_36t:auto_generated.dataa[3] -dataa[4] => mult_36t:auto_generated.dataa[4] -dataa[5] => mult_36t:auto_generated.dataa[5] -dataa[6] => mult_36t:auto_generated.dataa[6] -dataa[7] => mult_36t:auto_generated.dataa[7] -dataa[8] => mult_36t:auto_generated.dataa[8] -dataa[9] => mult_36t:auto_generated.dataa[9] -dataa[10] => mult_36t:auto_generated.dataa[10] -dataa[11] => mult_36t:auto_generated.dataa[11] -dataa[12] => mult_36t:auto_generated.dataa[12] -dataa[13] => mult_36t:auto_generated.dataa[13] -dataa[14] => mult_36t:auto_generated.dataa[14] -dataa[15] => mult_36t:auto_generated.dataa[15] -datab[0] => mult_36t:auto_generated.datab[0] -datab[1] => mult_36t:auto_generated.datab[1] -datab[2] => mult_36t:auto_generated.datab[2] -datab[3] => mult_36t:auto_generated.datab[3] -datab[4] => mult_36t:auto_generated.datab[4] -datab[5] => mult_36t:auto_generated.datab[5] -datab[6] => mult_36t:auto_generated.datab[6] -datab[7] => mult_36t:auto_generated.datab[7] -datab[8] => mult_36t:auto_generated.datab[8] -datab[9] => mult_36t:auto_generated.datab[9] -datab[10] => mult_36t:auto_generated.datab[10] -datab[11] => mult_36t:auto_generated.datab[11] -datab[12] => mult_36t:auto_generated.datab[12] -datab[13] => mult_36t:auto_generated.datab[13] -datab[14] => mult_36t:auto_generated.datab[14] -datab[15] => mult_36t:auto_generated.datab[15] -sum[0] => ~NO_FANOUT~ -aclr => ~NO_FANOUT~ -sclr => ~NO_FANOUT~ -clock => ~NO_FANOUT~ -clken => ~NO_FANOUT~ -result[0] <= mult_36t:auto_generated.result[0] -result[1] <= mult_36t:auto_generated.result[1] -result[2] <= mult_36t:auto_generated.result[2] -result[3] <= mult_36t:auto_generated.result[3] -result[4] <= mult_36t:auto_generated.result[4] -result[5] <= mult_36t:auto_generated.result[5] -result[6] <= mult_36t:auto_generated.result[6] -result[7] <= mult_36t:auto_generated.result[7] -result[8] <= mult_36t:auto_generated.result[8] -result[9] <= mult_36t:auto_generated.result[9] -result[10] <= mult_36t:auto_generated.result[10] -result[11] <= mult_36t:auto_generated.result[11] -result[12] <= mult_36t:auto_generated.result[12] -result[13] <= mult_36t:auto_generated.result[13] -result[14] <= mult_36t:auto_generated.result[14] -result[15] <= mult_36t:auto_generated.result[15] -result[16] <= mult_36t:auto_generated.result[16] -result[17] <= mult_36t:auto_generated.result[17] -result[18] <= mult_36t:auto_generated.result[18] -result[19] <= mult_36t:auto_generated.result[19] -result[20] <= mult_36t:auto_generated.result[20] -result[21] <= mult_36t:auto_generated.result[21] -result[22] <= mult_36t:auto_generated.result[22] -result[23] <= mult_36t:auto_generated.result[23] -result[24] <= mult_36t:auto_generated.result[24] -result[25] <= mult_36t:auto_generated.result[25] -result[26] <= mult_36t:auto_generated.result[26] -result[27] <= mult_36t:auto_generated.result[27] -result[28] <= mult_36t:auto_generated.result[28] -result[29] <= mult_36t:auto_generated.result[29] -result[30] <= mult_36t:auto_generated.result[30] -result[31] <= mult_36t:auto_generated.result[31] - - -|WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult0|mult_36t:auto_generated -dataa[0] => mac_mult1.DATAA -dataa[1] => mac_mult1.DATAA1 -dataa[2] => mac_mult1.DATAA2 -dataa[3] => mac_mult1.DATAA3 -dataa[4] => mac_mult1.DATAA4 -dataa[5] => mac_mult1.DATAA5 -dataa[6] => mac_mult1.DATAA6 -dataa[7] => mac_mult1.DATAA7 -dataa[8] => mac_mult1.DATAA8 -dataa[9] => mac_mult1.DATAA9 -dataa[10] => mac_mult1.DATAA10 -dataa[11] => mac_mult1.DATAA11 -dataa[12] => mac_mult1.DATAA12 -dataa[13] => mac_mult1.DATAA13 -dataa[14] => mac_mult1.DATAA14 -dataa[15] => mac_mult1.DATAA15 -datab[0] => mac_mult1.DATAB -datab[1] => mac_mult1.DATAB1 -datab[2] => mac_mult1.DATAB2 -datab[3] => mac_mult1.DATAB3 -datab[4] => mac_mult1.DATAB4 -datab[5] => mac_mult1.DATAB5 -datab[6] => mac_mult1.DATAB6 -datab[7] => mac_mult1.DATAB7 -datab[8] => mac_mult1.DATAB8 -datab[9] => mac_mult1.DATAB9 -datab[10] => mac_mult1.DATAB10 -datab[11] => mac_mult1.DATAB11 -datab[12] => mac_mult1.DATAB12 -datab[13] => mac_mult1.DATAB13 -datab[14] => mac_mult1.DATAB14 -datab[15] => mac_mult1.DATAB15 -result[0] <= mac_out2.DATAOUT -result[1] <= mac_out2.DATAOUT1 -result[2] <= mac_out2.DATAOUT2 -result[3] <= mac_out2.DATAOUT3 -result[4] <= mac_out2.DATAOUT4 -result[5] <= mac_out2.DATAOUT5 -result[6] <= mac_out2.DATAOUT6 -result[7] <= mac_out2.DATAOUT7 -result[8] <= mac_out2.DATAOUT8 -result[9] <= mac_out2.DATAOUT9 -result[10] <= mac_out2.DATAOUT10 -result[11] <= mac_out2.DATAOUT11 -result[12] <= mac_out2.DATAOUT12 -result[13] <= mac_out2.DATAOUT13 -result[14] <= mac_out2.DATAOUT14 -result[15] <= mac_out2.DATAOUT15 -result[16] <= mac_out2.DATAOUT16 -result[17] <= mac_out2.DATAOUT17 -result[18] <= mac_out2.DATAOUT18 -result[19] <= mac_out2.DATAOUT19 -result[20] <= mac_out2.DATAOUT20 -result[21] <= mac_out2.DATAOUT21 -result[22] <= mac_out2.DATAOUT22 -result[23] <= mac_out2.DATAOUT23 -result[24] <= mac_out2.DATAOUT24 -result[25] <= mac_out2.DATAOUT25 -result[26] <= mac_out2.DATAOUT26 -result[27] <= mac_out2.DATAOUT27 -result[28] <= mac_out2.DATAOUT28 -result[29] <= mac_out2.DATAOUT29 -result[30] <= mac_out2.DATAOUT30 -result[31] <= mac_out2.DATAOUT31 - - -|WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult1 -dataa[0] => mult_36t:auto_generated.dataa[0] -dataa[1] => mult_36t:auto_generated.dataa[1] -dataa[2] => mult_36t:auto_generated.dataa[2] -dataa[3] => mult_36t:auto_generated.dataa[3] -dataa[4] => mult_36t:auto_generated.dataa[4] -dataa[5] => mult_36t:auto_generated.dataa[5] -dataa[6] => mult_36t:auto_generated.dataa[6] -dataa[7] => mult_36t:auto_generated.dataa[7] -dataa[8] => mult_36t:auto_generated.dataa[8] -dataa[9] => mult_36t:auto_generated.dataa[9] -dataa[10] => mult_36t:auto_generated.dataa[10] -dataa[11] => mult_36t:auto_generated.dataa[11] -dataa[12] => mult_36t:auto_generated.dataa[12] -dataa[13] => mult_36t:auto_generated.dataa[13] -dataa[14] => mult_36t:auto_generated.dataa[14] -dataa[15] => mult_36t:auto_generated.dataa[15] -datab[0] => mult_36t:auto_generated.datab[0] -datab[1] => mult_36t:auto_generated.datab[1] -datab[2] => mult_36t:auto_generated.datab[2] -datab[3] => mult_36t:auto_generated.datab[3] -datab[4] => mult_36t:auto_generated.datab[4] -datab[5] => mult_36t:auto_generated.datab[5] -datab[6] => mult_36t:auto_generated.datab[6] -datab[7] => mult_36t:auto_generated.datab[7] -datab[8] => mult_36t:auto_generated.datab[8] -datab[9] => mult_36t:auto_generated.datab[9] -datab[10] => mult_36t:auto_generated.datab[10] -datab[11] => mult_36t:auto_generated.datab[11] -datab[12] => mult_36t:auto_generated.datab[12] -datab[13] => mult_36t:auto_generated.datab[13] -datab[14] => mult_36t:auto_generated.datab[14] -datab[15] => mult_36t:auto_generated.datab[15] -sum[0] => ~NO_FANOUT~ -aclr => ~NO_FANOUT~ -sclr => ~NO_FANOUT~ -clock => ~NO_FANOUT~ -clken => ~NO_FANOUT~ -result[0] <= mult_36t:auto_generated.result[0] -result[1] <= mult_36t:auto_generated.result[1] -result[2] <= mult_36t:auto_generated.result[2] -result[3] <= mult_36t:auto_generated.result[3] -result[4] <= mult_36t:auto_generated.result[4] -result[5] <= mult_36t:auto_generated.result[5] -result[6] <= mult_36t:auto_generated.result[6] -result[7] <= mult_36t:auto_generated.result[7] -result[8] <= mult_36t:auto_generated.result[8] -result[9] <= mult_36t:auto_generated.result[9] -result[10] <= mult_36t:auto_generated.result[10] -result[11] <= mult_36t:auto_generated.result[11] -result[12] <= mult_36t:auto_generated.result[12] -result[13] <= mult_36t:auto_generated.result[13] -result[14] <= mult_36t:auto_generated.result[14] -result[15] <= mult_36t:auto_generated.result[15] -result[16] <= mult_36t:auto_generated.result[16] -result[17] <= mult_36t:auto_generated.result[17] -result[18] <= mult_36t:auto_generated.result[18] -result[19] <= mult_36t:auto_generated.result[19] -result[20] <= mult_36t:auto_generated.result[20] -result[21] <= mult_36t:auto_generated.result[21] -result[22] <= mult_36t:auto_generated.result[22] -result[23] <= mult_36t:auto_generated.result[23] -result[24] <= mult_36t:auto_generated.result[24] -result[25] <= mult_36t:auto_generated.result[25] -result[26] <= mult_36t:auto_generated.result[26] -result[27] <= mult_36t:auto_generated.result[27] -result[28] <= mult_36t:auto_generated.result[28] -result[29] <= mult_36t:auto_generated.result[29] -result[30] <= mult_36t:auto_generated.result[30] -result[31] <= mult_36t:auto_generated.result[31] - - -|WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult1|mult_36t:auto_generated -dataa[0] => mac_mult1.DATAA -dataa[1] => mac_mult1.DATAA1 -dataa[2] => mac_mult1.DATAA2 -dataa[3] => mac_mult1.DATAA3 -dataa[4] => mac_mult1.DATAA4 -dataa[5] => mac_mult1.DATAA5 -dataa[6] => mac_mult1.DATAA6 -dataa[7] => mac_mult1.DATAA7 -dataa[8] => mac_mult1.DATAA8 -dataa[9] => mac_mult1.DATAA9 -dataa[10] => mac_mult1.DATAA10 -dataa[11] => mac_mult1.DATAA11 -dataa[12] => mac_mult1.DATAA12 -dataa[13] => mac_mult1.DATAA13 -dataa[14] => mac_mult1.DATAA14 -dataa[15] => mac_mult1.DATAA15 -datab[0] => mac_mult1.DATAB -datab[1] => mac_mult1.DATAB1 -datab[2] => mac_mult1.DATAB2 -datab[3] => mac_mult1.DATAB3 -datab[4] => mac_mult1.DATAB4 -datab[5] => mac_mult1.DATAB5 -datab[6] => mac_mult1.DATAB6 -datab[7] => mac_mult1.DATAB7 -datab[8] => mac_mult1.DATAB8 -datab[9] => mac_mult1.DATAB9 -datab[10] => mac_mult1.DATAB10 -datab[11] => mac_mult1.DATAB11 -datab[12] => mac_mult1.DATAB12 -datab[13] => mac_mult1.DATAB13 -datab[14] => mac_mult1.DATAB14 -datab[15] => mac_mult1.DATAB15 -result[0] <= mac_out2.DATAOUT -result[1] <= mac_out2.DATAOUT1 -result[2] <= mac_out2.DATAOUT2 -result[3] <= mac_out2.DATAOUT3 -result[4] <= mac_out2.DATAOUT4 -result[5] <= mac_out2.DATAOUT5 -result[6] <= mac_out2.DATAOUT6 -result[7] <= mac_out2.DATAOUT7 -result[8] <= mac_out2.DATAOUT8 -result[9] <= mac_out2.DATAOUT9 -result[10] <= mac_out2.DATAOUT10 -result[11] <= mac_out2.DATAOUT11 -result[12] <= mac_out2.DATAOUT12 -result[13] <= mac_out2.DATAOUT13 -result[14] <= mac_out2.DATAOUT14 -result[15] <= mac_out2.DATAOUT15 -result[16] <= mac_out2.DATAOUT16 -result[17] <= mac_out2.DATAOUT17 -result[18] <= mac_out2.DATAOUT18 -result[19] <= mac_out2.DATAOUT19 -result[20] <= mac_out2.DATAOUT20 -result[21] <= mac_out2.DATAOUT21 -result[22] <= mac_out2.DATAOUT22 -result[23] <= mac_out2.DATAOUT23 -result[24] <= mac_out2.DATAOUT24 -result[25] <= mac_out2.DATAOUT25 -result[26] <= mac_out2.DATAOUT26 -result[27] <= mac_out2.DATAOUT27 -result[28] <= mac_out2.DATAOUT28 -result[29] <= mac_out2.DATAOUT29 -result[30] <= mac_out2.DATAOUT30 -result[31] <= mac_out2.DATAOUT31 - - -|WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult0 -dataa[0] => mult_36t:auto_generated.dataa[0] -dataa[1] => mult_36t:auto_generated.dataa[1] -dataa[2] => mult_36t:auto_generated.dataa[2] -dataa[3] => mult_36t:auto_generated.dataa[3] -dataa[4] => mult_36t:auto_generated.dataa[4] -dataa[5] => mult_36t:auto_generated.dataa[5] -dataa[6] => mult_36t:auto_generated.dataa[6] -dataa[7] => mult_36t:auto_generated.dataa[7] -dataa[8] => mult_36t:auto_generated.dataa[8] -dataa[9] => mult_36t:auto_generated.dataa[9] -dataa[10] => mult_36t:auto_generated.dataa[10] -dataa[11] => mult_36t:auto_generated.dataa[11] -dataa[12] => mult_36t:auto_generated.dataa[12] -dataa[13] => mult_36t:auto_generated.dataa[13] -dataa[14] => mult_36t:auto_generated.dataa[14] -dataa[15] => mult_36t:auto_generated.dataa[15] -datab[0] => mult_36t:auto_generated.datab[0] -datab[1] => mult_36t:auto_generated.datab[1] -datab[2] => mult_36t:auto_generated.datab[2] -datab[3] => mult_36t:auto_generated.datab[3] -datab[4] => mult_36t:auto_generated.datab[4] -datab[5] => mult_36t:auto_generated.datab[5] -datab[6] => mult_36t:auto_generated.datab[6] -datab[7] => mult_36t:auto_generated.datab[7] -datab[8] => mult_36t:auto_generated.datab[8] -datab[9] => mult_36t:auto_generated.datab[9] -datab[10] => mult_36t:auto_generated.datab[10] -datab[11] => mult_36t:auto_generated.datab[11] -datab[12] => mult_36t:auto_generated.datab[12] -datab[13] => mult_36t:auto_generated.datab[13] -datab[14] => mult_36t:auto_generated.datab[14] -datab[15] => mult_36t:auto_generated.datab[15] -sum[0] => ~NO_FANOUT~ -aclr => ~NO_FANOUT~ -sclr => ~NO_FANOUT~ -clock => ~NO_FANOUT~ -clken => ~NO_FANOUT~ -result[0] <= mult_36t:auto_generated.result[0] -result[1] <= mult_36t:auto_generated.result[1] -result[2] <= mult_36t:auto_generated.result[2] -result[3] <= mult_36t:auto_generated.result[3] -result[4] <= mult_36t:auto_generated.result[4] -result[5] <= mult_36t:auto_generated.result[5] -result[6] <= mult_36t:auto_generated.result[6] -result[7] <= mult_36t:auto_generated.result[7] -result[8] <= mult_36t:auto_generated.result[8] -result[9] <= mult_36t:auto_generated.result[9] -result[10] <= mult_36t:auto_generated.result[10] -result[11] <= mult_36t:auto_generated.result[11] -result[12] <= mult_36t:auto_generated.result[12] -result[13] <= mult_36t:auto_generated.result[13] -result[14] <= mult_36t:auto_generated.result[14] -result[15] <= mult_36t:auto_generated.result[15] -result[16] <= mult_36t:auto_generated.result[16] -result[17] <= mult_36t:auto_generated.result[17] -result[18] <= mult_36t:auto_generated.result[18] -result[19] <= mult_36t:auto_generated.result[19] -result[20] <= mult_36t:auto_generated.result[20] -result[21] <= mult_36t:auto_generated.result[21] -result[22] <= mult_36t:auto_generated.result[22] -result[23] <= mult_36t:auto_generated.result[23] -result[24] <= mult_36t:auto_generated.result[24] -result[25] <= mult_36t:auto_generated.result[25] -result[26] <= mult_36t:auto_generated.result[26] -result[27] <= mult_36t:auto_generated.result[27] -result[28] <= mult_36t:auto_generated.result[28] -result[29] <= mult_36t:auto_generated.result[29] -result[30] <= mult_36t:auto_generated.result[30] -result[31] <= mult_36t:auto_generated.result[31] - - -|WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult0|mult_36t:auto_generated -dataa[0] => mac_mult1.DATAA -dataa[1] => mac_mult1.DATAA1 -dataa[2] => mac_mult1.DATAA2 -dataa[3] => mac_mult1.DATAA3 -dataa[4] => mac_mult1.DATAA4 -dataa[5] => mac_mult1.DATAA5 -dataa[6] => mac_mult1.DATAA6 -dataa[7] => mac_mult1.DATAA7 -dataa[8] => mac_mult1.DATAA8 -dataa[9] => mac_mult1.DATAA9 -dataa[10] => mac_mult1.DATAA10 -dataa[11] => mac_mult1.DATAA11 -dataa[12] => mac_mult1.DATAA12 -dataa[13] => mac_mult1.DATAA13 -dataa[14] => mac_mult1.DATAA14 -dataa[15] => mac_mult1.DATAA15 -datab[0] => mac_mult1.DATAB -datab[1] => mac_mult1.DATAB1 -datab[2] => mac_mult1.DATAB2 -datab[3] => mac_mult1.DATAB3 -datab[4] => mac_mult1.DATAB4 -datab[5] => mac_mult1.DATAB5 -datab[6] => mac_mult1.DATAB6 -datab[7] => mac_mult1.DATAB7 -datab[8] => mac_mult1.DATAB8 -datab[9] => mac_mult1.DATAB9 -datab[10] => mac_mult1.DATAB10 -datab[11] => mac_mult1.DATAB11 -datab[12] => mac_mult1.DATAB12 -datab[13] => mac_mult1.DATAB13 -datab[14] => mac_mult1.DATAB14 -datab[15] => mac_mult1.DATAB15 -result[0] <= mac_out2.DATAOUT -result[1] <= mac_out2.DATAOUT1 -result[2] <= mac_out2.DATAOUT2 -result[3] <= mac_out2.DATAOUT3 -result[4] <= mac_out2.DATAOUT4 -result[5] <= mac_out2.DATAOUT5 -result[6] <= mac_out2.DATAOUT6 -result[7] <= mac_out2.DATAOUT7 -result[8] <= mac_out2.DATAOUT8 -result[9] <= mac_out2.DATAOUT9 -result[10] <= mac_out2.DATAOUT10 -result[11] <= mac_out2.DATAOUT11 -result[12] <= mac_out2.DATAOUT12 -result[13] <= mac_out2.DATAOUT13 -result[14] <= mac_out2.DATAOUT14 -result[15] <= mac_out2.DATAOUT15 -result[16] <= mac_out2.DATAOUT16 -result[17] <= mac_out2.DATAOUT17 -result[18] <= mac_out2.DATAOUT18 -result[19] <= mac_out2.DATAOUT19 -result[20] <= mac_out2.DATAOUT20 -result[21] <= mac_out2.DATAOUT21 -result[22] <= mac_out2.DATAOUT22 -result[23] <= mac_out2.DATAOUT23 -result[24] <= mac_out2.DATAOUT24 -result[25] <= mac_out2.DATAOUT25 -result[26] <= mac_out2.DATAOUT26 -result[27] <= mac_out2.DATAOUT27 -result[28] <= mac_out2.DATAOUT28 -result[29] <= mac_out2.DATAOUT29 -result[30] <= mac_out2.DATAOUT30 -result[31] <= mac_out2.DATAOUT31 - - -|WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult1 -dataa[0] => mult_t5t:auto_generated.dataa[0] -dataa[1] => mult_t5t:auto_generated.dataa[1] -dataa[2] => mult_t5t:auto_generated.dataa[2] -dataa[3] => mult_t5t:auto_generated.dataa[3] -dataa[4] => mult_t5t:auto_generated.dataa[4] -dataa[5] => mult_t5t:auto_generated.dataa[5] -dataa[6] => mult_t5t:auto_generated.dataa[6] -dataa[7] => mult_t5t:auto_generated.dataa[7] -dataa[8] => mult_t5t:auto_generated.dataa[8] -dataa[9] => mult_t5t:auto_generated.dataa[9] -dataa[10] => mult_t5t:auto_generated.dataa[10] -dataa[11] => mult_t5t:auto_generated.dataa[11] -datab[0] => mult_t5t:auto_generated.datab[0] -datab[1] => mult_t5t:auto_generated.datab[1] -datab[2] => mult_t5t:auto_generated.datab[2] -datab[3] => mult_t5t:auto_generated.datab[3] -datab[4] => mult_t5t:auto_generated.datab[4] -datab[5] => mult_t5t:auto_generated.datab[5] -datab[6] => mult_t5t:auto_generated.datab[6] -datab[7] => mult_t5t:auto_generated.datab[7] -datab[8] => mult_t5t:auto_generated.datab[8] -datab[9] => mult_t5t:auto_generated.datab[9] -datab[10] => mult_t5t:auto_generated.datab[10] -datab[11] => mult_t5t:auto_generated.datab[11] -sum[0] => ~NO_FANOUT~ -aclr => ~NO_FANOUT~ -sclr => ~NO_FANOUT~ -clock => ~NO_FANOUT~ -clken => ~NO_FANOUT~ -result[0] <= mult_t5t:auto_generated.result[0] -result[1] <= mult_t5t:auto_generated.result[1] -result[2] <= mult_t5t:auto_generated.result[2] -result[3] <= mult_t5t:auto_generated.result[3] -result[4] <= mult_t5t:auto_generated.result[4] -result[5] <= mult_t5t:auto_generated.result[5] -result[6] <= mult_t5t:auto_generated.result[6] -result[7] <= mult_t5t:auto_generated.result[7] -result[8] <= mult_t5t:auto_generated.result[8] -result[9] <= mult_t5t:auto_generated.result[9] -result[10] <= mult_t5t:auto_generated.result[10] -result[11] <= mult_t5t:auto_generated.result[11] -result[12] <= mult_t5t:auto_generated.result[12] -result[13] <= mult_t5t:auto_generated.result[13] -result[14] <= mult_t5t:auto_generated.result[14] -result[15] <= mult_t5t:auto_generated.result[15] -result[16] <= mult_t5t:auto_generated.result[16] -result[17] <= mult_t5t:auto_generated.result[17] -result[18] <= mult_t5t:auto_generated.result[18] -result[19] <= mult_t5t:auto_generated.result[19] -result[20] <= mult_t5t:auto_generated.result[20] -result[21] <= mult_t5t:auto_generated.result[21] -result[22] <= mult_t5t:auto_generated.result[22] -result[23] <= mult_t5t:auto_generated.result[23] - - -|WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult1|mult_t5t:auto_generated -dataa[0] => mac_mult1.DATAA -dataa[1] => mac_mult1.DATAA1 -dataa[2] => mac_mult1.DATAA2 -dataa[3] => mac_mult1.DATAA3 -dataa[4] => mac_mult1.DATAA4 -dataa[5] => mac_mult1.DATAA5 -dataa[6] => mac_mult1.DATAA6 -dataa[7] => mac_mult1.DATAA7 -dataa[8] => mac_mult1.DATAA8 -dataa[9] => mac_mult1.DATAA9 -dataa[10] => mac_mult1.DATAA10 -dataa[11] => mac_mult1.DATAA11 -datab[0] => mac_mult1.DATAB -datab[1] => mac_mult1.DATAB1 -datab[2] => mac_mult1.DATAB2 -datab[3] => mac_mult1.DATAB3 -datab[4] => mac_mult1.DATAB4 -datab[5] => mac_mult1.DATAB5 -datab[6] => mac_mult1.DATAB6 -datab[7] => mac_mult1.DATAB7 -datab[8] => mac_mult1.DATAB8 -datab[9] => mac_mult1.DATAB9 -datab[10] => mac_mult1.DATAB10 -datab[11] => mac_mult1.DATAB11 -result[0] <= mac_out2.DATAOUT -result[1] <= mac_out2.DATAOUT1 -result[2] <= mac_out2.DATAOUT2 -result[3] <= mac_out2.DATAOUT3 -result[4] <= mac_out2.DATAOUT4 -result[5] <= mac_out2.DATAOUT5 -result[6] <= mac_out2.DATAOUT6 -result[7] <= mac_out2.DATAOUT7 -result[8] <= mac_out2.DATAOUT8 -result[9] <= mac_out2.DATAOUT9 -result[10] <= mac_out2.DATAOUT10 -result[11] <= mac_out2.DATAOUT11 -result[12] <= mac_out2.DATAOUT12 -result[13] <= mac_out2.DATAOUT13 -result[14] <= mac_out2.DATAOUT14 -result[15] <= mac_out2.DATAOUT15 -result[16] <= mac_out2.DATAOUT16 -result[17] <= mac_out2.DATAOUT17 -result[18] <= mac_out2.DATAOUT18 -result[19] <= mac_out2.DATAOUT19 -result[20] <= mac_out2.DATAOUT20 -result[21] <= mac_out2.DATAOUT21 -result[22] <= mac_out2.DATAOUT22 -result[23] <= mac_out2.DATAOUT23 - - -|WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult0 -dataa[0] => mult_t5t:auto_generated.dataa[0] -dataa[1] => mult_t5t:auto_generated.dataa[1] -dataa[2] => mult_t5t:auto_generated.dataa[2] -dataa[3] => mult_t5t:auto_generated.dataa[3] -dataa[4] => mult_t5t:auto_generated.dataa[4] -dataa[5] => mult_t5t:auto_generated.dataa[5] -dataa[6] => mult_t5t:auto_generated.dataa[6] -dataa[7] => mult_t5t:auto_generated.dataa[7] -dataa[8] => mult_t5t:auto_generated.dataa[8] -dataa[9] => mult_t5t:auto_generated.dataa[9] -dataa[10] => mult_t5t:auto_generated.dataa[10] -dataa[11] => mult_t5t:auto_generated.dataa[11] -datab[0] => mult_t5t:auto_generated.datab[0] -datab[1] => mult_t5t:auto_generated.datab[1] -datab[2] => mult_t5t:auto_generated.datab[2] -datab[3] => mult_t5t:auto_generated.datab[3] -datab[4] => mult_t5t:auto_generated.datab[4] -datab[5] => mult_t5t:auto_generated.datab[5] -datab[6] => mult_t5t:auto_generated.datab[6] -datab[7] => mult_t5t:auto_generated.datab[7] -datab[8] => mult_t5t:auto_generated.datab[8] -datab[9] => mult_t5t:auto_generated.datab[9] -datab[10] => mult_t5t:auto_generated.datab[10] -datab[11] => mult_t5t:auto_generated.datab[11] -sum[0] => ~NO_FANOUT~ -aclr => ~NO_FANOUT~ -sclr => ~NO_FANOUT~ -clock => ~NO_FANOUT~ -clken => ~NO_FANOUT~ -result[0] <= mult_t5t:auto_generated.result[0] -result[1] <= mult_t5t:auto_generated.result[1] -result[2] <= mult_t5t:auto_generated.result[2] -result[3] <= mult_t5t:auto_generated.result[3] -result[4] <= mult_t5t:auto_generated.result[4] -result[5] <= mult_t5t:auto_generated.result[5] -result[6] <= mult_t5t:auto_generated.result[6] -result[7] <= mult_t5t:auto_generated.result[7] -result[8] <= mult_t5t:auto_generated.result[8] -result[9] <= mult_t5t:auto_generated.result[9] -result[10] <= mult_t5t:auto_generated.result[10] -result[11] <= mult_t5t:auto_generated.result[11] -result[12] <= mult_t5t:auto_generated.result[12] -result[13] <= mult_t5t:auto_generated.result[13] -result[14] <= mult_t5t:auto_generated.result[14] -result[15] <= mult_t5t:auto_generated.result[15] -result[16] <= mult_t5t:auto_generated.result[16] -result[17] <= mult_t5t:auto_generated.result[17] -result[18] <= mult_t5t:auto_generated.result[18] -result[19] <= mult_t5t:auto_generated.result[19] -result[20] <= mult_t5t:auto_generated.result[20] -result[21] <= mult_t5t:auto_generated.result[21] -result[22] <= mult_t5t:auto_generated.result[22] -result[23] <= mult_t5t:auto_generated.result[23] - - -|WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult0|mult_t5t:auto_generated -dataa[0] => mac_mult1.DATAA -dataa[1] => mac_mult1.DATAA1 -dataa[2] => mac_mult1.DATAA2 -dataa[3] => mac_mult1.DATAA3 -dataa[4] => mac_mult1.DATAA4 -dataa[5] => mac_mult1.DATAA5 -dataa[6] => mac_mult1.DATAA6 -dataa[7] => mac_mult1.DATAA7 -dataa[8] => mac_mult1.DATAA8 -dataa[9] => mac_mult1.DATAA9 -dataa[10] => mac_mult1.DATAA10 -dataa[11] => mac_mult1.DATAA11 -datab[0] => mac_mult1.DATAB -datab[1] => mac_mult1.DATAB1 -datab[2] => mac_mult1.DATAB2 -datab[3] => mac_mult1.DATAB3 -datab[4] => mac_mult1.DATAB4 -datab[5] => mac_mult1.DATAB5 -datab[6] => mac_mult1.DATAB6 -datab[7] => mac_mult1.DATAB7 -datab[8] => mac_mult1.DATAB8 -datab[9] => mac_mult1.DATAB9 -datab[10] => mac_mult1.DATAB10 -datab[11] => mac_mult1.DATAB11 -result[0] <= mac_out2.DATAOUT -result[1] <= mac_out2.DATAOUT1 -result[2] <= mac_out2.DATAOUT2 -result[3] <= mac_out2.DATAOUT3 -result[4] <= mac_out2.DATAOUT4 -result[5] <= mac_out2.DATAOUT5 -result[6] <= mac_out2.DATAOUT6 -result[7] <= mac_out2.DATAOUT7 -result[8] <= mac_out2.DATAOUT8 -result[9] <= mac_out2.DATAOUT9 -result[10] <= mac_out2.DATAOUT10 -result[11] <= mac_out2.DATAOUT11 -result[12] <= mac_out2.DATAOUT12 -result[13] <= mac_out2.DATAOUT13 -result[14] <= mac_out2.DATAOUT14 -result[15] <= mac_out2.DATAOUT15 -result[16] <= mac_out2.DATAOUT16 -result[17] <= mac_out2.DATAOUT17 -result[18] <= mac_out2.DATAOUT18 -result[19] <= mac_out2.DATAOUT19 -result[20] <= mac_out2.DATAOUT20 -result[21] <= mac_out2.DATAOUT21 -result[22] <= mac_out2.DATAOUT22 -result[23] <= mac_out2.DATAOUT23 - - -|WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult1 -dataa[0] => mult_t5t:auto_generated.dataa[0] -dataa[1] => mult_t5t:auto_generated.dataa[1] -dataa[2] => mult_t5t:auto_generated.dataa[2] -dataa[3] => mult_t5t:auto_generated.dataa[3] -dataa[4] => mult_t5t:auto_generated.dataa[4] -dataa[5] => mult_t5t:auto_generated.dataa[5] -dataa[6] => mult_t5t:auto_generated.dataa[6] -dataa[7] => mult_t5t:auto_generated.dataa[7] -dataa[8] => mult_t5t:auto_generated.dataa[8] -dataa[9] => mult_t5t:auto_generated.dataa[9] -dataa[10] => mult_t5t:auto_generated.dataa[10] -dataa[11] => mult_t5t:auto_generated.dataa[11] -datab[0] => mult_t5t:auto_generated.datab[0] -datab[1] => mult_t5t:auto_generated.datab[1] -datab[2] => mult_t5t:auto_generated.datab[2] -datab[3] => mult_t5t:auto_generated.datab[3] -datab[4] => mult_t5t:auto_generated.datab[4] -datab[5] => mult_t5t:auto_generated.datab[5] -datab[6] => mult_t5t:auto_generated.datab[6] -datab[7] => mult_t5t:auto_generated.datab[7] -datab[8] => mult_t5t:auto_generated.datab[8] -datab[9] => mult_t5t:auto_generated.datab[9] -datab[10] => mult_t5t:auto_generated.datab[10] -datab[11] => mult_t5t:auto_generated.datab[11] -sum[0] => ~NO_FANOUT~ -aclr => ~NO_FANOUT~ -sclr => ~NO_FANOUT~ -clock => ~NO_FANOUT~ -clken => ~NO_FANOUT~ -result[0] <= mult_t5t:auto_generated.result[0] -result[1] <= mult_t5t:auto_generated.result[1] -result[2] <= mult_t5t:auto_generated.result[2] -result[3] <= mult_t5t:auto_generated.result[3] -result[4] <= mult_t5t:auto_generated.result[4] -result[5] <= mult_t5t:auto_generated.result[5] -result[6] <= mult_t5t:auto_generated.result[6] -result[7] <= mult_t5t:auto_generated.result[7] -result[8] <= mult_t5t:auto_generated.result[8] -result[9] <= mult_t5t:auto_generated.result[9] -result[10] <= mult_t5t:auto_generated.result[10] -result[11] <= mult_t5t:auto_generated.result[11] -result[12] <= mult_t5t:auto_generated.result[12] -result[13] <= mult_t5t:auto_generated.result[13] -result[14] <= mult_t5t:auto_generated.result[14] -result[15] <= mult_t5t:auto_generated.result[15] -result[16] <= mult_t5t:auto_generated.result[16] -result[17] <= mult_t5t:auto_generated.result[17] -result[18] <= mult_t5t:auto_generated.result[18] -result[19] <= mult_t5t:auto_generated.result[19] -result[20] <= mult_t5t:auto_generated.result[20] -result[21] <= mult_t5t:auto_generated.result[21] -result[22] <= mult_t5t:auto_generated.result[22] -result[23] <= mult_t5t:auto_generated.result[23] - - -|WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult1|mult_t5t:auto_generated -dataa[0] => mac_mult1.DATAA -dataa[1] => mac_mult1.DATAA1 -dataa[2] => mac_mult1.DATAA2 -dataa[3] => mac_mult1.DATAA3 -dataa[4] => mac_mult1.DATAA4 -dataa[5] => mac_mult1.DATAA5 -dataa[6] => mac_mult1.DATAA6 -dataa[7] => mac_mult1.DATAA7 -dataa[8] => mac_mult1.DATAA8 -dataa[9] => mac_mult1.DATAA9 -dataa[10] => mac_mult1.DATAA10 -dataa[11] => mac_mult1.DATAA11 -datab[0] => mac_mult1.DATAB -datab[1] => mac_mult1.DATAB1 -datab[2] => mac_mult1.DATAB2 -datab[3] => mac_mult1.DATAB3 -datab[4] => mac_mult1.DATAB4 -datab[5] => mac_mult1.DATAB5 -datab[6] => mac_mult1.DATAB6 -datab[7] => mac_mult1.DATAB7 -datab[8] => mac_mult1.DATAB8 -datab[9] => mac_mult1.DATAB9 -datab[10] => mac_mult1.DATAB10 -datab[11] => mac_mult1.DATAB11 -result[0] <= mac_out2.DATAOUT -result[1] <= mac_out2.DATAOUT1 -result[2] <= mac_out2.DATAOUT2 -result[3] <= mac_out2.DATAOUT3 -result[4] <= mac_out2.DATAOUT4 -result[5] <= mac_out2.DATAOUT5 -result[6] <= mac_out2.DATAOUT6 -result[7] <= mac_out2.DATAOUT7 -result[8] <= mac_out2.DATAOUT8 -result[9] <= mac_out2.DATAOUT9 -result[10] <= mac_out2.DATAOUT10 -result[11] <= mac_out2.DATAOUT11 -result[12] <= mac_out2.DATAOUT12 -result[13] <= mac_out2.DATAOUT13 -result[14] <= mac_out2.DATAOUT14 -result[15] <= mac_out2.DATAOUT15 -result[16] <= mac_out2.DATAOUT16 -result[17] <= mac_out2.DATAOUT17 -result[18] <= mac_out2.DATAOUT18 -result[19] <= mac_out2.DATAOUT19 -result[20] <= mac_out2.DATAOUT20 -result[21] <= mac_out2.DATAOUT21 -result[22] <= mac_out2.DATAOUT22 -result[23] <= mac_out2.DATAOUT23 - - -|WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult0 -dataa[0] => mult_t5t:auto_generated.dataa[0] -dataa[1] => mult_t5t:auto_generated.dataa[1] -dataa[2] => mult_t5t:auto_generated.dataa[2] -dataa[3] => mult_t5t:auto_generated.dataa[3] -dataa[4] => mult_t5t:auto_generated.dataa[4] -dataa[5] => mult_t5t:auto_generated.dataa[5] -dataa[6] => mult_t5t:auto_generated.dataa[6] -dataa[7] => mult_t5t:auto_generated.dataa[7] -dataa[8] => mult_t5t:auto_generated.dataa[8] -dataa[9] => mult_t5t:auto_generated.dataa[9] -dataa[10] => mult_t5t:auto_generated.dataa[10] -dataa[11] => mult_t5t:auto_generated.dataa[11] -datab[0] => mult_t5t:auto_generated.datab[0] -datab[1] => mult_t5t:auto_generated.datab[1] -datab[2] => mult_t5t:auto_generated.datab[2] -datab[3] => mult_t5t:auto_generated.datab[3] -datab[4] => mult_t5t:auto_generated.datab[4] -datab[5] => mult_t5t:auto_generated.datab[5] -datab[6] => mult_t5t:auto_generated.datab[6] -datab[7] => mult_t5t:auto_generated.datab[7] -datab[8] => mult_t5t:auto_generated.datab[8] -datab[9] => mult_t5t:auto_generated.datab[9] -datab[10] => mult_t5t:auto_generated.datab[10] -datab[11] => mult_t5t:auto_generated.datab[11] -sum[0] => ~NO_FANOUT~ -aclr => ~NO_FANOUT~ -sclr => ~NO_FANOUT~ -clock => ~NO_FANOUT~ -clken => ~NO_FANOUT~ -result[0] <= mult_t5t:auto_generated.result[0] -result[1] <= mult_t5t:auto_generated.result[1] -result[2] <= mult_t5t:auto_generated.result[2] -result[3] <= mult_t5t:auto_generated.result[3] -result[4] <= mult_t5t:auto_generated.result[4] -result[5] <= mult_t5t:auto_generated.result[5] -result[6] <= mult_t5t:auto_generated.result[6] -result[7] <= mult_t5t:auto_generated.result[7] -result[8] <= mult_t5t:auto_generated.result[8] -result[9] <= mult_t5t:auto_generated.result[9] -result[10] <= mult_t5t:auto_generated.result[10] -result[11] <= mult_t5t:auto_generated.result[11] -result[12] <= mult_t5t:auto_generated.result[12] -result[13] <= mult_t5t:auto_generated.result[13] -result[14] <= mult_t5t:auto_generated.result[14] -result[15] <= mult_t5t:auto_generated.result[15] -result[16] <= mult_t5t:auto_generated.result[16] -result[17] <= mult_t5t:auto_generated.result[17] -result[18] <= mult_t5t:auto_generated.result[18] -result[19] <= mult_t5t:auto_generated.result[19] -result[20] <= mult_t5t:auto_generated.result[20] -result[21] <= mult_t5t:auto_generated.result[21] -result[22] <= mult_t5t:auto_generated.result[22] -result[23] <= mult_t5t:auto_generated.result[23] - - -|WOLF-LITE|nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult0|mult_t5t:auto_generated -dataa[0] => mac_mult1.DATAA -dataa[1] => mac_mult1.DATAA1 -dataa[2] => mac_mult1.DATAA2 -dataa[3] => mac_mult1.DATAA3 -dataa[4] => mac_mult1.DATAA4 -dataa[5] => mac_mult1.DATAA5 -dataa[6] => mac_mult1.DATAA6 -dataa[7] => mac_mult1.DATAA7 -dataa[8] => mac_mult1.DATAA8 -dataa[9] => mac_mult1.DATAA9 -dataa[10] => mac_mult1.DATAA10 -dataa[11] => mac_mult1.DATAA11 -datab[0] => mac_mult1.DATAB -datab[1] => mac_mult1.DATAB1 -datab[2] => mac_mult1.DATAB2 -datab[3] => mac_mult1.DATAB3 -datab[4] => mac_mult1.DATAB4 -datab[5] => mac_mult1.DATAB5 -datab[6] => mac_mult1.DATAB6 -datab[7] => mac_mult1.DATAB7 -datab[8] => mac_mult1.DATAB8 -datab[9] => mac_mult1.DATAB9 -datab[10] => mac_mult1.DATAB10 -datab[11] => mac_mult1.DATAB11 -result[0] <= mac_out2.DATAOUT -result[1] <= mac_out2.DATAOUT1 -result[2] <= mac_out2.DATAOUT2 -result[3] <= mac_out2.DATAOUT3 -result[4] <= mac_out2.DATAOUT4 -result[5] <= mac_out2.DATAOUT5 -result[6] <= mac_out2.DATAOUT6 -result[7] <= mac_out2.DATAOUT7 -result[8] <= mac_out2.DATAOUT8 -result[9] <= mac_out2.DATAOUT9 -result[10] <= mac_out2.DATAOUT10 -result[11] <= mac_out2.DATAOUT11 -result[12] <= mac_out2.DATAOUT12 -result[13] <= mac_out2.DATAOUT13 -result[14] <= mac_out2.DATAOUT14 -result[15] <= mac_out2.DATAOUT15 -result[16] <= mac_out2.DATAOUT16 -result[17] <= mac_out2.DATAOUT17 -result[18] <= mac_out2.DATAOUT18 -result[19] <= mac_out2.DATAOUT19 -result[20] <= mac_out2.DATAOUT20 -result[21] <= mac_out2.DATAOUT21 -result[22] <= mac_out2.DATAOUT22 -result[23] <= mac_out2.DATAOUT23 - - diff --git a/FPGA_61.440/db/WOLF-LITE.hif b/FPGA_61.440/db/WOLF-LITE.hif deleted file mode 100644 index 0a232e0..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.hif and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.lpc.html b/FPGA_61.440/db/WOLF-LITE.lpc.html deleted file mode 100644 index 7d2a99a..0000000 --- a/FPGA_61.440/db/WOLF-LITE.lpc.html +++ /dev/null @@ -1,2274 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
DBG_ADC|in_system_sources_probes_012000000000000
DBG_ADC12000000000000
DAC_CORRECTOR410001400000000
DAC_IDLE00001400000000
DAC_MUX|LPM_MUX_component|auto_generated290001400000000
DAC_MUX290001400000000
MAIN_PLL|altpll_component|auto_generated2000500000000
MAIN_PLL1000200000000
RX_MIXER_Q|lpm_mult_component|auto_generated260002400000000
RX_MIXER_Q260002400000000
RX_CIC_Q|cic_ii_0|core43160163916161600000
RX_CIC_Q|cic_ii_0300003600000000
RX_CIC_Q282023622200000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:gen_outp_blk:0:outp_blk490204700000000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_im0_component|auto_generated280002600000000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_im4_component|auto_generated250002300000000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_memr0_dmem|auto_generated460003200000000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_in0_m0_wi0_wo0_assign_id1_q_134101111100000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_xIn_0_13351013211100000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_164101111100000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_154101111100000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_compute4101111100000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_memread4101111100000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core43160165516161600000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|intf_ctrl6111611100000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|source532325322200000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|sink400303600000000
RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst407075377700000
RX_CICOMP_Q|rx_ciccomp_inst370004900000000
RX_CICOMP_Q372024922200000
ADC_Latch|LPM_ADD_SUB_component|auto_generated260001200000000
ADC_Latch140001200000000
RX_MIXER_I|lpm_mult_component|auto_generated260002400000000
RX_MIXER_I260002400000000
RX_NCO|nco_ii_0|ux710isdr3000100000000
RX_NCO|nco_ii_0|blk12701101200000000
RX_NCO|nco_ii_0|blk02701101200000000
RX_NCO|nco_ii_0|ux0136480004800000000
RX_NCO|nco_ii_0|m0500002400000000
RX_NCO|nco_ii_0|m1500002400000000
RX_NCO|nco_ii_0|ux0123130001200000000
RX_NCO|nco_ii_0|ux0122130001200000000
RX_NCO|nco_ii_0|ux0220240002400000000
RX_NCO|nco_ii_0|ux008250003300000000
RX_NCO|nco_ii_0|ux000250002200000000
RX_NCO|nco_ii_0250002500000000
RX_NCO250002500000000
RX_CIC_I|cic_ii_0|core43160163916161600000
RX_CIC_I|cic_ii_0300003600000000
RX_CIC_I282023622200000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:gen_outp_blk:0:outp_blk490204700000000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_im0_component|auto_generated280002600000000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_im4_component|auto_generated250002300000000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_memr0_dmem|auto_generated460003200000000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_in0_m0_wi0_wo0_assign_id1_q_134101111100000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_xIn_0_13351013211100000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_164101111100000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_154101111100000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_compute4101111100000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_memread4101111100000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core43160165516161600000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|intf_ctrl6111611100000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|source532325322200000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|sink400303600000000
RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst407075377700000
RX_CICCOMP_I|rx_ciccomp_inst370004900000000
RX_CICCOMP_I372024922200000
RX_CICFIR_GAINER1031013411100000
FLASH128082088800000
TX_CIC_Q|cic_ii_0|core37170172317171700000
TX_CIC_Q|cic_ii_0231012011100000
TX_CIC_Q225052055500000
TX_MIXER_Q|lpm_mult_component|auto_generated340003200000000
TX_MIXER_Q340003200000000
TX_NCO|nco_ii_0|ux710isdr3000100000000
TX_NCO|nco_ii_0|blk13501501600000000
TX_NCO|nco_ii_0|blk03501501600000000
TX_NCO|nco_ii_0|ux0136640006400000000
TX_NCO|nco_ii_0|m0660003200000000
TX_NCO|nco_ii_0|m1660003200000000
TX_NCO|nco_ii_0|ux0123130001600000000
TX_NCO|nco_ii_0|ux0122130001600000000
TX_NCO|nco_ii_0|ux0220240003200000000
TX_NCO|nco_ii_0|ux008250003300000000
TX_NCO|nco_ii_0|ux000250002200000000
TX_NCO|nco_ii_0250003300000000
TX_NCO252023322200000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:gen_outp_blk:0:outp_blk330203100000000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_accum_p1_of_2_q_17231012011100000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_mtree_mult1_0_q_1627210212421212100000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_164101111100000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_aseq_q_164101111100000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_component|auto_generated260002400000000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_memr0_dmem|auto_generated300001600000000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_in0_m0_wi0_wo0_assign_id1_q_134101111100000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_xIn_0_13191011611100000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_154101111100000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_144101111100000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_compute4101111100000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_memread4101111100000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core27160163916161600000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|intf_ctrl6111611100000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|source372323722200000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|sink240302000000000
TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst247073777700000
TX_CICCOMP_Q|tx_ciccomp_inst210003300000000
TX_CICCOMP_Q190003300000000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:gen_outp_blk:0:outp_blk330203100000000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_accum_p1_of_2_q_17231012011100000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_mtree_mult1_0_q_1627210212421212100000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_164101111100000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_aseq_q_164101111100000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_component|auto_generated260002400000000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_memr0_dmem|auto_generated300001600000000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_in0_m0_wi0_wo0_assign_id1_q_134101111100000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_xIn_0_13191011611100000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_154101111100000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_144101111100000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_compute4101111100000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_memread4101111100000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core27160163916161600000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|intf_ctrl6111611100000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|source372323722200000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|sink240302000000000
TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst247073777700000
TX_CICCOMP_I|tx_ciccomp_inst210003300000000
TX_CICCOMP_I190003300000000
TX_CICCOMP_GAINER710003400000000
TX_CIC_I|cic_ii_0|core37170172317171700000
TX_CIC_I|cic_ii_0231012011100000
TX_CIC_I225052055500000
TX_MIXER_I|lpm_mult_component|auto_generated340003200000000
TX_MIXER_I340003200000000
SYSCLK_BUFFER|altclkctrl_0|clock_buffer_altclkctrl_0_sub_component5404144400000
SYSCLK_BUFFER|altclkctrl_01000100000000
SYSCLK_BUFFER1000100000000
TX_PLL|altpll_component|auto_generated2000500000000
TX_PLL1000100000000
TX_SUMMATOR|LPM_ADD_SUB_component|auto_generated660003300000000
TX_SUMMATOR660003300000000
STM32_INTERFACE592402415224242480000
diff --git a/FPGA_61.440/db/WOLF-LITE.lpc.rdb b/FPGA_61.440/db/WOLF-LITE.lpc.rdb deleted file mode 100644 index 9194650..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.lpc.rdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.lpc.txt b/FPGA_61.440/db/WOLF-LITE.lpc.txt deleted file mode 100644 index 3017408..0000000 --- a/FPGA_61.440/db/WOLF-LITE.lpc.txt +++ /dev/null @@ -1,147 +0,0 @@ -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Legal Partition Candidates ; -+---------------------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; -+---------------------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; DBG_ADC|in_system_sources_probes_0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DBG_ADC ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DAC_CORRECTOR ; 41 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DAC_IDLE ; 0 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DAC_MUX|LPM_MUX_component|auto_generated ; 29 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DAC_MUX ; 29 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; MAIN_PLL|altpll_component|auto_generated ; 2 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; MAIN_PLL ; 1 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_MIXER_Q|lpm_mult_component|auto_generated ; 26 ; 0 ; 0 ; 0 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_MIXER_Q ; 26 ; 0 ; 0 ; 0 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CIC_Q|cic_ii_0|core ; 43 ; 16 ; 0 ; 16 ; 39 ; 16 ; 16 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CIC_Q|cic_ii_0 ; 30 ; 0 ; 0 ; 0 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CIC_Q ; 28 ; 2 ; 0 ; 2 ; 36 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:gen_outp_blk:0:outp_blk ; 49 ; 0 ; 2 ; 0 ; 47 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_im0_component|auto_generated ; 28 ; 0 ; 0 ; 0 ; 26 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_im4_component|auto_generated ; 25 ; 0 ; 0 ; 0 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_memr0_dmem|auto_generated ; 46 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_in0_m0_wi0_wo0_assign_id1_q_13 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_xIn_0_13 ; 35 ; 1 ; 0 ; 1 ; 32 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_16 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_15 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_compute ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_memread ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core ; 43 ; 16 ; 0 ; 16 ; 55 ; 16 ; 16 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|intf_ctrl ; 6 ; 1 ; 1 ; 1 ; 6 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|source ; 53 ; 2 ; 3 ; 2 ; 53 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|sink ; 40 ; 0 ; 3 ; 0 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst ; 40 ; 7 ; 0 ; 7 ; 53 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q|rx_ciccomp_inst ; 37 ; 0 ; 0 ; 0 ; 49 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICOMP_Q ; 37 ; 2 ; 0 ; 2 ; 49 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; ADC_Latch|LPM_ADD_SUB_component|auto_generated ; 26 ; 0 ; 0 ; 0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; ADC_Latch ; 14 ; 0 ; 0 ; 0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_MIXER_I|lpm_mult_component|auto_generated ; 26 ; 0 ; 0 ; 0 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_MIXER_I ; 26 ; 0 ; 0 ; 0 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_NCO|nco_ii_0|ux710isdr ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_NCO|nco_ii_0|blk1 ; 27 ; 0 ; 11 ; 0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_NCO|nco_ii_0|blk0 ; 27 ; 0 ; 11 ; 0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_NCO|nco_ii_0|ux0136 ; 48 ; 0 ; 0 ; 0 ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_NCO|nco_ii_0|m0 ; 50 ; 0 ; 0 ; 0 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_NCO|nco_ii_0|m1 ; 50 ; 0 ; 0 ; 0 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_NCO|nco_ii_0|ux0123 ; 13 ; 0 ; 0 ; 0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_NCO|nco_ii_0|ux0122 ; 13 ; 0 ; 0 ; 0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_NCO|nco_ii_0|ux0220 ; 24 ; 0 ; 0 ; 0 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_NCO|nco_ii_0|ux008 ; 25 ; 0 ; 0 ; 0 ; 33 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_NCO|nco_ii_0|ux000 ; 25 ; 0 ; 0 ; 0 ; 22 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_NCO|nco_ii_0 ; 25 ; 0 ; 0 ; 0 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_NCO ; 25 ; 0 ; 0 ; 0 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CIC_I|cic_ii_0|core ; 43 ; 16 ; 0 ; 16 ; 39 ; 16 ; 16 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CIC_I|cic_ii_0 ; 30 ; 0 ; 0 ; 0 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CIC_I ; 28 ; 2 ; 0 ; 2 ; 36 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:gen_outp_blk:0:outp_blk ; 49 ; 0 ; 2 ; 0 ; 47 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_im0_component|auto_generated ; 28 ; 0 ; 0 ; 0 ; 26 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_im4_component|auto_generated ; 25 ; 0 ; 0 ; 0 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_memr0_dmem|auto_generated ; 46 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_in0_m0_wi0_wo0_assign_id1_q_13 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_xIn_0_13 ; 35 ; 1 ; 0 ; 1 ; 32 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_16 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_15 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_compute ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_memread ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core ; 43 ; 16 ; 0 ; 16 ; 55 ; 16 ; 16 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|intf_ctrl ; 6 ; 1 ; 1 ; 1 ; 6 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|source ; 53 ; 2 ; 3 ; 2 ; 53 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst|sink ; 40 ; 0 ; 3 ; 0 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst|rx_ciccomp_0002_ast_inst ; 40 ; 7 ; 0 ; 7 ; 53 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I|rx_ciccomp_inst ; 37 ; 0 ; 0 ; 0 ; 49 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICCOMP_I ; 37 ; 2 ; 0 ; 2 ; 49 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RX_CICFIR_GAINER ; 103 ; 1 ; 0 ; 1 ; 34 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; FLASH ; 12 ; 8 ; 0 ; 8 ; 20 ; 8 ; 8 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CIC_Q|cic_ii_0|core ; 37 ; 17 ; 0 ; 17 ; 23 ; 17 ; 17 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CIC_Q|cic_ii_0 ; 23 ; 1 ; 0 ; 1 ; 20 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CIC_Q ; 22 ; 5 ; 0 ; 5 ; 20 ; 5 ; 5 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_MIXER_Q|lpm_mult_component|auto_generated ; 34 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_MIXER_Q ; 34 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_NCO|nco_ii_0|ux710isdr ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_NCO|nco_ii_0|blk1 ; 35 ; 0 ; 15 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_NCO|nco_ii_0|blk0 ; 35 ; 0 ; 15 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_NCO|nco_ii_0|ux0136 ; 64 ; 0 ; 0 ; 0 ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_NCO|nco_ii_0|m0 ; 66 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_NCO|nco_ii_0|m1 ; 66 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_NCO|nco_ii_0|ux0123 ; 13 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_NCO|nco_ii_0|ux0122 ; 13 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_NCO|nco_ii_0|ux0220 ; 24 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_NCO|nco_ii_0|ux008 ; 25 ; 0 ; 0 ; 0 ; 33 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_NCO|nco_ii_0|ux000 ; 25 ; 0 ; 0 ; 0 ; 22 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_NCO|nco_ii_0 ; 25 ; 0 ; 0 ; 0 ; 33 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_NCO ; 25 ; 2 ; 0 ; 2 ; 33 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:gen_outp_blk:0:outp_blk ; 33 ; 0 ; 2 ; 0 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_accum_p1_of_2_q_17 ; 23 ; 1 ; 0 ; 1 ; 20 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_mtree_mult1_0_q_16 ; 27 ; 21 ; 0 ; 21 ; 24 ; 21 ; 21 ; 21 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_16 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_aseq_q_16 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_component|auto_generated ; 26 ; 0 ; 0 ; 0 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_memr0_dmem|auto_generated ; 30 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_in0_m0_wi0_wo0_assign_id1_q_13 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_xIn_0_13 ; 19 ; 1 ; 0 ; 1 ; 16 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_15 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_14 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_compute ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_memread ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core ; 27 ; 16 ; 0 ; 16 ; 39 ; 16 ; 16 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|intf_ctrl ; 6 ; 1 ; 1 ; 1 ; 6 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|source ; 37 ; 2 ; 3 ; 2 ; 37 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|sink ; 24 ; 0 ; 3 ; 0 ; 20 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst ; 24 ; 7 ; 0 ; 7 ; 37 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q|tx_ciccomp_inst ; 21 ; 0 ; 0 ; 0 ; 33 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_Q ; 19 ; 0 ; 0 ; 0 ; 33 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:gen_outp_blk:0:outp_blk ; 33 ; 0 ; 2 ; 0 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_accum_p1_of_2_q_17 ; 23 ; 1 ; 0 ; 1 ; 20 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_mtree_mult1_0_q_16 ; 27 ; 21 ; 0 ; 21 ; 24 ; 21 ; 21 ; 21 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_16 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_aseq_q_16 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_mtree_mult1_0_component|auto_generated ; 26 ; 0 ; 0 ; 0 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_wi0_r0_memr0_dmem|auto_generated ; 30 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_in0_m0_wi0_wo0_assign_id1_q_13 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_xIn_0_13 ; 19 ; 1 ; 0 ; 1 ; 16 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_15 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|d_u0_m0_wo0_compute_q_14 ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_compute ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core|u0_m0_wo0_memread ; 4 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|\real_passthrough:hpfircore_core ; 27 ; 16 ; 0 ; 16 ; 39 ; 16 ; 16 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|intf_ctrl ; 6 ; 1 ; 1 ; 1 ; 6 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|source ; 37 ; 2 ; 3 ; 2 ; 37 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst|sink ; 24 ; 0 ; 3 ; 0 ; 20 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst|tx_ciccomp_0002_ast_inst ; 24 ; 7 ; 0 ; 7 ; 37 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I|tx_ciccomp_inst ; 21 ; 0 ; 0 ; 0 ; 33 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_I ; 19 ; 0 ; 0 ; 0 ; 33 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CICCOMP_GAINER ; 71 ; 0 ; 0 ; 0 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CIC_I|cic_ii_0|core ; 37 ; 17 ; 0 ; 17 ; 23 ; 17 ; 17 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CIC_I|cic_ii_0 ; 23 ; 1 ; 0 ; 1 ; 20 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_CIC_I ; 22 ; 5 ; 0 ; 5 ; 20 ; 5 ; 5 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_MIXER_I|lpm_mult_component|auto_generated ; 34 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_MIXER_I ; 34 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; SYSCLK_BUFFER|altclkctrl_0|clock_buffer_altclkctrl_0_sub_component ; 5 ; 4 ; 0 ; 4 ; 1 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; SYSCLK_BUFFER|altclkctrl_0 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; SYSCLK_BUFFER ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_PLL|altpll_component|auto_generated ; 2 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_PLL ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_SUMMATOR|LPM_ADD_SUB_component|auto_generated ; 66 ; 0 ; 0 ; 0 ; 33 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TX_SUMMATOR ; 66 ; 0 ; 0 ; 0 ; 33 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; STM32_INTERFACE ; 59 ; 24 ; 0 ; 24 ; 152 ; 24 ; 24 ; 24 ; 8 ; 0 ; 0 ; 0 ; 0 ; -+---------------------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/FPGA_61.440/db/WOLF-LITE.main.hdb b/FPGA_61.440/db/WOLF-LITE.main.hdb deleted file mode 100644 index a2381ab..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.main.hdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.map.ammdb b/FPGA_61.440/db/WOLF-LITE.map.ammdb deleted file mode 100644 index a7850c6..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.map.ammdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.map.bpm b/FPGA_61.440/db/WOLF-LITE.map.bpm deleted file mode 100644 index d41cd5e..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.map.bpm and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.map.cdb b/FPGA_61.440/db/WOLF-LITE.map.cdb deleted file mode 100644 index cc04457..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.map.cdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.map.hdb b/FPGA_61.440/db/WOLF-LITE.map.hdb deleted file mode 100644 index b7c5465..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.map.hdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.map.kpt b/FPGA_61.440/db/WOLF-LITE.map.kpt deleted file mode 100644 index be3feac..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.map.kpt and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.map.logdb b/FPGA_61.440/db/WOLF-LITE.map.logdb deleted file mode 100644 index f672f38..0000000 --- a/FPGA_61.440/db/WOLF-LITE.map.logdb +++ /dev/null @@ -1,3 +0,0 @@ -v1 -PORT_SWAPPING,PORT_SWAP_TYPE_DSPMULT,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1, -PORT_SWAPPING,PORT_SWAP_TYPE_DSPMULT,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1, diff --git a/FPGA_61.440/db/WOLF-LITE.map.qmsg b/FPGA_61.440/db/WOLF-LITE.map.qmsg deleted file mode 100644 index 3e9df9d..0000000 --- a/FPGA_61.440/db/WOLF-LITE.map.qmsg +++ /dev/null @@ -1,631 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1617214480263 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1617214480297 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 31 21:14:39 2021 " "Processing started: Wed Mar 31 21:14:39 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1617214480297 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214480297 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off WOLF-LITE -c WOLF-LITE " "Command: quartus_map --read_settings_files=on --write_settings_files=off WOLF-LITE -c WOLF-LITE" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214480297 ""} -{ "Info" "IQCU_OPT_MODE_DESCRIPTION" "Aggressive Performance timing performance increased logic area and compilation time " "Aggressive Performance optimization mode selected -- timing performance will be prioritized at the potential cost of increased logic area and compilation time" { } { } 0 16303 "%1!s! optimization mode selected -- %2!s! will be prioritized at the potential cost of %3!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214482670 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1617214483167 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "clock_buffer.qsys " "Elaborating Platform Designer system entity \"clock_buffer.qsys\"" { } { } 0 12248 "Elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214498498 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:06 Progress: Loading FPGA/clock_buffer.qsys " "2021.03.31.22:15:06 Progress: Loading FPGA/clock_buffer.qsys" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214506119 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:07 Progress: Reading input file " "2021.03.31.22:15:07 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214507311 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:07 Progress: Adding altclkctrl_0 \[altclkctrl 18.1\] " "2021.03.31.22:15:07 Progress: Adding altclkctrl_0 \[altclkctrl 18.1\]" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214507441 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:08 Progress: Parameterizing module altclkctrl_0 " "2021.03.31.22:15:08 Progress: Parameterizing module altclkctrl_0" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214508188 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:08 Progress: Building connections " "2021.03.31.22:15:08 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214508192 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:08 Progress: Parameterizing connections " "2021.03.31.22:15:08 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214508193 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:08 Progress: Validating " "2021.03.31.22:15:08 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214508250 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:09 Progress: Done reading input file " "2021.03.31.22:15:09 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214509827 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:10 : clock_buffer.altclkctrl_0: Targeting device family: Cyclone IV E. " "2021.03.31.22:15:10 : clock_buffer.altclkctrl_0: Targeting device family: Cyclone IV E." { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214510438 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:10 : clock_buffer.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs. " "2021.03.31.22:15:10 : clock_buffer.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs." { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214510440 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Clock_buffer: Generating clock_buffer \"clock_buffer\" for QUARTUS_SYNTH " "Clock_buffer: Generating clock_buffer \"clock_buffer\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214511446 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Altclkctrl_0: Generating top-level entity clock_buffer_altclkctrl_0. " "Altclkctrl_0: Generating top-level entity clock_buffer_altclkctrl_0." { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214512520 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Altclkctrl_0: \"clock_buffer\" instantiated altclkctrl \"altclkctrl_0\" " "Altclkctrl_0: \"clock_buffer\" instantiated altclkctrl \"altclkctrl_0\"" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214512726 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Clock_buffer: Done \"clock_buffer\" with 2 modules, 2 files " "Clock_buffer: Done \"clock_buffer\" with 2 modules, 2 files" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214512728 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "clock_buffer.qsys " "Finished elaborating Platform Designer system entity \"clock_buffer.qsys\"" { } { } 0 12249 "Finished elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214513524 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "rx_cic.qsys " "Elaborating Platform Designer system entity \"rx_cic.qsys\"" { } { } 0 12248 "Elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214513567 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:20 Progress: Loading FPGA/rx_cic.qsys " "2021.03.31.22:15:20 Progress: Loading FPGA/rx_cic.qsys" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214521005 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:22 Progress: Reading input file " "2021.03.31.22:15:22 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214522066 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:22 Progress: Adding cic_ii_0 \[altera_cic_ii 18.1\] " "2021.03.31.22:15:22 Progress: Adding cic_ii_0 \[altera_cic_ii 18.1\]" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214522227 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:22 Progress: Parameterizing module cic_ii_0 " "2021.03.31.22:15:22 Progress: Parameterizing module cic_ii_0" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214522536 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:22 Progress: Building connections " "2021.03.31.22:15:22 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214522551 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:22 Progress: Parameterizing connections " "2021.03.31.22:15:22 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214522551 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:22 Progress: Validating " "2021.03.31.22:15:22 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214522601 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:24 Progress: Done reading input file " "2021.03.31.22:15:24 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214524334 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Rx_cic.cic_ii_0: Clock Enable Port is deprecated and may be removed in a future release " "Rx_cic.cic_ii_0: Clock Enable Port is deprecated and may be removed in a future release" { } { } 0 12251 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214524891 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rx_cic: Generating rx_cic \"rx_cic\" for QUARTUS_SYNTH " "Rx_cic: Generating rx_cic \"rx_cic\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214525806 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cic_ii_0: \"rx_cic\" instantiated altera_cic_ii \"cic_ii_0\" " "Cic_ii_0: \"rx_cic\" instantiated altera_cic_ii \"cic_ii_0\"" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214526920 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rx_cic: Done \"rx_cic\" with 2 modules, 30 files " "Rx_cic: Done \"rx_cic\" with 2 modules, 30 files" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214526946 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "rx_cic.qsys " "Finished elaborating Platform Designer system entity \"rx_cic.qsys\"" { } { } 0 12249 "Finished elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214527777 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "tx_cic.qsys " "Elaborating Platform Designer system entity \"tx_cic.qsys\"" { } { } 0 12248 "Elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214527826 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:35 Progress: Loading FPGA/tx_cic.qsys " "2021.03.31.22:15:35 Progress: Loading FPGA/tx_cic.qsys" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214535217 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:36 Progress: Reading input file " "2021.03.31.22:15:36 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214536282 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:36 Progress: Adding cic_ii_0 \[altera_cic_ii 18.1\] " "2021.03.31.22:15:36 Progress: Adding cic_ii_0 \[altera_cic_ii 18.1\]" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214536399 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:36 Progress: Parameterizing module cic_ii_0 " "2021.03.31.22:15:36 Progress: Parameterizing module cic_ii_0" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214536766 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:36 Progress: Building connections " "2021.03.31.22:15:36 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214536778 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:36 Progress: Parameterizing connections " "2021.03.31.22:15:36 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214536778 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:36 Progress: Validating " "2021.03.31.22:15:36 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214536833 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:38 Progress: Done reading input file " "2021.03.31.22:15:38 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214538546 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Tx_cic: Generating tx_cic \"tx_cic\" for QUARTUS_SYNTH " "Tx_cic: Generating tx_cic \"tx_cic\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214540099 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cic_ii_0: \"tx_cic\" instantiated altera_cic_ii \"cic_ii_0\" " "Cic_ii_0: \"tx_cic\" instantiated altera_cic_ii \"cic_ii_0\"" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214541230 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Tx_cic: Done \"tx_cic\" with 2 modules, 30 files " "Tx_cic: Done \"tx_cic\" with 2 modules, 30 files" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214541253 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "tx_cic.qsys " "Finished elaborating Platform Designer system entity \"tx_cic.qsys\"" { } { } 0 12249 "Finished elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214542052 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "tx_nco.qsys " "Elaborating Platform Designer system entity \"tx_nco.qsys\"" { } { } 0 12248 "Elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214542095 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:49 Progress: Loading FPGA/tx_nco.qsys " "2021.03.31.22:15:49 Progress: Loading FPGA/tx_nco.qsys" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214549507 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:50 Progress: Reading input file " "2021.03.31.22:15:50 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214550524 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:50 Progress: Adding nco_ii_0 \[altera_nco_ii 18.1\] " "2021.03.31.22:15:50 Progress: Adding nco_ii_0 \[altera_nco_ii 18.1\]" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214550631 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:50 Progress: Parameterizing module nco_ii_0 " "2021.03.31.22:15:50 Progress: Parameterizing module nco_ii_0" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214550914 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:50 Progress: Building connections " "2021.03.31.22:15:50 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214550929 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:50 Progress: Parameterizing connections " "2021.03.31.22:15:50 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214550929 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:50 Progress: Validating " "2021.03.31.22:15:50 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214550978 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:15:52 Progress: Done reading input file " "2021.03.31.22:15:52 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214552654 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Tx_nco: Generating tx_nco \"tx_nco\" for QUARTUS_SYNTH " "Tx_nco: Generating tx_nco \"tx_nco\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214555023 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nco_ii_0: \"tx_nco\" instantiated altera_nco_ii \"nco_ii_0\" " "Nco_ii_0: \"tx_nco\" instantiated altera_nco_ii \"nco_ii_0\"" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214556394 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Tx_nco: Done \"tx_nco\" with 2 modules, 18 files " "Tx_nco: Done \"tx_nco\" with 2 modules, 18 files" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214556422 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "tx_nco.qsys " "Finished elaborating Platform Designer system entity \"tx_nco.qsys\"" { } { } 0 12249 "Finished elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214557468 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "nco.qsys " "Elaborating Platform Designer system entity \"nco.qsys\"" { } { } 0 12248 "Elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214557512 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:11 Progress: Loading FPGA/nco.qsys " "2021.03.31.22:16:11 Progress: Loading FPGA/nco.qsys" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214571499 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:13 Progress: Reading input file " "2021.03.31.22:16:13 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214573822 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:14 Progress: Adding nco_ii_0 \[altera_nco_ii 18.1\] " "2021.03.31.22:16:14 Progress: Adding nco_ii_0 \[altera_nco_ii 18.1\]" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214574014 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:14 Progress: Parameterizing module nco_ii_0 " "2021.03.31.22:16:14 Progress: Parameterizing module nco_ii_0" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214574761 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:14 Progress: Building connections " "2021.03.31.22:16:14 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214574775 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:14 Progress: Parameterizing connections " "2021.03.31.22:16:14 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214574775 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:14 Progress: Validating " "2021.03.31.22:16:14 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214574838 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:16 Progress: Done reading input file " "2021.03.31.22:16:16 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214576791 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nco: Generating nco \"nco\" for QUARTUS_SYNTH " "Nco: Generating nco \"nco\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214578795 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nco_ii_0: \"nco\" instantiated altera_nco_ii \"nco_ii_0\" " "Nco_ii_0: \"nco\" instantiated altera_nco_ii \"nco_ii_0\"" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214580190 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nco: Done \"nco\" with 2 modules, 18 files " "Nco: Done \"nco\" with 2 modules, 18 files" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214580211 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "nco.qsys " "Finished elaborating Platform Designer system entity \"nco.qsys\"" { } { } 0 12249 "Finished elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214581264 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "DEBUG.qsys " "Elaborating Platform Designer system entity \"DEBUG.qsys\"" { } { } 0 12248 "Elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214581302 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:29 Progress: Loading FPGA/DEBUG.qsys " "2021.03.31.22:16:29 Progress: Loading FPGA/DEBUG.qsys" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214589145 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:30 Progress: Reading input file " "2021.03.31.22:16:30 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214590209 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:30 Progress: Adding in_system_sources_probes_0 \[altera_in_system_sources_probes 18.1\] " "2021.03.31.22:16:30 Progress: Adding in_system_sources_probes_0 \[altera_in_system_sources_probes 18.1\]" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214590329 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:30 Progress: Parameterizing module in_system_sources_probes_0 " "2021.03.31.22:16:30 Progress: Parameterizing module in_system_sources_probes_0" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214590583 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:30 Progress: Building connections " "2021.03.31.22:16:30 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214590589 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:30 Progress: Parameterizing connections " "2021.03.31.22:16:30 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214590589 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:30 Progress: Validating " "2021.03.31.22:16:30 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214590640 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:32 Progress: Done reading input file " "2021.03.31.22:16:32 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214592153 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "DEBUG: Generating DEBUG \"DEBUG\" for QUARTUS_SYNTH " "DEBUG: Generating DEBUG \"DEBUG\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214593632 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "In_system_sources_probes_0: \"DEBUG\" instantiated altera_in_system_sources_probes \"in_system_sources_probes_0\" " "In_system_sources_probes_0: \"DEBUG\" instantiated altera_in_system_sources_probes \"in_system_sources_probes_0\"" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214594659 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "DEBUG: Done \"DEBUG\" with 2 modules, 2 files " "DEBUG: Done \"DEBUG\" with 2 modules, 2 files" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214594661 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "DEBUG.qsys " "Finished elaborating Platform Designer system entity \"DEBUG.qsys\"" { } { } 0 12249 "Finished elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214595505 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "DEBUG2.qsys " "Elaborating Platform Designer system entity \"DEBUG2.qsys\"" { } { } 0 12248 "Elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214595544 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:43 Progress: Loading FPGA/DEBUG2.qsys " "2021.03.31.22:16:43 Progress: Loading FPGA/DEBUG2.qsys" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214603368 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:44 Progress: Reading input file " "2021.03.31.22:16:44 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214604366 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:44 Progress: Adding in_system_sources_probes_0 \[altera_in_system_sources_probes 18.1\] " "2021.03.31.22:16:44 Progress: Adding in_system_sources_probes_0 \[altera_in_system_sources_probes 18.1\]" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214604470 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:44 Progress: Parameterizing module in_system_sources_probes_0 " "2021.03.31.22:16:44 Progress: Parameterizing module in_system_sources_probes_0" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214604725 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:44 Progress: Building connections " "2021.03.31.22:16:44 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214604729 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:44 Progress: Parameterizing connections " "2021.03.31.22:16:44 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214604729 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:44 Progress: Validating " "2021.03.31.22:16:44 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214604776 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.31.22:16:46 Progress: Done reading input file " "2021.03.31.22:16:46 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214606156 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "DEBUG2: Generating DEBUG2 \"DEBUG2\" for QUARTUS_SYNTH " "DEBUG2: Generating DEBUG2 \"DEBUG2\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214607599 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "In_system_sources_probes_0: \"DEBUG2\" instantiated altera_in_system_sources_probes \"in_system_sources_probes_0\" " "In_system_sources_probes_0: \"DEBUG2\" instantiated altera_in_system_sources_probes \"in_system_sources_probes_0\"" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214608538 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "DEBUG2: Done \"DEBUG2\" with 2 modules, 2 files " "DEBUG2: Done \"DEBUG2\" with 2 modules, 2 files" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214608539 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "DEBUG2.qsys " "Finished elaborating Platform Designer system entity \"DEBUG2.qsys\"" { } { } 0 12249 "Finished elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214609386 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "wolf-lite.bdf 1 1 " "Found 1 design units, including 1 entities, in source file wolf-lite.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 WOLF-LITE " "Found entity 1: WOLF-LITE" { } { { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611101 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611101 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dac_corrector.v 1 1 " "Found 1 design units, including 1 entities, in source file dac_corrector.v" { { "Info" "ISGN_ENTITY_NAME" "1 DAC_corrector " "Found entity 1: DAC_corrector" { } { { "DAC_corrector.v" "" { Text "C:/FPGA/DAC_corrector.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611148 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611148 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file spi_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi_interface " "Found entity 1: spi_interface" { } { { "spi_interface.v" "" { Text "C:/FPGA/spi_interface.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611171 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611171 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "stm32_interface.v(93) " "Verilog HDL warning at stm32_interface.v(93): extended using \"x\" or \"z\"" { } { { "stm32_interface.v" "" { Text "C:/FPGA/stm32_interface.v" 93 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1617214611184 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "stm32_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file stm32_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 stm32_interface " "Found entity 1: stm32_interface" { } { { "stm32_interface.v" "" { Text "C:/FPGA/stm32_interface.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611196 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611196 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_shifter.v 1 1 " "Found 1 design units, including 1 entities, in source file data_shifter.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_shifter " "Found entity 1: data_shifter" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611214 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611214 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vcxo_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file vcxo_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 vcxo_controller " "Found entity 1: vcxo_controller" { } { { "vcxo_controller.v" "" { Text "C:/FPGA/vcxo_controller.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611237 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611237 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mixer.v 1 1 " "Found 1 design units, including 1 entities, in source file mixer.v" { { "Info" "ISGN_ENTITY_NAME" "1 mixer " "Found entity 1: mixer" { } { { "mixer.v" "" { Text "C:/FPGA/mixer.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611257 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611257 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux16.v 1 1 " "Found 1 design units, including 1 entities, in source file mux16.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux16 " "Found entity 1: mux16" { } { { "mux16.v" "" { Text "C:/FPGA/mux16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611279 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611279 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "main_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file main_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 MAIN_PLL " "Found entity 1: MAIN_PLL" { } { { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611309 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611309 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux14.v 1 1 " "Found 1 design units, including 1 entities, in source file mux14.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux14 " "Found entity 1: mux14" { } { { "mux14.v" "" { Text "C:/FPGA/mux14.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611336 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611336 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux1.v 1 1 " "Found 1 design units, including 1 entities, in source file mux1.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux1 " "Found entity 1: mux1" { } { { "mux1.v" "" { Text "C:/FPGA/mux1.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611361 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611361 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_mixer.v 1 1 " "Found 1 design units, including 1 entities, in source file tx_mixer.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_mixer " "Found entity 1: tx_mixer" { } { { "tx_mixer.v" "" { Text "C:/FPGA/tx_mixer.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611386 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611386 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_summator.v 1 1 " "Found 1 design units, including 1 entities, in source file tx_summator.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_summator " "Found entity 1: tx_summator" { } { { "tx_summator.v" "" { Text "C:/FPGA/tx_summator.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611406 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611406 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adc_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file adc_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 ADC_Latch " "Found entity 1: ADC_Latch" { } { { "ADC_Latch.v" "" { Text "C:/FPGA/ADC_Latch.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611428 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611428 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dac_null.v 1 1 " "Found 1 design units, including 1 entities, in source file dac_null.v" { { "Info" "ISGN_ENTITY_NAME" "1 dac_null " "Found entity 1: dac_null" { } { { "dac_null.v" "" { Text "C:/FPGA/dac_null.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611453 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611453 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp.v 1 1 " "Found 1 design units, including 1 entities, in source file rx_ciccomp.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_ciccomp " "Found entity 1: rx_ciccomp" { } { { "rx_ciccomp.v" "" { Text "C:/FPGA/rx_ciccomp.v" 8 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214611467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214611467 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/dspba_library_package.vhd 1 0 " "Found 1 design units, including 0 entities, in source file rx_ciccomp/dspba_library_package.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dspba_library_package (rx_ciccomp) " "Found design unit 1: dspba_library_package (rx_ciccomp)" { } { { "rx_ciccomp/dspba_library_package.vhd" "" { Text "C:/FPGA/rx_ciccomp/dspba_library_package.vhd" 17 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613136 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613136 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/dspba_library.vhd 6 3 " "Found 6 design units, including 3 entities, in source file rx_ciccomp/dspba_library.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dspba_delay-delay " "Found design unit 1: dspba_delay-delay" { } { { "rx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/rx_ciccomp/dspba_library.vhd" 34 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613146 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 dspba_sync_reg-sync_reg " "Found design unit 2: dspba_sync_reg-sync_reg" { } { { "rx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/rx_ciccomp/dspba_library.vhd" 117 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613146 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 dspba_pipe-rtl " "Found design unit 3: dspba_pipe-rtl" { } { { "rx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/rx_ciccomp/dspba_library.vhd" 356 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613146 ""} { "Info" "ISGN_ENTITY_NAME" "1 dspba_delay " "Found entity 1: dspba_delay" { } { { "rx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/rx_ciccomp/dspba_library.vhd" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613146 ""} { "Info" "ISGN_ENTITY_NAME" "2 dspba_sync_reg " "Found entity 2: dspba_sync_reg" { } { { "rx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/rx_ciccomp/dspba_library.vhd" 93 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613146 ""} { "Info" "ISGN_ENTITY_NAME" "3 dspba_pipe " "Found entity 3: dspba_pipe" { } { { "rx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/rx_ciccomp/dspba_library.vhd" 343 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613146 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613146 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd 2 0 " "Found 2 design units, including 0 entities, in source file rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_math_pkg_hpfir (rx_ciccomp) " "Found design unit 1: auk_dspip_math_pkg_hpfir (rx_ciccomp)" { } { { "rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" 54 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613157 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_dspip_math_pkg_hpfir-body " "Found design unit 2: auk_dspip_math_pkg_hpfir-body" { } { { "rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" 131 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613157 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613157 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd 1 0 " "Found 1 design units, including 0 entities, in source file rx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_lib_pkg_hpfir (rx_ciccomp) " "Found design unit 1: auk_dspip_lib_pkg_hpfir (rx_ciccomp)" { } { { "rx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd" 22 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613166 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613166 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_controller_hpfir-struct " "Found design unit 1: auk_dspip_avalon_streaming_controller_hpfir-struct" { } { { "rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613175 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_controller_hpfir " "Found entity 1: auk_dspip_avalon_streaming_controller_hpfir" { } { { "rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613175 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613175 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_sink_hpfir-rtl " "Found design unit 1: auk_dspip_avalon_streaming_sink_hpfir-rtl" { } { { "rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" 106 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613185 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_sink_hpfir " "Found entity 1: auk_dspip_avalon_streaming_sink_hpfir" { } { { "rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" 56 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613185 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613185 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_source_hpfir-rtl " "Found design unit 1: auk_dspip_avalon_streaming_source_hpfir-rtl" { } { { "rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" 109 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613196 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_source_hpfir " "Found entity 1: auk_dspip_avalon_streaming_source_hpfir" { } { { "rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" 70 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613196 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613196 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/auk_dspip_roundsat_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rx_ciccomp/auk_dspip_roundsat_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_roundsat_hpfir-beh " "Found design unit 1: auk_dspip_roundsat_hpfir-beh" { } { { "rx_ciccomp/auk_dspip_roundsat_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_roundsat_hpfir.vhd" 57 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613206 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_roundsat_hpfir " "Found entity 1: auk_dspip_roundsat_hpfir" { } { { "rx_ciccomp/auk_dspip_roundsat_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_roundsat_hpfir.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613206 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613206 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file rx_ciccomp/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "rx_ciccomp/altera_avalon_sc_fifo.v" "" { Text "C:/FPGA/rx_ciccomp/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613222 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613222 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx_ciccomp_0002_rtl_core-normal " "Found design unit 1: rx_ciccomp_0002_rtl_core-normal" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 47 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613233 ""} { "Info" "ISGN_ENTITY_NAME" "1 rx_ciccomp_0002_rtl_core " "Found entity 1: rx_ciccomp_0002_rtl_core" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613233 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613233 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/rx_ciccomp_0002_ast.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rx_ciccomp/rx_ciccomp_0002_ast.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx_ciccomp_0002_ast-struct " "Found design unit 1: rx_ciccomp_0002_ast-struct" { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 55 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613241 ""} { "Info" "ISGN_ENTITY_NAME" "1 rx_ciccomp_0002_ast " "Found entity 1: rx_ciccomp_0002_ast" { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613241 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613241 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/rx_ciccomp_0002.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rx_ciccomp/rx_ciccomp_0002.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx_ciccomp_0002-syn " "Found design unit 1: rx_ciccomp_0002-syn" { } { { "rx_ciccomp/rx_ciccomp_0002.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd" 33 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613249 ""} { "Info" "ISGN_ENTITY_NAME" "1 rx_ciccomp_0002 " "Found entity 1: rx_ciccomp_0002" { } { { "rx_ciccomp/rx_ciccomp_0002.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613249 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613249 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp.v 1 1 " "Found 1 design units, including 1 entities, in source file tx_ciccomp.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_ciccomp " "Found entity 1: tx_ciccomp" { } { { "tx_ciccomp.v" "" { Text "C:/FPGA/tx_ciccomp.v" 8 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613266 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613266 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/dspba_library_package.vhd 1 0 " "Found 1 design units, including 0 entities, in source file tx_ciccomp/dspba_library_package.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dspba_library_package (tx_ciccomp) " "Found design unit 1: dspba_library_package (tx_ciccomp)" { } { { "tx_ciccomp/dspba_library_package.vhd" "" { Text "C:/FPGA/tx_ciccomp/dspba_library_package.vhd" 17 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613274 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613274 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/dspba_library.vhd 6 3 " "Found 6 design units, including 3 entities, in source file tx_ciccomp/dspba_library.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dspba_delay-delay " "Found design unit 1: dspba_delay-delay" { } { { "tx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/tx_ciccomp/dspba_library.vhd" 34 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613286 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 dspba_sync_reg-sync_reg " "Found design unit 2: dspba_sync_reg-sync_reg" { } { { "tx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/tx_ciccomp/dspba_library.vhd" 117 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613286 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 dspba_pipe-rtl " "Found design unit 3: dspba_pipe-rtl" { } { { "tx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/tx_ciccomp/dspba_library.vhd" 356 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613286 ""} { "Info" "ISGN_ENTITY_NAME" "1 dspba_delay " "Found entity 1: dspba_delay" { } { { "tx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/tx_ciccomp/dspba_library.vhd" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613286 ""} { "Info" "ISGN_ENTITY_NAME" "2 dspba_sync_reg " "Found entity 2: dspba_sync_reg" { } { { "tx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/tx_ciccomp/dspba_library.vhd" 93 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613286 ""} { "Info" "ISGN_ENTITY_NAME" "3 dspba_pipe " "Found entity 3: dspba_pipe" { } { { "tx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/tx_ciccomp/dspba_library.vhd" 343 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613286 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613286 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd 2 0 " "Found 2 design units, including 0 entities, in source file tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_math_pkg_hpfir (tx_ciccomp) " "Found design unit 1: auk_dspip_math_pkg_hpfir (tx_ciccomp)" { } { { "tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" 54 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613296 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_dspip_math_pkg_hpfir-body " "Found design unit 2: auk_dspip_math_pkg_hpfir-body" { } { { "tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" 131 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613296 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613296 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd 1 0 " "Found 1 design units, including 0 entities, in source file tx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_lib_pkg_hpfir (tx_ciccomp) " "Found design unit 1: auk_dspip_lib_pkg_hpfir (tx_ciccomp)" { } { { "tx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd" 22 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613305 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613305 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_controller_hpfir-struct " "Found design unit 1: auk_dspip_avalon_streaming_controller_hpfir-struct" { } { { "tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613315 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_controller_hpfir " "Found entity 1: auk_dspip_avalon_streaming_controller_hpfir" { } { { "tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613315 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613315 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_sink_hpfir-rtl " "Found design unit 1: auk_dspip_avalon_streaming_sink_hpfir-rtl" { } { { "tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" 106 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613325 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_sink_hpfir " "Found entity 1: auk_dspip_avalon_streaming_sink_hpfir" { } { { "tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" 56 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613325 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613325 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_source_hpfir-rtl " "Found design unit 1: auk_dspip_avalon_streaming_source_hpfir-rtl" { } { { "tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" 109 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613337 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_source_hpfir " "Found entity 1: auk_dspip_avalon_streaming_source_hpfir" { } { { "tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" 70 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613337 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613337 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/auk_dspip_roundsat_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tx_ciccomp/auk_dspip_roundsat_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_roundsat_hpfir-beh " "Found design unit 1: auk_dspip_roundsat_hpfir-beh" { } { { "tx_ciccomp/auk_dspip_roundsat_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_roundsat_hpfir.vhd" 57 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613346 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_roundsat_hpfir " "Found entity 1: auk_dspip_roundsat_hpfir" { } { { "tx_ciccomp/auk_dspip_roundsat_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_roundsat_hpfir.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613346 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613346 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file tx_ciccomp/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "tx_ciccomp/altera_avalon_sc_fifo.v" "" { Text "C:/FPGA/tx_ciccomp/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613363 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613363 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tx_ciccomp_0002_rtl_core-normal " "Found design unit 1: tx_ciccomp_0002_rtl_core-normal" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 47 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613373 ""} { "Info" "ISGN_ENTITY_NAME" "1 tx_ciccomp_0002_rtl_core " "Found entity 1: tx_ciccomp_0002_rtl_core" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613373 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613373 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/tx_ciccomp_0002_ast.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tx_ciccomp/tx_ciccomp_0002_ast.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tx_ciccomp_0002_ast-struct " "Found design unit 1: tx_ciccomp_0002_ast-struct" { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 55 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613386 ""} { "Info" "ISGN_ENTITY_NAME" "1 tx_ciccomp_0002_ast " "Found entity 1: tx_ciccomp_0002_ast" { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613386 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613386 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/tx_ciccomp_0002.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tx_ciccomp/tx_ciccomp_0002.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tx_ciccomp_0002-syn " "Found design unit 1: tx_ciccomp_0002-syn" { } { { "tx_ciccomp/tx_ciccomp_0002.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002.vhd" 33 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613395 ""} { "Info" "ISGN_ENTITY_NAME" "1 tx_ciccomp_0002 " "Found entity 1: tx_ciccomp_0002" { } { { "tx_ciccomp/tx_ciccomp_0002.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002.vhd" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613395 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613395 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "diffclock_buff.v 2 2 " "Found 2 design units, including 2 entities, in source file diffclock_buff.v" { { "Info" "ISGN_ENTITY_NAME" "1 diffclock_buff_iobuf_in_k0j " "Found entity 1: diffclock_buff_iobuf_in_k0j" { } { { "diffclock_buff.v" "" { Text "C:/FPGA/diffclock_buff.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613515 ""} { "Info" "ISGN_ENTITY_NAME" "2 diffclock_buff " "Found entity 2: diffclock_buff" { } { { "diffclock_buff.v" "" { Text "C:/FPGA/diffclock_buff.v" 82 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613515 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613515 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dcdc_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file dcdc_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 dcdc_pll " "Found entity 1: dcdc_pll" { } { { "dcdc_pll.v" "" { Text "C:/FPGA/dcdc_pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613545 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613545 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file tx_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_pll " "Found entity 1: tx_pll" { } { { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613569 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613569 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/clock_buffer/clock_buffer.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/clock_buffer/clock_buffer.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_buffer " "Found entity 1: clock_buffer" { } { { "db/ip/clock_buffer/clock_buffer.v" "" { Text "C:/FPGA/db/ip/clock_buffer/clock_buffer.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613582 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613582 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_buffer_altclkctrl_0_sub " "Found entity 1: clock_buffer_altclkctrl_0_sub" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613684 ""} { "Info" "ISGN_ENTITY_NAME" "2 clock_buffer_altclkctrl_0 " "Found entity 2: clock_buffer_altclkctrl_0" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 89 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613684 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613684 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/rx_cic.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/rx_cic.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_cic " "Found entity 1: rx_cic" { } { { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214613709 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214613709 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/alt_cic_core.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_core.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_core " "Found entity 1: alt_cic_core" { } { { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214614914 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214614914 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/alt_cic_dec_miso.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_dec_miso.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_dec_miso " "Found entity 1: alt_cic_dec_miso" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_miso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_miso.sv" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214615158 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214615158 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_dec_siso " "Found entity 1: alt_cic_dec_siso" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214615415 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214615415 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/alt_cic_int_simo.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_int_simo.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_int_simo " "Found entity 1: alt_cic_int_simo" { } { { "db/ip/rx_cic/submodules/alt_cic_int_simo.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_int_simo.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214615685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214615685 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/alt_cic_int_siso.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_int_siso.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_int_siso " "Found entity 1: alt_cic_int_siso" { } { { "db/ip/rx_cic/submodules/alt_cic_int_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_int_siso.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214615940 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214615940 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/alt_dsp_cic_common_pkg.sv 1 0 " "Found 1 design units, including 0 entities, in source file db/ip/rx_cic/submodules/alt_dsp_cic_common_pkg.sv" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alt_dsp_cic_common_pkg (SystemVerilog) (rx_cic) " "Found design unit 1: alt_dsp_cic_common_pkg (SystemVerilog) (rx_cic)" { } { { "db/ip/rx_cic/submodules/alt_dsp_cic_common_pkg.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_dsp_cic_common_pkg.sv" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214616154 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214616154 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_controller-struct " "Found design unit 1: auk_dspip_avalon_streaming_controller-struct" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" 53 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214616395 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_controller " "Found entity 1: auk_dspip_avalon_streaming_controller" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214616395 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214616395 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_sink-rtl " "Found design unit 1: auk_dspip_avalon_streaming_sink-rtl" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214616608 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_sink " "Found entity 1: auk_dspip_avalon_streaming_sink" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214616608 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214616608 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_small_fifo-arch " "Found design unit 1: auk_dspip_avalon_streaming_small_fifo-arch" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" 50 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214616803 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_small_fifo " "Found entity 1: auk_dspip_avalon_streaming_small_fifo" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214616803 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214616803 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_source-rtl " "Found design unit 1: auk_dspip_avalon_streaming_source-rtl" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 57 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214616990 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_source " "Found entity 1: auk_dspip_avalon_streaming_source" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214616990 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214616990 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_channel_buffer-SYN " "Found design unit 1: auk_dspip_channel_buffer-SYN" { } { { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 47 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214617181 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_channel_buffer " "Found entity 1: auk_dspip_channel_buffer" { } { { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214617181 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214617181 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_cic_lib_pkg.vhd 1 0 " "Found 1 design units, including 0 entities, in source file db/ip/rx_cic/submodules/auk_dspip_cic_lib_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_cic_lib_pkg (rx_cic) " "Found design unit 1: auk_dspip_cic_lib_pkg (rx_cic)" { } { { "db/ip/rx_cic/submodules/auk_dspip_cic_lib_pkg.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_cic_lib_pkg.vhd" 23 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214617383 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214617383 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_delay.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_delay.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_delay-rtl " "Found design unit 1: auk_dspip_delay-rtl" { } { { "db/ip/rx_cic/submodules/auk_dspip_delay.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_delay.vhd" 79 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214617402 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_delay " "Found entity 1: auk_dspip_delay" { } { { "db/ip/rx_cic/submodules/auk_dspip_delay.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_delay.vhd" 52 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214617402 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214617402 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_differentiator-SYN " "Found design unit 1: auk_dspip_differentiator-SYN" { } { { "db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214617604 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_differentiator " "Found entity 1: auk_dspip_differentiator" { } { { "db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd" 57 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214617604 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214617604 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_downsample.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_downsample.sv" { { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_downsample " "Found entity 1: auk_dspip_downsample" { } { { "db/ip/rx_cic/submodules/auk_dspip_downsample.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214617801 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214617801 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_fastadd-beh " "Found design unit 1: auk_dspip_fastadd-beh" { } { { "db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd" 36 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214617809 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_fastadd " "Found entity 1: auk_dspip_fastadd" { } { { "db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214617809 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214617809 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_fastaddsub-beh " "Found design unit 1: auk_dspip_fastaddsub-beh" { } { { "db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd" 87 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214617827 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_fastaddsub " "Found entity 1: auk_dspip_fastaddsub" { } { { "db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd" 69 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214617827 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214617827 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_integrator.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_integrator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_integrator-SYN " "Found design unit 1: auk_dspip_integrator-SYN" { } { { "db/ip/rx_cic/submodules/auk_dspip_integrator.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_integrator.vhd" 74 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618038 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_integrator " "Found entity 1: auk_dspip_integrator" { } { { "db/ip/rx_cic/submodules/auk_dspip_integrator.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_integrator.vhd" 53 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618038 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214618038 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd 1 0 " "Found 1 design units, including 0 entities, in source file db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_lib_pkg (rx_cic) " "Found design unit 1: auk_dspip_lib_pkg (rx_cic)" { } { { "db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd" 28 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618056 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214618056 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd 2 0 " "Found 2 design units, including 0 entities, in source file db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_math_pkg (rx_cic) " "Found design unit 1: auk_dspip_math_pkg (rx_cic)" { } { { "db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd" 51 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618077 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_dspip_math_pkg-body " "Found design unit 2: auk_dspip_math_pkg-body" { } { { "db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd" 128 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618077 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214618077 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_pipelined_adder-rtl " "Found design unit 1: auk_dspip_pipelined_adder-rtl" { } { { "db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd" 80 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618093 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_pipelined_adder " "Found entity 1: auk_dspip_pipelined_adder" { } { { "db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd" 57 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618093 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214618093 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_roundsat-beh " "Found design unit 1: auk_dspip_roundsat-beh" { } { { "db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd" 61 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618113 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_roundsat " "Found entity 1: auk_dspip_roundsat" { } { { "db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618113 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214618113 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd 2 0 " "Found 2 design units, including 0 entities, in source file db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_text_pkg (rx_cic) " "Found design unit 1: auk_dspip_text_pkg (rx_cic)" { } { { "db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd" 60 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618130 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_dspip_text_pkg-body " "Found design unit 2: auk_dspip_text_pkg-body" { } { { "db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd" 76 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618130 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214618130 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_upsample.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_upsample.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_upsample-SYN " "Found design unit 1: auk_dspip_upsample-SYN" { } { { "db/ip/rx_cic/submodules/auk_dspip_upsample.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_upsample.vhd" 59 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618367 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_upsample " "Found entity 1: auk_dspip_upsample" { } { { "db/ip/rx_cic/submodules/auk_dspip_upsample.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_upsample.vhd" 44 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618367 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214618367 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_variable_downsample.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_variable_downsample.sv" { { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_variable_downsample " "Found entity 1: auk_dspip_variable_downsample" { } { { "db/ip/rx_cic/submodules/auk_dspip_variable_downsample.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_variable_downsample.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618552 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214618552 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/counter_module.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/counter_module.sv" { { "Info" "ISGN_ENTITY_NAME" "1 counter_module " "Found entity 1: counter_module" { } { { "db/ip/rx_cic/submodules/counter_module.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/counter_module.sv" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618761 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214618761 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/hyper_pipeline_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/hyper_pipeline_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 hyper_pipeline_interface " "Found entity 1: hyper_pipeline_interface" { } { { "db/ip/rx_cic/submodules/hyper_pipeline_interface.v" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/hyper_pipeline_interface.v" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618965 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214618965 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rx_cic_cic_ii_0 " "Found entity 1: rx_cic_cic_ii_0" { } { { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214618992 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214618992 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/alt_cic_core.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_core.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_core " "Found entity 1: alt_cic_core" { } { { "db/ip/tx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214619255 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214619255 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/alt_cic_dec_miso.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_dec_miso.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_dec_miso " "Found entity 1: alt_cic_dec_miso" { } { { "db/ip/tx_cic/submodules/alt_cic_dec_miso.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_dec_miso.sv" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214619576 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214619576 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/alt_cic_dec_siso.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_dec_siso.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_dec_siso " "Found entity 1: alt_cic_dec_siso" { } { { "db/ip/tx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_dec_siso.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214619852 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214619852 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/alt_cic_int_simo.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_int_simo.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_int_simo " "Found entity 1: alt_cic_int_simo" { } { { "db/ip/tx_cic/submodules/alt_cic_int_simo.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_simo.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214620131 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214620131 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/alt_cic_int_siso.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_int_siso.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_int_siso " "Found entity 1: alt_cic_int_siso" { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214620365 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214620365 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/alt_dsp_cic_common_pkg.sv 1 0 " "Found 1 design units, including 0 entities, in source file db/ip/tx_cic/submodules/alt_dsp_cic_common_pkg.sv" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alt_dsp_cic_common_pkg (SystemVerilog) (tx_cic) " "Found design unit 1: alt_dsp_cic_common_pkg (SystemVerilog) (tx_cic)" { } { { "db/ip/tx_cic/submodules/alt_dsp_cic_common_pkg.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_dsp_cic_common_pkg.sv" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214620579 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214620579 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_controller-struct " "Found design unit 1: auk_dspip_avalon_streaming_controller-struct" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" 53 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214620799 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_controller " "Found entity 1: auk_dspip_avalon_streaming_controller" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214620799 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214620799 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_sink-rtl " "Found design unit 1: auk_dspip_avalon_streaming_sink-rtl" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214621012 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_sink " "Found entity 1: auk_dspip_avalon_streaming_sink" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214621012 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214621012 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_small_fifo-arch " "Found design unit 1: auk_dspip_avalon_streaming_small_fifo-arch" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" 50 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214621247 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_small_fifo " "Found entity 1: auk_dspip_avalon_streaming_small_fifo" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214621247 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214621247 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_source-rtl " "Found design unit 1: auk_dspip_avalon_streaming_source-rtl" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 57 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214621487 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_source " "Found entity 1: auk_dspip_avalon_streaming_source" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214621487 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214621487 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_channel_buffer-SYN " "Found design unit 1: auk_dspip_channel_buffer-SYN" { } { { "db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd" 47 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214621681 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_channel_buffer " "Found entity 1: auk_dspip_channel_buffer" { } { { "db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214621681 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214621681 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_cic_lib_pkg.vhd 1 0 " "Found 1 design units, including 0 entities, in source file db/ip/tx_cic/submodules/auk_dspip_cic_lib_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_cic_lib_pkg (tx_cic) " "Found design unit 1: auk_dspip_cic_lib_pkg (tx_cic)" { } { { "db/ip/tx_cic/submodules/auk_dspip_cic_lib_pkg.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_cic_lib_pkg.vhd" 23 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214621876 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214621876 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_delay.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_delay.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_delay-rtl " "Found design unit 1: auk_dspip_delay-rtl" { } { { "db/ip/tx_cic/submodules/auk_dspip_delay.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_delay.vhd" 79 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214621897 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_delay " "Found entity 1: auk_dspip_delay" { } { { "db/ip/tx_cic/submodules/auk_dspip_delay.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_delay.vhd" 52 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214621897 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214621897 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_differentiator-SYN " "Found design unit 1: auk_dspip_differentiator-SYN" { } { { "db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622102 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_differentiator " "Found entity 1: auk_dspip_differentiator" { } { { "db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd" 57 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622102 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214622102 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_downsample.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_downsample.sv" { { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_downsample " "Found entity 1: auk_dspip_downsample" { } { { "db/ip/tx_cic/submodules/auk_dspip_downsample.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_downsample.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622300 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214622300 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_fastadd-beh " "Found design unit 1: auk_dspip_fastadd-beh" { } { { "db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd" 36 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622309 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_fastadd " "Found entity 1: auk_dspip_fastadd" { } { { "db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622309 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214622309 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_fastaddsub-beh " "Found design unit 1: auk_dspip_fastaddsub-beh" { } { { "db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd" 87 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622317 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_fastaddsub " "Found entity 1: auk_dspip_fastaddsub" { } { { "db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd" 69 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622317 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214622317 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_integrator.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_integrator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_integrator-SYN " "Found design unit 1: auk_dspip_integrator-SYN" { } { { "db/ip/tx_cic/submodules/auk_dspip_integrator.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_integrator.vhd" 74 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622503 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_integrator " "Found entity 1: auk_dspip_integrator" { } { { "db/ip/tx_cic/submodules/auk_dspip_integrator.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_integrator.vhd" 53 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622503 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214622503 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd 1 0 " "Found 1 design units, including 0 entities, in source file db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_lib_pkg (tx_cic) " "Found design unit 1: auk_dspip_lib_pkg (tx_cic)" { } { { "db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd" 28 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622521 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214622521 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd 2 0 " "Found 2 design units, including 0 entities, in source file db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_math_pkg (tx_cic) " "Found design unit 1: auk_dspip_math_pkg (tx_cic)" { } { { "db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd" 51 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622538 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_dspip_math_pkg-body " "Found design unit 2: auk_dspip_math_pkg-body" { } { { "db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd" 128 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622538 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214622538 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_pipelined_adder-rtl " "Found design unit 1: auk_dspip_pipelined_adder-rtl" { } { { "db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd" 80 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622556 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_pipelined_adder " "Found entity 1: auk_dspip_pipelined_adder" { } { { "db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd" 57 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622556 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214622556 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_roundsat-beh " "Found design unit 1: auk_dspip_roundsat-beh" { } { { "db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd" 61 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622571 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_roundsat " "Found entity 1: auk_dspip_roundsat" { } { { "db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622571 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214622571 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd 2 0 " "Found 2 design units, including 0 entities, in source file db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_text_pkg (tx_cic) " "Found design unit 1: auk_dspip_text_pkg (tx_cic)" { } { { "db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd" 60 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622579 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_dspip_text_pkg-body " "Found design unit 2: auk_dspip_text_pkg-body" { } { { "db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd" 76 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622579 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214622579 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_upsample.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_upsample.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_upsample-SYN " "Found design unit 1: auk_dspip_upsample-SYN" { } { { "db/ip/tx_cic/submodules/auk_dspip_upsample.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_upsample.vhd" 59 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622762 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_upsample " "Found entity 1: auk_dspip_upsample" { } { { "db/ip/tx_cic/submodules/auk_dspip_upsample.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_upsample.vhd" 44 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622762 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214622762 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_variable_downsample.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_variable_downsample.sv" { { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_variable_downsample " "Found entity 1: auk_dspip_variable_downsample" { } { { "db/ip/tx_cic/submodules/auk_dspip_variable_downsample.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_variable_downsample.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214622956 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214622956 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/counter_module.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/counter_module.sv" { { "Info" "ISGN_ENTITY_NAME" "1 counter_module " "Found entity 1: counter_module" { } { { "db/ip/tx_cic/submodules/counter_module.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/counter_module.sv" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214623197 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214623197 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/hyper_pipeline_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/hyper_pipeline_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 hyper_pipeline_interface " "Found entity 1: hyper_pipeline_interface" { } { { "db/ip/tx_cic/submodules/hyper_pipeline_interface.v" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/hyper_pipeline_interface.v" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214623407 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214623407 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 tx_cic_cic_ii_0 " "Found entity 1: tx_cic_cic_ii_0" { } { { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214623444 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214623444 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/tx_cic.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/tx_cic.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_cic " "Found entity 1: tx_cic" { } { { "db/ip/tx_cic/tx_cic.v" "" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214623465 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214623465 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_altqmcpipe.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_altqmcpipe.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_altqmcpipe " "Found entity 1: asj_altqmcpipe" { } { { "db/ip/tx_nco/submodules/asj_altqmcpipe.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_altqmcpipe.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214624487 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214624487 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_gam_dp.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_gam_dp.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_gam_dp " "Found entity 1: asj_gam_dp" { } { { "db/ip/tx_nco/submodules/asj_gam_dp.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_gam_dp.v" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214624710 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214624710 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_as_m_cen " "Found entity 1: asj_nco_as_m_cen" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214624926 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214624926 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_as_m_dp_cen " "Found entity 1: asj_nco_as_m_dp_cen" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" 63 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214625175 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214625175 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_nco_derot.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_derot.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_derot " "Found entity 1: asj_nco_derot" { } { { "db/ip/tx_nco/submodules/asj_nco_derot.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_derot.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214625369 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214625369 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_nco_isdr.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_isdr.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_isdr " "Found entity 1: asj_nco_isdr" { } { { "db/ip/tx_nco/submodules/asj_nco_isdr.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_isdr.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214625589 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214625589 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_nco_madx_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_madx_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_madx_cen " "Found entity 1: asj_nco_madx_cen" { } { { "db/ip/tx_nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214625776 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214625776 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_nco_mady_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_mady_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_mady_cen " "Found entity 1: asj_nco_mady_cen" { } { { "db/ip/tx_nco/submodules/asj_nco_mady_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mady_cen.v" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214625983 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214625983 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_nco_mob_w.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_mob_w.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_mob_w " "Found entity 1: asj_nco_mob_w" { } { { "db/ip/tx_nco/submodules/asj_nco_mob_w.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mob_w.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214626177 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214626177 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_nco_nco_ii_0 " "Found entity 1: tx_nco_nco_ii_0" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214626213 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214626213 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/tx_nco.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/tx_nco.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_nco " "Found entity 1: tx_nco" { } { { "db/ip/tx_nco/tx_nco.v" "" { Text "C:/FPGA/db/ip/tx_nco/tx_nco.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214626231 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214626231 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/nco.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/nco.v" { { "Info" "ISGN_ENTITY_NAME" "1 nco " "Found entity 1: nco" { } { { "db/ip/nco/nco.v" "" { Text "C:/FPGA/db/ip/nco/nco.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214626271 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214626271 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_altqmcpipe.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_altqmcpipe.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_altqmcpipe " "Found entity 1: asj_altqmcpipe" { } { { "db/ip/nco/submodules/asj_altqmcpipe.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_altqmcpipe.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214626460 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214626460 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_gam_dp.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_gam_dp.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_gam_dp " "Found entity 1: asj_gam_dp" { } { { "db/ip/nco/submodules/asj_gam_dp.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_gam_dp.v" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214626682 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214626682 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_nco_as_m_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_as_m_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_as_m_cen " "Found entity 1: asj_nco_as_m_cen" { } { { "db/ip/nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214626906 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214626906 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_nco_as_m_dp_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_as_m_dp_cen " "Found entity 1: asj_nco_as_m_dp_cen" { } { { "db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" 63 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214627132 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214627132 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_nco_derot.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_derot.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_derot " "Found entity 1: asj_nco_derot" { } { { "db/ip/nco/submodules/asj_nco_derot.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_derot.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214627329 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214627329 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_nco_isdr.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_isdr.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_isdr " "Found entity 1: asj_nco_isdr" { } { { "db/ip/nco/submodules/asj_nco_isdr.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_isdr.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214627531 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214627531 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_nco_madx_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_madx_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_madx_cen " "Found entity 1: asj_nco_madx_cen" { } { { "db/ip/nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214627734 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214627734 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_nco_mady_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_mady_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_mady_cen " "Found entity 1: asj_nco_mady_cen" { } { { "db/ip/nco/submodules/asj_nco_mady_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mady_cen.v" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214627937 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214627937 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_nco_mob_w.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_mob_w.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_mob_w " "Found entity 1: asj_nco_mob_w" { } { { "db/ip/nco/submodules/asj_nco_mob_w.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mob_w.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214628138 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214628138 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/nco_nco_ii_0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/nco_nco_ii_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 nco_nco_ii_0 " "Found entity 1: nco_nco_ii_0" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214628172 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214628172 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/debug/debug.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/debug/debug.v" { { "Info" "ISGN_ENTITY_NAME" "1 DEBUG " "Found entity 1: DEBUG" { } { { "db/ip/debug/debug.v" "" { Text "C:/FPGA/db/ip/debug/debug.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214628190 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214628190 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/debug/submodules/altsource_probe_top.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/debug/submodules/altsource_probe_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 altsource_probe_top " "Found entity 1: altsource_probe_top" { } { { "db/ip/debug/submodules/altsource_probe_top.v" "" { Text "C:/FPGA/db/ip/debug/submodules/altsource_probe_top.v" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214628209 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214628209 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/debug2/debug2.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/debug2/debug2.v" { { "Info" "ISGN_ENTITY_NAME" "1 DEBUG2 " "Found entity 1: DEBUG2" { } { { "db/ip/debug2/debug2.v" "" { Text "C:/FPGA/db/ip/debug2/debug2.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214628229 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214628229 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/debug2/submodules/altsource_probe_top.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/debug2/submodules/altsource_probe_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 altsource_probe_top " "Found entity 1: altsource_probe_top" { } { { "db/ip/debug2/submodules/altsource_probe_top.v" "" { Text "C:/FPGA/db/ip/debug2/submodules/altsource_probe_top.v" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214628252 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214628252 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "WOLF-LITE " "Elaborating entity \"WOLF-LITE\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1617214632573 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "stm32_interface stm32_interface:STM32_INTERFACE " "Elaborating entity \"stm32_interface\" for hierarchy \"stm32_interface:STM32_INTERFACE\"" { } { { "WOLF-LITE.bdf" "STM32_INTERFACE" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 144 3088 3376 704 "STM32_INTERFACE" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214632695 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_summator tx_summator:TX_SUMMATOR " "Elaborating entity \"tx_summator\" for hierarchy \"tx_summator:TX_SUMMATOR\"" { } { { "WOLF-LITE.bdf" "TX_SUMMATOR" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 5544 5704 280 "TX_SUMMATOR" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214633192 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component " "Elaborating entity \"lpm_add_sub\" for hierarchy \"tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component\"" { } { { "tx_summator.v" "LPM_ADD_SUB_component" { Text "C:/FPGA/tx_summator.v" 73 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214633566 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component " "Elaborated megafunction instantiation \"tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component\"" { } { { "tx_summator.v" "" { Text "C:/FPGA/tx_summator.v" 73 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214633626 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component " "Instantiated megafunction \"tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Parameter \"lpm_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214633627 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO " "Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214633627 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214633627 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Parameter \"lpm_representation\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214633627 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214633627 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 32 " "Parameter \"lpm_width\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214633627 ""} } { { "tx_summator.v" "" { Text "C:/FPGA/tx_summator.v" 73 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214633627 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_1vk.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_1vk.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_1vk " "Found entity 1: add_sub_1vk" { } { { "db/add_sub_1vk.tdf" "" { Text "C:/FPGA/db/add_sub_1vk.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214633821 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214633821 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_1vk tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component\|add_sub_1vk:auto_generated " "Elaborating entity \"add_sub_1vk\" for hierarchy \"tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component\|add_sub_1vk:auto_generated\"" { } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214633838 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_pll tx_pll:TX_PLL " "Elaborating entity \"tx_pll\" for hierarchy \"tx_pll:TX_PLL\"" { } { { "WOLF-LITE.bdf" "TX_PLL" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 720 3080 3320 872 "TX_PLL" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214634005 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll tx_pll:TX_PLL\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"tx_pll:TX_PLL\|altpll:altpll_component\"" { } { { "tx_pll.v" "altpll_component" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214634379 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_pll:TX_PLL\|altpll:altpll_component " "Elaborated megafunction instantiation \"tx_pll:TX_PLL\|altpll:altpll_component\"" { } { { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214634431 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_pll:TX_PLL\|altpll:altpll_component " "Instantiated megafunction \"tx_pll:TX_PLL\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2 " "Parameter \"clk0_divide_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 5 " "Parameter \"clk0_multiply_by\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 16276 " "Parameter \"inclk0_input_frequency\" = \"16276\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=tx_pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=tx_pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_UNUSED " "Parameter \"port_clk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214634432 ""} } { { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214634432 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/tx_pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/tx_pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_pll_altpll " "Found entity 1: tx_pll_altpll" { } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214634623 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214634623 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_pll_altpll tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated " "Elaborating entity \"tx_pll_altpll\" for hierarchy \"tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214634643 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_buffer clock_buffer:SYSCLK_BUFFER " "Elaborating entity \"clock_buffer\" for hierarchy \"clock_buffer:SYSCLK_BUFFER\"" { } { { "WOLF-LITE.bdf" "SYSCLK_BUFFER" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 624 2416 2688 728 "SYSCLK_BUFFER" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214634770 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_buffer_altclkctrl_0 clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0 " "Elaborating entity \"clock_buffer_altclkctrl_0\" for hierarchy \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\"" { } { { "db/ip/clock_buffer/clock_buffer.v" "altclkctrl_0" { Text "C:/FPGA/db/ip/clock_buffer/clock_buffer.v" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214634822 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_buffer_altclkctrl_0_sub clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component " "Elaborating entity \"clock_buffer_altclkctrl_0_sub\" for hierarchy \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\"" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "clock_buffer_altclkctrl_0_sub_component" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 112 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214634869 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_mixer tx_mixer:TX_MIXER_I " "Elaborating entity \"tx_mixer\" for hierarchy \"tx_mixer:TX_MIXER_I\"" { } { { "WOLF-LITE.bdf" "TX_MIXER_I" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 56 5272 5440 184 "TX_MIXER_I" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214634934 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component " "Elaborating entity \"lpm_mult\" for hierarchy \"tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\"" { } { { "tx_mixer.v" "lpm_mult_component" { Text "C:/FPGA/tx_mixer.v" 63 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214635309 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\"" { } { { "tx_mixer.v" "" { Text "C:/FPGA/tx_mixer.v" 63 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214635351 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component " "Instantiated megafunction \"tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9 " "Parameter \"lpm_hint\" = \"DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214635352 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214635352 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Parameter \"lpm_representation\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214635352 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MULT " "Parameter \"lpm_type\" = \"LPM_MULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214635352 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widtha 16 " "Parameter \"lpm_widtha\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214635352 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthb 16 " "Parameter \"lpm_widthb\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214635352 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthp 32 " "Parameter \"lpm_widthp\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214635352 ""} } { { "tx_mixer.v" "" { Text "C:/FPGA/tx_mixer.v" 63 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214635352 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_abt.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_abt.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_abt " "Found entity 1: mult_abt" { } { { "db/mult_abt.tdf" "" { Text "C:/FPGA/db/mult_abt.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214635531 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214635531 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_abt tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_abt:auto_generated " "Elaborating entity \"mult_abt\" for hierarchy \"tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_abt:auto_generated\"" { } { { "lpm_mult.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 376 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214635549 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_cic tx_cic:TX_CIC_I " "Elaborating entity \"tx_cic\" for hierarchy \"tx_cic:TX_CIC_I\"" { } { { "WOLF-LITE.bdf" "TX_CIC_I" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -40 4928 5184 192 "TX_CIC_I" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214635675 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_cic_cic_ii_0 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0 " "Elaborating entity \"tx_cic_cic_ii_0\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\"" { } { { "db/ip/tx_cic/tx_cic.v" "cic_ii_0" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 31 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214635739 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_cic_core tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core " "Elaborating entity \"alt_cic_core\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\"" { } { { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "core" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214635906 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_sink tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink " "Elaborating entity \"auk_dspip_avalon_streaming_sink\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\"" { } { { "db/ip/tx_cic/submodules/alt_cic_core.sv" "input_sink" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214636170 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\"" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "sink_FIFO" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214637018 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO " "Elaborated megafunction instantiation \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\"" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214637045 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO " "Instantiated megafunction \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Parameter \"add_ram_output_register\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214637045 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "allow_rwcycle_when_full OFF " "Parameter \"allow_rwcycle_when_full\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214637045 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_empty_value 4 " "Parameter \"almost_empty_value\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214637045 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_full_value 0 " "Parameter \"almost_full_value\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214637045 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 8 " "Parameter \"lpm_numwords\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214637045 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214637045 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 18 " "Parameter \"lpm_width\" = \"18\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214637045 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 3 " "Parameter \"lpm_widthu\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214637045 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214637045 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214637045 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214637045 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214637045 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214637045 ""} } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214637045 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_gf71.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_gf71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_gf71 " "Found entity 1: scfifo_gf71" { } { { "db/scfifo_gf71.tdf" "" { Text "C:/FPGA/db/scfifo_gf71.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214637258 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214637258 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_gf71 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated " "Elaborating entity \"scfifo_gf71\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214637283 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_1lv.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_1lv.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_1lv " "Found entity 1: a_dpfifo_1lv" { } { { "db/a_dpfifo_1lv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214637395 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214637395 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_1lv tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo " "Elaborating entity \"a_dpfifo_1lv\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\"" { } { { "db/scfifo_gf71.tdf" "dpfifo" { Text "C:/FPGA/db/scfifo_gf71.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214637431 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_l7h1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_l7h1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_l7h1 " "Found entity 1: altsyncram_l7h1" { } { { "db/altsyncram_l7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_l7h1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214637638 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214637638 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_l7h1 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram " "Elaborating entity \"altsyncram_l7h1\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\"" { } { { "db/a_dpfifo_1lv.tdf" "FIFOram" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214637683 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_gs8.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_gs8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_gs8 " "Found entity 1: cmpr_gs8" { } { { "db/cmpr_gs8.tdf" "" { Text "C:/FPGA/db/cmpr_gs8.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214637856 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214637856 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_gs8 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cmpr_gs8:almost_full_comparer " "Elaborating entity \"cmpr_gs8\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cmpr_gs8:almost_full_comparer\"" { } { { "db/a_dpfifo_1lv.tdf" "almost_full_comparer" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 52 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214637902 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_gs8 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cmpr_gs8:two_comparison " "Elaborating entity \"cmpr_gs8\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cmpr_gs8:two_comparison\"" { } { { "db/a_dpfifo_1lv.tdf" "two_comparison" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 53 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214637991 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_r9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_r9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_r9b " "Found entity 1: cntr_r9b" { } { { "db/cntr_r9b.tdf" "" { Text "C:/FPGA/db/cntr_r9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214638164 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214638164 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_r9b tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cntr_r9b:rd_ptr_msb " "Elaborating entity \"cntr_r9b\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cntr_r9b:rd_ptr_msb\"" { } { { "db/a_dpfifo_1lv.tdf" "rd_ptr_msb" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 54 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214638213 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_8a7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_8a7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_8a7 " "Found entity 1: cntr_8a7" { } { { "db/cntr_8a7.tdf" "" { Text "C:/FPGA/db/cntr_8a7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214638372 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214638372 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_8a7 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cntr_8a7:usedw_counter " "Elaborating entity \"cntr_8a7\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cntr_8a7:usedw_counter\"" { } { { "db/a_dpfifo_1lv.tdf" "usedw_counter" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 55 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214638416 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_s9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_s9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_s9b " "Found entity 1: cntr_s9b" { } { { "db/cntr_s9b.tdf" "" { Text "C:/FPGA/db/cntr_s9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214638574 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214638574 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_s9b tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cntr_s9b:wr_ptr " "Elaborating entity \"cntr_s9b\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cntr_s9b:wr_ptr\"" { } { { "db/a_dpfifo_1lv.tdf" "wr_ptr" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 56 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214638622 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_source tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0 " "Elaborating entity \"auk_dspip_avalon_streaming_source\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\"" { } { { "db/ip/tx_cic/submodules/alt_cic_core.sv" "output_source_0" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 358 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214638849 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\"" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "source_FIFO" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214639320 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO " "Elaborated megafunction instantiation \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\"" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214639354 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO " "Instantiated megafunction \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Parameter \"add_ram_output_register\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214639355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "allow_rwcycle_when_full OFF " "Parameter \"allow_rwcycle_when_full\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214639355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_empty_value 0 " "Parameter \"almost_empty_value\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214639355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_full_value 13 " "Parameter \"almost_full_value\" = \"13\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214639355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 21 " "Parameter \"lpm_numwords\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214639355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214639355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 17 " "Parameter \"lpm_width\" = \"17\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214639355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 5 " "Parameter \"lpm_widthu\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214639355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214639355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214639355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214639355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214639355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214639355 ""} } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214639355 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_ci71.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_ci71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_ci71 " "Found entity 1: scfifo_ci71" { } { { "db/scfifo_ci71.tdf" "" { Text "C:/FPGA/db/scfifo_ci71.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214639550 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214639550 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_ci71 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated " "Elaborating entity \"scfifo_ci71\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214639574 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_9qv.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_9qv.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_9qv " "Found entity 1: a_dpfifo_9qv" { } { { "db/a_dpfifo_9qv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214639679 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214639679 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_9qv tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo " "Elaborating entity \"a_dpfifo_9qv\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\"" { } { { "db/scfifo_ci71.tdf" "dpfifo" { Text "C:/FPGA/db/scfifo_ci71.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214639711 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_hah1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_hah1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_hah1 " "Found entity 1: altsyncram_hah1" { } { { "db/altsyncram_hah1.tdf" "" { Text "C:/FPGA/db/altsyncram_hah1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214639869 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214639869 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_hah1 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|altsyncram_hah1:FIFOram " "Elaborating entity \"altsyncram_hah1\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|altsyncram_hah1:FIFOram\"" { } { { "db/a_dpfifo_9qv.tdf" "FIFOram" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214639918 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_is8.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_is8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_is8 " "Found entity 1: cmpr_is8" { } { { "db/cmpr_is8.tdf" "" { Text "C:/FPGA/db/cmpr_is8.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214640090 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214640090 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_is8 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cmpr_is8:almost_full_comparer " "Elaborating entity \"cmpr_is8\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cmpr_is8:almost_full_comparer\"" { } { { "db/a_dpfifo_9qv.tdf" "almost_full_comparer" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 52 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214640139 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_is8 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cmpr_is8:two_comparison " "Elaborating entity \"cmpr_is8\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cmpr_is8:two_comparison\"" { } { { "db/a_dpfifo_9qv.tdf" "two_comparison" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 53 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214640230 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_t9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_t9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_t9b " "Found entity 1: cntr_t9b" { } { { "db/cntr_t9b.tdf" "" { Text "C:/FPGA/db/cntr_t9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214640401 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214640401 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_t9b tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cntr_t9b:rd_ptr_msb " "Elaborating entity \"cntr_t9b\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cntr_t9b:rd_ptr_msb\"" { } { { "db/a_dpfifo_9qv.tdf" "rd_ptr_msb" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 54 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214640453 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_aa7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_aa7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_aa7 " "Found entity 1: cntr_aa7" { } { { "db/cntr_aa7.tdf" "" { Text "C:/FPGA/db/cntr_aa7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214640604 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214640604 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_aa7 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cntr_aa7:usedw_counter " "Elaborating entity \"cntr_aa7\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cntr_aa7:usedw_counter\"" { } { { "db/a_dpfifo_9qv.tdf" "usedw_counter" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 55 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214640654 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_u9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_u9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_u9b " "Found entity 1: cntr_u9b" { } { { "db/cntr_u9b.tdf" "" { Text "C:/FPGA/db/cntr_u9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214640817 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214640817 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_u9b tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cntr_u9b:wr_ptr " "Elaborating entity \"cntr_u9b\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cntr_u9b:wr_ptr\"" { } { { "db/a_dpfifo_9qv.tdf" "wr_ptr" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 56 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214640858 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_controller tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller " "Elaborating entity \"auk_dspip_avalon_streaming_controller\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller\"" { } { { "db/ip/tx_cic/submodules/alt_cic_core.sv" "avalon_controller" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 408 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214641093 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_small_fifo tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller\|auk_dspip_avalon_streaming_small_fifo:ready_FIFO " "Elaborating entity \"auk_dspip_avalon_streaming_small_fifo\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller\|auk_dspip_avalon_streaming_small_fifo:ready_FIFO\"" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" "ready_FIFO" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" 196 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214641332 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_cic_int_siso tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one " "Elaborating entity \"alt_cic_int_siso\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\"" { } { { "db/ip/tx_cic/submodules/alt_cic_core.sv" "int_one" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 540 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214641632 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_module tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|counter_module:latency_cnt_inst " "Elaborating entity \"counter_module\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|counter_module:latency_cnt_inst\"" { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "latency_cnt_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 270 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214641962 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_module tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|counter_module:counter_fs_inst " "Elaborating entity \"counter_module\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|counter_module:counter_fs_inst\"" { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "counter_fs_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 298 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214642228 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_module tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|counter_module:counter_ch_inst " "Elaborating entity \"counter_module\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|counter_module:counter_ch_inst\"" { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "counter_ch_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 313 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214642396 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_differentiator tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_differentiator:COMB_LOOP\[0\].auk_dsp_diff " "Elaborating entity \"auk_dspip_differentiator\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_differentiator:COMB_LOOP\[0\].auk_dsp_diff\"" { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "COMB_LOOP\[0\].auk_dsp_diff" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 361 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214642558 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_delay tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_differentiator:COMB_LOOP\[0\].auk_dsp_diff\|auk_dspip_delay:\\glogic:u0 " "Elaborating entity \"auk_dspip_delay\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_differentiator:COMB_LOOP\[0\].auk_dsp_diff\|auk_dspip_delay:\\glogic:u0\"" { } { { "db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd" "\\glogic:u0" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd" 135 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214642726 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_upsample tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_upsample:first_upsample " "Elaborating entity \"auk_dspip_upsample\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_upsample:first_upsample\"" { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "first_upsample" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 379 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214643696 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_integrator tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_integrator:integrator_loop\[0\].auK_integrator " "Elaborating entity \"auk_dspip_integrator\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_integrator:integrator_loop\[0\].auK_integrator\"" { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "integrator_loop\[0\].auK_integrator" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 408 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214643912 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_shifter data_shifter:TX_CICCOMP_GAINER " "Elaborating entity \"data_shifter\" for hierarchy \"data_shifter:TX_CICCOMP_GAINER\"" { } { { "WOLF-LITE.bdf" "TX_CICCOMP_GAINER" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 224 4464 4768 368 "TX_CICCOMP_GAINER" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214644985 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 data_shifter.v(18) " "Verilog HDL assignment warning at data_shifter.v(18): truncated value with size 32 to match size of target (1)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1617214644987 "|WOLF-LITE|data_shifter:TX_CICCOMP_GAINER"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 data_shifter.v(19) " "Verilog HDL assignment warning at data_shifter.v(19): truncated value with size 32 to match size of target (1)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 19 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1617214644987 "|WOLF-LITE|data_shifter:TX_CICCOMP_GAINER"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 data_shifter.v(20) " "Verilog HDL assignment warning at data_shifter.v(20): truncated value with size 32 to match size of target (16)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1617214644988 "|WOLF-LITE|data_shifter:TX_CICCOMP_GAINER"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 data_shifter.v(21) " "Verilog HDL assignment warning at data_shifter.v(21): truncated value with size 32 to match size of target (16)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 21 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1617214644988 "|WOLF-LITE|data_shifter:TX_CICCOMP_GAINER"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_ciccomp tx_ciccomp:TX_CICCOMP_I " "Elaborating entity \"tx_ciccomp\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\"" { } { { "WOLF-LITE.bdf" "TX_CICCOMP_I" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 24 3968 4352 240 "TX_CICCOMP_I" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214645026 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_ciccomp_0002 tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst " "Elaborating entity \"tx_ciccomp_0002\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\"" { } { { "tx_ciccomp.v" "tx_ciccomp_inst" { Text "C:/FPGA/tx_ciccomp.v" 28 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214645068 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "coeff_in_read_sig tx_ciccomp_0002.vhd(54) " "Verilog HDL or VHDL warning at tx_ciccomp_0002.vhd(54): object \"coeff_in_read_sig\" assigned a value but never read" { } { { "tx_ciccomp/tx_ciccomp_0002.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002.vhd" 54 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "Analysis & Synthesis" 0 -1 1617214645069 "|WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_ciccomp_0002_ast tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst " "Elaborating entity \"tx_ciccomp_0002_ast\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\"" { } { { "tx_ciccomp/tx_ciccomp_0002.vhd" "tx_ciccomp_0002_ast_inst" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002.vhd" 62 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214645120 ""} -{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "core_channel_out_core tx_ciccomp_0002_ast.vhd(208) " "VHDL Signal Declaration warning at tx_ciccomp_0002_ast.vhd(208): used implicit default value for signal \"core_channel_out_core\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 208 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 1 0 "Analysis & Synthesis" 0 -1 1617214645128 "|WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_sink_hpfir tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_sink_hpfir:sink " "Elaborating entity \"auk_dspip_avalon_streaming_sink_hpfir\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_sink_hpfir:sink\"" { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "sink" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 89 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214645184 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_source_hpfir tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source " "Elaborating entity \"auk_dspip_avalon_streaming_source_hpfir\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\"" { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "source" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 109 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214645250 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_controller_hpfir tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_controller_hpfir:intf_ctrl " "Elaborating entity \"auk_dspip_avalon_streaming_controller_hpfir\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_controller_hpfir:intf_ctrl\"" { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "intf_ctrl" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 137 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214645313 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_ciccomp_0002_rtl_core tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core " "Elaborating entity \"tx_ciccomp_0002_rtl_core\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\"" { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "\\real_passthrough:hpfircore_core" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214645349 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_memread " "Elaborating entity \"dspba_delay\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_memread\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_memread" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 175 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214645452 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_compute " "Elaborating entity \"dspba_delay\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_compute\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_compute" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214645499 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_xIn_0_13 " "Elaborating entity \"dspba_delay\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_xIn_0_13\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "d_xIn_0_13" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214645573 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13 " "Elaborating entity \"dspba_delay\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "d_in0_m0_wi0_wo0_assign_id1_q_13" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 291 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214645627 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem " "Elaborating entity \"altsyncram\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_wi0_r0_memr0_dmem" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 313 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214646122 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem " "Elaborated megafunction instantiation \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 313 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214646164 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem " "Instantiated megafunction \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a UNUSED " "Parameter \"address_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_aclr_a UNUSED " "Parameter \"byteena_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_aclr_b NONE " "Parameter \"byteena_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_reg_b CLOCK0 " "Parameter \"byteena_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_core_a USE_INPUT_CLKEN " "Parameter \"clock_enable_core_a\" = \"USE_INPUT_CLKEN\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_core_b USE_INPUT_CLKEN " "Parameter \"clock_enable_core_b\" = \"USE_INPUT_CLKEN\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a NORMAL " "Parameter \"clock_enable_input_a\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b NORMAL " "Parameter \"clock_enable_input_b\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a NORMAL " "Parameter \"clock_enable_output_a\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b NORMAL " "Parameter \"clock_enable_output_b\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ecc_pipeline_stage_enabled FALSE " "Parameter \"ecc_pipeline_stage_enabled\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "enable_ecc FALSE " "Parameter \"enable_ecc\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "implement_in_les OFF " "Parameter \"implement_in_les\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a UNUSED " "Parameter \"indata_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Parameter \"init_file\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file_layout PORT_A " "Parameter \"init_file_layout\" = \"PORT_A\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 64 " "Parameter \"numwords_a\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 64 " "Parameter \"numwords_b\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type M9K " "Parameter \"ram_block_type\" = \"M9K\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_aclr_b NONE " "Parameter \"rdcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "stratixiv_m144k_allow_dual_clocks ON " "Parameter \"stratixiv_m144k_allow_dual_clocks\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_eccstatus 3 " "Parameter \"width_eccstatus\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 6 " "Parameter \"widthad_a\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 6 " "Parameter \"widthad_b\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a UNUSED " "Parameter \"wrcontrol_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646165 ""} } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 313 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214646165 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0mn3.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0mn3.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0mn3 " "Found entity 1: altsyncram_0mn3" { } { { "db/altsyncram_0mn3.tdf" "" { Text "C:/FPGA/db/altsyncram_0mn3.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214646395 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214646395 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0mn3 tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\|altsyncram_0mn3:auto_generated " "Elaborating entity \"altsyncram_0mn3\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\|altsyncram_0mn3:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214646417 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component " "Elaborating entity \"lpm_mult\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_mtree_mult1_0_component" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 446 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214646630 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component " "Elaborated megafunction instantiation \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 446 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214646659 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component " "Instantiated megafunction \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 8 " "Parameter \"LPM_WIDTHA\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 16 " "Parameter \"LPM_WIDTHB\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 24 " "Parameter \"LPM_WIDTHP\" = \"24\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_PIPELINE 2 " "Parameter \"LPM_PIPELINE\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_MULT " "Parameter \"LPM_TYPE\" = \"LPM_MULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5 " "Parameter \"LPM_HINT\" = \"DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214646659 ""} } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 446 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214646659 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_ncu.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_ncu.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_ncu " "Found entity 1: mult_ncu" { } { { "db/mult_ncu.tdf" "" { Text "C:/FPGA/db/mult_ncu.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214646825 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214646825 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_ncu tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component\|mult_ncu:auto_generated " "Elaborating entity \"mult_ncu\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component\|mult_ncu:auto_generated\"" { } { { "lpm_mult.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 376 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214646841 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16 " "Elaborating entity \"dspba_delay\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "d_u0_m0_wo0_mtree_mult1_0_q_16" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 502 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214646979 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17 " "Elaborating entity \"dspba_delay\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "d_u0_m0_wo0_accum_p1_of_2_q_17" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 537 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214647028 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_roundsat_hpfir tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_roundsat_hpfir:\\real_passthrough:gen_outp_blk:0:outp_blk " "Elaborating entity \"auk_dspip_roundsat_hpfir\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_roundsat_hpfir:\\real_passthrough:gen_outp_blk:0:outp_blk\"" { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "\\real_passthrough:gen_outp_blk:0:outp_blk" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 244 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214647088 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_nco tx_nco:TX_NCO " "Elaborating entity \"tx_nco\" for hierarchy \"tx_nco:TX_NCO\"" { } { { "WOLF-LITE.bdf" "TX_NCO" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 632 3792 4048 832 "TX_NCO" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214647806 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_nco_nco_ii_0 tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0 " "Elaborating entity \"tx_nco_nco_ii_0\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\"" { } { { "db/ip/tx_nco/tx_nco.v" "nco_ii_0" { Text "C:/FPGA/db/ip/tx_nco/tx_nco.v" 24 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214647879 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_altqmcpipe tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000 " "Elaborating entity \"asj_altqmcpipe\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "ux000" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 304 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214648061 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc " "Elaborating entity \"lpm_add_sub\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\"" { } { { "db/ip/tx_nco/submodules/asj_altqmcpipe.v" "acc" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_altqmcpipe.v" 63 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214648274 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\"" { } { { "db/ip/tx_nco/submodules/asj_altqmcpipe.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_altqmcpipe.v" 63 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214648317 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Parameter \"lpm_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214648317 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 22 " "Parameter \"lpm_width\" = \"22\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214648317 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214648317 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation UNSIGNED " "Parameter \"lpm_representation\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214648317 ""} } { { "db/ip/tx_nco/submodules/asj_altqmcpipe.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_altqmcpipe.v" 63 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214648317 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_u4i.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_u4i.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_u4i " "Found entity 1: add_sub_u4i" { } { { "db/add_sub_u4i.tdf" "" { Text "C:/FPGA/db/add_sub_u4i.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214648506 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214648506 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_u4i tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_u4i:auto_generated " "Elaborating entity \"add_sub_u4i\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_u4i:auto_generated\"" { } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214648532 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_gam_dp tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_gam_dp:ux008 " "Elaborating entity \"asj_gam_dp\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_gam_dp:ux008\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "ux008" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214648770 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_dp_cen tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220 " "Elaborating entity \"asj_nco_as_m_dp_cen\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "ux0220" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 338 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214649108 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\"" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" "altsyncram_component" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" 109 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214649314 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\"" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" 109 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214649360 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 11 " "Parameter \"widthad_b\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 2048 " "Parameter \"numwords_b\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file tx_nco_nco_ii_0_sin_c.hex " "Parameter \"init_file\" = \"tx_nco_nco_ii_0_sin_c.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214649361 ""} } { { "db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" 109 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214649361 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4k82.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4k82.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4k82 " "Found entity 1: altsyncram_4k82" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214649596 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214649596 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4k82 tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated " "Elaborating entity \"altsyncram_4k82\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214649624 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_cen tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122 " "Elaborating entity \"asj_nco_as_m_cen\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "ux0122" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 350 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214650592 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Elaborating entity \"altsyncram\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\"" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" "altsyncram_component0" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214650796 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\"" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214650836 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214650836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214650836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214650836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214650836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214650836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214650836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214650836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214650836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214650836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214650836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file tx_nco_nco_ii_0_sin_f.hex " "Parameter \"init_file\" = \"tx_nco_nco_ii_0_sin_f.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214650836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214650836 ""} } { { "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214650836 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_u8a1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_u8a1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_u8a1 " "Found entity 1: altsyncram_u8a1" { } { { "db/altsyncram_u8a1.tdf" "" { Text "C:/FPGA/db/altsyncram_u8a1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214651070 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214651070 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_u8a1 tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_u8a1:auto_generated " "Elaborating entity \"altsyncram_u8a1\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_u8a1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214651101 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_cen tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123 " "Elaborating entity \"asj_nco_as_m_cen\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "ux0123" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 362 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214651991 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Elaborating entity \"altsyncram\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\"" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" "altsyncram_component0" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214652116 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\"" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214652158 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214652159 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214652159 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214652159 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214652159 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214652159 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214652159 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214652159 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214652159 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214652159 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214652159 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file tx_nco_nco_ii_0_cos_f.hex " "Parameter \"init_file\" = \"tx_nco_nco_ii_0_cos_f.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214652159 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214652159 ""} } { { "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214652159 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_p8a1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_p8a1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_p8a1 " "Found entity 1: altsyncram_p8a1" { } { { "db/altsyncram_p8a1.tdf" "" { Text "C:/FPGA/db/altsyncram_p8a1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214652385 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214652385 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_p8a1 tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\|altsyncram_p8a1:auto_generated " "Elaborating entity \"altsyncram_p8a1\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\|altsyncram_p8a1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214652415 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_madx_cen tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1 " "Elaborating entity \"asj_nco_madx_cen\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "m1" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 377 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214653323 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_mady_cen tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0 " "Elaborating entity \"asj_nco_mady_cen\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "m0" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 389 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214653649 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_derot tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_derot:ux0136 " "Elaborating entity \"asj_nco_derot\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_derot:ux0136\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "ux0136" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 402 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214653959 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_mob_w tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0 " "Elaborating entity \"asj_nco_mob_w\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "blk0" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 410 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214654228 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Elaborating entity \"lpm_add_sub\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\"" { } { { "db/ip/tx_nco/submodules/asj_nco_mob_w.v" "lpm_add_sub_component" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mob_w.v" 75 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214654426 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\"" { } { { "db/ip/tx_nco/submodules/asj_nco_mob_w.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mob_w.v" 75 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214654464 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 16 " "Parameter \"lpm_width\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214654464 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Parameter \"lpm_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214654464 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214654464 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO " "Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214654464 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214654464 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Parameter \"lpm_representation\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214654464 ""} } { { "db/ip/tx_nco/submodules/asj_nco_mob_w.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mob_w.v" 75 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214654464 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_jpk.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_jpk.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_jpk " "Found entity 1: add_sub_jpk" { } { { "db/add_sub_jpk.tdf" "" { Text "C:/FPGA/db/add_sub_jpk.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214654681 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214654681 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_jpk tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\|add_sub_jpk:auto_generated " "Elaborating entity \"add_sub_jpk\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\|add_sub_jpk:auto_generated\"" { } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214654709 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_isdr tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr " "Elaborating entity \"asj_nco_isdr\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "ux710isdr" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 428 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214655238 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Elaborating entity \"lpm_counter\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\"" { } { { "db/ip/tx_nco/submodules/asj_nco_isdr.v" "lpm_counter_component" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_isdr.v" 59 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214655830 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\"" { } { { "db/ip/tx_nco/submodules/asj_nco_isdr.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_isdr.v" 59 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214655866 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 4 " "Parameter \"lpm_width\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214655866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_COUNTER " "Parameter \"lpm_type\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214655866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction UP " "Parameter \"lpm_direction\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214655866 ""} } { { "db/ip/tx_nco/submodules/asj_nco_isdr.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_isdr.v" 59 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214655866 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_asi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_asi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_asi " "Found entity 1: cntr_asi" { } { { "db/cntr_asi.tdf" "" { Text "C:/FPGA/db/cntr_asi.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214656089 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214656089 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_asi tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_asi:auto_generated " "Elaborating entity \"cntr_asi\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_asi:auto_generated\"" { } { { "lpm_counter.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_counter.tdf" 258 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214656112 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_interface spi_interface:FLASH " "Elaborating entity \"spi_interface\" for hierarchy \"spi_interface:FLASH\"" { } { { "WOLF-LITE.bdf" "FLASH" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 912 3936 4152 1056 "FLASH" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661120 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_shifter data_shifter:RX_CICFIR_GAINER " "Elaborating entity \"data_shifter\" for hierarchy \"data_shifter:RX_CICFIR_GAINER\"" { } { { "WOLF-LITE.bdf" "RX_CICFIR_GAINER" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 160 2248 2552 304 "RX_CICFIR_GAINER" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661157 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 data_shifter.v(18) " "Verilog HDL assignment warning at data_shifter.v(18): truncated value with size 32 to match size of target (1)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1617214661158 "|WOLF-LITE|data_shifter:RX_CICFIR_GAINER"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 data_shifter.v(19) " "Verilog HDL assignment warning at data_shifter.v(19): truncated value with size 32 to match size of target (1)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 19 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1617214661158 "|WOLF-LITE|data_shifter:RX_CICFIR_GAINER"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 data_shifter.v(20) " "Verilog HDL assignment warning at data_shifter.v(20): truncated value with size 32 to match size of target (16)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1617214661159 "|WOLF-LITE|data_shifter:RX_CICFIR_GAINER"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 data_shifter.v(21) " "Verilog HDL assignment warning at data_shifter.v(21): truncated value with size 32 to match size of target (16)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 21 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1617214661160 "|WOLF-LITE|data_shifter:RX_CICFIR_GAINER"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_ciccomp rx_ciccomp:RX_CICCOMP_I " "Elaborating entity \"rx_ciccomp\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\"" { } { { "WOLF-LITE.bdf" "RX_CICCOMP_I" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 8 1768 2152 224 "RX_CICCOMP_I" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661195 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_ciccomp_0002 rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst " "Elaborating entity \"rx_ciccomp_0002\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\"" { } { { "rx_ciccomp.v" "rx_ciccomp_inst" { Text "C:/FPGA/rx_ciccomp.v" 28 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661231 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "coeff_in_read_sig rx_ciccomp_0002.vhd(54) " "Verilog HDL or VHDL warning at rx_ciccomp_0002.vhd(54): object \"coeff_in_read_sig\" assigned a value but never read" { } { { "rx_ciccomp/rx_ciccomp_0002.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd" 54 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "Analysis & Synthesis" 0 -1 1617214661232 "|WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_ciccomp_0002_ast rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst " "Elaborating entity \"rx_ciccomp_0002_ast\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\"" { } { { "rx_ciccomp/rx_ciccomp_0002.vhd" "rx_ciccomp_0002_ast_inst" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd" 62 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661268 ""} -{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "core_channel_out_core rx_ciccomp_0002_ast.vhd(208) " "VHDL Signal Declaration warning at rx_ciccomp_0002_ast.vhd(208): used implicit default value for signal \"core_channel_out_core\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 208 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 1 0 "Analysis & Synthesis" 0 -1 1617214661273 "|WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_sink_hpfir rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_sink_hpfir:sink " "Elaborating entity \"auk_dspip_avalon_streaming_sink_hpfir\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_sink_hpfir:sink\"" { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "sink" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 89 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661320 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_source_hpfir rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source " "Elaborating entity \"auk_dspip_avalon_streaming_source_hpfir\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\"" { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "source" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 109 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661374 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_controller_hpfir rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_controller_hpfir:intf_ctrl " "Elaborating entity \"auk_dspip_avalon_streaming_controller_hpfir\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_controller_hpfir:intf_ctrl\"" { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "intf_ctrl" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 137 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661456 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_ciccomp_0002_rtl_core rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core " "Elaborating entity \"rx_ciccomp_0002_rtl_core\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\"" { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "\\real_passthrough:hpfircore_core" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661488 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_memread " "Elaborating entity \"dspba_delay\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_memread\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_memread" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 173 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661575 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_compute " "Elaborating entity \"dspba_delay\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_compute\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_compute" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 178 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661615 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_u0_m0_wo0_compute_q_15 " "Elaborating entity \"dspba_delay\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_u0_m0_wo0_compute_q_15\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "d_u0_m0_wo0_compute_q_15" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 183 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661648 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_xIn_0_13 " "Elaborating entity \"dspba_delay\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_xIn_0_13\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "d_xIn_0_13" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 375 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661693 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem " "Elaborating entity \"altsyncram\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_wi0_r0_memr0_dmem" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 402 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661784 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem " "Elaborated megafunction instantiation \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 402 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214661825 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem " "Instantiated megafunction \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a UNUSED " "Parameter \"address_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_aclr_a UNUSED " "Parameter \"byteena_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_aclr_b NONE " "Parameter \"byteena_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_reg_b CLOCK0 " "Parameter \"byteena_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_core_a USE_INPUT_CLKEN " "Parameter \"clock_enable_core_a\" = \"USE_INPUT_CLKEN\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_core_b USE_INPUT_CLKEN " "Parameter \"clock_enable_core_b\" = \"USE_INPUT_CLKEN\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a NORMAL " "Parameter \"clock_enable_input_a\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b NORMAL " "Parameter \"clock_enable_input_b\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a NORMAL " "Parameter \"clock_enable_output_a\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b NORMAL " "Parameter \"clock_enable_output_b\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ecc_pipeline_stage_enabled FALSE " "Parameter \"ecc_pipeline_stage_enabled\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "enable_ecc FALSE " "Parameter \"enable_ecc\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "implement_in_les OFF " "Parameter \"implement_in_les\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a UNUSED " "Parameter \"indata_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Parameter \"init_file\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file_layout PORT_A " "Parameter \"init_file_layout\" = \"PORT_A\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 64 " "Parameter \"numwords_a\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 64 " "Parameter \"numwords_b\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type M9K " "Parameter \"ram_block_type\" = \"M9K\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_aclr_b NONE " "Parameter \"rdcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "stratixiv_m144k_allow_dual_clocks ON " "Parameter \"stratixiv_m144k_allow_dual_clocks\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_eccstatus 3 " "Parameter \"width_eccstatus\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 6 " "Parameter \"widthad_a\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 6 " "Parameter \"widthad_b\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a UNUSED " "Parameter \"wrcontrol_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214661826 ""} } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 402 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214661826 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sln3.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sln3.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sln3 " "Found entity 1: altsyncram_sln3" { } { { "db/altsyncram_sln3.tdf" "" { Text "C:/FPGA/db/altsyncram_sln3.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214662041 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214662041 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sln3 rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\|altsyncram_sln3:auto_generated " "Elaborating entity \"altsyncram_sln3\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\|altsyncram_sln3:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214662059 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component " "Elaborating entity \"lpm_mult\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_mtree_mult1_0_im4_component" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214662246 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component " "Elaborated megafunction instantiation \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 448 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214662278 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component " "Instantiated megafunction \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 15 " "Parameter \"LPM_WIDTHA\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 8 " "Parameter \"LPM_WIDTHB\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 23 " "Parameter \"LPM_WIDTHP\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_PIPELINE 2 " "Parameter \"LPM_PIPELINE\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_MULT " "Parameter \"LPM_TYPE\" = \"LPM_MULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5 " "Parameter \"LPM_HINT\" = \"DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662278 ""} } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 448 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214662278 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_lcu.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_lcu.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_lcu " "Found entity 1: mult_lcu" { } { { "db/mult_lcu.tdf" "" { Text "C:/FPGA/db/mult_lcu.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214662453 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214662453 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_lcu rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component\|mult_lcu:auto_generated " "Elaborating entity \"mult_lcu\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component\|mult_lcu:auto_generated\"" { } { { "lpm_mult.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 376 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214662476 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component " "Elaborating entity \"lpm_mult\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_mtree_mult1_0_im0_component" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 480 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214662607 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component " "Elaborated megafunction instantiation \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 480 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214662641 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component " "Instantiated megafunction \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 18 " "Parameter \"LPM_WIDTHA\" = \"18\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 8 " "Parameter \"LPM_WIDTHB\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 26 " "Parameter \"LPM_WIDTHP\" = \"26\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_PIPELINE 2 " "Parameter \"LPM_PIPELINE\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_MULT " "Parameter \"LPM_TYPE\" = \"LPM_MULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5 " "Parameter \"LPM_HINT\" = \"DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214662641 ""} } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 480 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214662641 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_rcu.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_rcu.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_rcu " "Found entity 1: mult_rcu" { } { { "db/mult_rcu.tdf" "" { Text "C:/FPGA/db/mult_rcu.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214662802 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214662802 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_rcu rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component\|mult_rcu:auto_generated " "Elaborating entity \"mult_rcu\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component\|mult_rcu:auto_generated\"" { } { { "lpm_mult.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 376 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214662819 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_roundsat_hpfir rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_roundsat_hpfir:\\real_passthrough:gen_outp_blk:0:outp_blk " "Elaborating entity \"auk_dspip_roundsat_hpfir\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_roundsat_hpfir:\\real_passthrough:gen_outp_blk:0:outp_blk\"" { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "\\real_passthrough:gen_outp_blk:0:outp_blk" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 244 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214662919 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_cic rx_cic:RX_CIC_I " "Elaborating entity \"rx_cic\" for hierarchy \"rx_cic:RX_CIC_I\"" { } { { "WOLF-LITE.bdf" "RX_CIC_I" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214662968 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_cic_cic_ii_0 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0 " "Elaborating entity \"rx_cic_cic_ii_0\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\"" { } { { "db/ip/rx_cic/rx_cic.v" "cic_ii_0" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214663024 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_cic_core rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core " "Elaborating entity \"alt_cic_core\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\"" { } { { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "core" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214663165 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_sink rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink " "Elaborating entity \"auk_dspip_avalon_streaming_sink\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\"" { } { { "db/ip/rx_cic/submodules/alt_cic_core.sv" "input_sink" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214663384 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "sink_FIFO" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214663798 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO " "Elaborated megafunction instantiation \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214663827 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO " "Instantiated megafunction \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Parameter \"add_ram_output_register\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214663827 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "allow_rwcycle_when_full OFF " "Parameter \"allow_rwcycle_when_full\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214663827 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_empty_value 4 " "Parameter \"almost_empty_value\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214663827 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_full_value 0 " "Parameter \"almost_full_value\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214663827 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 8 " "Parameter \"lpm_numwords\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214663827 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214663827 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 25 " "Parameter \"lpm_width\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214663827 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 3 " "Parameter \"lpm_widthu\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214663827 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214663827 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214663827 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214663827 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214663827 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214663827 ""} } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214663827 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_ef71.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_ef71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_ef71 " "Found entity 1: scfifo_ef71" { } { { "db/scfifo_ef71.tdf" "" { Text "C:/FPGA/db/scfifo_ef71.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214664000 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214664000 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_ef71 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated " "Elaborating entity \"scfifo_ef71\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214664023 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_vkv.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_vkv.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_vkv " "Found entity 1: a_dpfifo_vkv" { } { { "db/a_dpfifo_vkv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_vkv.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214664138 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214664138 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_vkv rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo " "Elaborating entity \"a_dpfifo_vkv\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\"" { } { { "db/scfifo_ef71.tdf" "dpfifo" { Text "C:/FPGA/db/scfifo_ef71.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214664172 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_h7h1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_h7h1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_h7h1 " "Found entity 1: altsyncram_h7h1" { } { { "db/altsyncram_h7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_h7h1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214664346 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214664346 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_h7h1 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram " "Elaborating entity \"altsyncram_h7h1\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\"" { } { { "db/a_dpfifo_vkv.tdf" "FIFOram" { Text "C:/FPGA/db/a_dpfifo_vkv.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214664409 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_source rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0 " "Elaborating entity \"auk_dspip_avalon_streaming_source\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\"" { } { { "db/ip/rx_cic/submodules/alt_cic_core.sv" "output_source_0" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 358 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214665028 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "source_FIFO" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214665715 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO " "Elaborated megafunction instantiation \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214665758 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO " "Instantiated megafunction \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Parameter \"add_ram_output_register\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214665759 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "allow_rwcycle_when_full OFF " "Parameter \"allow_rwcycle_when_full\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214665759 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_empty_value 0 " "Parameter \"almost_empty_value\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214665759 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_full_value 13 " "Parameter \"almost_full_value\" = \"13\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214665759 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 21 " "Parameter \"lpm_numwords\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214665759 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214665759 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 33 " "Parameter \"lpm_width\" = \"33\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214665759 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 5 " "Parameter \"lpm_widthu\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214665759 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214665759 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214665759 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214665759 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214665759 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214665759 ""} } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214665759 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_ai71.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_ai71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_ai71 " "Found entity 1: scfifo_ai71" { } { { "db/scfifo_ai71.tdf" "" { Text "C:/FPGA/db/scfifo_ai71.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214666011 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214666011 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_ai71 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated " "Elaborating entity \"scfifo_ai71\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214666034 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_7qv.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_7qv.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_7qv " "Found entity 1: a_dpfifo_7qv" { } { { "db/a_dpfifo_7qv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_7qv.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214666175 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214666175 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_7qv rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo " "Elaborating entity \"a_dpfifo_7qv\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\"" { } { { "db/scfifo_ai71.tdf" "dpfifo" { Text "C:/FPGA/db/scfifo_ai71.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214666213 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_dah1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_dah1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_dah1 " "Found entity 1: altsyncram_dah1" { } { { "db/altsyncram_dah1.tdf" "" { Text "C:/FPGA/db/altsyncram_dah1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214666396 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214666396 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_dah1 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|altsyncram_dah1:FIFOram " "Elaborating entity \"altsyncram_dah1\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|altsyncram_dah1:FIFOram\"" { } { { "db/a_dpfifo_7qv.tdf" "FIFOram" { Text "C:/FPGA/db/a_dpfifo_7qv.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214666447 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_controller rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller " "Elaborating entity \"auk_dspip_avalon_streaming_controller\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller\"" { } { { "db/ip/rx_cic/submodules/alt_cic_core.sv" "avalon_controller" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 408 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214667036 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_small_fifo rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller\|auk_dspip_avalon_streaming_small_fifo:ready_FIFO " "Elaborating entity \"auk_dspip_avalon_streaming_small_fifo\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller\|auk_dspip_avalon_streaming_small_fifo:ready_FIFO\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" "ready_FIFO" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" 196 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214667254 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_cic_dec_siso rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one " "Elaborating entity \"alt_cic_dec_siso\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\"" { } { { "db/ip/rx_cic/submodules/alt_cic_core.sv" "dec_one" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214667500 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_integrator rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_integrator:integrator\[0\].integration " "Elaborating entity \"auk_dspip_integrator\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_integrator:integrator\[0\].integration\"" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "integrator\[0\].integration" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 275 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214667817 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_delay rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_integrator:integrator\[0\].integration\|auk_dspip_delay:\\glogic:integrator_pipeline_0_generate:u1 " "Elaborating entity \"auk_dspip_delay\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_integrator:integrator\[0\].integration\|auk_dspip_delay:\\glogic:integrator_pipeline_0_generate:u1\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_integrator.vhd" "\\glogic:integrator_pipeline_0_generate:u1" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_integrator.vhd" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214667957 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_downsample rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_downsample:vrc_en_0.first_dsample " "Elaborating entity \"auk_dspip_downsample\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_downsample:vrc_en_0.first_dsample\"" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "vrc_en_0.first_dsample" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 330 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214668734 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_module rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_downsample:vrc_en_0.first_dsample\|counter_module:counter_fs_inst " "Elaborating entity \"counter_module\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_downsample:vrc_en_0.first_dsample\|counter_module:counter_fs_inst\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_downsample.sv" "counter_fs_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv" 50 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214668974 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_module rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_downsample:vrc_en_0.first_dsample\|counter_module:counter_ch_inst " "Elaborating entity \"counter_module\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_downsample:vrc_en_0.first_dsample\|counter_module:counter_ch_inst\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_downsample.sv" "counter_ch_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv" 79 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214669207 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_channel_buffer rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator " "Elaborating entity \"auk_dspip_channel_buffer\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\"" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "fifo_regulator" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214669372 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "buffer_FIFO" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214670056 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO " "Elaborated megafunction instantiation \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214670089 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO " "Instantiated megafunction \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Parameter \"add_ram_output_register\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214670089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "allow_rwcycle_when_full OFF " "Parameter \"allow_rwcycle_when_full\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214670089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_empty_value 0 " "Parameter \"almost_empty_value\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214670089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_full_value 0 " "Parameter \"almost_full_value\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214670089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 3 " "Parameter \"lpm_numwords\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214670089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214670089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 85 " "Parameter \"lpm_width\" = \"85\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214670089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 2 " "Parameter \"lpm_widthu\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214670089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214670089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214670089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214670089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214670089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214670089 ""} } { { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214670089 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_pm51.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_pm51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_pm51 " "Found entity 1: scfifo_pm51" { } { { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214670296 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214670296 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_pm51 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated " "Elaborating entity \"scfifo_pm51\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214670319 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_4ku.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_4ku.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_4ku " "Found entity 1: a_dpfifo_4ku" { } { { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214670432 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214670432 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_4ku rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo " "Elaborating entity \"a_dpfifo_4ku\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\"" { } { { "db/scfifo_pm51.tdf" "dpfifo" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214670467 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_j7h1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_j7h1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_j7h1 " "Found entity 1: altsyncram_j7h1" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214670658 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214670658 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_j7h1 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram " "Elaborating entity \"altsyncram_j7h1\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\"" { } { { "db/a_dpfifo_4ku.tdf" "FIFOram" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214670704 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_fs8.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_fs8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_fs8 " "Found entity 1: cmpr_fs8" { } { { "db/cmpr_fs8.tdf" "" { Text "C:/FPGA/db/cmpr_fs8.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214670917 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214670917 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_fs8 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cmpr_fs8:almost_full_comparer " "Elaborating entity \"cmpr_fs8\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cmpr_fs8:almost_full_comparer\"" { } { { "db/a_dpfifo_4ku.tdf" "almost_full_comparer" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214670972 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_fs8 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cmpr_fs8:two_comparison " "Elaborating entity \"cmpr_fs8\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cmpr_fs8:two_comparison\"" { } { { "db/a_dpfifo_4ku.tdf" "two_comparison" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 51 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214671062 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_q9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_q9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_q9b " "Found entity 1: cntr_q9b" { } { { "db/cntr_q9b.tdf" "" { Text "C:/FPGA/db/cntr_q9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214671229 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214671229 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_q9b rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cntr_q9b:rd_ptr_msb " "Elaborating entity \"cntr_q9b\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cntr_q9b:rd_ptr_msb\"" { } { { "db/a_dpfifo_4ku.tdf" "rd_ptr_msb" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 52 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214671276 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_7a7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_7a7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_7a7 " "Found entity 1: cntr_7a7" { } { { "db/cntr_7a7.tdf" "" { Text "C:/FPGA/db/cntr_7a7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214671443 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214671443 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_7a7 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cntr_7a7:usedw_counter " "Elaborating entity \"cntr_7a7\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|cntr_7a7:usedw_counter\"" { } { { "db/a_dpfifo_4ku.tdf" "usedw_counter" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 53 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214671492 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_module rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|counter_module:latency_cnt_inst " "Elaborating entity \"counter_module\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|counter_module:latency_cnt_inst\"" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "latency_cnt_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 419 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214671780 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_module rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|counter_module:channel_out_int_inst " "Elaborating entity \"counter_module\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|counter_module:channel_out_int_inst\"" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "channel_out_int_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 432 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214671915 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_differentiator rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_differentiator:differentiate_stages\[0\].auk_dsp_diff " "Elaborating entity \"auk_dspip_differentiator\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_differentiator:differentiate_stages\[0\].auk_dsp_diff\"" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "differentiate_stages\[0\].auk_dsp_diff" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 658 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214672187 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nco nco:RX_NCO " "Elaborating entity \"nco\" for hierarchy \"nco:RX_NCO\"" { } { { "WOLF-LITE.bdf" "RX_NCO" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 152 480 736 352 "RX_NCO" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214673096 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nco_nco_ii_0 nco:RX_NCO\|nco_nco_ii_0:nco_ii_0 " "Elaborating entity \"nco_nco_ii_0\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\"" { } { { "db/ip/nco/nco.v" "nco_ii_0" { Text "C:/FPGA/db/ip/nco/nco.v" 24 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214673197 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_altqmcpipe nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000 " "Elaborating entity \"asj_altqmcpipe\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "ux000" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 304 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214673380 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc " "Elaborating entity \"lpm_add_sub\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\"" { } { { "db/ip/nco/submodules/asj_altqmcpipe.v" "acc" { Text "C:/FPGA/db/ip/nco/submodules/asj_altqmcpipe.v" 63 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214673581 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\"" { } { { "db/ip/nco/submodules/asj_altqmcpipe.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_altqmcpipe.v" 63 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214673614 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Parameter \"lpm_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214673614 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 22 " "Parameter \"lpm_width\" = \"22\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214673614 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214673614 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation UNSIGNED " "Parameter \"lpm_representation\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214673614 ""} } { { "db/ip/nco/submodules/asj_altqmcpipe.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_altqmcpipe.v" 63 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214673614 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_gam_dp nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_gam_dp:ux008 " "Elaborating entity \"asj_gam_dp\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_gam_dp:ux008\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "ux008" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214673905 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_dp_cen nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220 " "Elaborating entity \"asj_nco_as_m_dp_cen\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "ux0220" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 338 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214674205 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\"" { } { { "db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" "altsyncram_component" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" 109 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214674397 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\"" { } { { "db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" 109 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214674430 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 12 " "Parameter \"width_a\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 12 " "Parameter \"width_b\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 11 " "Parameter \"widthad_b\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 2048 " "Parameter \"numwords_b\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nco_nco_ii_0_sin_c.hex " "Parameter \"init_file\" = \"nco_nco_ii_0_sin_c.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214674430 ""} } { { "db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" 109 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214674430 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_h982.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_h982.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_h982 " "Found entity 1: altsyncram_h982" { } { { "db/altsyncram_h982.tdf" "" { Text "C:/FPGA/db/altsyncram_h982.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214674650 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214674650 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_h982 nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_h982:auto_generated " "Elaborating entity \"altsyncram_h982\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_h982:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214674676 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_cen nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122 " "Elaborating entity \"asj_nco_as_m_cen\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "ux0122" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 350 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214675411 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Elaborating entity \"altsyncram\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\"" { } { { "db/ip/nco/submodules/asj_nco_as_m_cen.v" "altsyncram_component0" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214675621 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\"" { } { { "db/ip/nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214675662 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214675662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 12 " "Parameter \"width_a\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214675662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214675662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214675662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214675662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214675662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214675662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214675662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214675662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214675662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nco_nco_ii_0_sin_f.hex " "Parameter \"init_file\" = \"nco_nco_ii_0_sin_f.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214675662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214675662 ""} } { { "db/ip/nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214675662 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fu91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_fu91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fu91 " "Found entity 1: altsyncram_fu91" { } { { "db/altsyncram_fu91.tdf" "" { Text "C:/FPGA/db/altsyncram_fu91.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214675946 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214675946 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fu91 nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_fu91:auto_generated " "Elaborating entity \"altsyncram_fu91\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_fu91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214675974 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_cen nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123 " "Elaborating entity \"asj_nco_as_m_cen\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "ux0123" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 362 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214676739 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Elaborating entity \"altsyncram\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\"" { } { { "db/ip/nco/submodules/asj_nco_as_m_cen.v" "altsyncram_component0" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214676854 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\"" { } { { "db/ip/nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214676892 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214676892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 12 " "Parameter \"width_a\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214676892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214676892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214676892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214676892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214676892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214676892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214676892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214676892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214676892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nco_nco_ii_0_cos_f.hex " "Parameter \"init_file\" = \"nco_nco_ii_0_cos_f.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214676892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214676892 ""} } { { "db/ip/nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214676892 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_au91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_au91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_au91 " "Found entity 1: altsyncram_au91" { } { { "db/altsyncram_au91.tdf" "" { Text "C:/FPGA/db/altsyncram_au91.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214677111 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214677111 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_au91 nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\|altsyncram_au91:auto_generated " "Elaborating entity \"altsyncram_au91\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\|altsyncram_au91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214677138 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_madx_cen nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1 " "Elaborating entity \"asj_nco_madx_cen\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "m1" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 377 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214677860 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_mady_cen nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0 " "Elaborating entity \"asj_nco_mady_cen\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "m0" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 389 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214678146 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_derot nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_derot:ux0136 " "Elaborating entity \"asj_nco_derot\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_derot:ux0136\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "ux0136" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 402 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214678465 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_mob_w nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0 " "Elaborating entity \"asj_nco_mob_w\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "blk0" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 410 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214678753 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Elaborating entity \"lpm_add_sub\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\"" { } { { "db/ip/nco/submodules/asj_nco_mob_w.v" "lpm_add_sub_component" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mob_w.v" 75 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214678950 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\"" { } { { "db/ip/nco/submodules/asj_nco_mob_w.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mob_w.v" 75 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214678986 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 12 " "Parameter \"lpm_width\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214678986 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Parameter \"lpm_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214678986 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214678986 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO " "Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214678986 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214678986 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Parameter \"lpm_representation\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214678986 ""} } { { "db/ip/nco/submodules/asj_nco_mob_w.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mob_w.v" 75 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214678986 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_fpk.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_fpk.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_fpk " "Found entity 1: add_sub_fpk" { } { { "db/add_sub_fpk.tdf" "" { Text "C:/FPGA/db/add_sub_fpk.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214679157 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214679157 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_fpk nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\|add_sub_fpk:auto_generated " "Elaborating entity \"add_sub_fpk\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\|add_sub_fpk:auto_generated\"" { } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214679187 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_isdr nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr " "Elaborating entity \"asj_nco_isdr\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "ux710isdr" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 428 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214679690 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Elaborating entity \"lpm_counter\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\"" { } { { "db/ip/nco/submodules/asj_nco_isdr.v" "lpm_counter_component" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_isdr.v" 59 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214679897 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\"" { } { { "db/ip/nco/submodules/asj_nco_isdr.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_isdr.v" 59 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214679926 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 4 " "Parameter \"lpm_width\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214679927 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_COUNTER " "Parameter \"lpm_type\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214679927 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction UP " "Parameter \"lpm_direction\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214679927 ""} } { { "db/ip/nco/submodules/asj_nco_isdr.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_isdr.v" 59 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214679927 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mixer mixer:RX_MIXER_I " "Elaborating entity \"mixer\" for hierarchy \"mixer:RX_MIXER_I\"" { } { { "WOLF-LITE.bdf" "RX_MIXER_I" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -24 528 696 104 "RX_MIXER_I" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214680348 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component " "Elaborating entity \"lpm_mult\" for hierarchy \"mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\"" { } { { "mixer.v" "lpm_mult_component" { Text "C:/FPGA/mixer.v" 63 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214680408 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\"" { } { { "mixer.v" "" { Text "C:/FPGA/mixer.v" 63 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214680441 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component " "Instantiated megafunction \"mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint MAXIMIZE_SPEED=5 " "Parameter \"lpm_hint\" = \"MAXIMIZE_SPEED=5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214680441 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214680441 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Parameter \"lpm_representation\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214680441 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MULT " "Parameter \"lpm_type\" = \"LPM_MULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214680441 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widtha 12 " "Parameter \"lpm_widtha\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214680441 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthb 12 " "Parameter \"lpm_widthb\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214680441 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthp 24 " "Parameter \"lpm_widthp\" = \"24\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214680441 ""} } { { "mixer.v" "" { Text "C:/FPGA/mixer.v" 63 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214680441 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_jnp.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_jnp.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_jnp " "Found entity 1: mult_jnp" { } { { "db/mult_jnp.tdf" "" { Text "C:/FPGA/db/mult_jnp.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214680608 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214680608 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_jnp mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated " "Elaborating entity \"mult_jnp\" for hierarchy \"mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated\"" { } { { "lpm_mult.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 376 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214680625 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADC_Latch ADC_Latch:ADC_Latch " "Elaborating entity \"ADC_Latch\" for hierarchy \"ADC_Latch:ADC_Latch\"" { } { { "WOLF-LITE.bdf" "ADC_Latch" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -88 160 320 24 "ADC_Latch" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214680736 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component " "Elaborating entity \"lpm_add_sub\" for hierarchy \"ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component\"" { } { { "ADC_Latch.v" "LPM_ADD_SUB_component" { Text "C:/FPGA/ADC_Latch.v" 69 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214680793 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component " "Elaborated megafunction instantiation \"ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component\"" { } { { "ADC_Latch.v" "" { Text "C:/FPGA/ADC_Latch.v" 69 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214680822 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component " "Instantiated megafunction \"ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Parameter \"lpm_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214680822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO " "Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214680822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214680822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Parameter \"lpm_representation\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214680822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214680822 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 12 " "Parameter \"lpm_width\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214680822 ""} } { { "ADC_Latch.v" "" { Text "C:/FPGA/ADC_Latch.v" 69 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214680822 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_b2k.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_b2k.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_b2k " "Found entity 1: add_sub_b2k" { } { { "db/add_sub_b2k.tdf" "" { Text "C:/FPGA/db/add_sub_b2k.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214681014 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214681014 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_b2k ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component\|add_sub_b2k:auto_generated " "Elaborating entity \"add_sub_b2k\" for hierarchy \"ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component\|add_sub_b2k:auto_generated\"" { } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214681037 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MAIN_PLL MAIN_PLL:MAIN_PLL " "Elaborating entity \"MAIN_PLL\" for hierarchy \"MAIN_PLL:MAIN_PLL\"" { } { { "WOLF-LITE.bdf" "MAIN_PLL" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214687408 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll MAIN_PLL:MAIN_PLL\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\"" { } { { "MAIN_PLL.v" "altpll_component" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214687512 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component " "Elaborated megafunction instantiation \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\"" { } { { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214687551 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component " "Instantiated megafunction \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 5 " "Parameter \"clk0_divide_by\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1 " "Parameter \"clk0_multiply_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1280 " "Parameter \"clk1_divide_by\" = \"1280\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 1 " "Parameter \"clk1_multiply_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 16276 " "Parameter \"inclk0_input_frequency\" = \"16276\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=MAIN_PLL " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=MAIN_PLL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214687552 ""} } { { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214687552 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/main_pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/main_pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 MAIN_PLL_altpll " "Found entity 1: MAIN_PLL_altpll" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214687739 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214687739 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MAIN_PLL_altpll MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated " "Elaborating entity \"MAIN_PLL_altpll\" for hierarchy \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214687758 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux14 mux14:DAC_MUX " "Elaborating entity \"mux14\" for hierarchy \"mux14:DAC_MUX\"" { } { { "WOLF-LITE.bdf" "DAC_MUX" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 6040 6184 248 "DAC_MUX" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214687871 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux mux14:DAC_MUX\|lpm_mux:LPM_MUX_component " "Elaborating entity \"lpm_mux\" for hierarchy \"mux14:DAC_MUX\|lpm_mux:LPM_MUX_component\"" { } { { "mux14.v" "LPM_MUX_component" { Text "C:/FPGA/mux14.v" 68 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214688190 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "mux14:DAC_MUX\|lpm_mux:LPM_MUX_component " "Elaborated megafunction instantiation \"mux14:DAC_MUX\|lpm_mux:LPM_MUX_component\"" { } { { "mux14.v" "" { Text "C:/FPGA/mux14.v" 68 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214688217 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mux14:DAC_MUX\|lpm_mux:LPM_MUX_component " "Instantiated megafunction \"mux14:DAC_MUX\|lpm_mux:LPM_MUX_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_size 2 " "Parameter \"lpm_size\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214688217 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MUX " "Parameter \"lpm_type\" = \"LPM_MUX\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214688217 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 14 " "Parameter \"lpm_width\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214688217 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widths 1 " "Parameter \"lpm_widths\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214688217 ""} } { { "mux14.v" "" { Text "C:/FPGA/mux14.v" 68 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214688217 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_rsc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_rsc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_rsc " "Found entity 1: mux_rsc" { } { { "db/mux_rsc.tdf" "" { Text "C:/FPGA/db/mux_rsc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214688403 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214688403 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_rsc mux14:DAC_MUX\|lpm_mux:LPM_MUX_component\|mux_rsc:auto_generated " "Elaborating entity \"mux_rsc\" for hierarchy \"mux14:DAC_MUX\|lpm_mux:LPM_MUX_component\|mux_rsc:auto_generated\"" { } { { "lpm_mux.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mux.tdf" 86 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214688419 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dac_null dac_null:DAC_IDLE " "Elaborating entity \"dac_null\" for hierarchy \"dac_null:DAC_IDLE\"" { } { { "WOLF-LITE.bdf" "DAC_IDLE" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 296 5896 6008 344 "DAC_IDLE" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214688532 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_constant dac_null:DAC_IDLE\|lpm_constant:LPM_CONSTANT_component " "Elaborating entity \"lpm_constant\" for hierarchy \"dac_null:DAC_IDLE\|lpm_constant:LPM_CONSTANT_component\"" { } { { "dac_null.v" "LPM_CONSTANT_component" { Text "C:/FPGA/dac_null.v" 48 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214688712 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "dac_null:DAC_IDLE\|lpm_constant:LPM_CONSTANT_component " "Elaborated megafunction instantiation \"dac_null:DAC_IDLE\|lpm_constant:LPM_CONSTANT_component\"" { } { { "dac_null.v" "" { Text "C:/FPGA/dac_null.v" 48 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214688733 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dac_null:DAC_IDLE\|lpm_constant:LPM_CONSTANT_component " "Instantiated megafunction \"dac_null:DAC_IDLE\|lpm_constant:LPM_CONSTANT_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_cvalue 8192 " "Parameter \"lpm_cvalue\" = \"8192\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214688733 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214688733 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_CONSTANT " "Parameter \"lpm_type\" = \"LPM_CONSTANT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214688733 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 14 " "Parameter \"lpm_width\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214688733 ""} } { { "dac_null.v" "" { Text "C:/FPGA/dac_null.v" 48 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214688733 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DAC_corrector DAC_corrector:DAC_CORRECTOR " "Elaborating entity \"DAC_corrector\" for hierarchy \"DAC_corrector:DAC_CORRECTOR\"" { } { { "WOLF-LITE.bdf" "DAC_CORRECTOR" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 176 5760 6008 288 "DAC_CORRECTOR" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214688767 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DEBUG DEBUG:DBG_ADC " "Elaborating entity \"DEBUG\" for hierarchy \"DEBUG:DBG_ADC\"" { } { { "WOLF-LITE.bdf" "DBG_ADC" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -176 520 696 -72 "DBG_ADC" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214688808 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsource_probe_top DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0 " "Elaborating entity \"altsource_probe_top\" for hierarchy \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\"" { } { { "db/ip/debug/debug.v" "in_system_sources_probes_0" { Text "C:/FPGA/db/ip/debug/debug.v" 19 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214688899 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsource_probe DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl " "Elaborating entity \"altsource_probe\" for hierarchy \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\"" { } { { "db/ip/debug/submodules/altsource_probe_top.v" "issp_impl" { Text "C:/FPGA/db/ip/debug/submodules/altsource_probe_top.v" 55 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214689122 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl " "Elaborated megafunction instantiation \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\"" { } { { "db/ip/debug/submodules/altsource_probe_top.v" "" { Text "C:/FPGA/db/ip/debug/submodules/altsource_probe_top.v" 55 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214689146 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl " "Instantiated megafunction \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsource_probe " "Parameter \"lpm_type\" = \"altsource_probe\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214689147 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214689147 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214689147 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214689147 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_NODE_INFO 4746752 " "Parameter \"SLD_NODE_INFO\" = \"4746752\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214689147 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 4 " "Parameter \"sld_ir_width\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214689147 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "instance_id ADC " "Parameter \"instance_id\" = \"ADC\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214689147 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "probe_width 12 " "Parameter \"probe_width\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214689147 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "source_width 0 " "Parameter \"source_width\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214689147 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "source_initial_value 0 " "Parameter \"source_initial_value\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214689147 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "enable_metastability NO " "Parameter \"enable_metastability\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1617214689147 ""} } { { "db/ip/debug/submodules/altsource_probe_top.v" "" { Text "C:/FPGA/db/ip/debug/submodules/altsource_probe_top.v" 55 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1617214689147 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_jtag_endpoint_adapter DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|sld_jtag_endpoint_adapter:jtag_signal_adapter " "Elaborating entity \"sld_jtag_endpoint_adapter\" for hierarchy \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|sld_jtag_endpoint_adapter:jtag_signal_adapter\"" { } { { "altsource_probe.v" "jtag_signal_adapter" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe.v" 168 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214689445 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_jtag_endpoint_adapter_impl DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|sld_jtag_endpoint_adapter:jtag_signal_adapter\|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst " "Elaborating entity \"sld_jtag_endpoint_adapter_impl\" for hierarchy \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|sld_jtag_endpoint_adapter:jtag_signal_adapter\|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst\"" { } { { "sld_jtag_endpoint_adapter.vhd" "sld_jtag_endpoint_adapter_impl_inst" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd" 232 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214689887 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsource_probe_body DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|altsource_probe_body:altsource_probe_body_inst " "Elaborating entity \"altsource_probe_body\" for hierarchy \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|altsource_probe_body:altsource_probe_body_inst\"" { } { { "altsource_probe.v" "altsource_probe_body_inst" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe.v" 280 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214690175 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsource_probe_impl DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|altsource_probe_body:altsource_probe_body_inst\|altsource_probe_impl:\\wider_probe_gen:wider_probe_inst " "Elaborating entity \"altsource_probe_impl\" for hierarchy \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|altsource_probe_body:altsource_probe_body_inst\|altsource_probe_impl:\\wider_probe_gen:wider_probe_inst\"" { } { { "altsource_probe_body.vhd" "\\wider_probe_gen:wider_probe_inst" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe_body.vhd" 507 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214690272 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_rom_sr DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|altsource_probe_body:altsource_probe_body_inst\|altsource_probe_impl:\\wider_probe_gen:wider_probe_inst\|sld_rom_sr:\\instance_id_gen:rom_info_inst " "Elaborating entity \"sld_rom_sr\" for hierarchy \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|altsource_probe_body:altsource_probe_body_inst\|altsource_probe_impl:\\wider_probe_gen:wider_probe_inst\|sld_rom_sr:\\instance_id_gen:rom_info_inst\"" { } { { "altsource_probe_body.vhd" "\\instance_id_gen:rom_info_inst" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe_body.vhd" 755 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1617214690641 ""} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max rate_cnt_inst 32 11 " "Port \"counter_max\" on the entity instantiation of \"rate_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 11. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "rate_cnt_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 486 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214691936 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max channel_out_int_inst 32 2 " "Port \"counter_max\" on the entity instantiation of \"channel_out_int_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 2. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "channel_out_int_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 432 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214691937 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:channel_out_int_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max latency_cnt_inst 32 4 " "Port \"counter_max\" on the entity instantiation of \"latency_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 4. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "latency_cnt_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 419 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214691937 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:latency_cnt_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_ch_inst 32 1 " "Port \"counter_max\" on the entity instantiation of \"counter_ch_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 1. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/auk_dspip_downsample.sv" "counter_ch_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv" 79 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214691941 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_ch_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_fs_inst 32 11 " "Port \"counter_max\" on the entity instantiation of \"counter_fs_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 11. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/auk_dspip_downsample.sv" "counter_fs_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv" 50 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214691942 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max rate_cnt_inst 32 11 " "Port \"counter_max\" on the entity instantiation of \"rate_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 11. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "rate_cnt_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 486 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214691987 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max channel_out_int_inst 32 2 " "Port \"counter_max\" on the entity instantiation of \"channel_out_int_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 2. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "channel_out_int_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 432 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214691988 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:channel_out_int_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max latency_cnt_inst 32 4 " "Port \"counter_max\" on the entity instantiation of \"latency_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 4. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "latency_cnt_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 419 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214691988 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:latency_cnt_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_ch_inst 32 1 " "Port \"counter_max\" on the entity instantiation of \"counter_ch_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 1. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/auk_dspip_downsample.sv" "counter_ch_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv" 79 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214691995 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_ch_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_fs_inst 32 11 " "Port \"counter_max\" on the entity instantiation of \"counter_fs_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 11. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/auk_dspip_downsample.sv" "counter_fs_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv" 50 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214691995 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_ch_inst 32 1 " "Port \"counter_max\" on the entity instantiation of \"counter_ch_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 1. The extra bits will be ignored." { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "counter_ch_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 313 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214692038 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_ch_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_fs_inst 32 12 " "Port \"counter_max\" on the entity instantiation of \"counter_fs_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 12. The extra bits will be ignored." { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "counter_fs_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 298 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214692039 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_fs_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max latency_cnt_inst 32 4 " "Port \"counter_max\" on the entity instantiation of \"latency_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 4. The extra bits will be ignored." { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "latency_cnt_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 270 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214692039 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_ch_inst 32 1 " "Port \"counter_max\" on the entity instantiation of \"counter_ch_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 1. The extra bits will be ignored." { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "counter_ch_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 313 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214692096 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_ch_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_fs_inst 32 12 " "Port \"counter_max\" on the entity instantiation of \"counter_fs_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 12. The extra bits will be ignored." { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "counter_fs_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 298 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214692096 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_fs_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max latency_cnt_inst 32 4 " "Port \"counter_max\" on the entity instantiation of \"latency_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 4. The extra bits will be ignored." { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "latency_cnt_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 270 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1617214692097 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst"} -{ "Info" "ISCI_START_SUPER_FABRIC_GEN" "alt_sld_fab " "Starting IP generation for the debug fabric: alt_sld_fab." { } { } 0 11170 "Starting IP generation for the debug fabric: %1!s!." 0 0 "Analysis & Synthesis" 0 -1 1617214692858 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "2021.03.31.22:18:19 Progress: Loading sld0b974a4e/alt_sld_fab_wrapper_hw.tcl " "2021.03.31.22:18:19 Progress: Loading sld0b974a4e/alt_sld_fab_wrapper_hw.tcl" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214699365 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG " "Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214709160 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: Generating alt_sld_fab \"alt_sld_fab\" for QUARTUS_SYNTH " "Alt_sld_fab: Generating alt_sld_fab \"alt_sld_fab\" for QUARTUS_SYNTH" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214709399 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: \"alt_sld_fab\" instantiated alt_sld_fab \"alt_sld_fab\" " "Alt_sld_fab: \"alt_sld_fab\" instantiated alt_sld_fab \"alt_sld_fab\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214715552 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Presplit: \"alt_sld_fab\" instantiated altera_super_splitter \"presplit\" " "Presplit: \"alt_sld_fab\" instantiated altera_super_splitter \"presplit\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214716471 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Splitter: \"alt_sld_fab\" instantiated altera_sld_splitter \"splitter\" " "Splitter: \"alt_sld_fab\" instantiated altera_sld_splitter \"splitter\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214717379 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Sldfabric: \"alt_sld_fab\" instantiated altera_sld_jtag_hub \"sldfabric\" " "Sldfabric: \"alt_sld_fab\" instantiated altera_sld_jtag_hub \"sldfabric\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214718324 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Ident: \"alt_sld_fab\" instantiated altera_connection_identification_hub \"ident\" " "Ident: \"alt_sld_fab\" instantiated altera_connection_identification_hub \"ident\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214718350 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: Done \"alt_sld_fab\" with 6 modules, 6 files " "Alt_sld_fab: Done \"alt_sld_fab\" with 6 modules, 6 files" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214718351 ""} -{ "Info" "ISCI_END_SUPER_FABRIC_GEN" "alt_sld_fab " "Finished IP generation for the debug fabric: alt_sld_fab." { } { } 0 11171 "Finished IP generation for the debug fabric: %1!s!." 0 0 "Analysis & Synthesis" 0 -1 1617214719144 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld0b974a4e/alt_sld_fab.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/alt_sld_fab.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab " "Found entity 1: alt_sld_fab" { } { { "db/ip/sld0b974a4e/alt_sld_fab.v" "" { Text "C:/FPGA/db/ip/sld0b974a4e/alt_sld_fab.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214719932 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214719932 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab " "Found entity 1: alt_sld_fab_alt_sld_fab" { } { { "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v" "" { Text "C:/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214720215 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214720215 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_ident " "Found entity 1: alt_sld_fab_alt_sld_fab_ident" { } { { "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv" "" { Text "C:/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214720306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214720306 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_presplit " "Found entity 1: alt_sld_fab_alt_sld_fab_presplit" { } { { "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" "" { Text "C:/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214720509 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214720509 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alt_sld_fab_alt_sld_fab_sldfabric-rtl " "Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl" { } { { "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" "" { Text "C:/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" 102 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214720748 ""} { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_sldfabric " "Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric" { } { { "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" "" { Text "C:/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" 11 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214720748 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214720748 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_splitter.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_splitter " "Found entity 1: alt_sld_fab_alt_sld_fab_splitter" { } { { "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" "" { Text "C:/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1617214720976 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214720976 ""} -{ "Info" "ISGN_QIC_SYNTHESIS_TOP_SEVERAL" "2 " "2 design partitions require synthesis" { { "Info" "ISGN_QIC_SYNTHESIS_REASON_FILE_CHANGE" "Top " "Partition \"Top\" requires synthesis because there were changes to its dependent source files" { } { } 0 12211 "Partition \"%1!s!\" requires synthesis because there were changes to its dependent source files" 0 0 "Design Software" 0 -1 1617214724230 ""} { "Info" "ISGN_QIC_SYNTHESIS_REASON_FILE_CHANGE" "sld_hub:auto_hub " "Partition \"sld_hub:auto_hub\" requires synthesis because there were changes to its dependent source files" { } { } 0 12211 "Partition \"%1!s!\" requires synthesis because there were changes to its dependent source files" 0 0 "Design Software" 0 -1 1617214724230 ""} } { } 0 12206 "%1!d! design partitions require synthesis" 0 0 "Analysis & Synthesis" 0 -1 1617214724230 ""} -{ "Info" "ISGN_QIC_NO_SYNTHESIS_TOP_ZERO" "" "No design partitions will skip synthesis in the current incremental compilation" { } { } 0 12209 "No design partitions will skip synthesis in the current incremental compilation" 0 0 "Analysis & Synthesis" 0 -1 1617214724231 ""} -{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|altsyncram_dah1:FIFOram\|q_b\[32\] " "Synthesized away node \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|altsyncram_dah1:FIFOram\|q_b\[32\]\"" { } { { "db/altsyncram_dah1.tdf" "" { Text "C:/FPGA/db/altsyncram_dah1.tdf" 1063 2 0 } } { "db/a_dpfifo_7qv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_7qv.tdf" 44 2 0 } } { "db/scfifo_ai71.tdf" "" { Text "C:/FPGA/db/scfifo_ai71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 358 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1617214725061 "|WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ai71:auto_generated|a_dpfifo_7qv:dpfifo|altsyncram_dah1:FIFOram|ram_block1a32"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[23\] " "Synthesized away node \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[23\]\"" { } { { "db/altsyncram_h7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_h7h1.tdf" 775 2 0 } } { "db/a_dpfifo_vkv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_vkv.tdf" 44 2 0 } } { "db/scfifo_ef71.tdf" "" { Text "C:/FPGA/db/scfifo_ef71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1617214725061 "|WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|altsyncram_h7h1:FIFOram|ram_block1a23"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[24\] " "Synthesized away node \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[24\]\"" { } { { "db/altsyncram_h7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_h7h1.tdf" 807 2 0 } } { "db/a_dpfifo_vkv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_vkv.tdf" 44 2 0 } } { "db/scfifo_ef71.tdf" "" { Text "C:/FPGA/db/scfifo_ef71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1617214725061 "|WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|altsyncram_h7h1:FIFOram|ram_block1a24"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|altsyncram_dah1:FIFOram\|q_b\[32\] " "Synthesized away node \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|altsyncram_dah1:FIFOram\|q_b\[32\]\"" { } { { "db/altsyncram_dah1.tdf" "" { Text "C:/FPGA/db/altsyncram_dah1.tdf" 1063 2 0 } } { "db/a_dpfifo_7qv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_7qv.tdf" 44 2 0 } } { "db/scfifo_ai71.tdf" "" { Text "C:/FPGA/db/scfifo_ai71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 358 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1617214725061 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ai71:auto_generated|a_dpfifo_7qv:dpfifo|altsyncram_dah1:FIFOram|ram_block1a32"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[23\] " "Synthesized away node \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[23\]\"" { } { { "db/altsyncram_h7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_h7h1.tdf" 775 2 0 } } { "db/a_dpfifo_vkv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_vkv.tdf" 44 2 0 } } { "db/scfifo_ef71.tdf" "" { Text "C:/FPGA/db/scfifo_ef71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1617214725061 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|altsyncram_h7h1:FIFOram|ram_block1a23"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[24\] " "Synthesized away node \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[24\]\"" { } { { "db/altsyncram_h7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_h7h1.tdf" 807 2 0 } } { "db/a_dpfifo_vkv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_vkv.tdf" 44 2 0 } } { "db/scfifo_ef71.tdf" "" { Text "C:/FPGA/db/scfifo_ef71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1617214725061 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|altsyncram_h7h1:FIFOram|ram_block1a24"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "tx_cic:TX_CIC_Q\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|altsyncram_hah1:FIFOram\|q_b\[16\] " "Synthesized away node \"tx_cic:TX_CIC_Q\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|altsyncram_hah1:FIFOram\|q_b\[16\]\"" { } { { "db/altsyncram_hah1.tdf" "" { Text "C:/FPGA/db/altsyncram_hah1.tdf" 551 2 0 } } { "db/a_dpfifo_9qv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 44 2 0 } } { "db/scfifo_ci71.tdf" "" { Text "C:/FPGA/db/scfifo_ci71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } { "db/ip/tx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 358 0 0 } } { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/tx_cic/tx_cic.v" "" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 31 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 248 4928 5184 480 "TX_CIC_Q" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1617214725061 "|WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|altsyncram_hah1:FIFOram|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "tx_cic:TX_CIC_Q\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[16\] " "Synthesized away node \"tx_cic:TX_CIC_Q\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[16\]\"" { } { { "db/altsyncram_l7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_l7h1.tdf" 551 2 0 } } { "db/a_dpfifo_1lv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 44 2 0 } } { "db/scfifo_gf71.tdf" "" { Text "C:/FPGA/db/scfifo_gf71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/tx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/tx_cic/tx_cic.v" "" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 31 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 248 4928 5184 480 "TX_CIC_Q" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1617214725061 "|WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|altsyncram_l7h1:FIFOram|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "tx_cic:TX_CIC_Q\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[17\] " "Synthesized away node \"tx_cic:TX_CIC_Q\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[17\]\"" { } { { "db/altsyncram_l7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_l7h1.tdf" 583 2 0 } } { "db/a_dpfifo_1lv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 44 2 0 } } { "db/scfifo_gf71.tdf" "" { Text "C:/FPGA/db/scfifo_gf71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/tx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/tx_cic/tx_cic.v" "" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 31 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 248 4928 5184 480 "TX_CIC_Q" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1617214725061 "|WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|altsyncram_l7h1:FIFOram|ram_block1a17"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|altsyncram_hah1:FIFOram\|q_b\[16\] " "Synthesized away node \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|altsyncram_hah1:FIFOram\|q_b\[16\]\"" { } { { "db/altsyncram_hah1.tdf" "" { Text "C:/FPGA/db/altsyncram_hah1.tdf" 551 2 0 } } { "db/a_dpfifo_9qv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 44 2 0 } } { "db/scfifo_ci71.tdf" "" { Text "C:/FPGA/db/scfifo_ci71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } { "db/ip/tx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 358 0 0 } } { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/tx_cic/tx_cic.v" "" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 31 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -40 4928 5184 192 "TX_CIC_I" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1617214725061 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|altsyncram_hah1:FIFOram|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[16\] " "Synthesized away node \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[16\]\"" { } { { "db/altsyncram_l7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_l7h1.tdf" 551 2 0 } } { "db/a_dpfifo_1lv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 44 2 0 } } { "db/scfifo_gf71.tdf" "" { Text "C:/FPGA/db/scfifo_gf71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/tx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/tx_cic/tx_cic.v" "" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 31 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -40 4928 5184 192 "TX_CIC_I" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1617214725061 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|altsyncram_l7h1:FIFOram|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[17\] " "Synthesized away node \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[17\]\"" { } { { "db/altsyncram_l7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_l7h1.tdf" 583 2 0 } } { "db/a_dpfifo_1lv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 44 2 0 } } { "db/scfifo_gf71.tdf" "" { Text "C:/FPGA/db/scfifo_gf71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/tx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/tx_cic/tx_cic.v" "" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 31 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -40 4928 5184 192 "TX_CIC_I" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1617214725061 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|altsyncram_l7h1:FIFOram|ram_block1a17"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1617214725061 ""} } { } 0 14284 "Synthesized away the following node(s):" 1 0 "Analysis & Synthesis" 0 -1 1617214725061 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1617214726599 ""} -{ "Info" "IQSYN_PARALLEL_SYNTHESIS" "8 2 " "Using 8 processors to synthesize 2 partitions in parallel" { } { } 0 281037 "Using %1!d! processors to synthesize %2!d! partitions in parallel" 0 0 "Analysis & Synthesis" 0 -1 1617214726905 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 0 1617214728639 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 0 1617214728651 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 31 21:18:47 2021 " "Processing started: Wed Mar 31 21:18:47 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 0 1617214728651 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214728651 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --parallel=1 --helper=0 --helper_type=user_partition --partition=Top WOLF-LITE -c WOLF-LITE " "Command: quartus_map --parallel=1 --helper=0 --helper_type=user_partition --partition=Top WOLF-LITE -c WOLF-LITE" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214728651 ""} -{ "Info" "ILPMS_INFERENCING_SUMMARY" "8 " "Inferred 8 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult1\"" { } { { "db/ip/tx_nco/submodules/asj_nco_madx_cen.v" "Mult1" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult0\"" { } { { "db/ip/tx_nco/submodules/asj_nco_madx_cen.v" "Mult0" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v" 50 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult1\"" { } { { "db/ip/tx_nco/submodules/asj_nco_mady_cen.v" "Mult1" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mady_cen.v" 52 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult0\"" { } { { "db/ip/tx_nco/submodules/asj_nco_mady_cen.v" "Mult0" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mady_cen.v" 51 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult1\"" { } { { "db/ip/nco/submodules/asj_nco_madx_cen.v" "Mult1" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult0\"" { } { { "db/ip/nco/submodules/asj_nco_madx_cen.v" "Mult0" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v" 50 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult1\"" { } { { "db/ip/nco/submodules/asj_nco_mady_cen.v" "Mult1" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mady_cen.v" 52 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult0\"" { } { { "db/ip/nco/submodules/asj_nco_mady_cen.v" "Mult0" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mady_cen.v" 51 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 0 1617214747284 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1\"" { } { { "db/ip/tx_nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 0 1617214747698 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1 " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 16 " "Parameter \"LPM_WIDTHA\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 16 " "Parameter \"LPM_WIDTHB\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 32 " "Parameter \"LPM_WIDTHP\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 32 " "Parameter \"LPM_WIDTHR\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} } { { "db/ip/tx_nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 0 1617214747700 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_36t.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_36t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_36t " "Found entity 1: mult_36t" { } { { "db/mult_36t.tdf" "" { Text "C:/FPGA/db/mult_36t.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1617214747875 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214747875 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1\"" { } { { "db/ip/nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 0 1617214748396 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1 " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 12 " "Parameter \"LPM_WIDTHA\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 12 " "Parameter \"LPM_WIDTHB\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 24 " "Parameter \"LPM_WIDTHP\" = \"24\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 24 " "Parameter \"LPM_WIDTHR\" = \"24\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} } { { "db/ip/nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 0 1617214748396 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_t5t.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_t5t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_t5t " "Found entity 1: mult_t5t" { } { { "db/mult_t5t.tdf" "" { Text "C:/FPGA/db/mult_t5t.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1617214748595 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214748595 ""} -{ "Info" "IBAL_BAL_CONVERTED_RAM_SLICES_TO_LCELLS_TOP_MSG" "2 " "Converted the following 2 logical RAM block slices to logic cells" { { "Info" "IBAL_BAL_CONVERTED_LOGICAL_RAM_GROUP_TO_LCELLS" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ALTSYNCRAM " "Converted the following logical RAM block \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ALTSYNCRAM\" slices to logic cells" { { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a53 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a53\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1735 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a54 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a54\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1767 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a55 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a55\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1799 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a56 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a56\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1831 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a57 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a57\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1863 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a58 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a58\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1895 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a59 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a59\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1927 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a60 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a60\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1959 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a61 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a61\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1991 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a62 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a62\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2023 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a63 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a63\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2055 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a64 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a64\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2087 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a65 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a65\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2119 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a66 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a66\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2151 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a67 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a67\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2183 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a68 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a68\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2215 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a69 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a69\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2247 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a70 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a70\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2279 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a71 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a71\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2311 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a72 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a72\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2343 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a73 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a73\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2375 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a74 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a74\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2407 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a75 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a75\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2439 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a76 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a76\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2471 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a77 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a77\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2503 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a78 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a78\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2535 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a79 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a79\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2567 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a80 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a80\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2599 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a81 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a81\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2631 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a82 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a82\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2663 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a83 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a83\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2695 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a84 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a84\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2727 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a52 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a52\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1703 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a51 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a51\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1671 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a50 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a50\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1639 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a49 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a49\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1607 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a48 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a48\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1575 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a47 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a47\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1543 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a46 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a46\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1511 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a45 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a45\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1479 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a44 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a44\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1447 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a43 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a43\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1415 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a42 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a42\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1383 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a41 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a41\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1351 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a40 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a40\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1319 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a39 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a39\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1287 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a38 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a38\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1255 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a37 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a37\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1223 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a36 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a36\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1191 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a35 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a35\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1159 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a34 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a34\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1127 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a33 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a33\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1095 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a32 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a32\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1063 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a31 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a31\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1031 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a30 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a30\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 999 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a29 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a29\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 967 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a28 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a28\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 935 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a27 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a27\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 903 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a26 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a26\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 871 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a25 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a25\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 839 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a24 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a24\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 807 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a23 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a23\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 775 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a22 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a22\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 743 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a21 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a21\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 711 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a20 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a20\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 679 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a19 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a19\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 647 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a18 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a18\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 615 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a17 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a17\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 583 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a16 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a16\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 551 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a15 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a15\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 519 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a14 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a14\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 487 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a13 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a13\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 455 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a12 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a12\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 423 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a11 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a11\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 391 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a10 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a10\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 359 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a9 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a9\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 327 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a8 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a8\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 295 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a7 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a7\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 263 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a6 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a6\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 231 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a5 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a5\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 199 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a4 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a4\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 167 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a3 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a3\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 135 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a2 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a2\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 103 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a1 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a1\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 71 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a0 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a0\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 39 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} } { } 0 270022 "Converted the following logical RAM block \"%1!s!\" slices to logic cells" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_CONVERTED_LOGICAL_RAM_GROUP_TO_LCELLS" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ALTSYNCRAM " "Converted the following logical RAM block \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ALTSYNCRAM\" slices to logic cells" { { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a53 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a53\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1735 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a54 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a54\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1767 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a55 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a55\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1799 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a56 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a56\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1831 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a57 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a57\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1863 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a58 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a58\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1895 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a59 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a59\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1927 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a60 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a60\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1959 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a61 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a61\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1991 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a62 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a62\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2023 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a63 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a63\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2055 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a64 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a64\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2087 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a65 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a65\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2119 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a66 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a66\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2151 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a67 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a67\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2183 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a68 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a68\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2215 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a69 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a69\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2247 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a70 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a70\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2279 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a71 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a71\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2311 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a72 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a72\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2343 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a73 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a73\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2375 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a74 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a74\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2407 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a75 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a75\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2439 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a76 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a76\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2471 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a77 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a77\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2503 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a78 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a78\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2535 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a79 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a79\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2567 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a80 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a80\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2599 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a81 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a81\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2631 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a82 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a82\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2663 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a83 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a83\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2695 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a84 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a84\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2727 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a52 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a52\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1703 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a51 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a51\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1671 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a50 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a50\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1639 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a49 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a49\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1607 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a48 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a48\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1575 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a47 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a47\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1543 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a46 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a46\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1511 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a45 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a45\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1479 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a44 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a44\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1447 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a43 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a43\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1415 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a42 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a42\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1383 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a41 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a41\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1351 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a40 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a40\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1319 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a39 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a39\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1287 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a38 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a38\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1255 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a37 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a37\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1223 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a36 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a36\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1191 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a35 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a35\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1159 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a34 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a34\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1127 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a33 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a33\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1095 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a32 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a32\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1063 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a31 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a31\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1031 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a30 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a30\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 999 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a29 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a29\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 967 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a28 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a28\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 935 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a27 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a27\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 903 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a26 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a26\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 871 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a25 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a25\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 839 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a24 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a24\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 807 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a23 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a23\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 775 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a22 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a22\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 743 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a21 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a21\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 711 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a20 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a20\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 679 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a19 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a19\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 647 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a18 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a18\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 615 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a17 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a17\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 583 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a16 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a16\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 551 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a15 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a15\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 519 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a14 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a14\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 487 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a13 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a13\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 455 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a12 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a12\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 423 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a11 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a11\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 391 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a10 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a10\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 359 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a9 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a9\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 327 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a8 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a8\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 295 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a7 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a7\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 263 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a6 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a6\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 231 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a5 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a5\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 199 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a4 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a4\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 167 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a3 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a3\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 135 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a2 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a2\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 103 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a1 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a1\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 71 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a0 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a0\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 39 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} } { } 0 270022 "Converted the following logical RAM block \"%1!s!\" slices to logic cells" 0 0 "Design Software" 0 0 1617214749566 ""} } { } 0 270023 "Converted the following %1!d! logical RAM block slices to logic cells" 0 0 "Analysis & Synthesis" 0 0 1617214749566 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|altsyncram:ram_block1a0 " "Elaborated megafunction instantiation \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|altsyncram:ram_block1a0\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 39 2 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 0 1617214750267 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|altsyncram:ram_block1a0 " "Instantiated megafunction \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|altsyncram:ram_block1a0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE altsyncram " "Parameter \"LPM_TYPE\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 85 " "Parameter \"WIDTH_A\" = \"85\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 2 " "Parameter \"WIDTHAD_A\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 4 " "Parameter \"NUMWORDS_A\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_A UNREGISTERED " "Parameter \"OUTDATA_REG_A\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_A NONE " "Parameter \"OUTDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "BYTEENA_ACLR_A NONE " "Parameter \"BYTEENA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_INPUT_A BYPASS " "Parameter \"CLOCK_ENABLE_INPUT_A\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_OUTPUT_A BYPASS " "Parameter \"CLOCK_ENABLE_OUTPUT_A\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 85 " "Parameter \"WIDTH_B\" = \"85\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 2 " "Parameter \"WIDTHAD_B\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 4 " "Parameter \"NUMWORDS_B\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_REG_B UNUSED " "Parameter \"INDATA_REG_B\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_WRADDRESS_REG_B CLOCK1 " "Parameter \"WRCONTROL_WRADDRESS_REG_B\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RDCONTROL_REG_B CLOCK1 " "Parameter \"RDCONTROL_REG_B\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK1 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "BYTEENA_REG_B UNUSED " "Parameter \"BYTEENA_REG_B\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B CLOCK1 " "Parameter \"OUTDATA_REG_B\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_B NONE " "Parameter \"INDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_B NONE " "Parameter \"WRCONTROL_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RDCONTROL_ACLR_B NONE " "Parameter \"RDCONTROL_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "BYTEENA_ACLR_B NONE " "Parameter \"BYTEENA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_INPUT_B BYPASS " "Parameter \"CLOCK_ENABLE_INPUT_B\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_OUTPUT_B NORMAL " "Parameter \"CLOCK_ENABLE_OUTPUT_B\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_BYTEENA_A 1 " "Parameter \"WIDTH_BYTEENA_A\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_BYTEENA_B 1 " "Parameter \"WIDTH_BYTEENA_B\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RAM_BLOCK_TYPE AUTO " "Parameter \"RAM_BLOCK_TYPE\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "BYTE_SIZE 8 " "Parameter \"BYTE_SIZE\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS DONT_CARE " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE " "Parameter \"INIT_FILE\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE_LAYOUT PORT_B " "Parameter \"INIT_FILE_LAYOUT\" = \"PORT_B\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMUM_DEPTH 4 " "Parameter \"MAXIMUM_DEPTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ENABLE_RUNTIME_MOD NO " "Parameter \"ENABLE_RUNTIME_MOD\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_NAME UNUSED " "Parameter \"INSTANCE_NAME\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ENABLE_ECC FALSE " "Parameter \"ENABLE_ECC\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ECCSTATUS_REG UNREGISTERED " "Parameter \"ECCSTATUS_REG\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_CORE_A BYPASS " "Parameter \"CLOCK_ENABLE_CORE_A\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_CORE_B BYPASS " "Parameter \"CLOCK_ENABLE_CORE_B\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_PORT_A NEW_DATA_WITH_NBE_READ " "Parameter \"READ_DURING_WRITE_MODE_PORT_A\" = \"NEW_DATA_WITH_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_PORT_B NEW_DATA_WITH_NBE_READ " "Parameter \"READ_DURING_WRITE_MODE_PORT_B\" = \"NEW_DATA_WITH_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_ECC_STATUS NORMAL " "Parameter \"CLOCK_ENABLE_ECC_STATUS\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IMPLEMENT_IN_LES ON " "Parameter \"IMPLEMENT_IN_LES\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 39 2 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 0 1617214750267 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_lci3.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_lci3.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_lci3 " "Found entity 1: altsyncram_lci3" { } { { "db/altsyncram_lci3.tdf" "" { Text "C:/FPGA/db/altsyncram_lci3.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1617214750512 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214750512 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "C:/FPGA/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1617214750778 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214750778 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_rob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_rob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_rob " "Found entity 1: mux_rob" { } { { "db/mux_rob.tdf" "" { Text "C:/FPGA/db/mux_rob.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1617214751033 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214751033 ""} -{ "Info" "IQSYN_SYNTHESIZE_TOP_PARTITION" "" "Starting Logic Optimization and Technology Mapping for Top Partition" { } { } 0 281020 "Starting Logic Optimization and Technology Mapping for Top Partition" 0 0 "Analysis & Synthesis" 0 0 1617214753213 ""} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 speed 102 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"speed\" technology mapper which leaves 102 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 0 1617214753685 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 388 -1 0 } } { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 299 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 0 1617214754076 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 0 1617214754076 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 0 1617214761017 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "37 " "37 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 0 1617214771659 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" { } { } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214772323 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Analysis & Synthesis" 0 0 1617214774011 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1617214774011 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1617214774011 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 16.276 clk_sys " " 16.276 clk_sys" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1617214774011 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 clock_stm32 " " 40.000 clock_stm32" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1617214774011 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 81.380 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 81.380 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1617214774011 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "20833.280 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\] " "20833.280 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1617214774011 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 6.510 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 6.510 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1617214774011 ""} } { } 0 332111 "%1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214774011 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" { } { } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214775099 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" { } { } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Analysis & Synthesis" 0 0 1617214775450 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:03 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:03" { } { } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Analysis & Synthesis" 0 0 1617214775476 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "10680 " "Implemented 10680 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "33 " "Implemented 33 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 0 1617214775615 ""} { "Info" "ICUT_CUT_TM_OPINS" "41 " "Implemented 41 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 0 1617214775615 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 0 1617214775615 ""} { "Info" "ICUT_CUT_TM_LCELLS" "10205 " "Implemented 10205 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 0 1617214775615 ""} { "Info" "ICUT_CUT_TM_RAMS" "354 " "Implemented 354 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 0 1617214775615 ""} { "Info" "ICUT_CUT_TM_PLLS" "2 " "Implemented 2 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 0 1617214775615 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "36 " "Implemented 36 DSP elements" { } { } 0 21062 "Implemented %1!d! DSP elements" 0 0 "Design Software" 0 0 1617214775615 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 0 1617214775615 ""} -{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DEBUG2 16 " "Ignored 16 assignments for entity \"DEBUG2\" -- entity does not exist in design" { } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 0 1617214776316 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4914 " "Peak virtual memory: 4914 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 0 1617214776663 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 31 21:19:36 2021 " "Processing ended: Wed Mar 31 21:19:36 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 0 1617214776663 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:49 " "Elapsed time: 00:00:49" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 0 1617214776663 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:56 " "Total CPU time (on all processors): 00:00:56" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 0 1617214776663 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 0 1617214776663 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 1 1617214728618 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 1 1617214728631 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 31 21:18:47 2021 " "Processing started: Wed Mar 31 21:18:47 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 1 1617214728631 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 1 1617214728631 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --parallel=1 --helper=1 --helper_type=user_partition --partition=sld_hub:auto_hub WOLF-LITE -c WOLF-LITE " "Command: quartus_map --parallel=1 --helper=1 --helper_type=user_partition --partition=sld_hub:auto_hub WOLF-LITE -c WOLF-LITE" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 1 1617214728631 ""} -{ "Info" "IQSYN_SYNTHESIZE_PARTITION" "sld_hub:auto_hub " "Starting Logic Optimization and Technology Mapping for Partition sld_hub:auto_hub" { } { } 0 281019 "Starting Logic Optimization and Technology Mapping for Partition %1!s!" 0 0 "Analysis & Synthesis" 0 1 1617214732400 ""} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 speed 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"speed\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 1 1617214732892 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "sld_jtag_hub.vhd" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 386 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 1 1617214732913 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 1 1617214732913 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_hub:auto_hub " "Timing-Driven Synthesis is running on partition \"sld_hub:auto_hub\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 1 1617214733211 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" { } { } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Analysis & Synthesis" 0 1 1617214734699 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Analysis & Synthesis" 0 1 1617214735119 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1617214735121 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1617214735121 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 16.276 clk_sys " " 16.276 clk_sys" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1617214735121 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 clock_stm32 " " 40.000 clock_stm32" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1617214735121 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 81.380 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 81.380 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1617214735121 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "20833.280 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\] " "20833.280 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1617214735121 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 6.510 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 6.510 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1617214735121 ""} } { } 0 332111 "%1!s!" 0 0 "Analysis & Synthesis" 0 1 1617214735121 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" { } { } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Analysis & Synthesis" 0 1 1617214735145 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" { } { } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Analysis & Synthesis" 0 1 1617214735298 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:01 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:01" { } { } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Analysis & Synthesis" 0 1 1617214735301 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "239 " "Implemented 239 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "39 " "Implemented 39 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 1 1617214735405 ""} { "Info" "ICUT_CUT_TM_OPINS" "56 " "Implemented 56 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 1 1617214735405 ""} { "Info" "ICUT_CUT_TM_LCELLS" "144 " "Implemented 144 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 1 1617214735405 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 1 1617214735405 ""} -{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DEBUG2 16 " "Ignored 16 assignments for entity \"DEBUG2\" -- entity does not exist in design" { } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 1 1617214735438 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4817 " "Peak virtual memory: 4817 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 1 1617214735530 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 31 21:18:55 2021 " "Processing ended: Wed Mar 31 21:18:55 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 1 1617214735530 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 1 1617214735530 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 1 1617214735530 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 1 1617214735530 ""} -{ "Info" "IQSYN_PARALLEL_SYNTHESIS_SUCCESS" "" "Finished parallel synthesis of all partitions" { } { } 0 281038 "Finished parallel synthesis of all partitions" 0 0 "Analysis & Synthesis" 0 -1 1617214777497 ""} -{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DEBUG2 16 " "Ignored 16 assignments for entity \"DEBUG2\" -- entity does not exist in design" { } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 -1 1617214777602 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/FPGA/output_files/WOLF-LITE.map.smsg " "Generated suppressed messages file C:/FPGA/output_files/WOLF-LITE.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214782129 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4976 " "Peak virtual memory: 4976 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1617214790232 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 31 21:19:50 2021 " "Processing ended: Wed Mar 31 21:19:50 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1617214790232 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:05:11 " "Elapsed time: 00:05:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1617214790232 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:07:52 " "Total CPU time (on all processors): 00:07:52" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1617214790232 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1617214790232 ""} diff --git a/FPGA_61.440/db/WOLF-LITE.map.rcfdb b/FPGA_61.440/db/WOLF-LITE.map.rcfdb deleted file mode 100644 index fab7039..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.map.rcfdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.map.rdb b/FPGA_61.440/db/WOLF-LITE.map.rdb deleted file mode 100644 index 77748a0..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.map.rdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.map_bb.cdb b/FPGA_61.440/db/WOLF-LITE.map_bb.cdb deleted file mode 100644 index fbc15e3..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.map_bb.cdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.map_bb.hdb b/FPGA_61.440/db/WOLF-LITE.map_bb.hdb deleted file mode 100644 index d20b698..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.map_bb.hdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.map_bb.logdb b/FPGA_61.440/db/WOLF-LITE.map_bb.logdb deleted file mode 100644 index f32998d..0000000 --- a/FPGA_61.440/db/WOLF-LITE.map_bb.logdb +++ /dev/null @@ -1,19 +0,0 @@ -v1 -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,tx_mixer:TX_MIXER_Q|lpm_mult:lpm_mult_component|mult_abt:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,tx_mixer:TX_MIXER_I|lpm_mult:lpm_mult_component|mult_abt:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component|mult_rcu:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component|mult_lcu:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,mixer:RX_MIXER_Q|lpm_mult:lpm_mult_component|mult_jnp:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,mixer:RX_MIXER_I|lpm_mult:lpm_mult_component|mult_jnp:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult0|mult_t5t:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult1|mult_t5t:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult0|mult_t5t:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,nco:RX_NCO|nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult1|mult_t5t:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult0|mult_36t:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_mady_cen:m0|lpm_mult:Mult1|mult_36t:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult0|mult_36t:auto_generated|mac_out2, -DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_madx_cen:m1|lpm_mult:Mult1|mult_36t:auto_generated|mac_out2, diff --git a/FPGA_61.440/db/WOLF-LITE.merge.qmsg b/FPGA_61.440/db/WOLF-LITE.merge.qmsg deleted file mode 100644 index cc6c8fc..0000000 --- a/FPGA_61.440/db/WOLF-LITE.merge.qmsg +++ /dev/null @@ -1,9 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1620759450304 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Partition Merge Quartus Prime " "Running Quartus Prime Partition Merge" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1620759450330 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 11 21:57:28 2021 " "Processing started: Tue May 11 21:57:28 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1620759450330 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1620759450330 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb --read_settings_files=on --write_settings_files=off WOLF-LITE -c WOLF-LITE --merge=on " "Command: quartus_cdb --read_settings_files=on --write_settings_files=off WOLF-LITE -c WOLF-LITE --merge=on" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1620759450330 ""} -{ "Info" "IAMERGE_PARTITION_SOURCE_POST_FIT" "Top " "Using previously generated Fitter netlist for partition \"Top\"" { } { } 0 35006 "Using previously generated Fitter netlist for partition \"%1!s!\"" 0 0 "Design Software" 0 -1 1620759453104 ""} -{ "Info" "IAMERGE_PARTITION_SOURCE_SOURCE" "sld_hub:auto_hub " "Using synthesis netlist for partition \"sld_hub:auto_hub\"" { } { } 0 35007 "Using synthesis netlist for partition \"%1!s!\"" 0 0 "Design Software" 0 -1 1620759455605 ""} -{ "Info" "IAMERGE_ATOM_BLACKBOX_RESOLVED" "2 " "Resolved and merged 2 partition(s)" { } { } 0 35002 "Resolved and merged %1!d! partition(s)" 0 0 "Design Software" 0 -1 1620759457769 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "2 0 2 0 0 " "Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1620759457982 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Design Software" 0 -1 1620759457982 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "10515 " "Implemented 10515 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "20 " "Implemented 20 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1620759459462 ""} { "Info" "ICUT_CUT_TM_OPINS" "37 " "Implemented 37 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1620759459462 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1620759459462 ""} { "Info" "ICUT_CUT_TM_LCELLS" "10374 " "Implemented 10374 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1620759459462 ""} { "Info" "ICUT_CUT_TM_RAMS" "33 " "Implemented 33 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1620759459462 ""} { "Info" "ICUT_CUT_TM_PLLS" "2 " "Implemented 2 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1620759459462 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "36 " "Implemented 36 DSP elements" { } { } 0 21062 "Implemented %1!d! DSP elements" 0 0 "Design Software" 0 -1 1620759459462 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Design Software" 0 -1 1620759459462 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Partition Merge 0 s 0 s Quartus Prime " "Quartus Prime Partition Merge was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4775 " "Peak virtual memory: 4775 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1620759461727 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 11 21:57:41 2021 " "Processing ended: Tue May 11 21:57:41 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1620759461727 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1620759461727 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1620759461727 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1620759461727 ""} diff --git a/FPGA_61.440/db/WOLF-LITE.pow.qmsg b/FPGA_61.440/db/WOLF-LITE.pow.qmsg deleted file mode 100644 index 6cceea5..0000000 --- a/FPGA_61.440/db/WOLF-LITE.pow.qmsg +++ /dev/null @@ -1,41 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1620759540225 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Power Analyzer Quartus Prime " "Running Quartus Prime Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1620759540244 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 11 21:58:59 2021 " "Processing started: Tue May 11 21:58:59 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1620759540244 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Power Analyzer" 0 -1 1620759540244 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=off --write_settings_files=off WOLF-LITE -c WOLF-LITE " "Command: quartus_pow --read_settings_files=off --write_settings_files=off WOLF-LITE -c WOLF-LITE" { } { } 0 0 "Command: %1!s!" 0 0 "Power Analyzer" 0 -1 1620759540244 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1620759541123 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1620759541123 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1620759542572 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1620759542572 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1620759542572 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Power Analyzer" 0 -1 1620759542572 ""} -{ "Info" "ISTA_SDC_FOUND" "SDC.sdc " "Reading SDC File: 'SDC.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Power Analyzer" 0 -1 1620759542689 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 5 rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid port or pin or register or keeper or net or combinational node or node " "Ignored filter at SDC.sdc(5): rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid could not be matched with a port or pin or register or keeper or net or combinational node or node" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542692 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock SDC.sdc 5 Argument is not an object ID " "Ignored create_clock at SDC.sdc(5): Argument is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name \"iq_valid\" -period 48KHz \{rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid\} " "create_clock -name \"iq_valid\" -period 48KHz \{rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid\}" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759542694 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542694 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 7 clock_sys clock " "Ignored filter at SDC.sdc(7): clock_sys could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 7 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542694 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 7 iq_valid clock " "Ignored filter at SDC.sdc(7): iq_valid could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 7 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542695 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Power Analyzer" 0 -1 1620759542695 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{TX_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{TX_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1620759542697 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1620759542697 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 1280 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 1280 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1620759542697 ""} } { } 0 332110 "%1!s!" 0 0 "Power Analyzer" 0 -1 1620759542697 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 13 clock_crystal clock " "Ignored filter at SDC.sdc(13): clock_crystal could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542698 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_output_delay SDC.sdc 13 Argument -clock is not an object ID " "Ignored set_output_delay at SDC.sdc(13): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_output_delay -clock clock_crystal -max 36ps \[get_ports \{DAC_OUTPUT\[*\]\}\] " "set_output_delay -clock clock_crystal -max 36ps \[get_ports \{DAC_OUTPUT\[*\]\}\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759542698 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542698 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_output_delay SDC.sdc 14 Argument -clock is not an object ID " "Ignored set_output_delay at SDC.sdc(14): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_output_delay -clock clock_crystal -min 0ps \[get_ports \{DAC_OUTPUT\[*\]\}\] " "set_output_delay -clock clock_crystal -min 0ps \[get_ports \{DAC_OUTPUT\[*\]\}\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 14 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759542698 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 14 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542698 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 18 clock_adc clock " "Ignored filter at SDC.sdc(18): clock_adc could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542699 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 18 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(18): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_INPUT\[*\]\] " "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_INPUT\[*\]\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759542699 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542699 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 19 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(19): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_INPUT\[*\]\] " "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_INPUT\[*\]\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 19 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759542700 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 19 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542700 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 20 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(20): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_OTR\] " "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_OTR\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 20 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759542700 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 20 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542700 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 21 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(21): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_OTR\] " "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_OTR\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759542700 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542700 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 27 iq_valid clock " "Ignored filter at SDC.sdc(27): iq_valid could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542701 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 27 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(27): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759542701 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542701 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 28 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(28): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 28 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759542702 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 28 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542702 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 29 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(29): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 29 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759542702 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 29 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542702 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 30 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(30): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 30 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759542703 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 30 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542703 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 31 clock_sys clock " "Ignored filter at SDC.sdc(31): clock_sys could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542703 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 31 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(31): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759542703 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542703 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 32 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(32): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 32 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759542704 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 32 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1620759542704 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Node: rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_Q\[6\]\[15\] rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_Q\[6\]\[15\] is being clocked by rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1620759542755 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 1 0 "Power Analyzer" 0 -1 1620759542755 "|WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Power Analyzer" 0 -1 1620759542882 ""} -{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1620759543185 ""} -{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1620759543642 ""} -{ "Info" "IPUTIL_EXTERNAL_PUTIL_SAF_WRITTEN" "output_files/signal_activity.saf " "Created Signal Activity File output_files/signal_activity.saf" { } { } 0 221012 "Created Signal Activity File %1!s!" 0 0 "Power Analyzer" 0 -1 1620759543985 ""} -{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" { } { } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "Power Analyzer" 0 -1 1620759544185 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Power Analyzer" 0 -1 1620759544406 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Power Analyzer" 0 -1 1620759546322 ""} -{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "9.375 millions of transitions / sec " "Average toggle rate for this design is 9.375 millions of transitions / sec" { } { } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "Power Analyzer" 0 -1 1620759552349 ""} -{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "289.60 mW " "Total thermal power estimate for the design is 289.60 mW" { } { { "c:/intelfpga/18.1/quartus/bin64/Report_Window_01.qrpt" "" { Report "c:/intelfpga/18.1/quartus/bin64/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } } } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "Power Analyzer" 0 -1 1620759553377 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/FPGA/output_files/WOLF-LITE.pow.smsg " "Generated suppressed messages file C:/FPGA/output_files/WOLF-LITE.pow.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Power Analyzer" 0 -1 1620759553503 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Power Analyzer 0 s 20 s Quartus Prime " "Quartus Prime Power Analyzer was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4933 " "Peak virtual memory: 4933 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1620759554322 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 11 21:59:14 2021 " "Processing ended: Tue May 11 21:59:14 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1620759554322 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1620759554322 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:18 " "Total CPU time (on all processors): 00:00:18" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1620759554322 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Power Analyzer" 0 -1 1620759554322 ""} diff --git a/FPGA_61.440/db/WOLF-LITE.pre_map.hdb b/FPGA_61.440/db/WOLF-LITE.pre_map.hdb deleted file mode 100644 index 20fffd4..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.pre_map.hdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.quartus_db.empty-vpr.rcfdb b/FPGA_61.440/db/WOLF-LITE.quartus_db.empty-vpr.rcfdb deleted file mode 100644 index 8a40ff2..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.quartus_db.empty-vpr.rcfdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.quartus_db.retry.rcfdb b/FPGA_61.440/db/WOLF-LITE.quartus_db.retry.rcfdb deleted file mode 100644 index 3fd1548..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.quartus_db.retry.rcfdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.root_partition.map.reg_db.cdb b/FPGA_61.440/db/WOLF-LITE.root_partition.map.reg_db.cdb deleted file mode 100644 index 22f325e..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.root_partition.map.reg_db.cdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.root_partition.qmsg b/FPGA_61.440/db/WOLF-LITE.root_partition.qmsg deleted file mode 100644 index b5407c5..0000000 --- a/FPGA_61.440/db/WOLF-LITE.root_partition.qmsg +++ /dev/null @@ -1,28 +0,0 @@ -{ "Info" "ILPMS_INFERENCING_SUMMARY" "8 " "Inferred 8 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult1\"" { } { { "db/ip/tx_nco/submodules/asj_nco_madx_cen.v" "Mult1" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult0\"" { } { { "db/ip/tx_nco/submodules/asj_nco_madx_cen.v" "Mult0" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v" 50 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult1\"" { } { { "db/ip/tx_nco/submodules/asj_nco_mady_cen.v" "Mult1" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mady_cen.v" 52 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult0\"" { } { { "db/ip/tx_nco/submodules/asj_nco_mady_cen.v" "Mult0" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mady_cen.v" 51 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult1\"" { } { { "db/ip/nco/submodules/asj_nco_madx_cen.v" "Mult1" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult0\"" { } { { "db/ip/nco/submodules/asj_nco_madx_cen.v" "Mult0" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v" 50 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult1\"" { } { { "db/ip/nco/submodules/asj_nco_mady_cen.v" "Mult1" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mady_cen.v" 52 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult0\"" { } { { "db/ip/nco/submodules/asj_nco_mady_cen.v" "Mult0" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mady_cen.v" 51 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1617214747284 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 0 1617214747284 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1\"" { } { { "db/ip/tx_nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 0 1617214747698 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1 " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 16 " "Parameter \"LPM_WIDTHA\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 16 " "Parameter \"LPM_WIDTHB\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 32 " "Parameter \"LPM_WIDTHP\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 32 " "Parameter \"LPM_WIDTHR\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214747700 ""} } { { "db/ip/tx_nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 0 1617214747700 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_36t.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_36t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_36t " "Found entity 1: mult_36t" { } { { "db/mult_36t.tdf" "" { Text "C:/FPGA/db/mult_36t.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1617214747875 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214747875 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1\"" { } { { "db/ip/nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 0 1617214748396 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1 " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 12 " "Parameter \"LPM_WIDTHA\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 12 " "Parameter \"LPM_WIDTHB\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 24 " "Parameter \"LPM_WIDTHP\" = \"24\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 24 " "Parameter \"LPM_WIDTHR\" = \"24\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214748396 ""} } { { "db/ip/nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 0 1617214748396 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_t5t.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_t5t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_t5t " "Found entity 1: mult_t5t" { } { { "db/mult_t5t.tdf" "" { Text "C:/FPGA/db/mult_t5t.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1617214748595 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214748595 ""} -{ "Info" "IBAL_BAL_CONVERTED_RAM_SLICES_TO_LCELLS_TOP_MSG" "2 " "Converted the following 2 logical RAM block slices to logic cells" { { "Info" "IBAL_BAL_CONVERTED_LOGICAL_RAM_GROUP_TO_LCELLS" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ALTSYNCRAM " "Converted the following logical RAM block \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ALTSYNCRAM\" slices to logic cells" { { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a53 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a53\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1735 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a54 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a54\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1767 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a55 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a55\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1799 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a56 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a56\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1831 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a57 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a57\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1863 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a58 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a58\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1895 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a59 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a59\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1927 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a60 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a60\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1959 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a61 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a61\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1991 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a62 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a62\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2023 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a63 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a63\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2055 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a64 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a64\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2087 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a65 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a65\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2119 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a66 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a66\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2151 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a67 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a67\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2183 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a68 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a68\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2215 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a69 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a69\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2247 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a70 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a70\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2279 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a71 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a71\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2311 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a72 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a72\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2343 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a73 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a73\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2375 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a74 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a74\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2407 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a75 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a75\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2439 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a76 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a76\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2471 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a77 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a77\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2503 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a78 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a78\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2535 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a79 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a79\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2567 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a80 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a80\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2599 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a81 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a81\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2631 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a82 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a82\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2663 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a83 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a83\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2695 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a84 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a84\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2727 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a52 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a52\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1703 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a51 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a51\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1671 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a50 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a50\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1639 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a49 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a49\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1607 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a48 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a48\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1575 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a47 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a47\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1543 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a46 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a46\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1511 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a45 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a45\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1479 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a44 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a44\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1447 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a43 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a43\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1415 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a42 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a42\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1383 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a41 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a41\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1351 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a40 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a40\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1319 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a39 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a39\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1287 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a38 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a38\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1255 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a37 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a37\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1223 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a36 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a36\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1191 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a35 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a35\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1159 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a34 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a34\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1127 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a33 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a33\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1095 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a32 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a32\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1063 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a31 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a31\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1031 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a30 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a30\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 999 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a29 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a29\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 967 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a28 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a28\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 935 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a27 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a27\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 903 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a26 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a26\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 871 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a25 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a25\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 839 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a24 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a24\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 807 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a23 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a23\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 775 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a22 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a22\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 743 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a21 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a21\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 711 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a20 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a20\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 679 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a19 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a19\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 647 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a18 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a18\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 615 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a17 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a17\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 583 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a16 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a16\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 551 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a15 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a15\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 519 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a14 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a14\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 487 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a13 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a13\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 455 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a12 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a12\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 423 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a11 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a11\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 391 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a10 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a10\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 359 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a9 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a9\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 327 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a8 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a8\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 295 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a7 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a7\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 263 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a6 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a6\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 231 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a5 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a5\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 199 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a4 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a4\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 167 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a3 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a3\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 135 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a2 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a2\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 103 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a1 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a1\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 71 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a0 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a0\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 39 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} } { } 0 270022 "Converted the following logical RAM block \"%1!s!\" slices to logic cells" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_CONVERTED_LOGICAL_RAM_GROUP_TO_LCELLS" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ALTSYNCRAM " "Converted the following logical RAM block \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ALTSYNCRAM\" slices to logic cells" { { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a53 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a53\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1735 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a54 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a54\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1767 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a55 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a55\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1799 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a56 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a56\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1831 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a57 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a57\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1863 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a58 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a58\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1895 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a59 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a59\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1927 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a60 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a60\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1959 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a61 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a61\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1991 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a62 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a62\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2023 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a63 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a63\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2055 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a64 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a64\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2087 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a65 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a65\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2119 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a66 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a66\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2151 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a67 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a67\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2183 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a68 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a68\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2215 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a69 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a69\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2247 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a70 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a70\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2279 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a71 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a71\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2311 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a72 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a72\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2343 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a73 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a73\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2375 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a74 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a74\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2407 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a75 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a75\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2439 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a76 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a76\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2471 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a77 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a77\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2503 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a78 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a78\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2535 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a79 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a79\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2567 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a80 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a80\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2599 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a81 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a81\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2631 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a82 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a82\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2663 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a83 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a83\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2695 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a84 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a84\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 2727 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a52 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a52\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1703 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a51 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a51\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1671 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a50 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a50\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1639 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a49 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a49\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1607 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a48 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a48\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1575 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a47 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a47\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1543 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a46 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a46\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1511 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a45 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a45\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1479 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a44 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a44\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1447 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a43 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a43\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1415 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a42 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a42\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1383 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a41 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a41\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1351 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a40 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a40\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1319 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a39 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a39\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1287 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a38 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a38\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1255 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a37 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a37\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1223 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a36 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a36\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1191 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a35 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a35\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1159 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a34 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a34\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1127 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a33 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a33\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1095 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a32 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a32\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1063 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a31 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a31\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 1031 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a30 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a30\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 999 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a29 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a29\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 967 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a28 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a28\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 935 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a27 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a27\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 903 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a26 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a26\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 871 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a25 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a25\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 839 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a24 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a24\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 807 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a23 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a23\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 775 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a22 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a22\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 743 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a21 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a21\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 711 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a20 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a20\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 679 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a19 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a19\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 647 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a18 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a18\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 615 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a17 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a17\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 583 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a16 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a16\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 551 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a15 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a15\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 519 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a14 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a14\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 487 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a13 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a13\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 455 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a12 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a12\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 423 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a11 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a11\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 391 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a10 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a10\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 359 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a9 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a9\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 327 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a8 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a8\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 295 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a7 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a7\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 263 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a6 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a6\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 231 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a5 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a5\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 199 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a4 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a4\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 167 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a3 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a3\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 135 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a2 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a2\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 103 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a1 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a1\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 71 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a0 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|ram_block1a0\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 39 2 0 } } { "db/a_dpfifo_4ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_4ku.tdf" 42 2 0 } } { "db/scfifo_pm51.tdf" "" { Text "C:/FPGA/db/scfifo_pm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1617214749566 ""} } { } 0 270022 "Converted the following logical RAM block \"%1!s!\" slices to logic cells" 0 0 "Design Software" 0 0 1617214749566 ""} } { } 0 270023 "Converted the following %1!d! logical RAM block slices to logic cells" 0 0 "Analysis & Synthesis" 0 0 1617214749566 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|altsyncram:ram_block1a0 " "Elaborated megafunction instantiation \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|altsyncram:ram_block1a0\"" { } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 39 2 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 0 1617214750267 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|altsyncram:ram_block1a0 " "Instantiated megafunction \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_pm51:auto_generated\|a_dpfifo_4ku:dpfifo\|altsyncram_j7h1:FIFOram\|altsyncram:ram_block1a0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE altsyncram " "Parameter \"LPM_TYPE\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 85 " "Parameter \"WIDTH_A\" = \"85\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 2 " "Parameter \"WIDTHAD_A\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 4 " "Parameter \"NUMWORDS_A\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_A UNREGISTERED " "Parameter \"OUTDATA_REG_A\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_A NONE " "Parameter \"OUTDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "BYTEENA_ACLR_A NONE " "Parameter \"BYTEENA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_INPUT_A BYPASS " "Parameter \"CLOCK_ENABLE_INPUT_A\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_OUTPUT_A BYPASS " "Parameter \"CLOCK_ENABLE_OUTPUT_A\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 85 " "Parameter \"WIDTH_B\" = \"85\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 2 " "Parameter \"WIDTHAD_B\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 4 " "Parameter \"NUMWORDS_B\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_REG_B UNUSED " "Parameter \"INDATA_REG_B\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_WRADDRESS_REG_B CLOCK1 " "Parameter \"WRCONTROL_WRADDRESS_REG_B\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RDCONTROL_REG_B CLOCK1 " "Parameter \"RDCONTROL_REG_B\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK1 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "BYTEENA_REG_B UNUSED " "Parameter \"BYTEENA_REG_B\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B CLOCK1 " "Parameter \"OUTDATA_REG_B\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_B NONE " "Parameter \"INDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_B NONE " "Parameter \"WRCONTROL_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RDCONTROL_ACLR_B NONE " "Parameter \"RDCONTROL_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "BYTEENA_ACLR_B NONE " "Parameter \"BYTEENA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_INPUT_B BYPASS " "Parameter \"CLOCK_ENABLE_INPUT_B\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_OUTPUT_B NORMAL " "Parameter \"CLOCK_ENABLE_OUTPUT_B\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_BYTEENA_A 1 " "Parameter \"WIDTH_BYTEENA_A\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_BYTEENA_B 1 " "Parameter \"WIDTH_BYTEENA_B\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RAM_BLOCK_TYPE AUTO " "Parameter \"RAM_BLOCK_TYPE\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "BYTE_SIZE 8 " "Parameter \"BYTE_SIZE\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS DONT_CARE " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE " "Parameter \"INIT_FILE\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE_LAYOUT PORT_B " "Parameter \"INIT_FILE_LAYOUT\" = \"PORT_B\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMUM_DEPTH 4 " "Parameter \"MAXIMUM_DEPTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ENABLE_RUNTIME_MOD NO " "Parameter \"ENABLE_RUNTIME_MOD\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_NAME UNUSED " "Parameter \"INSTANCE_NAME\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ENABLE_ECC FALSE " "Parameter \"ENABLE_ECC\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ECCSTATUS_REG UNREGISTERED " "Parameter \"ECCSTATUS_REG\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_CORE_A BYPASS " "Parameter \"CLOCK_ENABLE_CORE_A\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_CORE_B BYPASS " "Parameter \"CLOCK_ENABLE_CORE_B\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_PORT_A NEW_DATA_WITH_NBE_READ " "Parameter \"READ_DURING_WRITE_MODE_PORT_A\" = \"NEW_DATA_WITH_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_PORT_B NEW_DATA_WITH_NBE_READ " "Parameter \"READ_DURING_WRITE_MODE_PORT_B\" = \"NEW_DATA_WITH_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_ECC_STATUS NORMAL " "Parameter \"CLOCK_ENABLE_ECC_STATUS\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IMPLEMENT_IN_LES ON " "Parameter \"IMPLEMENT_IN_LES\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1617214750267 ""} } { { "db/altsyncram_j7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_j7h1.tdf" 39 2 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 0 1617214750267 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_lci3.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_lci3.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_lci3 " "Found entity 1: altsyncram_lci3" { } { { "db/altsyncram_lci3.tdf" "" { Text "C:/FPGA/db/altsyncram_lci3.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1617214750512 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214750512 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "C:/FPGA/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1617214750778 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214750778 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_rob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_rob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_rob " "Found entity 1: mux_rob" { } { { "db/mux_rob.tdf" "" { Text "C:/FPGA/db/mux_rob.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1617214751033 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214751033 ""} -{ "Info" "IQSYN_SYNTHESIZE_TOP_PARTITION" "" "Starting Logic Optimization and Technology Mapping for Top Partition" { } { } 0 281020 "Starting Logic Optimization and Technology Mapping for Top Partition" 0 0 "Analysis & Synthesis" 0 0 1617214753213 ""} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 speed 102 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"speed\" technology mapper which leaves 102 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 0 1617214753685 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 388 -1 0 } } { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 299 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 0 1617214754076 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 0 1617214754076 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 0 1617214761017 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "37 " "37 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 0 1617214771659 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" { } { } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214772323 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Analysis & Synthesis" 0 0 1617214774011 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1617214774011 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1617214774011 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 16.276 clk_sys " " 16.276 clk_sys" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1617214774011 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 clock_stm32 " " 40.000 clock_stm32" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1617214774011 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 81.380 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 81.380 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1617214774011 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "20833.280 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\] " "20833.280 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1617214774011 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 6.510 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 6.510 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1617214774011 ""} } { } 0 332111 "%1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214774011 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" { } { } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Analysis & Synthesis" 0 0 1617214775099 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" { } { } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Analysis & Synthesis" 0 0 1617214775450 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:03 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:03" { } { } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Analysis & Synthesis" 0 0 1617214775476 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "10680 " "Implemented 10680 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "33 " "Implemented 33 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 0 1617214775615 ""} { "Info" "ICUT_CUT_TM_OPINS" "41 " "Implemented 41 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 0 1617214775615 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 0 1617214775615 ""} { "Info" "ICUT_CUT_TM_LCELLS" "10205 " "Implemented 10205 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 0 1617214775615 ""} { "Info" "ICUT_CUT_TM_RAMS" "354 " "Implemented 354 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 0 1617214775615 ""} { "Info" "ICUT_CUT_TM_PLLS" "2 " "Implemented 2 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 0 1617214775615 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "36 " "Implemented 36 DSP elements" { } { } 0 21062 "Implemented %1!d! DSP elements" 0 0 "Design Software" 0 0 1617214775615 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 0 1617214775615 ""} -{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DEBUG2 16 " "Ignored 16 assignments for entity \"DEBUG2\" -- entity does not exist in design" { } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 0 1617214776316 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4914 " "Peak virtual memory: 4914 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 0 1617214776663 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 31 21:19:36 2021 " "Processing ended: Wed Mar 31 21:19:36 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 0 1617214776663 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:49 " "Elapsed time: 00:00:49" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 0 1617214776663 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:56 " "Total CPU time (on all processors): 00:00:56" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 0 1617214776663 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 0 1617214776663 ""} diff --git a/FPGA_61.440/db/WOLF-LITE.routing.rdb b/FPGA_61.440/db/WOLF-LITE.routing.rdb deleted file mode 100644 index 6142a7b..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.routing.rdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.rtlv.hdb b/FPGA_61.440/db/WOLF-LITE.rtlv.hdb deleted file mode 100644 index 6d5b9a2..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.rtlv.hdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.rtlv_sg.cdb b/FPGA_61.440/db/WOLF-LITE.rtlv_sg.cdb deleted file mode 100644 index 35eda8c..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.rtlv_sg.cdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.rtlv_sg_swap.cdb b/FPGA_61.440/db/WOLF-LITE.rtlv_sg_swap.cdb deleted file mode 100644 index 9b3c010..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.rtlv_sg_swap.cdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.sld_design_entry.sci b/FPGA_61.440/db/WOLF-LITE.sld_design_entry.sci deleted file mode 100644 index 0cf4f27..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.sld_design_entry.sci and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.sld_design_entry_dsc.sci b/FPGA_61.440/db/WOLF-LITE.sld_design_entry_dsc.sci deleted file mode 100644 index 0e9bd88..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.sld_design_entry_dsc.sci and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.smart_action.txt b/FPGA_61.440/db/WOLF-LITE.smart_action.txt deleted file mode 100644 index c8e8a13..0000000 --- a/FPGA_61.440/db/WOLF-LITE.smart_action.txt +++ /dev/null @@ -1 +0,0 @@ -DONE diff --git a/FPGA_61.440/db/WOLF-LITE.smp_dump.txt b/FPGA_61.440/db/WOLF-LITE.smp_dump.txt deleted file mode 100644 index 00d17b3..0000000 --- a/FPGA_61.440/db/WOLF-LITE.smp_dump.txt +++ /dev/null @@ -1,32 +0,0 @@ - -State Machine - |WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state -Name sink_state.end1 sink_state.st_err sink_state.run1 sink_state.stall sink_state.start -sink_state.start 0 0 0 0 0 -sink_state.stall 0 0 0 1 1 -sink_state.run1 0 0 1 0 1 -sink_state.st_err 0 1 0 0 1 -sink_state.end1 1 0 0 0 1 - -State Machine - |WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state -Name sink_state.end1 sink_state.st_err sink_state.run1 sink_state.stall sink_state.start -sink_state.start 0 0 0 0 0 -sink_state.stall 0 0 0 1 1 -sink_state.run1 0 0 1 0 1 -sink_state.st_err 0 1 0 0 1 -sink_state.end1 1 0 0 0 1 - -State Machine - |WOLF-LITE|tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state -Name sink_state.end1 sink_state.st_err sink_state.run1 sink_state.stall sink_state.start -sink_state.start 0 0 0 0 0 -sink_state.stall 0 0 0 1 1 -sink_state.run1 0 0 1 0 1 -sink_state.st_err 0 1 0 0 1 -sink_state.end1 1 0 0 0 1 - -State Machine - |WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_sink_hpfir:sink|sink_state -Name sink_state.end1 sink_state.st_err sink_state.run1 sink_state.stall sink_state.start -sink_state.start 0 0 0 0 0 -sink_state.stall 0 0 0 1 1 -sink_state.run1 0 0 1 0 1 -sink_state.st_err 0 1 0 0 1 -sink_state.end1 1 0 0 0 1 diff --git a/FPGA_61.440/db/WOLF-LITE.sta.qmsg b/FPGA_61.440/db/WOLF-LITE.sta.qmsg deleted file mode 100644 index c286865..0000000 --- a/FPGA_61.440/db/WOLF-LITE.sta.qmsg +++ /dev/null @@ -1,67 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1620759557639 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1620759557656 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 11 21:59:16 2021 " "Processing started: Tue May 11 21:59:16 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1620759557656 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1620759557656 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta WOLF-LITE -c WOLF-LITE " "Command: quartus_sta WOLF-LITE -c WOLF-LITE" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1620759557657 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1620759557952 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1620759560450 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759560521 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759560522 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1620759561543 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1620759561543 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1620759561543 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Timing Analyzer" 0 -1 1620759561543 ""} -{ "Info" "ISTA_SDC_FOUND" "SDC.sdc " "Reading SDC File: 'SDC.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1620759561658 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 5 rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid port or pin or register or keeper or net or combinational node or node " "Ignored filter at SDC.sdc(5): rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid could not be matched with a port or pin or register or keeper or net or combinational node or node" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561661 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock SDC.sdc 5 Argument is not an object ID " "Ignored create_clock at SDC.sdc(5): Argument is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name \"iq_valid\" -period 48KHz \{rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid\} " "create_clock -name \"iq_valid\" -period 48KHz \{rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid\}" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759561661 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561661 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 7 clock_sys clock " "Ignored filter at SDC.sdc(7): clock_sys could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 7 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561662 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 7 iq_valid clock " "Ignored filter at SDC.sdc(7): iq_valid could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 7 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561662 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Timing Analyzer" 0 -1 1620759561662 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{TX_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{TX_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1620759561665 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1620759561665 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 1280 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 1280 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1620759561665 ""} } { } 0 332110 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1620759561665 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 13 clock_crystal clock " "Ignored filter at SDC.sdc(13): clock_crystal could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561665 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_output_delay SDC.sdc 13 Argument -clock is not an object ID " "Ignored set_output_delay at SDC.sdc(13): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_output_delay -clock clock_crystal -max 36ps \[get_ports \{DAC_OUTPUT\[*\]\}\] " "set_output_delay -clock clock_crystal -max 36ps \[get_ports \{DAC_OUTPUT\[*\]\}\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759561665 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561665 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_output_delay SDC.sdc 14 Argument -clock is not an object ID " "Ignored set_output_delay at SDC.sdc(14): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_output_delay -clock clock_crystal -min 0ps \[get_ports \{DAC_OUTPUT\[*\]\}\] " "set_output_delay -clock clock_crystal -min 0ps \[get_ports \{DAC_OUTPUT\[*\]\}\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 14 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759561666 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 14 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561666 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 18 clock_adc clock " "Ignored filter at SDC.sdc(18): clock_adc could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561666 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 18 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(18): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_INPUT\[*\]\] " "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_INPUT\[*\]\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759561666 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561666 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 19 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(19): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_INPUT\[*\]\] " "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_INPUT\[*\]\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 19 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759561667 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 19 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561667 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 20 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(20): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_OTR\] " "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_OTR\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 20 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759561667 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 20 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561667 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 21 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(21): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_OTR\] " "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_OTR\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759561668 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561668 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 27 iq_valid clock " "Ignored filter at SDC.sdc(27): iq_valid could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561668 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 27 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(27): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759561668 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561668 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 28 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(28): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 28 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759561669 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 28 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561669 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 29 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(29): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 29 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759561669 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 29 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561669 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 30 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(30): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 30 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759561669 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 30 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561669 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 31 clock_sys clock " "Ignored filter at SDC.sdc(31): clock_sys could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561670 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 31 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(31): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759561670 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561670 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 32 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(32): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 32 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1620759561670 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 32 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1620759561670 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Node: rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_Q\[6\]\[15\] rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_Q\[6\]\[15\] is being clocked by rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1620759561729 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 1 0 "Timing Analyzer" 0 -1 1620759561729 "|WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1620759561817 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = OFF" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = OFF" 0 0 "Timing Analyzer" 0 0 1620759561823 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1620759561927 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1620759562438 ""} } { } 1 332148 "Timing requirements not met" 1 0 "Timing Analyzer" 0 -1 1620759562438 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.047 " "Worst-case setup slack is -4.047" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562442 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562442 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.047 -281.793 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -4.047 -281.793 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562442 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.278 0.000 clk_sys " " 2.278 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562442 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 30.116 0.000 clock_stm32 " " 30.116 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562442 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 43.798 0.000 altera_reserved_tck " " 43.798 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562442 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759562442 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.405 " "Worst-case hold slack is 0.405" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562522 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562522 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.405 0.000 clk_sys " " 0.405 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562522 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.406 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.406 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562522 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.453 0.000 altera_reserved_tck " " 0.453 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562522 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.485 0.000 clock_stm32 " " 0.485 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562522 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759562522 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 2.835 " "Worst-case recovery slack is 2.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562536 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562536 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.835 0.000 clk_sys " " 2.835 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562536 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 94.965 0.000 altera_reserved_tck " " 94.965 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562536 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759562536 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.644 " "Worst-case removal slack is 1.644" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562557 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562557 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.644 0.000 altera_reserved_tck " " 1.644 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562557 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 12.574 0.000 clk_sys " " 12.574 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562557 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759562557 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.510 " "Worst-case minimum pulse width slack is 1.510" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.510 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.510 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.590 0.000 clk_sys " " 7.590 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.682 0.000 clock_stm32 " " 19.682 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.533 0.000 altera_reserved_tck " " 49.533 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759562570 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759562570 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 33 synchronizer chains. " "Report Metastability: Found 33 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759563076 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 33 " "Number of Synchronizer Chains Found: 33" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759563076 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 3 Registers " "Shortest Synchronizer Chain: 3 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759563076 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759563076 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 14.659 ns " "Worst Case Available Settling Time: 14.659 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759563076 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759563076 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1620759563076 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1620759563086 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1620759563150 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1620759565097 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Node: rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_Q\[6\]\[15\] rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_Q\[6\]\[15\] is being clocked by rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1620759565729 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 1 0 "Timing Analyzer" 0 -1 1620759565729 "|WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1620759565765 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1620759565991 ""} } { } 1 332148 "Timing requirements not met" 1 0 "Timing Analyzer" 0 -1 1620759565991 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.077 " "Worst-case setup slack is -3.077" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759565998 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759565998 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.077 -124.098 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -3.077 -124.098 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759565998 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.555 0.000 clk_sys " " 2.555 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759565998 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 30.946 0.000 clock_stm32 " " 30.946 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759565998 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 44.281 0.000 altera_reserved_tck " " 44.281 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759565998 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759565998 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.389 " "Worst-case hold slack is 0.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566079 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566079 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.389 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.389 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566079 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.389 0.000 clk_sys " " 0.389 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566079 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.401 0.000 altera_reserved_tck " " 0.401 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566079 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.430 0.000 clock_stm32 " " 0.430 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566079 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759566079 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 3.222 " "Worst-case recovery slack is 3.222" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566095 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566095 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.222 0.000 clk_sys " " 3.222 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566095 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 95.300 0.000 altera_reserved_tck " " 95.300 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566095 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759566095 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.477 " "Worst-case removal slack is 1.477" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566111 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566111 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.477 0.000 altera_reserved_tck " " 1.477 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566111 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 12.125 0.000 clk_sys " " 12.125 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566111 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759566111 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.510 " "Worst-case minimum pulse width slack is 1.510" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566125 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566125 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.510 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.510 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566125 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.615 0.000 clk_sys " " 7.615 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566125 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.593 0.000 clock_stm32 " " 19.593 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566125 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.414 0.000 altera_reserved_tck " " 49.414 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759566125 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759566125 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 33 synchronizer chains. " "Report Metastability: Found 33 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759566641 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 33 " "Number of Synchronizer Chains Found: 33" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759566641 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 3 Registers " "Shortest Synchronizer Chain: 3 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759566641 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759566641 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 14.900 ns " "Worst Case Available Settling Time: 14.900 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759566641 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759566641 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1620759566641 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1620759566653 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Node: rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_Q\[6\]\[15\] rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_Q\[6\]\[15\] is being clocked by rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1620759567143 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 1 0 "Timing Analyzer" 0 -1 1620759567143 "|WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1620759567175 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.697 " "Worst-case setup slack is 1.697" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.697 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.697 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.885 0.000 clk_sys " " 4.885 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.971 0.000 clock_stm32 " " 34.971 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.333 0.000 altera_reserved_tck " " 47.333 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567265 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759567265 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.132 " "Worst-case hold slack is 0.132" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567355 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567355 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.132 0.000 clk_sys " " 0.132 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567355 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.144 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.144 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567355 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 altera_reserved_tck " " 0.186 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567355 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.201 0.000 clock_stm32 " " 0.201 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567355 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759567355 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 5.083 " "Worst-case recovery slack is 5.083" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567373 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567373 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.083 0.000 clk_sys " " 5.083 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567373 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.756 0.000 altera_reserved_tck " " 97.756 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567373 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759567373 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.689 " "Worst-case removal slack is 0.689" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.689 0.000 altera_reserved_tck " " 0.689 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 10.625 0.000 clk_sys " " 10.625 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567392 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759567392 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 2.987 " "Worst-case minimum pulse width slack is 2.987" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567408 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567408 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.987 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.987 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567408 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.336 0.000 clk_sys " " 7.336 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567408 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.193 0.000 clock_stm32 " " 19.193 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567408 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.468 0.000 altera_reserved_tck " " 49.468 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1620759567408 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1620759567408 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 33 synchronizer chains. " "Report Metastability: Found 33 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759567973 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 33 " "Number of Synchronizer Chains Found: 33" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759567973 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 3 Registers " "Shortest Synchronizer Chain: 3 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759567973 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759567973 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17.360 ns " "Worst Case Available Settling Time: 17.360 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759567973 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1620759567973 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1620759567973 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1620759568497 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1620759568499 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/FPGA/output_files/WOLF-LITE.sta.smsg " "Generated suppressed messages file C:/FPGA/output_files/WOLF-LITE.sta.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Timing Analyzer" 0 -1 1620759568599 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 20 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4954 " "Peak virtual memory: 4954 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1620759568860 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 11 21:59:28 2021 " "Processing ended: Tue May 11 21:59:28 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1620759568860 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1620759568860 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1620759568860 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1620759568860 ""} diff --git a/FPGA_61.440/db/WOLF-LITE.sta.rdb b/FPGA_61.440/db/WOLF-LITE.sta.rdb deleted file mode 100644 index a36b46f..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.sta.rdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.sta_cmp.8_slow_1200mv_85c.tdb b/FPGA_61.440/db/WOLF-LITE.sta_cmp.8_slow_1200mv_85c.tdb deleted file mode 100644 index b8787a3..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.sta_cmp.8_slow_1200mv_85c.tdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.tis_db_list.ddb b/FPGA_61.440/db/WOLF-LITE.tis_db_list.ddb deleted file mode 100644 index 7dc5f0b..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.tis_db_list.ddb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.tiscmp.fast_1200mv_0c.ddb b/FPGA_61.440/db/WOLF-LITE.tiscmp.fast_1200mv_0c.ddb deleted file mode 100644 index 8faee6d..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.tiscmp.fast_1200mv_0c.ddb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.tiscmp.fastest_slow_1200mv_0c.ddb b/FPGA_61.440/db/WOLF-LITE.tiscmp.fastest_slow_1200mv_0c.ddb deleted file mode 100644 index 067468a..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.tiscmp.fastest_slow_1200mv_0c.ddb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.tiscmp.fastest_slow_1200mv_85c.ddb b/FPGA_61.440/db/WOLF-LITE.tiscmp.fastest_slow_1200mv_85c.ddb deleted file mode 100644 index b22c981..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.tiscmp.fastest_slow_1200mv_85c.ddb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.tiscmp.slow_1200mv_0c.ddb b/FPGA_61.440/db/WOLF-LITE.tiscmp.slow_1200mv_0c.ddb deleted file mode 100644 index 3d4883f..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.tiscmp.slow_1200mv_0c.ddb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.tiscmp.slow_1200mv_85c.ddb b/FPGA_61.440/db/WOLF-LITE.tiscmp.slow_1200mv_85c.ddb deleted file mode 100644 index 34a57e9..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.tiscmp.slow_1200mv_85c.ddb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE.tmw_info b/FPGA_61.440/db/WOLF-LITE.tmw_info deleted file mode 100644 index 9a8ee02..0000000 --- a/FPGA_61.440/db/WOLF-LITE.tmw_info +++ /dev/null @@ -1,5 +0,0 @@ -start_full_compilation:s -start_partition_merge:s-start_full_compilation -start_io_assignment_analysis:s-start_full_compilation -start_assembler:s-start_full_compilation -start_timing_analyzer:s-start_full_compilation diff --git a/FPGA_61.440/db/WOLF-LITE.vpr.ammdb b/FPGA_61.440/db/WOLF-LITE.vpr.ammdb deleted file mode 100644 index 70fa901..0000000 Binary files a/FPGA_61.440/db/WOLF-LITE.vpr.ammdb and /dev/null differ diff --git a/FPGA_61.440/db/WOLF-LITE_partition_pins.json b/FPGA_61.440/db/WOLF-LITE_partition_pins.json deleted file mode 100644 index 283b14f..0000000 --- a/FPGA_61.440/db/WOLF-LITE_partition_pins.json +++ /dev/null @@ -1,257 +0,0 @@ -{ - "partitions" : [ - { - "name" : "Top", - "pins" : [ - { - "name" : "PREAMP", - "strict" : false - }, - { - "name" : "FLASH_C", - "strict" : false - }, - { - "name" : "FLASH_S", - "strict" : false - }, - { - "name" : "FLASH_MOSI", - "strict" : false - }, - { - "name" : "DAC_PD", - "strict" : false - }, - { - "name" : "ATT_05", - "strict" : false - }, - { - "name" : "ATT_1", - "strict" : false - }, - { - "name" : "ATT_2", - "strict" : false - }, - { - "name" : "ATT_4", - "strict" : false - }, - { - "name" : "ATT_8", - "strict" : false - }, - { - "name" : "ATT_16", - "strict" : false - }, - { - "name" : "BPF_A", - "strict" : false - }, - { - "name" : "BPF_B", - "strict" : false - }, - { - "name" : "BPF_OE1", - "strict" : false - }, - { - "name" : "BPF_OE2", - "strict" : false - }, - { - "name" : "LPF_1", - "strict" : false - }, - { - "name" : "LPF_2", - "strict" : false - }, - { - "name" : "LPF_3", - "strict" : false - }, - { - "name" : "TXRX_OUT", - "strict" : false - }, - { - "name" : "DAC_OUTPUT[13]", - "strict" : false - }, - { - "name" : "DAC_OUTPUT[12]", - "strict" : false - }, - { - "name" : "DAC_OUTPUT[11]", - "strict" : false - }, - { - "name" : "DAC_OUTPUT[10]", - "strict" : false - }, - { - "name" : "DAC_OUTPUT[9]", - "strict" : false - }, - { - "name" : "DAC_OUTPUT[8]", - "strict" : false - }, - { - "name" : "DAC_OUTPUT[7]", - "strict" : false - }, - { - "name" : "DAC_OUTPUT[6]", - "strict" : false - }, - { - "name" : "DAC_OUTPUT[5]", - "strict" : false - }, - { - "name" : "DAC_OUTPUT[4]", - "strict" : false - }, - { - "name" : "DAC_OUTPUT[3]", - "strict" : false - }, - { - "name" : "DAC_OUTPUT[2]", - "strict" : false - }, - { - "name" : "DAC_OUTPUT[1]", - "strict" : false - }, - { - "name" : "DAC_OUTPUT[0]", - "strict" : false - }, - { - "name" : "STM32_DATA_BUS[7]", - "strict" : false - }, - { - "name" : "STM32_DATA_BUS[6]", - "strict" : false - }, - { - "name" : "STM32_DATA_BUS[5]", - "strict" : false - }, - { - "name" : "STM32_DATA_BUS[4]", - "strict" : false - }, - { - "name" : "STM32_DATA_BUS[3]", - "strict" : false - }, - { - "name" : "STM32_DATA_BUS[2]", - "strict" : false - }, - { - "name" : "STM32_DATA_BUS[1]", - "strict" : false - }, - { - "name" : "STM32_DATA_BUS[0]", - "strict" : false - }, - { - "name" : "STM32_CLK", - "strict" : false - }, - { - "name" : "STM32_SYNC", - "strict" : false - }, - { - "name" : "clk_sys", - "strict" : false - }, - { - "name" : "ADC_INPUT[0]", - "strict" : false - }, - { - "name" : "ADC_INPUT[1]", - "strict" : false - }, - { - "name" : "ADC_OTR", - "strict" : false - }, - { - "name" : "ADC_INPUT[2]", - "strict" : false - }, - { - "name" : "FLASH_MISO", - "strict" : false - }, - { - "name" : "ADC_INPUT[3]", - "strict" : false - }, - { - "name" : "ADC_INPUT[7]", - "strict" : false - }, - { - "name" : "ADC_INPUT[6]", - "strict" : false - }, - { - "name" : "ADC_INPUT[5]", - "strict" : false - }, - { - "name" : "ADC_INPUT[4]", - "strict" : false - }, - { - "name" : "ADC_INPUT[11]", - "strict" : false - }, - { - "name" : "ADC_INPUT[10]", - "strict" : false - }, - { - "name" : "ADC_INPUT[9]", - "strict" : false - }, - { - "name" : "ADC_INPUT[8]", - "strict" : false - }, - { - "name" : "altera_reserved_tms", - "strict" : false - }, - { - "name" : "altera_reserved_tck", - "strict" : false - }, - { - "name" : "altera_reserved_tdi", - "strict" : false - }, - { - "name" : "altera_reserved_tdo", - "strict" : false - } - ] - } - ] -} \ No newline at end of file diff --git a/FPGA_61.440/db/a_dpfifo_1lv.tdf b/FPGA_61.440/db/a_dpfifo_1lv.tdf deleted file mode 100644 index 17bd8f3..0000000 --- a/FPGA_61.440/db/a_dpfifo_1lv.tdf +++ /dev/null @@ -1,136 +0,0 @@ ---a_dpfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=8 LPM_SHOWAHEAD="OFF" lpm_width=18 lpm_widthu=3 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" clock data full q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ---VERSION_BEGIN 18.1 cbx_altdpram 2018:09:12:13:04:24:SJ cbx_altera_counter 2018:09:12:13:04:24:SJ cbx_altera_syncram 2018:09:12:13:04:24:SJ cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_fifo_common 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_scfifo 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION altsyncram_l7h1 (address_a[2..0], address_b[2..0], clock0, clock1, clocken1, data_a[17..0], wren_a) -RETURNS ( q_b[17..0]); -FUNCTION cmpr_gs8 (dataa[2..0], datab[2..0]) -RETURNS ( aeb); -FUNCTION cntr_r9b (clock, cnt_en, sclr) -RETURNS ( q[1..0]); -FUNCTION cntr_8a7 (clock, cnt_en, sclr, updown) -RETURNS ( q[2..0]); -FUNCTION cntr_s9b (clock, cnt_en, sclr) -RETURNS ( q[2..0]); - ---synthesis_resources = lut 8 M9K 1 reg 17 -SUBDESIGN a_dpfifo_1lv -( - clock : input; - data[17..0] : input; - full : output; - q[17..0] : output; - rreq : input; - sclr : input; - usedw[2..0] : output; - wreq : input; -) -VARIABLE - FIFOram : altsyncram_l7h1; - empty_dff : dffe; - full_dff : dffe; - low_addressa[2..0] : dffe; - rd_ptr_lsb : dffe; - usedw_is_0_dff : dffe; - usedw_is_1_dff : dffe; - wrreq_delay : dffe; - almost_full_comparer : cmpr_gs8; - two_comparison : cmpr_gs8; - rd_ptr_msb : cntr_r9b; - usedw_counter : cntr_8a7; - wr_ptr : cntr_s9b; - aclr : NODE; - asynch_read_counter_enable : WIRE; - empty_out : WIRE; - full_out : WIRE; - pulse_ram_output : WIRE; - ram_read_address[2..0] : WIRE; - rd_ptr[2..0] : WIRE; - usedw_is_0 : WIRE; - usedw_is_1 : WIRE; - usedw_is_2 : WIRE; - usedw_will_be_0 : WIRE; - usedw_will_be_1 : WIRE; - valid_rreq : WIRE; - valid_wreq : WIRE; - wait_state : WIRE; - -BEGIN - FIFOram.address_a[] = wr_ptr.q[]; - FIFOram.address_b[] = ram_read_address[]; - FIFOram.clock0 = clock; - FIFOram.clock1 = clock; - FIFOram.clocken1 = pulse_ram_output; - FIFOram.data_a[] = data[]; - FIFOram.wren_a = valid_wreq; - empty_dff.clk = clock; - empty_dff.clrn = (! aclr); - empty_dff.d = ((! (usedw_will_be_0 # wait_state)) & (! sclr)); - full_dff.clk = clock; - full_dff.clrn = (! aclr); - full_dff.d = ((! sclr) & (((valid_wreq & (! valid_rreq)) & almost_full_comparer.aeb) # (full_dff.q & (! (valid_wreq $ valid_rreq))))); - low_addressa[].clk = clock; - low_addressa[].clrn = (! aclr); - low_addressa[].d = ((! sclr) & ((asynch_read_counter_enable & rd_ptr[]) # ((! asynch_read_counter_enable) & low_addressa[].q))); - rd_ptr_lsb.clk = clock; - rd_ptr_lsb.clrn = (! aclr); - rd_ptr_lsb.d = ((! rd_ptr_lsb.q) & (! sclr)); - rd_ptr_lsb.ena = (asynch_read_counter_enable # sclr); - usedw_is_0_dff.clk = clock; - usedw_is_0_dff.clrn = (! aclr); - usedw_is_0_dff.d = (! usedw_will_be_0); - usedw_is_1_dff.clk = clock; - usedw_is_1_dff.clrn = (! aclr); - usedw_is_1_dff.d = usedw_will_be_1; - wrreq_delay.clk = clock; - wrreq_delay.clrn = (! aclr); - wrreq_delay.d = ((! sclr) & valid_wreq); - almost_full_comparer.dataa[] = B"111"; - almost_full_comparer.datab[] = usedw_counter.q[]; - two_comparison.dataa[] = usedw_counter.q[]; - two_comparison.datab[] = ( B"0", B"1", B"0"); - rd_ptr_msb.clock = clock; - rd_ptr_msb.cnt_en = (asynch_read_counter_enable & (! rd_ptr_lsb.q)); - rd_ptr_msb.sclr = sclr; - usedw_counter.clock = clock; - usedw_counter.cnt_en = (valid_wreq $ valid_rreq); - usedw_counter.sclr = sclr; - usedw_counter.updown = valid_wreq; - wr_ptr.clock = clock; - wr_ptr.cnt_en = valid_wreq; - wr_ptr.sclr = sclr; - aclr = GND; - asynch_read_counter_enable = pulse_ram_output; - empty_out = (! empty_dff.q); - full = full_out; - full_out = full_dff.q; - pulse_ram_output = valid_rreq; - q[] = FIFOram.q_b[]; - ram_read_address[] = (((! asynch_read_counter_enable) & low_addressa[].q) # (asynch_read_counter_enable & rd_ptr[])); - rd_ptr[] = ( rd_ptr_msb.q[], (! rd_ptr_lsb.q)); - usedw[] = usedw_counter.q[]; - usedw_is_0 = (! usedw_is_0_dff.q); - usedw_is_1 = usedw_is_1_dff.q; - usedw_is_2 = two_comparison.aeb; - usedw_will_be_0 = (! ((! sclr) & (! (((usedw_is_1 & valid_rreq) & (! valid_wreq)) # (usedw_is_0 & (! (valid_wreq $ valid_rreq))))))); - usedw_will_be_1 = ((! sclr) & ((((usedw_is_2 & (! valid_wreq)) & valid_rreq) # (usedw_is_1 & (! (valid_wreq $ valid_rreq)))) # ((usedw_is_0 & valid_wreq) & (! valid_rreq)))); - valid_rreq = (rreq & (! empty_out)); - valid_wreq = (wreq & (! full_out)); - wait_state = (usedw_will_be_1 & valid_wreq); -END; ---VALID FILE diff --git a/FPGA_61.440/db/a_dpfifo_4ku.tdf b/FPGA_61.440/db/a_dpfifo_4ku.tdf deleted file mode 100644 index 07a76d8..0000000 --- a/FPGA_61.440/db/a_dpfifo_4ku.tdf +++ /dev/null @@ -1,132 +0,0 @@ ---a_dpfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=3 LPM_SHOWAHEAD="OFF" lpm_width=85 lpm_widthu=2 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" clock data q rreq sclr wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ---VERSION_BEGIN 18.1 cbx_altdpram 2018:09:12:13:04:24:SJ cbx_altera_counter 2018:09:12:13:04:24:SJ cbx_altera_syncram 2018:09:12:13:04:24:SJ cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_fifo_common 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_scfifo 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION altsyncram_j7h1 (address_a[1..0], address_b[1..0], clock0, clock1, clocken1, data_a[84..0], wren_a) -RETURNS ( q_b[84..0]); -FUNCTION cmpr_fs8 (dataa[1..0], datab[1..0]) -RETURNS ( aeb); -FUNCTION cntr_q9b (clock, cnt_en, sclr) -RETURNS ( q[0..0]); -FUNCTION cntr_7a7 (clock, cnt_en, sclr, updown) -RETURNS ( q[1..0]); -FUNCTION cntr_r9b (clock, cnt_en, sclr) -RETURNS ( q[1..0]); - ---synthesis_resources = M9K 3 reg 8 -SUBDESIGN a_dpfifo_4ku -( - clock : input; - data[84..0] : input; - q[84..0] : output; - rreq : input; - sclr : input; - wreq : input; -) -VARIABLE - FIFOram : altsyncram_j7h1; - empty_dff : dffe; - full_dff : dffe; - low_addressa[1..0] : dffe; - rd_ptr_lsb : dffe; - usedw_is_0_dff : dffe; - usedw_is_1_dff : dffe; - wrreq_delay : dffe; - almost_full_comparer : cmpr_fs8; - two_comparison : cmpr_fs8; - rd_ptr_msb : cntr_q9b; - usedw_counter : cntr_7a7; - wr_ptr : cntr_r9b; - aclr : NODE; - asynch_read_counter_enable : WIRE; - empty_out : WIRE; - full_out : WIRE; - pulse_ram_output : WIRE; - ram_read_address[1..0] : WIRE; - rd_ptr[1..0] : WIRE; - usedw_is_0 : WIRE; - usedw_is_1 : WIRE; - usedw_is_2 : WIRE; - usedw_will_be_0 : WIRE; - usedw_will_be_1 : WIRE; - valid_rreq : WIRE; - valid_wreq : WIRE; - wait_state : WIRE; - -BEGIN - FIFOram.address_a[] = wr_ptr.q[]; - FIFOram.address_b[] = ram_read_address[]; - FIFOram.clock0 = clock; - FIFOram.clock1 = clock; - FIFOram.clocken1 = pulse_ram_output; - FIFOram.data_a[] = data[]; - FIFOram.wren_a = valid_wreq; - empty_dff.clk = clock; - empty_dff.clrn = (! aclr); - empty_dff.d = ((! (usedw_will_be_0 # wait_state)) & (! sclr)); - full_dff.clk = clock; - full_dff.clrn = (! aclr); - full_dff.d = ((! sclr) & (((valid_wreq & (! valid_rreq)) & almost_full_comparer.aeb) # (full_dff.q & (! (valid_wreq $ valid_rreq))))); - low_addressa[].clk = clock; - low_addressa[].clrn = (! aclr); - low_addressa[].d = ((! sclr) & ((asynch_read_counter_enable & rd_ptr[]) # ((! asynch_read_counter_enable) & low_addressa[].q))); - rd_ptr_lsb.clk = clock; - rd_ptr_lsb.clrn = (! aclr); - rd_ptr_lsb.d = ((! rd_ptr_lsb.q) & (! sclr)); - rd_ptr_lsb.ena = (asynch_read_counter_enable # sclr); - usedw_is_0_dff.clk = clock; - usedw_is_0_dff.clrn = (! aclr); - usedw_is_0_dff.d = (! usedw_will_be_0); - usedw_is_1_dff.clk = clock; - usedw_is_1_dff.clrn = (! aclr); - usedw_is_1_dff.d = usedw_will_be_1; - wrreq_delay.clk = clock; - wrreq_delay.clrn = (! aclr); - wrreq_delay.d = ((! sclr) & valid_wreq); - almost_full_comparer.dataa[] = B"10"; - almost_full_comparer.datab[] = usedw_counter.q[]; - two_comparison.dataa[] = usedw_counter.q[]; - two_comparison.datab[] = ( B"1", B"0"); - rd_ptr_msb.clock = clock; - rd_ptr_msb.cnt_en = (asynch_read_counter_enable & (! rd_ptr_lsb.q)); - rd_ptr_msb.sclr = sclr; - usedw_counter.clock = clock; - usedw_counter.cnt_en = (valid_wreq $ valid_rreq); - usedw_counter.sclr = sclr; - usedw_counter.updown = valid_wreq; - wr_ptr.clock = clock; - wr_ptr.cnt_en = valid_wreq; - wr_ptr.sclr = sclr; - aclr = GND; - asynch_read_counter_enable = pulse_ram_output; - empty_out = (! empty_dff.q); - full_out = full_dff.q; - pulse_ram_output = valid_rreq; - q[] = FIFOram.q_b[]; - ram_read_address[] = (((! asynch_read_counter_enable) & low_addressa[].q) # (asynch_read_counter_enable & rd_ptr[])); - rd_ptr[] = ( rd_ptr_msb.q[], (! rd_ptr_lsb.q)); - usedw_is_0 = (! usedw_is_0_dff.q); - usedw_is_1 = usedw_is_1_dff.q; - usedw_is_2 = two_comparison.aeb; - usedw_will_be_0 = (! ((! sclr) & (! (((usedw_is_1 & valid_rreq) & (! valid_wreq)) # (usedw_is_0 & (! (valid_wreq $ valid_rreq))))))); - usedw_will_be_1 = ((! sclr) & ((((usedw_is_2 & (! valid_wreq)) & valid_rreq) # (usedw_is_1 & (! (valid_wreq $ valid_rreq)))) # ((usedw_is_0 & valid_wreq) & (! valid_rreq)))); - valid_rreq = (rreq & (! empty_out)); - valid_wreq = (wreq & (! full_out)); - wait_state = (usedw_will_be_1 & valid_wreq); -END; ---VALID FILE diff --git a/FPGA_61.440/db/a_dpfifo_5ku.tdf b/FPGA_61.440/db/a_dpfifo_5ku.tdf deleted file mode 100644 index a836e92..0000000 --- a/FPGA_61.440/db/a_dpfifo_5ku.tdf +++ /dev/null @@ -1,132 +0,0 @@ ---a_dpfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=3 LPM_SHOWAHEAD="OFF" lpm_width=86 lpm_widthu=2 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" clock data q rreq sclr wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ---VERSION_BEGIN 18.1 cbx_altdpram 2018:09:12:13:04:24:SJ cbx_altera_counter 2018:09:12:13:04:24:SJ cbx_altera_syncram 2018:09:12:13:04:24:SJ cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_fifo_common 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_scfifo 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION altsyncram_m7h1 (address_a[1..0], address_b[1..0], clock0, clock1, clocken1, data_a[85..0], wren_a) -RETURNS ( q_b[85..0]); -FUNCTION cmpr_fs8 (dataa[1..0], datab[1..0]) -RETURNS ( aeb); -FUNCTION cntr_q9b (clock, cnt_en, sclr) -RETURNS ( q[0..0]); -FUNCTION cntr_7a7 (clock, cnt_en, sclr, updown) -RETURNS ( q[1..0]); -FUNCTION cntr_r9b (clock, cnt_en, sclr) -RETURNS ( q[1..0]); - ---synthesis_resources = lut 3 M9K 3 reg 11 -SUBDESIGN a_dpfifo_5ku -( - clock : input; - data[85..0] : input; - q[85..0] : output; - rreq : input; - sclr : input; - wreq : input; -) -VARIABLE - FIFOram : altsyncram_m7h1; - empty_dff : dffe; - full_dff : dffe; - low_addressa[1..0] : dffe; - rd_ptr_lsb : dffe; - usedw_is_0_dff : dffe; - usedw_is_1_dff : dffe; - wrreq_delay : dffe; - almost_full_comparer : cmpr_fs8; - two_comparison : cmpr_fs8; - rd_ptr_msb : cntr_q9b; - usedw_counter : cntr_7a7; - wr_ptr : cntr_r9b; - aclr : NODE; - asynch_read_counter_enable : WIRE; - empty_out : WIRE; - full_out : WIRE; - pulse_ram_output : WIRE; - ram_read_address[1..0] : WIRE; - rd_ptr[1..0] : WIRE; - usedw_is_0 : WIRE; - usedw_is_1 : WIRE; - usedw_is_2 : WIRE; - usedw_will_be_0 : WIRE; - usedw_will_be_1 : WIRE; - valid_rreq : WIRE; - valid_wreq : WIRE; - wait_state : WIRE; - -BEGIN - FIFOram.address_a[] = wr_ptr.q[]; - FIFOram.address_b[] = ram_read_address[]; - FIFOram.clock0 = clock; - FIFOram.clock1 = clock; - FIFOram.clocken1 = pulse_ram_output; - FIFOram.data_a[] = data[]; - FIFOram.wren_a = valid_wreq; - empty_dff.clk = clock; - empty_dff.clrn = (! aclr); - empty_dff.d = ((! (usedw_will_be_0 # wait_state)) & (! sclr)); - full_dff.clk = clock; - full_dff.clrn = (! aclr); - full_dff.d = ((! sclr) & (((valid_wreq & (! valid_rreq)) & almost_full_comparer.aeb) # (full_dff.q & (! (valid_wreq $ valid_rreq))))); - low_addressa[].clk = clock; - low_addressa[].clrn = (! aclr); - low_addressa[].d = ((! sclr) & ((asynch_read_counter_enable & rd_ptr[]) # ((! asynch_read_counter_enable) & low_addressa[].q))); - rd_ptr_lsb.clk = clock; - rd_ptr_lsb.clrn = (! aclr); - rd_ptr_lsb.d = ((! rd_ptr_lsb.q) & (! sclr)); - rd_ptr_lsb.ena = (asynch_read_counter_enable # sclr); - usedw_is_0_dff.clk = clock; - usedw_is_0_dff.clrn = (! aclr); - usedw_is_0_dff.d = (! usedw_will_be_0); - usedw_is_1_dff.clk = clock; - usedw_is_1_dff.clrn = (! aclr); - usedw_is_1_dff.d = usedw_will_be_1; - wrreq_delay.clk = clock; - wrreq_delay.clrn = (! aclr); - wrreq_delay.d = ((! sclr) & valid_wreq); - almost_full_comparer.dataa[] = B"10"; - almost_full_comparer.datab[] = usedw_counter.q[]; - two_comparison.dataa[] = usedw_counter.q[]; - two_comparison.datab[] = ( B"1", B"0"); - rd_ptr_msb.clock = clock; - rd_ptr_msb.cnt_en = (asynch_read_counter_enable & (! rd_ptr_lsb.q)); - rd_ptr_msb.sclr = sclr; - usedw_counter.clock = clock; - usedw_counter.cnt_en = (valid_wreq $ valid_rreq); - usedw_counter.sclr = sclr; - usedw_counter.updown = valid_wreq; - wr_ptr.clock = clock; - wr_ptr.cnt_en = valid_wreq; - wr_ptr.sclr = sclr; - aclr = GND; - asynch_read_counter_enable = pulse_ram_output; - empty_out = (! empty_dff.q); - full_out = full_dff.q; - pulse_ram_output = valid_rreq; - q[] = FIFOram.q_b[]; - ram_read_address[] = (((! asynch_read_counter_enable) & low_addressa[].q) # (asynch_read_counter_enable & rd_ptr[])); - rd_ptr[] = ( rd_ptr_msb.q[], (! rd_ptr_lsb.q)); - usedw_is_0 = (! usedw_is_0_dff.q); - usedw_is_1 = usedw_is_1_dff.q; - usedw_is_2 = two_comparison.aeb; - usedw_will_be_0 = (! ((! sclr) & (! (((usedw_is_1 & valid_rreq) & (! valid_wreq)) # (usedw_is_0 & (! (valid_wreq $ valid_rreq))))))); - usedw_will_be_1 = ((! sclr) & ((((usedw_is_2 & (! valid_wreq)) & valid_rreq) # (usedw_is_1 & (! (valid_wreq $ valid_rreq)))) # ((usedw_is_0 & valid_wreq) & (! valid_rreq)))); - valid_rreq = (rreq & (! empty_out)); - valid_wreq = (wreq & (! full_out)); - wait_state = (usedw_will_be_1 & valid_wreq); -END; ---VALID FILE diff --git a/FPGA_61.440/db/a_dpfifo_7qv.tdf b/FPGA_61.440/db/a_dpfifo_7qv.tdf deleted file mode 100644 index 5f8d33c..0000000 --- a/FPGA_61.440/db/a_dpfifo_7qv.tdf +++ /dev/null @@ -1,136 +0,0 @@ ---a_dpfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=21 LPM_SHOWAHEAD="OFF" lpm_width=33 lpm_widthu=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" clock data empty q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ---VERSION_BEGIN 18.1 cbx_altdpram 2018:09:12:13:04:24:SJ cbx_altera_counter 2018:09:12:13:04:24:SJ cbx_altera_syncram 2018:09:12:13:04:24:SJ cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_fifo_common 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_scfifo 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION altsyncram_dah1 (address_a[4..0], address_b[4..0], clock0, clock1, clocken1, data_a[32..0], wren_a) -RETURNS ( q_b[32..0]); -FUNCTION cmpr_is8 (dataa[4..0], datab[4..0]) -RETURNS ( aeb); -FUNCTION cntr_t9b (clock, cnt_en, sclr) -RETURNS ( q[3..0]); -FUNCTION cntr_aa7 (clock, cnt_en, sclr, updown) -RETURNS ( q[4..0]); -FUNCTION cntr_u9b (clock, cnt_en, sclr) -RETURNS ( q[4..0]); - ---synthesis_resources = M9K 1 reg 11 -SUBDESIGN a_dpfifo_7qv -( - clock : input; - data[32..0] : input; - empty : output; - q[32..0] : output; - rreq : input; - sclr : input; - usedw[4..0] : output; - wreq : input; -) -VARIABLE - FIFOram : altsyncram_dah1; - empty_dff : dffe; - full_dff : dffe; - low_addressa[4..0] : dffe; - rd_ptr_lsb : dffe; - usedw_is_0_dff : dffe; - usedw_is_1_dff : dffe; - wrreq_delay : dffe; - almost_full_comparer : cmpr_is8; - two_comparison : cmpr_is8; - rd_ptr_msb : cntr_t9b; - usedw_counter : cntr_aa7; - wr_ptr : cntr_u9b; - aclr : NODE; - asynch_read_counter_enable : WIRE; - empty_out : WIRE; - full_out : WIRE; - pulse_ram_output : WIRE; - ram_read_address[4..0] : WIRE; - rd_ptr[4..0] : WIRE; - usedw_is_0 : WIRE; - usedw_is_1 : WIRE; - usedw_is_2 : WIRE; - usedw_will_be_0 : WIRE; - usedw_will_be_1 : WIRE; - valid_rreq : WIRE; - valid_wreq : WIRE; - wait_state : WIRE; - -BEGIN - FIFOram.address_a[] = wr_ptr.q[]; - FIFOram.address_b[] = ram_read_address[]; - FIFOram.clock0 = clock; - FIFOram.clock1 = clock; - FIFOram.clocken1 = pulse_ram_output; - FIFOram.data_a[] = data[]; - FIFOram.wren_a = valid_wreq; - empty_dff.clk = clock; - empty_dff.clrn = (! aclr); - empty_dff.d = ((! (usedw_will_be_0 # wait_state)) & (! sclr)); - full_dff.clk = clock; - full_dff.clrn = (! aclr); - full_dff.d = ((! sclr) & (((valid_wreq & (! valid_rreq)) & almost_full_comparer.aeb) # (full_dff.q & (! (valid_wreq $ valid_rreq))))); - low_addressa[].clk = clock; - low_addressa[].clrn = (! aclr); - low_addressa[].d = ((! sclr) & ((asynch_read_counter_enable & rd_ptr[]) # ((! asynch_read_counter_enable) & low_addressa[].q))); - rd_ptr_lsb.clk = clock; - rd_ptr_lsb.clrn = (! aclr); - rd_ptr_lsb.d = ((! rd_ptr_lsb.q) & (! sclr)); - rd_ptr_lsb.ena = (asynch_read_counter_enable # sclr); - usedw_is_0_dff.clk = clock; - usedw_is_0_dff.clrn = (! aclr); - usedw_is_0_dff.d = (! usedw_will_be_0); - usedw_is_1_dff.clk = clock; - usedw_is_1_dff.clrn = (! aclr); - usedw_is_1_dff.d = usedw_will_be_1; - wrreq_delay.clk = clock; - wrreq_delay.clrn = (! aclr); - wrreq_delay.d = ((! sclr) & valid_wreq); - almost_full_comparer.dataa[] = B"10100"; - almost_full_comparer.datab[] = usedw_counter.q[]; - two_comparison.dataa[] = usedw_counter.q[]; - two_comparison.datab[] = ( B"000", B"1", B"0"); - rd_ptr_msb.clock = clock; - rd_ptr_msb.cnt_en = (asynch_read_counter_enable & (! rd_ptr_lsb.q)); - rd_ptr_msb.sclr = sclr; - usedw_counter.clock = clock; - usedw_counter.cnt_en = (valid_wreq $ valid_rreq); - usedw_counter.sclr = sclr; - usedw_counter.updown = valid_wreq; - wr_ptr.clock = clock; - wr_ptr.cnt_en = valid_wreq; - wr_ptr.sclr = sclr; - aclr = GND; - asynch_read_counter_enable = pulse_ram_output; - empty = empty_out; - empty_out = (! empty_dff.q); - full_out = full_dff.q; - pulse_ram_output = valid_rreq; - q[] = FIFOram.q_b[]; - ram_read_address[] = (((! asynch_read_counter_enable) & low_addressa[].q) # (asynch_read_counter_enable & rd_ptr[])); - rd_ptr[] = ( rd_ptr_msb.q[], (! rd_ptr_lsb.q)); - usedw[] = usedw_counter.q[]; - usedw_is_0 = (! usedw_is_0_dff.q); - usedw_is_1 = usedw_is_1_dff.q; - usedw_is_2 = two_comparison.aeb; - usedw_will_be_0 = (! ((! sclr) & (! (((usedw_is_1 & valid_rreq) & (! valid_wreq)) # (usedw_is_0 & (! (valid_wreq $ valid_rreq))))))); - usedw_will_be_1 = ((! sclr) & ((((usedw_is_2 & (! valid_wreq)) & valid_rreq) # (usedw_is_1 & (! (valid_wreq $ valid_rreq)))) # ((usedw_is_0 & valid_wreq) & (! valid_rreq)))); - valid_rreq = (rreq & (! empty_out)); - valid_wreq = (wreq & (! full_out)); - wait_state = (usedw_will_be_1 & valid_wreq); -END; ---VALID FILE diff --git a/FPGA_61.440/db/a_dpfifo_9qv.tdf b/FPGA_61.440/db/a_dpfifo_9qv.tdf deleted file mode 100644 index 48e9cfe..0000000 --- a/FPGA_61.440/db/a_dpfifo_9qv.tdf +++ /dev/null @@ -1,136 +0,0 @@ ---a_dpfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=21 LPM_SHOWAHEAD="OFF" lpm_width=17 lpm_widthu=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" clock data empty q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ---VERSION_BEGIN 18.1 cbx_altdpram 2018:09:12:13:04:24:SJ cbx_altera_counter 2018:09:12:13:04:24:SJ cbx_altera_syncram 2018:09:12:13:04:24:SJ cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_fifo_common 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_scfifo 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION altsyncram_hah1 (address_a[4..0], address_b[4..0], clock0, clock1, clocken1, data_a[16..0], wren_a) -RETURNS ( q_b[16..0]); -FUNCTION cmpr_is8 (dataa[4..0], datab[4..0]) -RETURNS ( aeb); -FUNCTION cntr_t9b (clock, cnt_en, sclr) -RETURNS ( q[3..0]); -FUNCTION cntr_aa7 (clock, cnt_en, sclr, updown) -RETURNS ( q[4..0]); -FUNCTION cntr_u9b (clock, cnt_en, sclr) -RETURNS ( q[4..0]); - ---synthesis_resources = lut 14 M9K 1 reg 25 -SUBDESIGN a_dpfifo_9qv -( - clock : input; - data[16..0] : input; - empty : output; - q[16..0] : output; - rreq : input; - sclr : input; - usedw[4..0] : output; - wreq : input; -) -VARIABLE - FIFOram : altsyncram_hah1; - empty_dff : dffe; - full_dff : dffe; - low_addressa[4..0] : dffe; - rd_ptr_lsb : dffe; - usedw_is_0_dff : dffe; - usedw_is_1_dff : dffe; - wrreq_delay : dffe; - almost_full_comparer : cmpr_is8; - two_comparison : cmpr_is8; - rd_ptr_msb : cntr_t9b; - usedw_counter : cntr_aa7; - wr_ptr : cntr_u9b; - aclr : NODE; - asynch_read_counter_enable : WIRE; - empty_out : WIRE; - full_out : WIRE; - pulse_ram_output : WIRE; - ram_read_address[4..0] : WIRE; - rd_ptr[4..0] : WIRE; - usedw_is_0 : WIRE; - usedw_is_1 : WIRE; - usedw_is_2 : WIRE; - usedw_will_be_0 : WIRE; - usedw_will_be_1 : WIRE; - valid_rreq : WIRE; - valid_wreq : WIRE; - wait_state : WIRE; - -BEGIN - FIFOram.address_a[] = wr_ptr.q[]; - FIFOram.address_b[] = ram_read_address[]; - FIFOram.clock0 = clock; - FIFOram.clock1 = clock; - FIFOram.clocken1 = pulse_ram_output; - FIFOram.data_a[] = data[]; - FIFOram.wren_a = valid_wreq; - empty_dff.clk = clock; - empty_dff.clrn = (! aclr); - empty_dff.d = ((! (usedw_will_be_0 # wait_state)) & (! sclr)); - full_dff.clk = clock; - full_dff.clrn = (! aclr); - full_dff.d = ((! sclr) & (((valid_wreq & (! valid_rreq)) & almost_full_comparer.aeb) # (full_dff.q & (! (valid_wreq $ valid_rreq))))); - low_addressa[].clk = clock; - low_addressa[].clrn = (! aclr); - low_addressa[].d = ((! sclr) & ((asynch_read_counter_enable & rd_ptr[]) # ((! asynch_read_counter_enable) & low_addressa[].q))); - rd_ptr_lsb.clk = clock; - rd_ptr_lsb.clrn = (! aclr); - rd_ptr_lsb.d = ((! rd_ptr_lsb.q) & (! sclr)); - rd_ptr_lsb.ena = (asynch_read_counter_enable # sclr); - usedw_is_0_dff.clk = clock; - usedw_is_0_dff.clrn = (! aclr); - usedw_is_0_dff.d = (! usedw_will_be_0); - usedw_is_1_dff.clk = clock; - usedw_is_1_dff.clrn = (! aclr); - usedw_is_1_dff.d = usedw_will_be_1; - wrreq_delay.clk = clock; - wrreq_delay.clrn = (! aclr); - wrreq_delay.d = ((! sclr) & valid_wreq); - almost_full_comparer.dataa[] = B"10100"; - almost_full_comparer.datab[] = usedw_counter.q[]; - two_comparison.dataa[] = usedw_counter.q[]; - two_comparison.datab[] = ( B"000", B"1", B"0"); - rd_ptr_msb.clock = clock; - rd_ptr_msb.cnt_en = (asynch_read_counter_enable & (! rd_ptr_lsb.q)); - rd_ptr_msb.sclr = sclr; - usedw_counter.clock = clock; - usedw_counter.cnt_en = (valid_wreq $ valid_rreq); - usedw_counter.sclr = sclr; - usedw_counter.updown = valid_wreq; - wr_ptr.clock = clock; - wr_ptr.cnt_en = valid_wreq; - wr_ptr.sclr = sclr; - aclr = GND; - asynch_read_counter_enable = pulse_ram_output; - empty = empty_out; - empty_out = (! empty_dff.q); - full_out = full_dff.q; - pulse_ram_output = valid_rreq; - q[] = FIFOram.q_b[]; - ram_read_address[] = (((! asynch_read_counter_enable) & low_addressa[].q) # (asynch_read_counter_enable & rd_ptr[])); - rd_ptr[] = ( rd_ptr_msb.q[], (! rd_ptr_lsb.q)); - usedw[] = usedw_counter.q[]; - usedw_is_0 = (! usedw_is_0_dff.q); - usedw_is_1 = usedw_is_1_dff.q; - usedw_is_2 = two_comparison.aeb; - usedw_will_be_0 = (! ((! sclr) & (! (((usedw_is_1 & valid_rreq) & (! valid_wreq)) # (usedw_is_0 & (! (valid_wreq $ valid_rreq))))))); - usedw_will_be_1 = ((! sclr) & ((((usedw_is_2 & (! valid_wreq)) & valid_rreq) # (usedw_is_1 & (! (valid_wreq $ valid_rreq)))) # ((usedw_is_0 & valid_wreq) & (! valid_rreq)))); - valid_rreq = (rreq & (! empty_out)); - valid_wreq = (wreq & (! full_out)); - wait_state = (usedw_will_be_1 & valid_wreq); -END; ---VALID FILE diff --git a/FPGA_61.440/db/a_dpfifo_vkv.tdf b/FPGA_61.440/db/a_dpfifo_vkv.tdf deleted file mode 100644 index 2318833..0000000 --- a/FPGA_61.440/db/a_dpfifo_vkv.tdf +++ /dev/null @@ -1,136 +0,0 @@ ---a_dpfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=8 LPM_SHOWAHEAD="OFF" lpm_width=25 lpm_widthu=3 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" clock data full q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ---VERSION_BEGIN 18.1 cbx_altdpram 2018:09:12:13:04:24:SJ cbx_altera_counter 2018:09:12:13:04:24:SJ cbx_altera_syncram 2018:09:12:13:04:24:SJ cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_fifo_common 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_scfifo 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION altsyncram_h7h1 (address_a[2..0], address_b[2..0], clock0, clock1, clocken1, data_a[24..0], wren_a) -RETURNS ( q_b[24..0]); -FUNCTION cmpr_gs8 (dataa[2..0], datab[2..0]) -RETURNS ( aeb); -FUNCTION cntr_r9b (clock, cnt_en, sclr) -RETURNS ( q[1..0]); -FUNCTION cntr_8a7 (clock, cnt_en, sclr, updown) -RETURNS ( q[2..0]); -FUNCTION cntr_s9b (clock, cnt_en, sclr) -RETURNS ( q[2..0]); - ---synthesis_resources = M9K 1 reg 9 -SUBDESIGN a_dpfifo_vkv -( - clock : input; - data[24..0] : input; - full : output; - q[24..0] : output; - rreq : input; - sclr : input; - usedw[2..0] : output; - wreq : input; -) -VARIABLE - FIFOram : altsyncram_h7h1; - empty_dff : dffe; - full_dff : dffe; - low_addressa[2..0] : dffe; - rd_ptr_lsb : dffe; - usedw_is_0_dff : dffe; - usedw_is_1_dff : dffe; - wrreq_delay : dffe; - almost_full_comparer : cmpr_gs8; - two_comparison : cmpr_gs8; - rd_ptr_msb : cntr_r9b; - usedw_counter : cntr_8a7; - wr_ptr : cntr_s9b; - aclr : NODE; - asynch_read_counter_enable : WIRE; - empty_out : WIRE; - full_out : WIRE; - pulse_ram_output : WIRE; - ram_read_address[2..0] : WIRE; - rd_ptr[2..0] : WIRE; - usedw_is_0 : WIRE; - usedw_is_1 : WIRE; - usedw_is_2 : WIRE; - usedw_will_be_0 : WIRE; - usedw_will_be_1 : WIRE; - valid_rreq : WIRE; - valid_wreq : WIRE; - wait_state : WIRE; - -BEGIN - FIFOram.address_a[] = wr_ptr.q[]; - FIFOram.address_b[] = ram_read_address[]; - FIFOram.clock0 = clock; - FIFOram.clock1 = clock; - FIFOram.clocken1 = pulse_ram_output; - FIFOram.data_a[] = data[]; - FIFOram.wren_a = valid_wreq; - empty_dff.clk = clock; - empty_dff.clrn = (! aclr); - empty_dff.d = ((! (usedw_will_be_0 # wait_state)) & (! sclr)); - full_dff.clk = clock; - full_dff.clrn = (! aclr); - full_dff.d = ((! sclr) & (((valid_wreq & (! valid_rreq)) & almost_full_comparer.aeb) # (full_dff.q & (! (valid_wreq $ valid_rreq))))); - low_addressa[].clk = clock; - low_addressa[].clrn = (! aclr); - low_addressa[].d = ((! sclr) & ((asynch_read_counter_enable & rd_ptr[]) # ((! asynch_read_counter_enable) & low_addressa[].q))); - rd_ptr_lsb.clk = clock; - rd_ptr_lsb.clrn = (! aclr); - rd_ptr_lsb.d = ((! rd_ptr_lsb.q) & (! sclr)); - rd_ptr_lsb.ena = (asynch_read_counter_enable # sclr); - usedw_is_0_dff.clk = clock; - usedw_is_0_dff.clrn = (! aclr); - usedw_is_0_dff.d = (! usedw_will_be_0); - usedw_is_1_dff.clk = clock; - usedw_is_1_dff.clrn = (! aclr); - usedw_is_1_dff.d = usedw_will_be_1; - wrreq_delay.clk = clock; - wrreq_delay.clrn = (! aclr); - wrreq_delay.d = ((! sclr) & valid_wreq); - almost_full_comparer.dataa[] = B"111"; - almost_full_comparer.datab[] = usedw_counter.q[]; - two_comparison.dataa[] = usedw_counter.q[]; - two_comparison.datab[] = ( B"0", B"1", B"0"); - rd_ptr_msb.clock = clock; - rd_ptr_msb.cnt_en = (asynch_read_counter_enable & (! rd_ptr_lsb.q)); - rd_ptr_msb.sclr = sclr; - usedw_counter.clock = clock; - usedw_counter.cnt_en = (valid_wreq $ valid_rreq); - usedw_counter.sclr = sclr; - usedw_counter.updown = valid_wreq; - wr_ptr.clock = clock; - wr_ptr.cnt_en = valid_wreq; - wr_ptr.sclr = sclr; - aclr = GND; - asynch_read_counter_enable = pulse_ram_output; - empty_out = (! empty_dff.q); - full = full_out; - full_out = full_dff.q; - pulse_ram_output = valid_rreq; - q[] = FIFOram.q_b[]; - ram_read_address[] = (((! asynch_read_counter_enable) & low_addressa[].q) # (asynch_read_counter_enable & rd_ptr[])); - rd_ptr[] = ( rd_ptr_msb.q[], (! rd_ptr_lsb.q)); - usedw[] = usedw_counter.q[]; - usedw_is_0 = (! usedw_is_0_dff.q); - usedw_is_1 = usedw_is_1_dff.q; - usedw_is_2 = two_comparison.aeb; - usedw_will_be_0 = (! ((! sclr) & (! (((usedw_is_1 & valid_rreq) & (! valid_wreq)) # (usedw_is_0 & (! (valid_wreq $ valid_rreq))))))); - usedw_will_be_1 = ((! sclr) & ((((usedw_is_2 & (! valid_wreq)) & valid_rreq) # (usedw_is_1 & (! (valid_wreq $ valid_rreq)))) # ((usedw_is_0 & valid_wreq) & (! valid_rreq)))); - valid_rreq = (rreq & (! empty_out)); - valid_wreq = (wreq & (! full_out)); - wait_state = (usedw_will_be_1 & valid_wreq); -END; ---VALID FILE diff --git a/FPGA_61.440/db/add_sub_1vk.tdf b/FPGA_61.440/db/add_sub_1vk.tdf deleted file mode 100644 index a3332e5..0000000 --- a/FPGA_61.440/db/add_sub_1vk.tdf +++ /dev/null @@ -1,52 +0,0 @@ ---lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="SIGNED" LPM_WIDTH=32 ONE_INPUT_IS_CONSTANT="NO" clken clock dataa datab overflow result ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - - ---synthesis_resources = lut 33 -SUBDESIGN add_sub_1vk -( - clken : input; - clock : input; - dataa[31..0] : input; - datab[31..0] : input; - overflow : output; - result[31..0] : output; -) -VARIABLE - pipeline_dffe[31..0] : DFFE - WITH ( - power_up ="low" - ); - overflow_dffe[31..0] : DFFE - WITH ( - power_up ="low" - ); - result_int[31..0] : WIRE; -BEGIN - result_int[] = dataa[] + datab[]; - pipeline_dffe[].clk = clock; - pipeline_dffe[].ena = clken; - overflow_dffe[].clk = clock; - overflow_dffe[].ena = clken; - result[] = pipeline_dffe[31..0].q; - pipeline_dffe[31..0].d = result_int[]; - overflow = overflow_dffe[0..0].q; - overflow_dffe[0].d = ! (dataa[31] $ datab[31]) & (dataa[31] $ result_int[31]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/add_sub_b2k.tdf b/FPGA_61.440/db/add_sub_b2k.tdf deleted file mode 100644 index 2fa8828..0000000 --- a/FPGA_61.440/db/add_sub_b2k.tdf +++ /dev/null @@ -1,43 +0,0 @@ ---lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="SIGNED" LPM_WIDTH=12 ONE_INPUT_IS_CONSTANT="NO" clken clock dataa datab result ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - - ---synthesis_resources = lut 12 -SUBDESIGN add_sub_b2k -( - clken : input; - clock : input; - dataa[11..0] : input; - datab[11..0] : input; - result[11..0] : output; -) -VARIABLE - pipeline_dffe[11..0] : DFFE - WITH ( - power_up ="low" - ); - result_int[11..0] : WIRE; -BEGIN - result_int[] = dataa[] + datab[]; - pipeline_dffe[].clk = clock; - pipeline_dffe[].ena = clken; - result[] = pipeline_dffe[11..0].q; - pipeline_dffe[11..0].d = result_int[]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/add_sub_fpk.tdf b/FPGA_61.440/db/add_sub_fpk.tdf deleted file mode 100644 index 495ce6d..0000000 --- a/FPGA_61.440/db/add_sub_fpk.tdf +++ /dev/null @@ -1,46 +0,0 @@ ---lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="SIGNED" LPM_WIDTH=12 ONE_INPUT_IS_CONSTANT="NO" cin clken clock dataa datab(gnd) result ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - - ---synthesis_resources = lut 12 -SUBDESIGN add_sub_fpk -( - cin : input; - clken : input; - clock : input; - dataa[11..0] : input; - datab[11..0] : input; - result[11..0] : output; -) -VARIABLE - pipeline_dffe[11..0] : DFFE - WITH ( - power_up ="low" - ); - result_int[12..0] : WIRE; - const_used_datab[11..0] : WIRE; -BEGIN - result_int[] = (dataa[], cin) + (B"000000000000", cin); - pipeline_dffe[].clk = clock; - pipeline_dffe[].ena = clken; - result[] = pipeline_dffe[11..0].q; - pipeline_dffe[11..0].d = result_int[12..1]; - const_used_datab[] = datab[]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/add_sub_jpk.tdf b/FPGA_61.440/db/add_sub_jpk.tdf deleted file mode 100644 index b8fbb02..0000000 --- a/FPGA_61.440/db/add_sub_jpk.tdf +++ /dev/null @@ -1,46 +0,0 @@ ---lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="SIGNED" LPM_WIDTH=16 ONE_INPUT_IS_CONSTANT="NO" cin clken clock dataa datab(gnd) result ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - - ---synthesis_resources = lut 16 -SUBDESIGN add_sub_jpk -( - cin : input; - clken : input; - clock : input; - dataa[15..0] : input; - datab[15..0] : input; - result[15..0] : output; -) -VARIABLE - pipeline_dffe[15..0] : DFFE - WITH ( - power_up ="low" - ); - result_int[16..0] : WIRE; - const_used_datab[15..0] : WIRE; -BEGIN - result_int[] = (dataa[], cin) + (B"0000000000000000", cin); - pipeline_dffe[].clk = clock; - pipeline_dffe[].ena = clken; - result[] = pipeline_dffe[15..0].q; - pipeline_dffe[15..0].d = result_int[16..1]; - const_used_datab[] = datab[]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/add_sub_u4i.tdf b/FPGA_61.440/db/add_sub_u4i.tdf deleted file mode 100644 index 6e7ba5a..0000000 --- a/FPGA_61.440/db/add_sub_u4i.tdf +++ /dev/null @@ -1,45 +0,0 @@ ---lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=22 aclr clken clock dataa datab result ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - - ---synthesis_resources = lut 22 -SUBDESIGN add_sub_u4i -( - aclr : input; - clken : input; - clock : input; - dataa[21..0] : input; - datab[21..0] : input; - result[21..0] : output; -) -VARIABLE - pipeline_dffe[21..0] : DFFE - WITH ( - power_up ="low" - ); - result_int[21..0] : WIRE; -BEGIN - result_int[] = dataa[] + datab[]; - pipeline_dffe[].clk = clock; - pipeline_dffe[].clrn = !aclr; - pipeline_dffe[].ena = clken; - result[] = pipeline_dffe[21..0].q; - pipeline_dffe[21..0].d = result_int[]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_0mn3.tdf b/FPGA_61.440/db/altsyncram_0mn3.tdf deleted file mode 100644 index b0e68b1..0000000 --- a/FPGA_61.440/db/altsyncram_0mn3.tdf +++ /dev/null @@ -1,596 +0,0 @@ ---altsyncram ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" BYTE_SIZE=8 BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="NORMAL" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_ECC="FALSE" IMPLEMENT_IN_LES="OFF" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK0" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=64 NUMWORDS_B=64 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="M9K" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" stratixiv_m144k_allow_dual_clocks="ON" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCSTATUS=3 WIDTHAD_A=6 WIDTHAD_B=6 WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK0" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 1 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_0mn3 -( - address_a[5..0] : input; - address_b[5..0] : input; - clock0 : input; - data_a[15..0] : input; - q_b[15..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 8, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 9, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 10, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 11, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 12, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 13, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 14, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 15, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - address_a_wire[5..0] : WIRE; - address_b_wire[5..0] : WIRE; - -BEGIN - ram_block1a[15..0].clk0 = clock0; - ram_block1a[15..0].clk1 = clock0; - ram_block1a[15..0].ena0 = wren_a; - ram_block1a[15..0].portaaddr[] = ( address_a_wire[5..0]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[15..0].portawe = wren_a; - ram_block1a[15..0].portbaddr[] = ( address_b_wire[5..0]); - ram_block1a[15..0].portbre = B"1111111111111111"; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_b[] = ( ram_block1a[15..0].portbdataout[0..0]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_4k82.tdf b/FPGA_61.440/db/altsyncram_4k82.tdf deleted file mode 100644 index b055f65..0000000 --- a/FPGA_61.440/db/altsyncram_4k82.tdf +++ /dev/null @@ -1,684 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK0" INIT_FILE="tx_nco_nco_ii_0_sin_c.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=2048 NUMWORDS_B=2048 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="CLOCK0" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=11 WIDTHAD_B=11 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK0" address_a address_b clock0 clocken0 data_a data_b q_a q_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 4 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_4k82 -( - address_a[10..0] : input; - address_b[10..0] : input; - clock0 : input; - clocken0 : input; - data_a[15..0] : input; - data_b[15..0] : input; - q_a[15..0] : output; - q_b[15..0] : output; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 8, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 9, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 10, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 11, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 12, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 13, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 14, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 15, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 16, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[10..0] : WIRE; - address_b_wire[10..0] : WIRE; - wren_a : NODE; - wren_b : NODE; - -BEGIN - ram_block1a[15..0].clk0 = clock0; - ram_block1a[15..0].ena0 = clocken0; - ram_block1a[15..0].portaaddr[] = ( address_a_wire[10..0]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[15..0].portare = B"1111111111111111"; - ram_block1a[15..0].portawe = wren_a; - ram_block1a[15..0].portbaddr[] = ( address_b_wire[10..0]); - ram_block1a[0].portbdatain[] = ( data_b[0..0]); - ram_block1a[1].portbdatain[] = ( data_b[1..1]); - ram_block1a[2].portbdatain[] = ( data_b[2..2]); - ram_block1a[3].portbdatain[] = ( data_b[3..3]); - ram_block1a[4].portbdatain[] = ( data_b[4..4]); - ram_block1a[5].portbdatain[] = ( data_b[5..5]); - ram_block1a[6].portbdatain[] = ( data_b[6..6]); - ram_block1a[7].portbdatain[] = ( data_b[7..7]); - ram_block1a[8].portbdatain[] = ( data_b[8..8]); - ram_block1a[9].portbdatain[] = ( data_b[9..9]); - ram_block1a[10].portbdatain[] = ( data_b[10..10]); - ram_block1a[11].portbdatain[] = ( data_b[11..11]); - ram_block1a[12].portbdatain[] = ( data_b[12..12]); - ram_block1a[13].portbdatain[] = ( data_b[13..13]); - ram_block1a[14].portbdatain[] = ( data_b[14..14]); - ram_block1a[15].portbdatain[] = ( data_b[15..15]); - ram_block1a[15..0].portbre = B"1111111111111111"; - ram_block1a[15..0].portbwe = wren_b; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_a[] = ( ram_block1a[15..0].portadataout[0..0]); - q_b[] = ( ram_block1a[15..0].portbdataout[0..0]); - wren_a = GND; - wren_b = GND; -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_au91.tdf b/FPGA_61.440/db/altsyncram_au91.tdf deleted file mode 100644 index 425a5b5..0000000 --- a/FPGA_61.440/db/altsyncram_au91.tdf +++ /dev/null @@ -1,309 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nco_nco_ii_0_cos_f.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=2048 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=12 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 address_a clock0 clocken0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 3 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_au91 -( - address_a[10..0] : input; - clock0 : input; - clocken0 : input; - q_a[11..0] : output; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[10..0] : WIRE; - -BEGIN - ram_block1a[11..0].clk0 = clock0; - ram_block1a[11..0].ena0 = clocken0; - ram_block1a[11..0].portaaddr[] = ( address_a_wire[10..0]); - ram_block1a[11..0].portare = B"111111111111"; - address_a_wire[] = address_a[]; - q_a[] = ( ram_block1a[11..0].portadataout[0..0]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_dah1.tdf b/FPGA_61.440/db/altsyncram_dah1.tdf deleted file mode 100644 index 831cab0..0000000 --- a/FPGA_61.440/db/altsyncram_dah1.tdf +++ /dev/null @@ -1,1143 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_ECC="FALSE" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK1" WIDTH_A=33 WIDTH_B=33 WIDTH_BYTEENA_A=1 WIDTH_ECCSTATUS=2 WIDTHAD_A=5 WIDTHAD_B=5 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 1 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_dah1 -( - address_a[4..0] : input; - address_b[4..0] : input; - clock0 : input; - clock1 : input; - clocken1 : input; - data_a[32..0] : input; - q_b[32..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 8, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 9, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 10, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 11, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 12, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 13, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 14, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 15, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 16, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 17, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 18, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 19, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 20, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 21, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 22, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 23, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 24, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 25, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 26, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 27, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 28, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 29, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 30, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 31, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a32 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 32, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 33, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 32, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 33, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[4..0] : WIRE; - address_b_wire[4..0] : WIRE; - -BEGIN - ram_block1a[32..0].clk0 = clock0; - ram_block1a[32..0].clk1 = clock1; - ram_block1a[32..0].ena1 = clocken1; - ram_block1a[32..0].portaaddr[] = ( address_a_wire[4..0]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[32].portadatain[] = ( data_a[32..32]); - ram_block1a[32..0].portawe = wren_a; - ram_block1a[32..0].portbaddr[] = ( address_b_wire[4..0]); - ram_block1a[32..0].portbre = B"111111111111111111111111111111111"; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_b[] = ( ram_block1a[32..0].portbdataout[0..0]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_fu91.tdf b/FPGA_61.440/db/altsyncram_fu91.tdf deleted file mode 100644 index 5c023f1..0000000 --- a/FPGA_61.440/db/altsyncram_fu91.tdf +++ /dev/null @@ -1,309 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nco_nco_ii_0_sin_f.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=2048 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=12 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 address_a clock0 clocken0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 3 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_fu91 -( - address_a[10..0] : input; - clock0 : input; - clocken0 : input; - q_a[11..0] : output; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[10..0] : WIRE; - -BEGIN - ram_block1a[11..0].clk0 = clock0; - ram_block1a[11..0].ena0 = clocken0; - ram_block1a[11..0].portaaddr[] = ( address_a_wire[10..0]); - ram_block1a[11..0].portare = B"111111111111"; - address_a_wire[] = address_a[]; - q_a[] = ( ram_block1a[11..0].portadataout[0..0]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_h7h1.tdf b/FPGA_61.440/db/altsyncram_h7h1.tdf deleted file mode 100644 index eea3436..0000000 --- a/FPGA_61.440/db/altsyncram_h7h1.tdf +++ /dev/null @@ -1,879 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_ECC="FALSE" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=8 NUMWORDS_B=8 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK1" WIDTH_A=25 WIDTH_B=25 WIDTH_BYTEENA_A=1 WIDTH_ECCSTATUS=2 WIDTHAD_A=3 WIDTHAD_B=3 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 1 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_h7h1 -( - address_a[2..0] : input; - address_b[2..0] : input; - clock0 : input; - clock1 : input; - clocken1 : input; - data_a[24..0] : input; - q_b[24..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 8, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 9, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 10, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 11, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 12, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 13, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 14, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 15, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 16, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 17, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 18, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 19, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 20, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 21, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 22, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 23, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 25, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 24, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 25, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[2..0] : WIRE; - address_b_wire[2..0] : WIRE; - -BEGIN - ram_block1a[24..0].clk0 = clock0; - ram_block1a[24..0].clk1 = clock1; - ram_block1a[24..0].ena1 = clocken1; - ram_block1a[24..0].portaaddr[] = ( address_a_wire[2..0]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[24..0].portawe = wren_a; - ram_block1a[24..0].portbaddr[] = ( address_b_wire[2..0]); - ram_block1a[24..0].portbre = B"1111111111111111111111111"; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_b[] = ( ram_block1a[24..0].portbdataout[0..0]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_h982.tdf b/FPGA_61.440/db/altsyncram_h982.tdf deleted file mode 100644 index 215ecd3..0000000 --- a/FPGA_61.440/db/altsyncram_h982.tdf +++ /dev/null @@ -1,528 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK0" INIT_FILE="nco_nco_ii_0_sin_c.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=2048 NUMWORDS_B=2048 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="CLOCK0" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=12 WIDTH_B=12 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=11 WIDTHAD_B=11 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK0" address_a address_b clock0 clocken0 data_a data_b q_a q_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 3 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_h982 -( - address_a[10..0] : input; - address_b[10..0] : input; - clock0 : input; - clocken0 : input; - data_a[11..0] : input; - data_b[11..0] : input; - q_a[11..0] : output; - q_b[11..0] : output; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 12, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 12, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 12, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 12, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 12, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 12, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 12, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 12, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 8, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 12, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 9, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 12, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 10, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 12, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nco_nco_ii_0_sin_c.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "bidir_dual_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 12, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 11, - PORT_B_DATA_IN_CLOCK = "clock0", - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock0", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 11, - PORT_B_LAST_ADDRESS = 2047, - PORT_B_LOGICAL_RAM_DEPTH = 2048, - PORT_B_LOGICAL_RAM_WIDTH = 12, - PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - PORT_B_READ_ENABLE_CLOCK = "clock0", - PORT_B_WRITE_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[10..0] : WIRE; - address_b_wire[10..0] : WIRE; - wren_a : NODE; - wren_b : NODE; - -BEGIN - ram_block1a[11..0].clk0 = clock0; - ram_block1a[11..0].ena0 = clocken0; - ram_block1a[11..0].portaaddr[] = ( address_a_wire[10..0]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[11..0].portare = B"111111111111"; - ram_block1a[11..0].portawe = wren_a; - ram_block1a[11..0].portbaddr[] = ( address_b_wire[10..0]); - ram_block1a[0].portbdatain[] = ( data_b[0..0]); - ram_block1a[1].portbdatain[] = ( data_b[1..1]); - ram_block1a[2].portbdatain[] = ( data_b[2..2]); - ram_block1a[3].portbdatain[] = ( data_b[3..3]); - ram_block1a[4].portbdatain[] = ( data_b[4..4]); - ram_block1a[5].portbdatain[] = ( data_b[5..5]); - ram_block1a[6].portbdatain[] = ( data_b[6..6]); - ram_block1a[7].portbdatain[] = ( data_b[7..7]); - ram_block1a[8].portbdatain[] = ( data_b[8..8]); - ram_block1a[9].portbdatain[] = ( data_b[9..9]); - ram_block1a[10].portbdatain[] = ( data_b[10..10]); - ram_block1a[11].portbdatain[] = ( data_b[11..11]); - ram_block1a[11..0].portbre = B"111111111111"; - ram_block1a[11..0].portbwe = wren_b; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_a[] = ( ram_block1a[11..0].portadataout[0..0]); - q_b[] = ( ram_block1a[11..0].portbdataout[0..0]); - wren_a = GND; - wren_b = GND; -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_hah1.tdf b/FPGA_61.440/db/altsyncram_hah1.tdf deleted file mode 100644 index b8c2409..0000000 --- a/FPGA_61.440/db/altsyncram_hah1.tdf +++ /dev/null @@ -1,615 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_ECC="FALSE" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK1" WIDTH_A=17 WIDTH_B=17 WIDTH_BYTEENA_A=1 WIDTH_ECCSTATUS=2 WIDTHAD_A=5 WIDTHAD_B=5 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 1 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_hah1 -( - address_a[4..0] : input; - address_b[4..0] : input; - clock0 : input; - clock1 : input; - clocken1 : input; - data_a[16..0] : input; - q_b[16..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 8, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 9, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 10, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 11, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 12, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 13, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 14, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 15, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 17, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 16, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 17, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[4..0] : WIRE; - address_b_wire[4..0] : WIRE; - -BEGIN - ram_block1a[16..0].clk0 = clock0; - ram_block1a[16..0].clk1 = clock1; - ram_block1a[16..0].ena1 = clocken1; - ram_block1a[16..0].portaaddr[] = ( address_a_wire[4..0]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[16..0].portawe = wren_a; - ram_block1a[16..0].portbaddr[] = ( address_b_wire[4..0]); - ram_block1a[16..0].portbre = B"11111111111111111"; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_b[] = ( ram_block1a[16..0].portbdataout[0..0]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_j7h1.tdf b/FPGA_61.440/db/altsyncram_j7h1.tdf deleted file mode 100644 index 9be0982..0000000 --- a/FPGA_61.440/db/altsyncram_j7h1.tdf +++ /dev/null @@ -1,2859 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_ECC="FALSE" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=4 NUMWORDS_B=4 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK1" WIDTH_A=85 WIDTH_B=85 WIDTH_BYTEENA_A=1 WIDTH_ECCSTATUS=2 WIDTHAD_A=2 WIDTHAD_B=2 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 3 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_j7h1 -( - address_a[1..0] : input; - address_b[1..0] : input; - clock0 : input; - clock1 : input; - clocken1 : input; - data_a[84..0] : input; - q_b[84..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 8, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 9, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 10, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 11, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 12, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 13, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 14, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 15, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 16, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 17, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 18, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 19, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 20, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 21, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 22, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 23, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 24, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 25, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 26, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 27, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 28, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 29, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 30, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 31, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a32 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 32, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 32, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a33 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 33, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 33, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a34 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 34, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 34, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a35 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 35, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 35, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a36 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 36, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 36, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a37 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 37, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 37, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a38 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 38, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 38, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a39 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 39, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 39, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a40 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 40, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 40, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a41 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 41, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 41, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a42 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 42, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 42, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a43 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 43, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 43, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a44 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 44, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 44, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a45 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 45, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 45, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a46 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 46, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 46, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a47 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 47, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 47, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a48 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 48, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 48, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a49 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 49, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 49, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a50 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 50, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 50, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a51 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 51, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 51, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a52 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 52, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 52, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a53 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 53, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 53, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a54 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 54, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 54, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a55 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 55, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 55, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a56 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 56, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 56, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a57 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 57, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 57, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a58 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 58, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 58, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a59 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 59, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 59, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a60 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 60, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 60, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a61 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 61, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 61, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a62 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 62, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 62, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a63 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 63, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 63, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a64 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 64, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 64, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a65 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 65, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 65, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a66 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 66, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 66, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a67 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 67, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 67, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a68 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 68, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 68, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a69 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 69, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 69, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a70 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 70, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 70, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a71 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 71, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 71, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a72 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 72, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 72, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a73 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 73, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 73, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a74 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 74, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 74, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a75 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 75, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 75, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a76 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 76, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 76, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a77 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 77, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 77, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a78 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 78, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 78, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a79 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 79, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 79, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a80 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 80, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 80, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a81 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 81, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 81, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a82 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 82, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 82, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a83 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 83, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 83, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a84 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 84, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 85, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 84, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 85, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[1..0] : WIRE; - address_b_wire[1..0] : WIRE; - -BEGIN - ram_block1a[84..0].clk0 = clock0; - ram_block1a[84..0].clk1 = clock1; - ram_block1a[84..0].ena1 = clocken1; - ram_block1a[84..0].portaaddr[] = ( address_a_wire[1..0]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[32].portadatain[] = ( data_a[32..32]); - ram_block1a[33].portadatain[] = ( data_a[33..33]); - ram_block1a[34].portadatain[] = ( data_a[34..34]); - ram_block1a[35].portadatain[] = ( data_a[35..35]); - ram_block1a[36].portadatain[] = ( data_a[36..36]); - ram_block1a[37].portadatain[] = ( data_a[37..37]); - ram_block1a[38].portadatain[] = ( data_a[38..38]); - ram_block1a[39].portadatain[] = ( data_a[39..39]); - ram_block1a[40].portadatain[] = ( data_a[40..40]); - ram_block1a[41].portadatain[] = ( data_a[41..41]); - ram_block1a[42].portadatain[] = ( data_a[42..42]); - ram_block1a[43].portadatain[] = ( data_a[43..43]); - ram_block1a[44].portadatain[] = ( data_a[44..44]); - ram_block1a[45].portadatain[] = ( data_a[45..45]); - ram_block1a[46].portadatain[] = ( data_a[46..46]); - ram_block1a[47].portadatain[] = ( data_a[47..47]); - ram_block1a[48].portadatain[] = ( data_a[48..48]); - ram_block1a[49].portadatain[] = ( data_a[49..49]); - ram_block1a[50].portadatain[] = ( data_a[50..50]); - ram_block1a[51].portadatain[] = ( data_a[51..51]); - ram_block1a[52].portadatain[] = ( data_a[52..52]); - ram_block1a[53].portadatain[] = ( data_a[53..53]); - ram_block1a[54].portadatain[] = ( data_a[54..54]); - ram_block1a[55].portadatain[] = ( data_a[55..55]); - ram_block1a[56].portadatain[] = ( data_a[56..56]); - ram_block1a[57].portadatain[] = ( data_a[57..57]); - ram_block1a[58].portadatain[] = ( data_a[58..58]); - ram_block1a[59].portadatain[] = ( data_a[59..59]); - ram_block1a[60].portadatain[] = ( data_a[60..60]); - ram_block1a[61].portadatain[] = ( data_a[61..61]); - ram_block1a[62].portadatain[] = ( data_a[62..62]); - ram_block1a[63].portadatain[] = ( data_a[63..63]); - ram_block1a[64].portadatain[] = ( data_a[64..64]); - ram_block1a[65].portadatain[] = ( data_a[65..65]); - ram_block1a[66].portadatain[] = ( data_a[66..66]); - ram_block1a[67].portadatain[] = ( data_a[67..67]); - ram_block1a[68].portadatain[] = ( data_a[68..68]); - ram_block1a[69].portadatain[] = ( data_a[69..69]); - ram_block1a[70].portadatain[] = ( data_a[70..70]); - ram_block1a[71].portadatain[] = ( data_a[71..71]); - ram_block1a[72].portadatain[] = ( data_a[72..72]); - ram_block1a[73].portadatain[] = ( data_a[73..73]); - ram_block1a[74].portadatain[] = ( data_a[74..74]); - ram_block1a[75].portadatain[] = ( data_a[75..75]); - ram_block1a[76].portadatain[] = ( data_a[76..76]); - ram_block1a[77].portadatain[] = ( data_a[77..77]); - ram_block1a[78].portadatain[] = ( data_a[78..78]); - ram_block1a[79].portadatain[] = ( data_a[79..79]); - ram_block1a[80].portadatain[] = ( data_a[80..80]); - ram_block1a[81].portadatain[] = ( data_a[81..81]); - ram_block1a[82].portadatain[] = ( data_a[82..82]); - ram_block1a[83].portadatain[] = ( data_a[83..83]); - ram_block1a[84].portadatain[] = ( data_a[84..84]); - ram_block1a[84..0].portawe = wren_a; - ram_block1a[84..0].portbaddr[] = ( address_b_wire[1..0]); - ram_block1a[84..0].portbre = B"1111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_b[] = ( ram_block1a[84..0].portbdataout[0..0]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_l7h1.tdf b/FPGA_61.440/db/altsyncram_l7h1.tdf deleted file mode 100644 index 9183996..0000000 --- a/FPGA_61.440/db/altsyncram_l7h1.tdf +++ /dev/null @@ -1,648 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_ECC="FALSE" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=8 NUMWORDS_B=8 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK1" WIDTH_A=18 WIDTH_B=18 WIDTH_BYTEENA_A=1 WIDTH_ECCSTATUS=2 WIDTHAD_A=3 WIDTHAD_B=3 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 1 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_l7h1 -( - address_a[2..0] : input; - address_b[2..0] : input; - clock0 : input; - clock1 : input; - clocken1 : input; - data_a[17..0] : input; - q_b[17..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 8, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 9, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 10, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 11, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 12, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 13, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 14, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 15, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 16, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 3, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 7, - PORT_A_LOGICAL_RAM_DEPTH = 8, - PORT_A_LOGICAL_RAM_WIDTH = 18, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 3, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 17, - PORT_B_LAST_ADDRESS = 7, - PORT_B_LOGICAL_RAM_DEPTH = 8, - PORT_B_LOGICAL_RAM_WIDTH = 18, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[2..0] : WIRE; - address_b_wire[2..0] : WIRE; - -BEGIN - ram_block1a[17..0].clk0 = clock0; - ram_block1a[17..0].clk1 = clock1; - ram_block1a[17..0].ena1 = clocken1; - ram_block1a[17..0].portaaddr[] = ( address_a_wire[2..0]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[17..0].portawe = wren_a; - ram_block1a[17..0].portbaddr[] = ( address_b_wire[2..0]); - ram_block1a[17..0].portbre = B"111111111111111111"; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_b[] = ( ram_block1a[17..0].portbdataout[0..0]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_lci3.tdf b/FPGA_61.440/db/altsyncram_lci3.tdf deleted file mode 100644 index f7bfb7c..0000000 --- a/FPGA_61.440/db/altsyncram_lci3.tdf +++ /dev/null @@ -1,72 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_A="NONE" BYTEENA_ACLR_B="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="BYPASS" CLOCK_ENABLE_CORE_B="BYPASS" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_ECC="FALSE" ENABLE_RUNTIME_MOD="NO" IMPLEMENT_IN_LES="ON" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" INIT_FILE_LAYOUT="PORT_B" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=4 NUMWORDS_A=4 NUMWORDS_B=4 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="CLOCK1" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_WITH_NBE_READ" read_during_write_mode_port_b="NEW_DATA_WITH_NBE_READ" WIDTH_A=85 WIDTH_B=85 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=2 WIDTHAD_B=2 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION decode_msa (data[1..0], enable) -RETURNS ( eq[3..0]); -FUNCTION mux_rob (data[339..0], sel[1..0]) -RETURNS ( result[84..0]); - ---synthesis_resources = lut 170 reg 598 -OPTIONS ALTERA_INTERNAL_OPTION = "SUPPRESS_DA_RULE_INTERNAL=C106"; - -SUBDESIGN altsyncram_lci3 -( - address_a[1..0] : input; - address_b[1..0] : input; - clock0 : input; - clock1 : input; - clocken1 : input; - data_a[84..0] : input; - q_b[84..0] : output; - wren_a : input; -) -VARIABLE - address_reg[1..0] : dffe; - data_reg[84..0] : dffe; - outdata_reg[84..0] : dffe; - ram_block[339..0] : dffe; - rd_data_out_latch[84..0] : dffe; - wren_reg : dffe; - address_decoder : decode_msa; - output_mux : mux_rob; - address_b_wire[1..0] : WIRE; - -BEGIN - address_reg[].clk = clock0; - address_reg[].d = address_a[]; - data_reg[].clk = clock0; - data_reg[].d = data_a[]; - outdata_reg[].clk = clock1; - outdata_reg[].d = rd_data_out_latch[].q; - outdata_reg[].ena = clocken1; - ram_block[].clk = (! clock0); - ram_block[].d = ( data_reg[].q, data_reg[].q, data_reg[].q, data_reg[].q); - ram_block[].ena = ( address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0]); - rd_data_out_latch[].clk = clock1; - rd_data_out_latch[].d = output_mux.result[]; - wren_reg.clk = clock0; - wren_reg.d = wren_a; - address_decoder.data[] = address_reg[].q; - address_decoder.enable = wren_reg.q; - output_mux.data[] = ram_block[].q; - output_mux.sel[] = address_b_wire[]; - address_b_wire[] = address_b[]; - q_b[] = outdata_reg[].q; -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_m7h1.tdf b/FPGA_61.440/db/altsyncram_m7h1.tdf deleted file mode 100644 index c0b178a..0000000 --- a/FPGA_61.440/db/altsyncram_m7h1.tdf +++ /dev/null @@ -1,2892 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_ECC="FALSE" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=4 NUMWORDS_B=4 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK1" WIDTH_A=86 WIDTH_B=86 WIDTH_BYTEENA_A=1 WIDTH_ECCSTATUS=2 WIDTHAD_A=2 WIDTHAD_B=2 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 3 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_m7h1 -( - address_a[1..0] : input; - address_b[1..0] : input; - clock0 : input; - clock1 : input; - clocken1 : input; - data_a[85..0] : input; - q_b[85..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 8, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 9, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 10, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 11, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 12, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 13, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 14, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 15, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 16, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 17, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 18, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 19, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 20, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 21, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 22, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 23, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 24, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 25, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 26, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 27, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 28, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 29, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 30, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 31, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a32 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 32, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 32, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a33 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 33, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 33, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a34 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 34, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 34, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a35 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 35, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 35, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a36 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 36, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 36, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a37 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 37, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 37, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a38 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 38, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 38, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a39 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 39, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 39, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a40 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 40, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 40, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a41 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 41, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 41, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a42 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 42, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 42, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a43 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 43, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 43, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a44 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 44, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 44, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a45 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 45, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 45, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a46 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 46, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 46, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a47 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 47, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 47, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a48 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 48, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 48, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a49 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 49, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 49, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a50 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 50, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 50, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a51 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 51, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 51, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a52 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 52, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 52, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a53 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 53, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 53, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a54 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 54, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 54, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a55 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 55, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 55, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a56 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 56, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 56, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a57 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 57, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 57, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a58 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 58, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 58, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a59 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 59, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 59, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a60 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 60, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 60, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a61 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 61, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 61, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a62 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 62, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 62, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a63 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 63, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 63, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a64 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 64, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 64, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a65 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 65, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 65, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a66 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 66, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 66, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a67 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 67, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 67, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a68 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 68, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 68, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a69 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 69, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 69, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a70 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 70, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 70, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a71 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 71, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 71, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a72 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 72, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 72, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a73 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 73, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 73, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a74 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 74, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 74, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a75 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 75, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 75, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a76 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 76, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 76, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a77 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 77, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 77, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a78 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 78, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 78, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a79 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 79, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 79, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a80 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 80, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 80, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a81 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 81, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 81, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a82 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 82, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 82, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a83 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 83, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 83, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a84 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 84, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 84, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a85 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 2, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 85, - PORT_A_LAST_ADDRESS = 3, - PORT_A_LOGICAL_RAM_DEPTH = 4, - PORT_A_LOGICAL_RAM_WIDTH = 86, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 2, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 85, - PORT_B_LAST_ADDRESS = 3, - PORT_B_LOGICAL_RAM_DEPTH = 4, - PORT_B_LOGICAL_RAM_WIDTH = 86, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[1..0] : WIRE; - address_b_wire[1..0] : WIRE; - -BEGIN - ram_block1a[85..0].clk0 = clock0; - ram_block1a[85..0].clk1 = clock1; - ram_block1a[85..0].ena1 = clocken1; - ram_block1a[85..0].portaaddr[] = ( address_a_wire[1..0]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[32].portadatain[] = ( data_a[32..32]); - ram_block1a[33].portadatain[] = ( data_a[33..33]); - ram_block1a[34].portadatain[] = ( data_a[34..34]); - ram_block1a[35].portadatain[] = ( data_a[35..35]); - ram_block1a[36].portadatain[] = ( data_a[36..36]); - ram_block1a[37].portadatain[] = ( data_a[37..37]); - ram_block1a[38].portadatain[] = ( data_a[38..38]); - ram_block1a[39].portadatain[] = ( data_a[39..39]); - ram_block1a[40].portadatain[] = ( data_a[40..40]); - ram_block1a[41].portadatain[] = ( data_a[41..41]); - ram_block1a[42].portadatain[] = ( data_a[42..42]); - ram_block1a[43].portadatain[] = ( data_a[43..43]); - ram_block1a[44].portadatain[] = ( data_a[44..44]); - ram_block1a[45].portadatain[] = ( data_a[45..45]); - ram_block1a[46].portadatain[] = ( data_a[46..46]); - ram_block1a[47].portadatain[] = ( data_a[47..47]); - ram_block1a[48].portadatain[] = ( data_a[48..48]); - ram_block1a[49].portadatain[] = ( data_a[49..49]); - ram_block1a[50].portadatain[] = ( data_a[50..50]); - ram_block1a[51].portadatain[] = ( data_a[51..51]); - ram_block1a[52].portadatain[] = ( data_a[52..52]); - ram_block1a[53].portadatain[] = ( data_a[53..53]); - ram_block1a[54].portadatain[] = ( data_a[54..54]); - ram_block1a[55].portadatain[] = ( data_a[55..55]); - ram_block1a[56].portadatain[] = ( data_a[56..56]); - ram_block1a[57].portadatain[] = ( data_a[57..57]); - ram_block1a[58].portadatain[] = ( data_a[58..58]); - ram_block1a[59].portadatain[] = ( data_a[59..59]); - ram_block1a[60].portadatain[] = ( data_a[60..60]); - ram_block1a[61].portadatain[] = ( data_a[61..61]); - ram_block1a[62].portadatain[] = ( data_a[62..62]); - ram_block1a[63].portadatain[] = ( data_a[63..63]); - ram_block1a[64].portadatain[] = ( data_a[64..64]); - ram_block1a[65].portadatain[] = ( data_a[65..65]); - ram_block1a[66].portadatain[] = ( data_a[66..66]); - ram_block1a[67].portadatain[] = ( data_a[67..67]); - ram_block1a[68].portadatain[] = ( data_a[68..68]); - ram_block1a[69].portadatain[] = ( data_a[69..69]); - ram_block1a[70].portadatain[] = ( data_a[70..70]); - ram_block1a[71].portadatain[] = ( data_a[71..71]); - ram_block1a[72].portadatain[] = ( data_a[72..72]); - ram_block1a[73].portadatain[] = ( data_a[73..73]); - ram_block1a[74].portadatain[] = ( data_a[74..74]); - ram_block1a[75].portadatain[] = ( data_a[75..75]); - ram_block1a[76].portadatain[] = ( data_a[76..76]); - ram_block1a[77].portadatain[] = ( data_a[77..77]); - ram_block1a[78].portadatain[] = ( data_a[78..78]); - ram_block1a[79].portadatain[] = ( data_a[79..79]); - ram_block1a[80].portadatain[] = ( data_a[80..80]); - ram_block1a[81].portadatain[] = ( data_a[81..81]); - ram_block1a[82].portadatain[] = ( data_a[82..82]); - ram_block1a[83].portadatain[] = ( data_a[83..83]); - ram_block1a[84].portadatain[] = ( data_a[84..84]); - ram_block1a[85].portadatain[] = ( data_a[85..85]); - ram_block1a[85..0].portawe = wren_a; - ram_block1a[85..0].portbaddr[] = ( address_b_wire[1..0]); - ram_block1a[85..0].portbre = B"11111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_b[] = ( ram_block1a[85..0].portbdataout[0..0]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_nci3.tdf b/FPGA_61.440/db/altsyncram_nci3.tdf deleted file mode 100644 index 2a6ab3c..0000000 --- a/FPGA_61.440/db/altsyncram_nci3.tdf +++ /dev/null @@ -1,72 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_A="NONE" BYTEENA_ACLR_B="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="BYPASS" CLOCK_ENABLE_CORE_B="BYPASS" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_ECC="FALSE" ENABLE_RUNTIME_MOD="NO" IMPLEMENT_IN_LES="ON" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" INIT_FILE_LAYOUT="PORT_B" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=4 NUMWORDS_A=4 NUMWORDS_B=4 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="CLOCK1" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_WITH_NBE_READ" read_during_write_mode_port_b="NEW_DATA_WITH_NBE_READ" WIDTH_A=86 WIDTH_B=86 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=2 WIDTHAD_B=2 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION decode_msa (data[1..0], enable) -RETURNS ( eq[3..0]); -FUNCTION mux_sob (data[343..0], sel[1..0]) -RETURNS ( result[85..0]); - ---synthesis_resources = lut 176 reg 605 -OPTIONS ALTERA_INTERNAL_OPTION = "SUPPRESS_DA_RULE_INTERNAL=C106"; - -SUBDESIGN altsyncram_nci3 -( - address_a[1..0] : input; - address_b[1..0] : input; - clock0 : input; - clock1 : input; - clocken1 : input; - data_a[85..0] : input; - q_b[85..0] : output; - wren_a : input; -) -VARIABLE - address_reg[1..0] : dffe; - data_reg[85..0] : dffe; - outdata_reg[85..0] : dffe; - ram_block[343..0] : dffe; - rd_data_out_latch[85..0] : dffe; - wren_reg : dffe; - address_decoder : decode_msa; - output_mux : mux_sob; - address_b_wire[1..0] : WIRE; - -BEGIN - address_reg[].clk = clock0; - address_reg[].d = address_a[]; - data_reg[].clk = clock0; - data_reg[].d = data_a[]; - outdata_reg[].clk = clock1; - outdata_reg[].d = rd_data_out_latch[].q; - outdata_reg[].ena = clocken1; - ram_block[].clk = (! clock0); - ram_block[].d = ( data_reg[].q, data_reg[].q, data_reg[].q, data_reg[].q); - ram_block[].ena = ( address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..3], address_decoder.eq[3..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..2], address_decoder.eq[2..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..1], address_decoder.eq[1..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0], address_decoder.eq[0..0]); - rd_data_out_latch[].clk = clock1; - rd_data_out_latch[].d = output_mux.result[]; - wren_reg.clk = clock0; - wren_reg.d = wren_a; - address_decoder.data[] = address_reg[].q; - address_decoder.enable = wren_reg.q; - output_mux.data[] = ram_block[].q; - output_mux.sel[] = address_b_wire[]; - address_b_wire[] = address_b[]; - q_b[] = outdata_reg[].q; -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_p8a1.tdf b/FPGA_61.440/db/altsyncram_p8a1.tdf deleted file mode 100644 index 2071722..0000000 --- a/FPGA_61.440/db/altsyncram_p8a1.tdf +++ /dev/null @@ -1,397 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="tx_nco_nco_ii_0_cos_f.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=2048 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 address_a clock0 clocken0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 4 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_p8a1 -( - address_a[10..0] : input; - clock0 : input; - clocken0 : input; - q_a[15..0] : output; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_cos_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[10..0] : WIRE; - -BEGIN - ram_block1a[15..0].clk0 = clock0; - ram_block1a[15..0].ena0 = clocken0; - ram_block1a[15..0].portaaddr[] = ( address_a_wire[10..0]); - ram_block1a[15..0].portare = B"1111111111111111"; - address_a_wire[] = address_a[]; - q_a[] = ( ram_block1a[15..0].portadataout[0..0]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_sln3.tdf b/FPGA_61.440/db/altsyncram_sln3.tdf deleted file mode 100644 index a0c19d3..0000000 --- a/FPGA_61.440/db/altsyncram_sln3.tdf +++ /dev/null @@ -1,1140 +0,0 @@ ---altsyncram ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" BYTE_SIZE=8 BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="NORMAL" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_ECC="FALSE" IMPLEMENT_IN_LES="OFF" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK0" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=64 NUMWORDS_B=64 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="M9K" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" stratixiv_m144k_allow_dual_clocks="ON" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCSTATUS=3 WIDTHAD_A=6 WIDTHAD_B=6 WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK0" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 1 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_sln3 -( - address_a[5..0] : input; - address_b[5..0] : input; - clock0 : input; - data_a[31..0] : input; - q_b[31..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 8, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 9, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 10, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 11, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 12, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 13, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 14, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 15, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 16, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 17, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 18, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 19, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 20, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 21, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 22, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 23, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 24, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 25, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 26, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 27, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 28, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 29, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 30, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "none", - CLK1_INPUT_CLOCK_ENABLE = "none", - CLK1_OUTPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_OUT_CLOCK = "clock1", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 31, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock1", - POWER_UP_UNINITIALIZED = "false", - RAM_BLOCK_TYPE = "M9K" - ); - address_a_wire[5..0] : WIRE; - address_b_wire[5..0] : WIRE; - -BEGIN - ram_block1a[31..0].clk0 = clock0; - ram_block1a[31..0].clk1 = clock0; - ram_block1a[31..0].ena0 = wren_a; - ram_block1a[31..0].portaaddr[] = ( address_a_wire[5..0]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[31..0].portawe = wren_a; - ram_block1a[31..0].portbaddr[] = ( address_b_wire[5..0]); - ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/altsyncram_u8a1.tdf b/FPGA_61.440/db/altsyncram_u8a1.tdf deleted file mode 100644 index a0b6c56..0000000 --- a/FPGA_61.440/db/altsyncram_u8a1.tdf +++ /dev/null @@ -1,397 +0,0 @@ ---altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="tx_nco_nco_ii_0_sin_f.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=2048 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 address_a clock0 clocken0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 4 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_u8a1 -( - address_a[10..0] : input; - clock0 : input; - clocken0 : input; - q_a[15..0] : output; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CLK0_OUTPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "tx_nco_nco_ii_0_sin_f.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "rom", - PORT_A_ADDRESS_CLEAR = "none", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "clock0", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 2047, - PORT_A_LOGICAL_RAM_DEPTH = 2048, - PORT_A_LOGICAL_RAM_WIDTH = 16, - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[10..0] : WIRE; - -BEGIN - ram_block1a[15..0].clk0 = clock0; - ram_block1a[15..0].ena0 = clocken0; - ram_block1a[15..0].portaaddr[] = ( address_a_wire[10..0]); - ram_block1a[15..0].portare = B"1111111111111111"; - address_a_wire[] = address_a[]; - q_a[] = ( ram_block1a[15..0].portadataout[0..0]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/cmpr_fs8.tdf b/FPGA_61.440/db/cmpr_fs8.tdf deleted file mode 100644 index b307ed0..0000000 --- a/FPGA_61.440/db/cmpr_fs8.tdf +++ /dev/null @@ -1,41 +0,0 @@ ---lpm_compare DEVICE_FAMILY="Cyclone IV E" LPM_WIDTH=2 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - - ---synthesis_resources = -SUBDESIGN cmpr_fs8 -( - aeb : output; - dataa[1..0] : input; - datab[1..0] : input; -) -VARIABLE - aeb_result_wire[0..0] : WIRE; - aneb_result_wire[0..0] : WIRE; - data_wire[3..0] : WIRE; - eq_wire : WIRE; - -BEGIN - aeb = eq_wire; - aeb_result_wire[] = (! aneb_result_wire[]); - aneb_result_wire[] = ((data_wire[0..0] $ data_wire[1..1]) # (data_wire[2..2] $ data_wire[3..3])); - data_wire[] = ( datab[1..1], dataa[1..1], datab[0..0], dataa[0..0]); - eq_wire = aeb_result_wire[]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/cmpr_gs8.tdf b/FPGA_61.440/db/cmpr_gs8.tdf deleted file mode 100644 index 7aee186..0000000 --- a/FPGA_61.440/db/cmpr_gs8.tdf +++ /dev/null @@ -1,41 +0,0 @@ ---lpm_compare DEVICE_FAMILY="Cyclone IV E" LPM_WIDTH=3 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - - ---synthesis_resources = -SUBDESIGN cmpr_gs8 -( - aeb : output; - dataa[2..0] : input; - datab[2..0] : input; -) -VARIABLE - aeb_result_wire[0..0] : WIRE; - aneb_result_wire[0..0] : WIRE; - data_wire[7..0] : WIRE; - eq_wire : WIRE; - -BEGIN - aeb = eq_wire; - aeb_result_wire[] = (! aneb_result_wire[]); - aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]); - data_wire[] = ( datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[6..6] $ data_wire[7..7]), ((data_wire[2..2] $ data_wire[3..3]) # (data_wire[4..4] $ data_wire[5..5]))); - eq_wire = aeb_result_wire[]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/cmpr_is8.tdf b/FPGA_61.440/db/cmpr_is8.tdf deleted file mode 100644 index 09c9d1f..0000000 --- a/FPGA_61.440/db/cmpr_is8.tdf +++ /dev/null @@ -1,41 +0,0 @@ ---lpm_compare DEVICE_FAMILY="Cyclone IV E" LPM_WIDTH=5 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - - ---synthesis_resources = -SUBDESIGN cmpr_is8 -( - aeb : output; - dataa[4..0] : input; - datab[4..0] : input; -) -VARIABLE - aeb_result_wire[0..0] : WIRE; - aneb_result_wire[0..0] : WIRE; - data_wire[12..0] : WIRE; - eq_wire : WIRE; - -BEGIN - aeb = eq_wire; - aeb_result_wire[] = (! aneb_result_wire[]); - aneb_result_wire[] = ((data_wire[0..0] # data_wire[1..1]) # data_wire[2..2]); - data_wire[] = ( datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[11..11] $ data_wire[12..12]), ((data_wire[7..7] $ data_wire[8..8]) # (data_wire[9..9] $ data_wire[10..10])), ((data_wire[3..3] $ data_wire[4..4]) # (data_wire[5..5] $ data_wire[6..6]))); - eq_wire = aeb_result_wire[]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/cntr_7a7.tdf b/FPGA_61.440/db/cntr_7a7.tdf deleted file mode 100644 index ef90ba8..0000000 --- a/FPGA_61.440/db/cntr_7a7.tdf +++ /dev/null @@ -1,77 +0,0 @@ ---lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_width=2 clock cnt_en q sclr updown ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) -WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) -RETURNS ( combout, cout); - ---synthesis_resources = lut 2 reg 2 -SUBDESIGN cntr_7a7 -( - clock : input; - cnt_en : input; - q[1..0] : output; - sclr : input; - updown : input; -) -VARIABLE - counter_comb_bita0 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita1 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_reg_bit[1..0] : dffeas; - aclr_actual : WIRE; - clk_en : NODE; - data[1..0] : NODE; - external_cin : WIRE; - s_val[1..0] : WIRE; - safe_q[1..0] : WIRE; - sload : NODE; - sset : NODE; - updown_dir : WIRE; - -BEGIN - counter_comb_bita[1..0].cin = ( counter_comb_bita[0].cout, external_cin); - counter_comb_bita[1..0].dataa = ( counter_reg_bit[1..0].q); - counter_comb_bita[1..0].datab = ( updown_dir, updown_dir); - counter_comb_bita[1..0].datad = ( B"1", B"1"); - counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); - counter_reg_bit[].clk = clock; - counter_reg_bit[].clrn = (! aclr_actual); - counter_reg_bit[].d = ( counter_comb_bita[1..0].combout); - counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); - counter_reg_bit[].sload = ((sclr # sset) # sload); - aclr_actual = B"0"; - clk_en = VCC; - data[] = GND; - external_cin = B"1"; - q[] = safe_q[]; - s_val[] = B"11"; - safe_q[] = counter_reg_bit[].q; - sload = GND; - sset = GND; - updown_dir = updown; -END; ---VALID FILE diff --git a/FPGA_61.440/db/cntr_8a7.tdf b/FPGA_61.440/db/cntr_8a7.tdf deleted file mode 100644 index 4050298..0000000 --- a/FPGA_61.440/db/cntr_8a7.tdf +++ /dev/null @@ -1,82 +0,0 @@ ---lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_width=3 clock cnt_en q sclr updown ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) -WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) -RETURNS ( combout, cout); - ---synthesis_resources = lut 3 reg 3 -SUBDESIGN cntr_8a7 -( - clock : input; - cnt_en : input; - q[2..0] : output; - sclr : input; - updown : input; -) -VARIABLE - counter_comb_bita0 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita1 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita2 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_reg_bit[2..0] : dffeas; - aclr_actual : WIRE; - clk_en : NODE; - data[2..0] : NODE; - external_cin : WIRE; - s_val[2..0] : WIRE; - safe_q[2..0] : WIRE; - sload : NODE; - sset : NODE; - updown_dir : WIRE; - -BEGIN - counter_comb_bita[2..0].cin = ( counter_comb_bita[1..0].cout, external_cin); - counter_comb_bita[2..0].dataa = ( counter_reg_bit[2..0].q); - counter_comb_bita[2..0].datab = ( updown_dir, updown_dir, updown_dir); - counter_comb_bita[2..0].datad = ( B"1", B"1", B"1"); - counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); - counter_reg_bit[].clk = clock; - counter_reg_bit[].clrn = (! aclr_actual); - counter_reg_bit[].d = ( counter_comb_bita[2..0].combout); - counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); - counter_reg_bit[].sload = ((sclr # sset) # sload); - aclr_actual = B"0"; - clk_en = VCC; - data[] = GND; - external_cin = B"1"; - q[] = safe_q[]; - s_val[] = B"111"; - safe_q[] = counter_reg_bit[].q; - sload = GND; - sset = GND; - updown_dir = updown; -END; ---VALID FILE diff --git a/FPGA_61.440/db/cntr_aa7.tdf b/FPGA_61.440/db/cntr_aa7.tdf deleted file mode 100644 index b155a85..0000000 --- a/FPGA_61.440/db/cntr_aa7.tdf +++ /dev/null @@ -1,92 +0,0 @@ ---lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_width=5 clock cnt_en q sclr updown ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) -WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) -RETURNS ( combout, cout); - ---synthesis_resources = lut 5 reg 5 -SUBDESIGN cntr_aa7 -( - clock : input; - cnt_en : input; - q[4..0] : output; - sclr : input; - updown : input; -) -VARIABLE - counter_comb_bita0 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita1 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita2 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita3 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita4 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_reg_bit[4..0] : dffeas; - aclr_actual : WIRE; - clk_en : NODE; - data[4..0] : NODE; - external_cin : WIRE; - s_val[4..0] : WIRE; - safe_q[4..0] : WIRE; - sload : NODE; - sset : NODE; - updown_dir : WIRE; - -BEGIN - counter_comb_bita[4..0].cin = ( counter_comb_bita[3..0].cout, external_cin); - counter_comb_bita[4..0].dataa = ( counter_reg_bit[4..0].q); - counter_comb_bita[4..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); - counter_comb_bita[4..0].datad = ( B"1", B"1", B"1", B"1", B"1"); - counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); - counter_reg_bit[].clk = clock; - counter_reg_bit[].clrn = (! aclr_actual); - counter_reg_bit[].d = ( counter_comb_bita[4..0].combout); - counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); - counter_reg_bit[].sload = ((sclr # sset) # sload); - aclr_actual = B"0"; - clk_en = VCC; - data[] = GND; - external_cin = B"1"; - q[] = safe_q[]; - s_val[] = B"11111"; - safe_q[] = counter_reg_bit[].q; - sload = GND; - sset = GND; - updown_dir = updown; -END; ---VALID FILE diff --git a/FPGA_61.440/db/cntr_asi.tdf b/FPGA_61.440/db/cntr_asi.tdf deleted file mode 100644 index 7a97ac5..0000000 --- a/FPGA_61.440/db/cntr_asi.tdf +++ /dev/null @@ -1,86 +0,0 @@ ---lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=4 clk_en clock q sclr CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) -WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) -RETURNS ( combout, cout); - ---synthesis_resources = lut 4 reg 4 -SUBDESIGN cntr_asi -( - clk_en : input; - clock : input; - q[3..0] : output; - sclr : input; -) -VARIABLE - counter_comb_bita0 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita1 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita2 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita3 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_reg_bit[3..0] : dffeas; - aclr_actual : WIRE; - cnt_en : NODE; - data[3..0] : NODE; - external_cin : WIRE; - s_val[3..0] : WIRE; - safe_q[3..0] : WIRE; - sload : NODE; - sset : NODE; - updown_dir : WIRE; - -BEGIN - counter_comb_bita[3..0].cin = ( counter_comb_bita[2..0].cout, external_cin); - counter_comb_bita[3..0].dataa = ( counter_reg_bit[3..0].q); - counter_comb_bita[3..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir); - counter_comb_bita[3..0].datad = ( B"1", B"1", B"1", B"1"); - counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); - counter_reg_bit[].clk = clock; - counter_reg_bit[].clrn = (! aclr_actual); - counter_reg_bit[].d = ( counter_comb_bita[3..0].combout); - counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); - counter_reg_bit[].sload = ((sclr # sset) # sload); - aclr_actual = B"0"; - cnt_en = VCC; - data[] = GND; - external_cin = B"1"; - q[] = safe_q[]; - s_val[] = B"1111"; - safe_q[] = counter_reg_bit[].q; - sload = GND; - sset = GND; - updown_dir = B"1"; -END; ---VALID FILE diff --git a/FPGA_61.440/db/cntr_q9b.tdf b/FPGA_61.440/db/cntr_q9b.tdf deleted file mode 100644 index 56e680b..0000000 --- a/FPGA_61.440/db/cntr_q9b.tdf +++ /dev/null @@ -1,71 +0,0 @@ ---lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=1 clock cnt_en q sclr ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) -WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) -RETURNS ( combout, cout); - ---synthesis_resources = lut 1 reg 1 -SUBDESIGN cntr_q9b -( - clock : input; - cnt_en : input; - q[0..0] : output; - sclr : input; -) -VARIABLE - counter_comb_bita0 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_reg_bit[0..0] : dffeas; - aclr_actual : WIRE; - clk_en : NODE; - data[0..0] : NODE; - external_cin : WIRE; - s_val[0..0] : WIRE; - safe_q[0..0] : WIRE; - sload : NODE; - sset : NODE; - updown_dir : WIRE; - -BEGIN - counter_comb_bita[0..0].cin = ( external_cin); - counter_comb_bita[0..0].dataa = ( counter_reg_bit[0..0].q); - counter_comb_bita[0..0].datab = ( updown_dir); - counter_comb_bita[0..0].datad = ( B"1"); - counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); - counter_reg_bit[].clk = clock; - counter_reg_bit[].clrn = (! aclr_actual); - counter_reg_bit[].d = ( counter_comb_bita[0].combout); - counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); - counter_reg_bit[].sload = ((sclr # sset) # sload); - aclr_actual = B"0"; - clk_en = VCC; - data[] = GND; - external_cin = B"1"; - q[] = safe_q[]; - s_val[] = B"1"; - safe_q[] = counter_reg_bit[].q; - sload = GND; - sset = GND; - updown_dir = B"1"; -END; ---VALID FILE diff --git a/FPGA_61.440/db/cntr_r9b.tdf b/FPGA_61.440/db/cntr_r9b.tdf deleted file mode 100644 index c60306c..0000000 --- a/FPGA_61.440/db/cntr_r9b.tdf +++ /dev/null @@ -1,76 +0,0 @@ ---lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=2 clock cnt_en q sclr ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) -WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) -RETURNS ( combout, cout); - ---synthesis_resources = lut 2 reg 2 -SUBDESIGN cntr_r9b -( - clock : input; - cnt_en : input; - q[1..0] : output; - sclr : input; -) -VARIABLE - counter_comb_bita0 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita1 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_reg_bit[1..0] : dffeas; - aclr_actual : WIRE; - clk_en : NODE; - data[1..0] : NODE; - external_cin : WIRE; - s_val[1..0] : WIRE; - safe_q[1..0] : WIRE; - sload : NODE; - sset : NODE; - updown_dir : WIRE; - -BEGIN - counter_comb_bita[1..0].cin = ( counter_comb_bita[0].cout, external_cin); - counter_comb_bita[1..0].dataa = ( counter_reg_bit[1..0].q); - counter_comb_bita[1..0].datab = ( updown_dir, updown_dir); - counter_comb_bita[1..0].datad = ( B"1", B"1"); - counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); - counter_reg_bit[].clk = clock; - counter_reg_bit[].clrn = (! aclr_actual); - counter_reg_bit[].d = ( counter_comb_bita[1..0].combout); - counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); - counter_reg_bit[].sload = ((sclr # sset) # sload); - aclr_actual = B"0"; - clk_en = VCC; - data[] = GND; - external_cin = B"1"; - q[] = safe_q[]; - s_val[] = B"11"; - safe_q[] = counter_reg_bit[].q; - sload = GND; - sset = GND; - updown_dir = B"1"; -END; ---VALID FILE diff --git a/FPGA_61.440/db/cntr_s9b.tdf b/FPGA_61.440/db/cntr_s9b.tdf deleted file mode 100644 index edbb738..0000000 --- a/FPGA_61.440/db/cntr_s9b.tdf +++ /dev/null @@ -1,81 +0,0 @@ ---lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=3 clock cnt_en q sclr ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) -WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) -RETURNS ( combout, cout); - ---synthesis_resources = lut 3 reg 3 -SUBDESIGN cntr_s9b -( - clock : input; - cnt_en : input; - q[2..0] : output; - sclr : input; -) -VARIABLE - counter_comb_bita0 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita1 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita2 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_reg_bit[2..0] : dffeas; - aclr_actual : WIRE; - clk_en : NODE; - data[2..0] : NODE; - external_cin : WIRE; - s_val[2..0] : WIRE; - safe_q[2..0] : WIRE; - sload : NODE; - sset : NODE; - updown_dir : WIRE; - -BEGIN - counter_comb_bita[2..0].cin = ( counter_comb_bita[1..0].cout, external_cin); - counter_comb_bita[2..0].dataa = ( counter_reg_bit[2..0].q); - counter_comb_bita[2..0].datab = ( updown_dir, updown_dir, updown_dir); - counter_comb_bita[2..0].datad = ( B"1", B"1", B"1"); - counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); - counter_reg_bit[].clk = clock; - counter_reg_bit[].clrn = (! aclr_actual); - counter_reg_bit[].d = ( counter_comb_bita[2..0].combout); - counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); - counter_reg_bit[].sload = ((sclr # sset) # sload); - aclr_actual = B"0"; - clk_en = VCC; - data[] = GND; - external_cin = B"1"; - q[] = safe_q[]; - s_val[] = B"111"; - safe_q[] = counter_reg_bit[].q; - sload = GND; - sset = GND; - updown_dir = B"1"; -END; ---VALID FILE diff --git a/FPGA_61.440/db/cntr_t9b.tdf b/FPGA_61.440/db/cntr_t9b.tdf deleted file mode 100644 index df50af2..0000000 --- a/FPGA_61.440/db/cntr_t9b.tdf +++ /dev/null @@ -1,86 +0,0 @@ ---lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=4 clock cnt_en q sclr ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) -WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) -RETURNS ( combout, cout); - ---synthesis_resources = lut 4 reg 4 -SUBDESIGN cntr_t9b -( - clock : input; - cnt_en : input; - q[3..0] : output; - sclr : input; -) -VARIABLE - counter_comb_bita0 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita1 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita2 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita3 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_reg_bit[3..0] : dffeas; - aclr_actual : WIRE; - clk_en : NODE; - data[3..0] : NODE; - external_cin : WIRE; - s_val[3..0] : WIRE; - safe_q[3..0] : WIRE; - sload : NODE; - sset : NODE; - updown_dir : WIRE; - -BEGIN - counter_comb_bita[3..0].cin = ( counter_comb_bita[2..0].cout, external_cin); - counter_comb_bita[3..0].dataa = ( counter_reg_bit[3..0].q); - counter_comb_bita[3..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir); - counter_comb_bita[3..0].datad = ( B"1", B"1", B"1", B"1"); - counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); - counter_reg_bit[].clk = clock; - counter_reg_bit[].clrn = (! aclr_actual); - counter_reg_bit[].d = ( counter_comb_bita[3..0].combout); - counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); - counter_reg_bit[].sload = ((sclr # sset) # sload); - aclr_actual = B"0"; - clk_en = VCC; - data[] = GND; - external_cin = B"1"; - q[] = safe_q[]; - s_val[] = B"1111"; - safe_q[] = counter_reg_bit[].q; - sload = GND; - sset = GND; - updown_dir = B"1"; -END; ---VALID FILE diff --git a/FPGA_61.440/db/cntr_u9b.tdf b/FPGA_61.440/db/cntr_u9b.tdf deleted file mode 100644 index ababc46..0000000 --- a/FPGA_61.440/db/cntr_u9b.tdf +++ /dev/null @@ -1,91 +0,0 @@ ---lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=5 clock cnt_en q sclr ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) -WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) -RETURNS ( combout, cout); - ---synthesis_resources = lut 5 reg 5 -SUBDESIGN cntr_u9b -( - clock : input; - cnt_en : input; - q[4..0] : output; - sclr : input; -) -VARIABLE - counter_comb_bita0 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita1 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita2 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita3 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita4 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_reg_bit[4..0] : dffeas; - aclr_actual : WIRE; - clk_en : NODE; - data[4..0] : NODE; - external_cin : WIRE; - s_val[4..0] : WIRE; - safe_q[4..0] : WIRE; - sload : NODE; - sset : NODE; - updown_dir : WIRE; - -BEGIN - counter_comb_bita[4..0].cin = ( counter_comb_bita[3..0].cout, external_cin); - counter_comb_bita[4..0].dataa = ( counter_reg_bit[4..0].q); - counter_comb_bita[4..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); - counter_comb_bita[4..0].datad = ( B"1", B"1", B"1", B"1", B"1"); - counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); - counter_reg_bit[].clk = clock; - counter_reg_bit[].clrn = (! aclr_actual); - counter_reg_bit[].d = ( counter_comb_bita[4..0].combout); - counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); - counter_reg_bit[].sload = ((sclr # sset) # sload); - aclr_actual = B"0"; - clk_en = VCC; - data[] = GND; - external_cin = B"1"; - q[] = safe_q[]; - s_val[] = B"11111"; - safe_q[] = counter_reg_bit[].q; - sload = GND; - sset = GND; - updown_dir = B"1"; -END; ---VALID FILE diff --git a/FPGA_61.440/db/decode_msa.tdf b/FPGA_61.440/db/decode_msa.tdf deleted file mode 100644 index a660949..0000000 --- a/FPGA_61.440/db/decode_msa.tdf +++ /dev/null @@ -1,49 +0,0 @@ ---lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=4 LPM_WIDTH=2 data enable eq ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - - ---synthesis_resources = lut 4 -SUBDESIGN decode_msa -( - data[1..0] : input; - enable : input; - eq[3..0] : output; -) -VARIABLE - data_wire[1..0] : WIRE; - enable_wire : WIRE; - eq_node[3..0] : WIRE; - eq_wire[3..0] : WIRE; - w_anode19w[2..0] : WIRE; - w_anode32w[2..0] : WIRE; - w_anode40w[2..0] : WIRE; - w_anode48w[2..0] : WIRE; - -BEGIN - data_wire[] = data[]; - enable_wire = enable; - eq[] = eq_node[]; - eq_node[3..0] = eq_wire[3..0]; - eq_wire[] = ( w_anode48w[2..2], w_anode40w[2..2], w_anode32w[2..2], w_anode19w[2..2]); - w_anode19w[] = ( (w_anode19w[1..1] & (! data_wire[1..1])), (w_anode19w[0..0] & (! data_wire[0..0])), enable_wire); - w_anode32w[] = ( (w_anode32w[1..1] & (! data_wire[1..1])), (w_anode32w[0..0] & data_wire[0..0]), enable_wire); - w_anode40w[] = ( (w_anode40w[1..1] & data_wire[1..1]), (w_anode40w[0..0] & (! data_wire[0..0])), enable_wire); - w_anode48w[] = ( (w_anode48w[1..1] & data_wire[1..1]), (w_anode48w[0..0] & data_wire[0..0]), enable_wire); -END; ---VALID FILE diff --git a/FPGA_61.440/db/ip/DEBUG/DEBUG.bsf b/FPGA_61.440/db/ip/DEBUG/DEBUG.bsf deleted file mode 100644 index ee8dbb9..0000000 --- a/FPGA_61.440/db/ip/DEBUG/DEBUG.bsf +++ /dev/null @@ -1,48 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 2018 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 176 104) - (text "DEBUG" (rect 66 -1 100 11)(font "Arial" (font_size 10))) - (text "inst" (rect 8 88 20 100)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "probe[11..0]" (rect 0 0 44 12)(font "Arial" (font_size 8))) - (text "probe[11..0]" (rect 4 61 76 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 64 72)(line_width 3)) - ) - (drawing - (text "probes" (rect 25 43 86 99)(font "Arial" (color 128 0 0)(font_size 9))) - (text "probe" (rect 69 67 168 144)(font "Arial" (color 0 0 0))) - (text " DEBUG " (rect 139 88 320 186)(font "Arial" )) - (line (pt 64 32)(pt 112 32)(line_width 1)) - (line (pt 112 32)(pt 112 88)(line_width 1)) - (line (pt 64 88)(pt 112 88)(line_width 1)) - (line (pt 64 32)(pt 64 88)(line_width 1)) - (line (pt 65 52)(pt 65 76)(line_width 1)) - (line (pt 66 52)(pt 66 76)(line_width 1)) - (line (pt 0 0)(pt 176 0)(line_width 1)) - (line (pt 176 0)(pt 176 104)(line_width 1)) - (line (pt 0 104)(pt 176 104)(line_width 1)) - (line (pt 0 0)(pt 0 104)(line_width 1)) - ) -) diff --git a/FPGA_61.440/db/ip/DEBUG/DEBUG.debuginfo b/FPGA_61.440/db/ip/DEBUG/DEBUG.debuginfo deleted file mode 100644 index ec9dea3..0000000 --- a/FPGA_61.440/db/ip/DEBUG/DEBUG.debuginfo +++ /dev/null @@ -1,338 +0,0 @@ - - - - - - - com.altera.sopcmodel.ensemble.EClockAdapter - HANDSHAKE - false - true - true - true - - - java.lang.String - EP4CE10E22C8 - false - true - true - true - - - java.lang.String - CYCLONEIVE - false - true - true - true - - - java.lang.String - 8 - false - true - false - true - - - com.altera.sopcmodel.ensemble.Ensemble$EFabricMode - QSYS - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1617214592 - false - true - true - true - - - boolean - false - false - true - false - true - - - com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage - VERILOG - false - false - false - true - - - boolean - true - false - true - true - true - - - com.altera.sopcmodel.definition.BoundaryDefinition - - false - true - false - true - - - int - 1 - false - true - true - true - - - java.lang.String - WOLF.qpf - false - true - false - true - - - boolean - false - false - true - false - true - - - long - 0 - false - true - false - true - - - java.lang.String - - false - true - false - true - - - long - 0 - false - true - false - true - - - boolean - false - false - true - false - true - - - - - embeddedsw.dts.group - ignore - - - embeddedsw.dts.name - debug - - - embeddedsw.dts.vendor - altr - - - java.lang.String - CYCLONEIVE - false - true - false - true - DEVICE_FAMILY - - - boolean - true - false - true - true - true - - - java.lang.String - YES - true - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - ADC - false - true - true - true - - - int - 12 - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - 0 - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - NO - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - probe - Input - 12 - probe - - - - - 1 - altera_in_system_sources_probes - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - - 18.1 - - - 1 - conduit_end - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit - 18.1 - - 18.1 625 - 08626627EDAB0000017889805D37 - diff --git a/FPGA_61.440/db/ip/DEBUG/DEBUG.qip b/FPGA_61.440/db/ip/DEBUG/DEBUG.qip deleted file mode 100644 index 19941eb..0000000 --- a/FPGA_61.440/db/ip/DEBUG/DEBUG.qip +++ /dev/null @@ -1,41 +0,0 @@ -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_TOOL_NAME "Qsys" -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_TOOL_ENV "Qsys" -set_global_assignment -library "DEBUG" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../../DEBUG.sopcinfo"] -set_global_assignment -entity "DEBUG" -library "DEBUG" -name SLD_INFO "QSYS_NAME DEBUG HAS_SOPCINFO 1 GENERATION_ID 1617214592" -set_global_assignment -library "DEBUG" -name SLD_FILE [file join $::quartus(qip_path) "DEBUG.debuginfo"] -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E" -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_QSYS_MODE "STANDALONE" -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -library "DEBUG" -name MISC_FILE [file join $::quartus(qip_path) "../../../DEBUG.qsys"] -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_NAME "REVCVUc=" -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_DISPLAY_NAME "REVCVUc=" -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_REPORT_HIERARCHY "On" -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_VERSION "MS4w" -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYxNzIxNDU5Mg==::QXV0byBHRU5FUkFUSU9OX0lE" -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMEUyMkM4::QXV0byBERVZJQ0U=" -set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_NAME "YWx0c291cmNlX3Byb2JlX3RvcA==" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIEluLVN5c3RlbSBTb3VyY2VzICYgUHJvYmVz" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_DESCRIPTION "SW4tc3lzdGVtIHNvdXJjZXMgJiBwcm9iZXMgZGVidWdnaW5nIG1lZ2FmdW5jdGlvbi4gIFRoZSBJbi1TeXN0ZW0gU291cmNlcyBhbmQgUHJvYmVzIG1lZ2FmdW5jdGlvbiBpcwphdmFpbGFibGUgZm9yIGFsbCBBbHRlcmEgZGV2aWNlIGZhbWlsaWVzIHN1cHBvcnRlZCBieSB0aGUgUXVhcnR1cyBQcmltZSBzb2Z0d2FyZS4=" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlX2ZhbWlseQ==" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hdXRvX2luZGV4::dHJ1ZQ==::QXV0b21hdGljIEluc3RhbmNlIEluZGV4IEFzc2lnbm1lbnQ=" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_PARAMETER "c2xkX2F1dG9faW5zdGFuY2VfaW5kZXg=::WUVT::c2xkX2F1dG9faW5zdGFuY2VfaW5kZXg=" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_PARAMETER "aW5zdGFuY2VfaWQ=::QURD::VGhlICdJbnN0YW5jZSBJRCcgb2YgdGhpcyBpbnN0YW5jZSAob3B0aW9uYWwp" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_PARAMETER "cHJvYmVfd2lkdGg=::MTI=::UHJvYmUgUG9ydCBXaWR0aCBbMC4uNTEyXQ==" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_PARAMETER "c291cmNlX3dpZHRo::MA==::U291cmNlIFBvcnQgV2lkdGggWzAuLjUxMl0=" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX21ldGFzdGFiaWxpdHk=::Tk8=::ZW5hYmxlX21ldGFzdGFiaWxpdHk=" - -set_global_assignment -library "DEBUG" -name VERILOG_FILE [file join $::quartus(qip_path) "DEBUG.v"] -set_global_assignment -library "DEBUG" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altsource_probe_top.v"] - -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_TOOL_NAME "altera_in_system_sources_probes" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_TOOL_ENV "Qsys" diff --git a/FPGA_61.440/db/ip/DEBUG/DEBUG.v b/FPGA_61.440/db/ip/DEBUG/DEBUG.v deleted file mode 100644 index 506d9af..0000000 --- a/FPGA_61.440/db/ip/DEBUG/DEBUG.v +++ /dev/null @@ -1,21 +0,0 @@ -// DEBUG.v - -// Generated using ACDS version 18.1 625 - -`timescale 1 ps / 1 ps -module DEBUG ( - input wire [11:0] probe // probes.probe - ); - - altsource_probe_top #( - .sld_auto_instance_index ("YES"), - .sld_instance_index (0), - .instance_id ("ADC"), - .probe_width (12), - .source_width (0), - .enable_metastability ("NO") - ) in_system_sources_probes_0 ( - .probe (probe) // probes.probe - ); - -endmodule diff --git a/FPGA_61.440/db/ip/DEBUG/DEBUG__report.html b/FPGA_61.440/db/ip/DEBUG/DEBUG__report.html deleted file mode 100644 index 10f14aa..0000000 --- a/FPGA_61.440/db/ip/DEBUG/DEBUG__report.html +++ /dev/null @@ -1,177 +0,0 @@ - - - - - datasheet for DEBUG - - - - - - - - -
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2021.03.31.22:16:33Datasheet
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in_system_sources_probes_0

altera_in_system_sources_probes v18.1 -
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Parameters

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device_familyCYCLONEIVE
gui_use_auto_indextrue
sld_auto_instance_indexYES
sld_instance_index0
instance_idADC
probe_width12
source_width0
source_initial_value0
create_source_clockfalse
create_source_clock_enablefalse
enable_metastabilityNO
deviceFamilyUNKNOWN
generateLegacySimfalse
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Software Assignments

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generation took 0,01 secondsrendering took 0,03 seconds
- - diff --git a/FPGA_61.440/db/ip/DEBUG/DEBUG__report.xml b/FPGA_61.440/db/ip/DEBUG/DEBUG__report.xml deleted file mode 100644 index 102d1c4..0000000 --- a/FPGA_61.440/db/ip/DEBUG/DEBUG__report.xml +++ /dev/null @@ -1,123 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:DEBUG "DEBUG" - - - - Transform: CustomInstructionTransform - No custom instruction connections, skipping transform - 1 modules, 0 connections]]> - Transform: MMTransform - Transform: InterruptMapperTransform - Transform: InterruptSyncTransform - Transform: InterruptFanoutTransform - Transform: AvalonStreamingTransform - Transform: ResetAdaptation - DEBUG" reuses altera_in_system_sources_probes "submodules/altsource_probe_top"]]> - queue size: 0 starting:altera_in_system_sources_probes "submodules/altsource_probe_top" - DEBUG" instantiated altera_in_system_sources_probes "in_system_sources_probes_0"]]> - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:altera_in_system_sources_probes "submodules/altsource_probe_top" - DEBUG" instantiated altera_in_system_sources_probes "in_system_sources_probes_0"]]> - - - diff --git a/FPGA_61.440/db/ip/DEBUG/submodules/altsource_probe_top.v b/FPGA_61.440/db/ip/DEBUG/submodules/altsource_probe_top.v deleted file mode 100644 index 4011e56..0000000 --- a/FPGA_61.440/db/ip/DEBUG/submodules/altsource_probe_top.v +++ /dev/null @@ -1,57 +0,0 @@ -// (C) 2001-2018 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -module altsource_probe_top -#( - parameter lpm_type = "altsource_probe", // required by the coding standard - parameter lpm_hint = "UNUSED", // required by the coding standard - - parameter sld_auto_instance_index = "YES", // Yes, if the instance index should be automatically assigned. - parameter sld_instance_index = 0, // unique identifier for the altsource_probe instance. - parameter sld_node_info_parameter = 4746752 + sld_instance_index, // The NODE ID to uniquely identify this node on the hub. Type ID: 9 Version: 0 Inst: 0 MFG ID 110 -- ***NOTE*** this parameter cannot be called SLD_NODE_INFO or Quartus Standard will think it's an ISSP impl. - parameter sld_ir_width = 4, - - parameter instance_id = "UNUSED", // optional name for the instance. - parameter probe_width = 1, // probe port width - parameter source_width= 1, // source port width - parameter source_initial_value = "0", // initial source port value - parameter enable_metastability = "NO" // yes to add two register -) -( - input [probe_width - 1 : 0] probe, // probe inputs - output [source_width - 1 : 0] source, // source outputs - input source_clk, // clock of the registers used to metastabilize the source output - input tri1 source_ena // enable of the registers used to metastabilize the source output -); - - altsource_probe #( - .lpm_type(lpm_type), - .lpm_hint(lpm_hint), - .sld_auto_instance_index(sld_auto_instance_index), - .sld_instance_index(sld_instance_index), - .SLD_NODE_INFO(sld_node_info_parameter), - .sld_ir_width(sld_ir_width), - .instance_id(instance_id), - .probe_width(probe_width), - .source_width(source_width), - .source_initial_value(source_initial_value), - .enable_metastability(enable_metastability) - )issp_impl - ( - .probe(probe), - .source(source), - .source_clk(source_clk), - .source_ena(source_ena) - ); - -endmodule \ No newline at end of file diff --git a/FPGA_61.440/db/ip/DEBUG2/DEBUG2.bsf b/FPGA_61.440/db/ip/DEBUG2/DEBUG2.bsf deleted file mode 100644 index efd4145..0000000 --- a/FPGA_61.440/db/ip/DEBUG2/DEBUG2.bsf +++ /dev/null @@ -1,48 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 2018 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 208 104) - (text "DEBUG2" (rect 78 -1 116 11)(font "Arial" (font_size 10))) - (text "inst" (rect 8 88 20 100)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "probe[23..0]" (rect 0 0 47 12)(font "Arial" (font_size 8))) - (text "probe[23..0]" (rect 4 61 76 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 80 72)(line_width 3)) - ) - (drawing - (text "probes" (rect 41 43 118 99)(font "Arial" (color 128 0 0)(font_size 9))) - (text "probe" (rect 85 67 200 144)(font "Arial" (color 0 0 0))) - (text " DEBUG2 " (rect 166 88 380 186)(font "Arial" )) - (line (pt 80 32)(pt 128 32)(line_width 1)) - (line (pt 128 32)(pt 128 88)(line_width 1)) - (line (pt 80 88)(pt 128 88)(line_width 1)) - (line (pt 80 32)(pt 80 88)(line_width 1)) - (line (pt 81 52)(pt 81 76)(line_width 1)) - (line (pt 82 52)(pt 82 76)(line_width 1)) - (line (pt 0 0)(pt 208 0)(line_width 1)) - (line (pt 208 0)(pt 208 104)(line_width 1)) - (line (pt 0 104)(pt 208 104)(line_width 1)) - (line (pt 0 0)(pt 0 104)(line_width 1)) - ) -) diff --git a/FPGA_61.440/db/ip/DEBUG2/DEBUG2.debuginfo b/FPGA_61.440/db/ip/DEBUG2/DEBUG2.debuginfo deleted file mode 100644 index 0744c13..0000000 --- a/FPGA_61.440/db/ip/DEBUG2/DEBUG2.debuginfo +++ /dev/null @@ -1,338 +0,0 @@ - - - - - - - com.altera.sopcmodel.ensemble.EClockAdapter - HANDSHAKE - false - true - true - true - - - java.lang.String - EP4CE10E22C8 - false - true - true - true - - - java.lang.String - CYCLONEIVE - false - true - true - true - - - java.lang.String - 8 - false - true - false - true - - - com.altera.sopcmodel.ensemble.Ensemble$EFabricMode - QSYS - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1617214606 - false - true - true - true - - - boolean - false - false - true - false - true - - - com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage - VERILOG - false - false - false - true - - - boolean - true - false - true - true - true - - - com.altera.sopcmodel.definition.BoundaryDefinition - - false - true - false - true - - - int - 1 - false - true - true - true - - - java.lang.String - UA3REO.qpf - false - true - false - true - - - boolean - false - false - true - false - true - - - long - 0 - false - true - false - true - - - java.lang.String - - false - true - false - true - - - long - 0 - false - true - false - true - - - boolean - false - false - true - false - true - - - - - embeddedsw.dts.group - ignore - - - embeddedsw.dts.name - debug - - - embeddedsw.dts.vendor - altr - - - java.lang.String - CYCLONEIVE - false - true - false - true - DEVICE_FAMILY - - - boolean - true - false - true - true - true - - - java.lang.String - YES - true - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - DBG2 - false - true - true - true - - - int - 24 - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - 0 - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - NO - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - probe - Input - 24 - probe - - - - - 1 - altera_in_system_sources_probes - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - - 18.1 - - - 1 - conduit_end - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit - 18.1 - - 18.1 625 - 08626627EDAB00000178898093A8 - diff --git a/FPGA_61.440/db/ip/DEBUG2/DEBUG2.qip b/FPGA_61.440/db/ip/DEBUG2/DEBUG2.qip deleted file mode 100644 index 4c6a26a..0000000 --- a/FPGA_61.440/db/ip/DEBUG2/DEBUG2.qip +++ /dev/null @@ -1,41 +0,0 @@ -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_TOOL_NAME "Qsys" -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_TOOL_ENV "Qsys" -set_global_assignment -library "DEBUG2" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../../DEBUG2.sopcinfo"] -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name SLD_INFO "QSYS_NAME DEBUG2 HAS_SOPCINFO 1 GENERATION_ID 1617214606" -set_global_assignment -library "DEBUG2" -name SLD_FILE [file join $::quartus(qip_path) "DEBUG2.debuginfo"] -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E" -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_QSYS_MODE "STANDALONE" -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -library "DEBUG2" -name MISC_FILE [file join $::quartus(qip_path) "../../../DEBUG2.qsys"] -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_NAME "REVCVUcy" -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_DISPLAY_NAME "REVCVUcy" -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_REPORT_HIERARCHY "On" -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_VERSION "MS4w" -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYxNzIxNDYwNg==::QXV0byBHRU5FUkFUSU9OX0lE" -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMEUyMkM4::QXV0byBERVZJQ0U=" -set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_NAME "YWx0c291cmNlX3Byb2JlX3RvcA==" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIEluLVN5c3RlbSBTb3VyY2VzICYgUHJvYmVz" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_DESCRIPTION "SW4tc3lzdGVtIHNvdXJjZXMgJiBwcm9iZXMgZGVidWdnaW5nIG1lZ2FmdW5jdGlvbi4gIFRoZSBJbi1TeXN0ZW0gU291cmNlcyBhbmQgUHJvYmVzIG1lZ2FmdW5jdGlvbiBpcwphdmFpbGFibGUgZm9yIGFsbCBBbHRlcmEgZGV2aWNlIGZhbWlsaWVzIHN1cHBvcnRlZCBieSB0aGUgUXVhcnR1cyBQcmltZSBzb2Z0d2FyZS4=" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlX2ZhbWlseQ==" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hdXRvX2luZGV4::dHJ1ZQ==::QXV0b21hdGljIEluc3RhbmNlIEluZGV4IEFzc2lnbm1lbnQ=" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "c2xkX2F1dG9faW5zdGFuY2VfaW5kZXg=::WUVT::c2xkX2F1dG9faW5zdGFuY2VfaW5kZXg=" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "aW5zdGFuY2VfaWQ=::REJHMg==::VGhlICdJbnN0YW5jZSBJRCcgb2YgdGhpcyBpbnN0YW5jZSAob3B0aW9uYWwp" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "cHJvYmVfd2lkdGg=::MjQ=::UHJvYmUgUG9ydCBXaWR0aCBbMC4uNTEyXQ==" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "c291cmNlX3dpZHRo::MA==::U291cmNlIFBvcnQgV2lkdGggWzAuLjUxMl0=" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX21ldGFzdGFiaWxpdHk=::Tk8=::ZW5hYmxlX21ldGFzdGFiaWxpdHk=" - -set_global_assignment -library "DEBUG2" -name VERILOG_FILE [file join $::quartus(qip_path) "DEBUG2.v"] -set_global_assignment -library "DEBUG2" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altsource_probe_top.v"] - -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_TOOL_NAME "altera_in_system_sources_probes" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_TOOL_ENV "Qsys" diff --git a/FPGA_61.440/db/ip/DEBUG2/DEBUG2.v b/FPGA_61.440/db/ip/DEBUG2/DEBUG2.v deleted file mode 100644 index 4059e1b..0000000 --- a/FPGA_61.440/db/ip/DEBUG2/DEBUG2.v +++ /dev/null @@ -1,21 +0,0 @@ -// DEBUG2.v - -// Generated using ACDS version 18.1 625 - -`timescale 1 ps / 1 ps -module DEBUG2 ( - input wire [23:0] probe // probes.probe - ); - - altsource_probe_top #( - .sld_auto_instance_index ("YES"), - .sld_instance_index (0), - .instance_id ("DBG2"), - .probe_width (24), - .source_width (0), - .enable_metastability ("NO") - ) in_system_sources_probes_0 ( - .probe (probe) // probes.probe - ); - -endmodule diff --git a/FPGA_61.440/db/ip/DEBUG2/DEBUG2__report.html b/FPGA_61.440/db/ip/DEBUG2/DEBUG2__report.html deleted file mode 100644 index 95b1135..0000000 --- a/FPGA_61.440/db/ip/DEBUG2/DEBUG2__report.html +++ /dev/null @@ -1,177 +0,0 @@ - - - - - datasheet for DEBUG2 - - - - - - - - -
DEBUG2 -
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2021.03.31.22:16:47Datasheet
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Overview
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in_system_sources_probes_0

altera_in_system_sources_probes v18.1 -
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Parameters

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device_familyCYCLONEIVE
gui_use_auto_indextrue
sld_auto_instance_indexYES
sld_instance_index0
instance_idDBG2
probe_width24
source_width0
source_initial_value0
create_source_clockfalse
create_source_clock_enablefalse
enable_metastabilityNO
deviceFamilyUNKNOWN
generateLegacySimfalse
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Software Assignments

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generation took 0,01 secondsrendering took 0,03 seconds
- - diff --git a/FPGA_61.440/db/ip/DEBUG2/DEBUG2__report.xml b/FPGA_61.440/db/ip/DEBUG2/DEBUG2__report.xml deleted file mode 100644 index c13c415..0000000 --- a/FPGA_61.440/db/ip/DEBUG2/DEBUG2__report.xml +++ /dev/null @@ -1,123 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:DEBUG2 "DEBUG2" - - - - Transform: CustomInstructionTransform - No custom instruction connections, skipping transform - 1 modules, 0 connections]]> - Transform: MMTransform - Transform: InterruptMapperTransform - Transform: InterruptSyncTransform - Transform: InterruptFanoutTransform - Transform: AvalonStreamingTransform - Transform: ResetAdaptation - DEBUG2" reuses altera_in_system_sources_probes "submodules/altsource_probe_top"]]> - queue size: 0 starting:altera_in_system_sources_probes "submodules/altsource_probe_top" - DEBUG2" instantiated altera_in_system_sources_probes "in_system_sources_probes_0"]]> - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:altera_in_system_sources_probes "submodules/altsource_probe_top" - DEBUG2" instantiated altera_in_system_sources_probes "in_system_sources_probes_0"]]> - - - diff --git a/FPGA_61.440/db/ip/DEBUG2/submodules/altsource_probe_top.v b/FPGA_61.440/db/ip/DEBUG2/submodules/altsource_probe_top.v deleted file mode 100644 index 4011e56..0000000 --- a/FPGA_61.440/db/ip/DEBUG2/submodules/altsource_probe_top.v +++ /dev/null @@ -1,57 +0,0 @@ -// (C) 2001-2018 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -module altsource_probe_top -#( - parameter lpm_type = "altsource_probe", // required by the coding standard - parameter lpm_hint = "UNUSED", // required by the coding standard - - parameter sld_auto_instance_index = "YES", // Yes, if the instance index should be automatically assigned. - parameter sld_instance_index = 0, // unique identifier for the altsource_probe instance. - parameter sld_node_info_parameter = 4746752 + sld_instance_index, // The NODE ID to uniquely identify this node on the hub. Type ID: 9 Version: 0 Inst: 0 MFG ID 110 -- ***NOTE*** this parameter cannot be called SLD_NODE_INFO or Quartus Standard will think it's an ISSP impl. - parameter sld_ir_width = 4, - - parameter instance_id = "UNUSED", // optional name for the instance. - parameter probe_width = 1, // probe port width - parameter source_width= 1, // source port width - parameter source_initial_value = "0", // initial source port value - parameter enable_metastability = "NO" // yes to add two register -) -( - input [probe_width - 1 : 0] probe, // probe inputs - output [source_width - 1 : 0] source, // source outputs - input source_clk, // clock of the registers used to metastabilize the source output - input tri1 source_ena // enable of the registers used to metastabilize the source output -); - - altsource_probe #( - .lpm_type(lpm_type), - .lpm_hint(lpm_hint), - .sld_auto_instance_index(sld_auto_instance_index), - .sld_instance_index(sld_instance_index), - .SLD_NODE_INFO(sld_node_info_parameter), - .sld_ir_width(sld_ir_width), - .instance_id(instance_id), - .probe_width(probe_width), - .source_width(source_width), - .source_initial_value(source_initial_value), - .enable_metastability(enable_metastability) - )issp_impl - ( - .probe(probe), - .source(source), - .source_clk(source_clk), - .source_ena(source_ena) - ); - -endmodule \ No newline at end of file diff --git a/FPGA_61.440/db/ip/WOLF-LITE__master__.qip b/FPGA_61.440/db/ip/WOLF-LITE__master__.qip deleted file mode 100644 index 316ede9..0000000 --- a/FPGA_61.440/db/ip/WOLF-LITE__master__.qip +++ /dev/null @@ -1,7 +0,0 @@ -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) clock_buffer/clock_buffer.qip] -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) rx_cic/rx_cic.qip] -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) tx_cic/tx_cic.qip] -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) tx_nco/tx_nco.qip] -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) nco/nco.qip] -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) DEBUG/DEBUG.qip] -set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) DEBUG2/DEBUG2.qip] diff --git a/FPGA_61.440/db/ip/clock_buffer/clock_buffer.bsf b/FPGA_61.440/db/ip/clock_buffer/clock_buffer.bsf deleted file mode 100644 index 07b8201..0000000 --- a/FPGA_61.440/db/ip/clock_buffer/clock_buffer.bsf +++ /dev/null @@ -1,59 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 2018 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 272 104) - (text "clock_buffer" (rect 99 -1 149 11)(font "Arial" (font_size 10))) - (text "inst" (rect 8 88 20 100)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "inclk" (rect 0 0 16 12)(font "Arial" (font_size 8))) - (text "inclk" (rect 4 61 34 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 96 72)(line_width 1)) - ) - (port - (pt 272 72) - (output) - (text "outclk" (rect 0 0 22 12)(font "Arial" (font_size 8))) - (text "outclk" (rect 242 61 278 72)(font "Arial" (font_size 8))) - (line (pt 272 72)(pt 160 72)(line_width 1)) - ) - (drawing - (text "altclkctrl_input" (rect 13 43 122 99)(font "Arial" (color 128 0 0)(font_size 9))) - (text "inclk" (rect 101 67 232 144)(font "Arial" (color 0 0 0))) - (text "altclkctrl_output" (rect 161 43 424 99)(font "Arial" (color 128 0 0)(font_size 9))) - (text "outclk" (rect 132 67 300 144)(font "Arial" (color 0 0 0))) - (text " clock_buffer " (rect 214 88 512 186)(font "Arial" )) - (line (pt 96 32)(pt 160 32)(line_width 1)) - (line (pt 160 32)(pt 160 88)(line_width 1)) - (line (pt 96 88)(pt 160 88)(line_width 1)) - (line (pt 96 32)(pt 96 88)(line_width 1)) - (line (pt 97 52)(pt 97 76)(line_width 1)) - (line (pt 98 52)(pt 98 76)(line_width 1)) - (line (pt 159 52)(pt 159 76)(line_width 1)) - (line (pt 158 52)(pt 158 76)(line_width 1)) - (line (pt 0 0)(pt 272 0)(line_width 1)) - (line (pt 272 0)(pt 272 104)(line_width 1)) - (line (pt 0 104)(pt 272 104)(line_width 1)) - (line (pt 0 0)(pt 0 104)(line_width 1)) - ) -) diff --git a/FPGA_61.440/db/ip/clock_buffer/clock_buffer.debuginfo b/FPGA_61.440/db/ip/clock_buffer/clock_buffer.debuginfo deleted file mode 100644 index f153eff..0000000 --- a/FPGA_61.440/db/ip/clock_buffer/clock_buffer.debuginfo +++ /dev/null @@ -1,339 +0,0 @@ - - - - - - - com.altera.sopcmodel.ensemble.EClockAdapter - HANDSHAKE - false - true - true - true - - - java.lang.String - EP4CE10E22C8 - false - true - true - true - - - java.lang.String - CYCLONEIVE - false - true - true - true - - - java.lang.String - 8 - false - true - false - true - - - com.altera.sopcmodel.ensemble.Ensemble$EFabricMode - QSYS - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1617214510 - false - true - true - true - - - boolean - false - false - true - false - true - - - com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage - VERILOG - false - false - false - true - - - boolean - true - false - true - true - true - - - com.altera.sopcmodel.definition.BoundaryDefinition - - false - true - false - true - - - int - 1 - false - true - true - true - - - java.lang.String - - false - true - false - true - - - boolean - false - false - true - false - true - - - long - 0 - false - true - false - true - - - java.lang.String - - false - true - false - true - - - long - 0 - false - true - false - true - - - boolean - false - false - true - false - true - - - - - java.lang.String - CYCLONEIVE - false - true - false - true - DEVICE_FAMILY - - - int - 1 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 1 - false - false - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - ui.blockdiagram.direction - input - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - inclk - Input - 1 - inclk - - - - - - ui.blockdiagram.direction - output - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - outclk - Output - 1 - outclk - - - - - 1 - altclkctrl - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - ALTCLKCTRL Intel FPGA IP - 18.1 - - - 2 - conduit_end - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit - 18.1 - - 18.1 625 - 08626627EDAB00000178897F1C78 - diff --git a/FPGA_61.440/db/ip/clock_buffer/clock_buffer.qip b/FPGA_61.440/db/ip/clock_buffer/clock_buffer.qip deleted file mode 100644 index 39a38b6..0000000 --- a/FPGA_61.440/db/ip/clock_buffer/clock_buffer.qip +++ /dev/null @@ -1,38 +0,0 @@ -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_TOOL_NAME "Qsys" -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_TOOL_ENV "Qsys" -set_global_assignment -library "clock_buffer" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../../clock_buffer.sopcinfo"] -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name SLD_INFO "QSYS_NAME clock_buffer HAS_SOPCINFO 1 GENERATION_ID 1617214510" -set_global_assignment -library "clock_buffer" -name SLD_FILE [file join $::quartus(qip_path) "clock_buffer.debuginfo"] -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E" -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_QSYS_MODE "STANDALONE" -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -library "clock_buffer" -name MISC_FILE [file join $::quartus(qip_path) "../../../clock_buffer.qsys"] -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_NAME "Y2xvY2tfYnVmZmVy" -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_DISPLAY_NAME "Y2xvY2tfYnVmZmVy" -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_REPORT_HIERARCHY "On" -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_VERSION "MS4w" -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYxNzIxNDUxMA==::QXV0byBHRU5FUkFUSU9OX0lE" -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMEUyMkM4::QXV0byBERVZJQ0U=" -set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" -set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_NAME "Y2xvY2tfYnVmZmVyX2FsdGNsa2N0cmxfMA==" -set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_DISPLAY_NAME "QUxUQ0xLQ1RSTCBJbnRlbCBGUEdBIElQ" -set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" -set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBJViBF::RGV2aWNlIEZhbWlseQ==" -set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfVFlQRQ==::MQ==::SG93IGRvIHlvdSB3YW50IHRvIHVzZSB0aGUgQUxUQ0xLQ1RSTD8=" -set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NMT0NLUw==::MQ==::SG93IG1hbnkgY2xvY2sgaW5wdXRzIHdvdWxkIHlvdSBsaWtlPw==" -set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "R1VJX1VTRV9FTkE=::ZmFsc2U=::Q3JlYXRlICdlbmEnIHBvcnQgdG8gZW5hYmxlIG9yIGRpc2FibGUgdGhlIGNsb2NrIG5ldHdvcmsgZHJpdmVuIGJ5IHRoaXMgYnVmZmVyPw==" -set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "VVNFX0dMSVRDSF9GUkVFX1NXSVRDSF9PVkVSX0lNUExFTUVOVEFUSU9O::ZmFsc2U=::RW5zdXJlIGdsaXRjaC1mcmVlIHN3aXRjaG92ZXIgaW1wbGVtZW50YXRpb24=" - -set_global_assignment -library "clock_buffer" -name VERILOG_FILE [file join $::quartus(qip_path) "clock_buffer.v"] -set_global_assignment -library "clock_buffer" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/clock_buffer_altclkctrl_0.v"] - -set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_TOOL_NAME "altclkctrl" -set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_TOOL_ENV "Qsys" diff --git a/FPGA_61.440/db/ip/clock_buffer/clock_buffer.v b/FPGA_61.440/db/ip/clock_buffer/clock_buffer.v deleted file mode 100644 index 593f41c..0000000 --- a/FPGA_61.440/db/ip/clock_buffer/clock_buffer.v +++ /dev/null @@ -1,16 +0,0 @@ -// clock_buffer.v - -// Generated using ACDS version 18.1 625 - -`timescale 1 ps / 1 ps -module clock_buffer ( - input wire inclk, // altclkctrl_input.inclk - output wire outclk // altclkctrl_output.outclk - ); - - clock_buffer_altclkctrl_0 altclkctrl_0 ( - .inclk (inclk), // altclkctrl_input.inclk - .outclk (outclk) // altclkctrl_output.outclk - ); - -endmodule diff --git a/FPGA_61.440/db/ip/clock_buffer/clock_buffer__report.html b/FPGA_61.440/db/ip/clock_buffer/clock_buffer__report.html deleted file mode 100644 index 7961eb0..0000000 --- a/FPGA_61.440/db/ip/clock_buffer/clock_buffer__report.html +++ /dev/null @@ -1,157 +0,0 @@ - - - - - datasheet for clock_buffer - - - - - - - - -
clock_buffer -
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2021.03.31.22:15:11Datasheet
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altclkctrl_0

altclkctrl v18.1 -
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Parameters

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DEVICE_FAMILYCYCLONEIVE
CLOCK_TYPE1
NUMBER_OF_CLOCKS1
ENA_REGISTER_MODE1
GUI_USE_ENAfalse
USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATIONfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
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Software Assignments

(none)
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- - - - - -
generation took 0,01 secondsrendering took 0,05 seconds
- - diff --git a/FPGA_61.440/db/ip/clock_buffer/clock_buffer__report.xml b/FPGA_61.440/db/ip/clock_buffer/clock_buffer__report.xml deleted file mode 100644 index 2c3c7ca..0000000 --- a/FPGA_61.440/db/ip/clock_buffer/clock_buffer__report.xml +++ /dev/null @@ -1,129 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:clock_buffer "clock_buffer" - - - - Transform: CustomInstructionTransform - No custom instruction connections, skipping transform - 1 modules, 0 connections]]> - Transform: MMTransform - Transform: InterruptMapperTransform - Transform: InterruptSyncTransform - Transform: InterruptFanoutTransform - Transform: AvalonStreamingTransform - Transform: ResetAdaptation - clock_buffer" reuses altclkctrl "submodules/clock_buffer_altclkctrl_0"]]> - queue size: 0 starting:altclkctrl "submodules/clock_buffer_altclkctrl_0" - Generating top-level entity clock_buffer_altclkctrl_0. - Current quartus bindir: C:/intelfpga/18.1/quartus/bin64/. - clock_buffer" instantiated altclkctrl "altclkctrl_0"]]> - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:altclkctrl "submodules/clock_buffer_altclkctrl_0" - Generating top-level entity clock_buffer_altclkctrl_0. - Current quartus bindir: C:/intelfpga/18.1/quartus/bin64/. - clock_buffer" instantiated altclkctrl "altclkctrl_0"]]> - - - diff --git a/FPGA_61.440/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v b/FPGA_61.440/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v deleted file mode 100644 index 30c4f3b..0000000 --- a/FPGA_61.440/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v +++ /dev/null @@ -1,114 +0,0 @@ -//altclkctrl CBX_SINGLE_OUTPUT_FILE="ON" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Cyclone IV E" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk -//VERSION_BEGIN 18.1 cbx_altclkbuf 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ VERSION_END -// synthesis VERILOG_INPUT_VERSION VERILOG_2001 -// altera message_off 10463 - - - -// Copyright (C) 2018 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License -// Subscription Agreement, the Intel Quartus Prime License Agreement, -// the Intel FPGA IP License Agreement, or other applicable license -// agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by -// Intel and sold by Intel or its authorized distributors. Please -// refer to the applicable agreement for further details. - - - -//synthesis_resources = clkctrl 1 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module clock_buffer_altclkctrl_0_sub - ( - ena, - inclk, - outclk) /* synthesis synthesis_clearbox=1 */; - input ena; - input [3:0] inclk; - output outclk; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 ena; - tri0 [3:0] inclk; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire wire_clkctrl1_outclk; - wire [1:0] clkselect; - wire [1:0] clkselect_wire; - wire [3:0] inclk_wire; - - cycloneive_clkctrl clkctrl1 - ( - .clkselect(clkselect_wire), - .ena(ena), - .inclk(inclk_wire), - .outclk(wire_clkctrl1_outclk) - // synopsys translate_off - , - .devclrn(1'b1), - .devpor(1'b1) - // synopsys translate_on - ); - defparam - clkctrl1.clock_type = "Global Clock", - clkctrl1.ena_register_mode = "falling edge", - clkctrl1.lpm_type = "cycloneive_clkctrl"; - assign - clkselect = {2{1'b0}}, - clkselect_wire = {clkselect}, - inclk_wire = {inclk}, - outclk = wire_clkctrl1_outclk; -endmodule //clock_buffer_altclkctrl_0_sub -//VALID FILE // (C) 2001-2018 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module clock_buffer_altclkctrl_0 ( - inclk, - outclk); - - input inclk; - output outclk; - - wire sub_wire0; - wire outclk; - wire sub_wire1; - wire sub_wire2; - wire [3:0] sub_wire3; - wire [2:0] sub_wire4; - - assign outclk = sub_wire0; - assign sub_wire1 = 1'h1; - assign sub_wire2 = inclk; - assign sub_wire3[3:0] = {sub_wire4, sub_wire2}; - assign sub_wire4[2:0] = 3'h0; - - clock_buffer_altclkctrl_0_sub clock_buffer_altclkctrl_0_sub_component ( - .ena (sub_wire1), - .inclk (sub_wire3), - .outclk (sub_wire0)); - -endmodule \ No newline at end of file diff --git a/FPGA_61.440/db/ip/nco/nco.bsf b/FPGA_61.440/db/ip/nco/nco.bsf deleted file mode 100644 index 62902af..0000000 --- a/FPGA_61.440/db/ip/nco/nco.bsf +++ /dev/null @@ -1,105 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 2018 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 256 200) - (text "nco" (rect 118 -1 132 11)(font "Arial" (font_size 10))) - (text "inst" (rect 8 184 20 196)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "clk" (rect 0 0 10 12)(font "Arial" (font_size 8))) - (text "clk" (rect 4 61 22 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 80 72)(line_width 1)) - ) - (port - (pt 0 112) - (input) - (text "clken" (rect 0 0 20 12)(font "Arial" (font_size 8))) - (text "clken" (rect 4 101 34 112)(font "Arial" (font_size 8))) - (line (pt 0 112)(pt 80 112)(line_width 1)) - ) - (port - (pt 0 128) - (input) - (text "phi_inc_i[21..0]" (rect 0 0 57 12)(font "Arial" (font_size 8))) - (text "phi_inc_i[21..0]" (rect 4 117 100 128)(font "Arial" (font_size 8))) - (line (pt 0 128)(pt 80 128)(line_width 3)) - ) - (port - (pt 0 168) - (input) - (text "reset_n" (rect 0 0 30 12)(font "Arial" (font_size 8))) - (text "reset_n" (rect 4 157 46 168)(font "Arial" (font_size 8))) - (line (pt 0 168)(pt 80 168)(line_width 1)) - ) - (port - (pt 256 72) - (output) - (text "fsin_o[11..0]" (rect 0 0 47 12)(font "Arial" (font_size 8))) - (text "fsin_o[11..0]" (rect 196 61 274 72)(font "Arial" (font_size 8))) - (line (pt 256 72)(pt 176 72)(line_width 3)) - ) - (port - (pt 256 88) - (output) - (text "fcos_o[11..0]" (rect 0 0 50 12)(font "Arial" (font_size 8))) - (text "fcos_o[11..0]" (rect 192 77 270 88)(font "Arial" (font_size 8))) - (line (pt 256 88)(pt 176 88)(line_width 3)) - ) - (port - (pt 256 104) - (output) - (text "out_valid" (rect 0 0 35 12)(font "Arial" (font_size 8))) - (text "out_valid" (rect 210 93 264 104)(font "Arial" (font_size 8))) - (line (pt 256 104)(pt 176 104)(line_width 1)) - ) - (drawing - (text "clk" (rect 65 43 148 99)(font "Arial" (color 128 0 0)(font_size 9))) - (text "clk" (rect 85 67 188 144)(font "Arial" (color 0 0 0))) - (text "in" (rect 71 83 154 179)(font "Arial" (color 128 0 0)(font_size 9))) - (text "clken" (rect 85 107 200 224)(font "Arial" (color 0 0 0))) - (text "phi_inc_i" (rect 85 123 224 256)(font "Arial" (color 0 0 0))) - (text "out" (rect 177 43 372 99)(font "Arial" (color 128 0 0)(font_size 9))) - (text "fsin_o" (rect 146 67 328 144)(font "Arial" (color 0 0 0))) - (text "fcos_o" (rect 143 83 322 176)(font "Arial" (color 0 0 0))) - (text "out_valid" (rect 134 99 322 208)(font "Arial" (color 0 0 0))) - (text "rst" (rect 65 139 148 291)(font "Arial" (color 128 0 0)(font_size 9))) - (text "reset_n" (rect 85 163 212 336)(font "Arial" (color 0 0 0))) - (text " nco " (rect 238 184 506 378)(font "Arial" )) - (line (pt 80 32)(pt 176 32)(line_width 1)) - (line (pt 176 32)(pt 176 184)(line_width 1)) - (line (pt 80 184)(pt 176 184)(line_width 1)) - (line (pt 80 32)(pt 80 184)(line_width 1)) - (line (pt 81 52)(pt 81 76)(line_width 1)) - (line (pt 82 52)(pt 82 76)(line_width 1)) - (line (pt 81 92)(pt 81 132)(line_width 1)) - (line (pt 82 92)(pt 82 132)(line_width 1)) - (line (pt 175 52)(pt 175 108)(line_width 1)) - (line (pt 174 52)(pt 174 108)(line_width 1)) - (line (pt 81 148)(pt 81 172)(line_width 1)) - (line (pt 82 148)(pt 82 172)(line_width 1)) - (line (pt 0 0)(pt 256 0)(line_width 1)) - (line (pt 256 0)(pt 256 200)(line_width 1)) - (line (pt 0 200)(pt 256 200)(line_width 1)) - (line (pt 0 0)(pt 0 200)(line_width 1)) - ) -) diff --git a/FPGA_61.440/db/ip/nco/nco.debuginfo b/FPGA_61.440/db/ip/nco/nco.debuginfo deleted file mode 100644 index 745a9b1..0000000 --- a/FPGA_61.440/db/ip/nco/nco.debuginfo +++ /dev/null @@ -1,624 +0,0 @@ - - - - - - - com.altera.sopcmodel.ensemble.EClockAdapter - HANDSHAKE - false - true - true - true - - - java.lang.String - EP4CE10E22C8 - false - true - true - true - - - java.lang.String - CYCLONEIVE - false - true - true - true - - - java.lang.String - 8 - false - true - false - true - - - com.altera.sopcmodel.ensemble.Ensemble$EFabricMode - QSYS - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1617214577 - false - true - true - true - - - boolean - false - false - true - false - true - - - com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage - VERILOG - false - false - false - true - - - boolean - true - false - true - true - true - - - com.altera.sopcmodel.definition.BoundaryDefinition - - false - true - false - true - - - int - 1 - false - true - true - true - - - java.lang.String - WOLF-LITE.qpf - false - true - false - true - - - boolean - false - false - true - false - true - - - long - 0 - false - true - false - true - - - java.lang.String - - false - true - false - true - - - long - 0 - false - true - false - true - - - boolean - false - false - true - false - true - - - - - java.lang.String - NATIVE - false - true - false - true - DESIGN_ENVIRONMENT - - - java.lang.String - trig - false - true - true - true - - - java.lang.String - dual_output - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - true - false - true - true - true - - - java.lang.String - CYCLONEIVE - false - true - true - true - DEVICE_FAMILY - - - int - 22 - false - true - true - true - - - int - 22 - false - true - true - true - - - int - 12 - false - true - true - true - - - java.lang.String - parallel - false - true - false - true - - - int - 1 - false - true - true - true - - - int - 1 - true - true - false - true - - - boolean - false - false - true - true - true - - - int - 10 - false - false - true - true - - - double - 61.44 - false - true - true - true - - - double - 7.1 - false - true - true - true - - - long - 484693 - true - true - true - true - - - double - 7.1 - true - true - true - true - - - boolean - false - false - true - true - true - - - int - 32 - false - false - true - true - - - int - 1 - false - false - true - true - - - boolean - false - false - true - true - true - - - int - 16 - false - false - true - true - - - int - 1 - false - false - true - true - - - boolean - false - true - true - false - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - rst - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - clken - Input - 1 - clken - - - phi_inc_i - Input - 22 - phi_inc_i - - - - - - ui.blockdiagram.direction - OUTPUT - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - rst - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - fsin_o - Output - 12 - fsin_o - - - fcos_o - Output - 12 - fcos_o - - - out_valid - Output - 1 - out_valid - - - - - 1 - altera_nco_ii - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - NCO - 18.1 - - - 1 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 18.1 - - - 1 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 18.1 - - - 2 - conduit_end - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit - 18.1 - - 18.1 625 - 08626627EDAB000001788980232B - diff --git a/FPGA_61.440/db/ip/nco/nco.qip b/FPGA_61.440/db/ip/nco/nco.qip deleted file mode 100644 index 5c1caaa..0000000 --- a/FPGA_61.440/db/ip/nco/nco.qip +++ /dev/null @@ -1,75 +0,0 @@ -set_global_assignment -entity "nco" -library "nco" -name IP_TOOL_NAME "Qsys" -set_global_assignment -entity "nco" -library "nco" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "nco" -library "nco" -name IP_TOOL_ENV "Qsys" -set_global_assignment -library "nco" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../../nco.sopcinfo"] -set_global_assignment -entity "nco" -library "nco" -name SLD_INFO "QSYS_NAME nco HAS_SOPCINFO 1 GENERATION_ID 1617214577" -set_global_assignment -library "nco" -name SLD_FILE [file join $::quartus(qip_path) "nco.debuginfo"] -set_global_assignment -entity "nco" -library "nco" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E" -set_global_assignment -entity "nco" -library "nco" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" -set_global_assignment -entity "nco" -library "nco" -name IP_QSYS_MODE "STANDALONE" -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -library "nco" -name MISC_FILE [file join $::quartus(qip_path) "../../../nco.qsys"] -set_global_assignment -entity "nco" -library "nco" -name IP_COMPONENT_NAME "bmNv" -set_global_assignment -entity "nco" -library "nco" -name IP_COMPONENT_DISPLAY_NAME "bmNv" -set_global_assignment -entity "nco" -library "nco" -name IP_COMPONENT_REPORT_HIERARCHY "On" -set_global_assignment -entity "nco" -library "nco" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "nco" -library "nco" -name IP_COMPONENT_VERSION "MS4w" -set_global_assignment -entity "nco" -library "nco" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYxNzIxNDU3Nw==::QXV0byBHRU5FUkFUSU9OX0lE" -set_global_assignment -entity "nco" -library "nco" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" -set_global_assignment -entity "nco" -library "nco" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMEUyMkM4::QXV0byBERVZJQ0U=" -set_global_assignment -entity "nco" -library "nco" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" -set_global_assignment -entity "nco" -library "nco" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF" -set_global_assignment -entity "nco" -library "nco" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4=" -set_global_assignment -entity "nco" -library "nco" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4=" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_NAME "bmNvX25jb19paV8w" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_DISPLAY_NAME "TkNP" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIE51bWVyaWNhbGx5IENvbnRyb2xsZWQgT3NjaWxsYXRvcg==" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "ZGVzaWduX2Vudg==::TkFUSVZF::ZGVzaWduX2Vudg==" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "YXJjaA==::dHJpZw==::R2VuZXJhdGlvbiBBbGdvcml0aG0=" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "d2FudF9zaW5fYW5kX2Nvcw==::ZHVhbF9vdXRwdXQ=::T3V0cHV0cw==" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "bnVtY2g=::MQ==::TnVtYmVyIG9mIENoYW5uZWxz" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "bnVtYmE=::MQ==::TnVtYmVyIG9mIEJhbmRz" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "dXNlX2RlZGljYXRlZF9tdWx0aXBsaWVycw==::dHJ1ZQ==::VXNlIGRlZGljYXRlZCBtdWx0aXBsaWVycw==" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBJViBF::RGV2aWNlIEZhbWlseQ==" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "YXBy::MjI=::UGhhc2UgQWNjdW11bGF0b3IgUHJlY2lzaW9u" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "YXByaQ==::MjI=::QW5ndWxhciBSZXNvbHV0aW9u" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "bXBy::MTI=::TWFnbml0dWRlIFJlc29sdXRpb24=" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "Y29yZGljX2FyY2g=::cGFyYWxsZWw=::Q09SRElDIEFyY2hpdGVjdHVyZQ==" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "dHJpZ19jeWNsZXNfcGVyX291dHB1dA==::MQ==::Q2xvY2sgY3ljbGVzIHBlciBvdXRwdXQ=" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "Y3ljbGVzX3Blcl9vdXRwdXQ=::MQ==::Q2xvY2sgY3ljbGVzIHBlciBvdXRwdXQ=" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "d2FudF9kaXRoZXI=::ZmFsc2U=::SW1wbGVtZW50IFBoYXNlIERpdGhlcmluZw==" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "ZnNhbXA=::NjEuNDQ=::Q2xvY2sgUmF0ZQ==" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "ZnJlcV9vdXQ=::Ny4x::RGVzaXJlZCBPdXRwdXQgRnJlcXVlbmN5" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "cGhpX2luYw==::NDg0Njkz::UGhhc2UgSW5jcmVtZW50IFZhbHVl" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "cmVhbF9mcmVxX291dA==::Ny4x::UmVhbCBPdXRwdXQgRnJlcXVlbmN5" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "d2FudF9mcmVxX21vZA==::ZmFsc2U=::RnJlcXVlbmN5IE1vZHVsYXRpb24gSW5wdXQ=" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "d2FudF9waGFzZV9tb2Q=::ZmFsc2U=::UGhhc2UgTW9kdWxhdGlvbiBJbnB1dA==" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "aHlwZXJfb3B0::ZmFsc2U=::aHlwZXJfb3B0" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_COMPONENT_PARAMETER "aHlwZXJfb3B0X3NlbGVjdA==::ZmFsc2U=::T3B0aW1pemUgZm9yIFN0cmF0aXggMTA=" - -set_global_assignment -library "nco" -name VERILOG_FILE [file join $::quartus(qip_path) "nco.v"] -set_global_assignment -library "nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_nco_madx_cen.v"] -set_global_assignment -library "nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_nco_mady_cen.v"] -set_global_assignment -library "nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_nco_isdr.v"] -set_global_assignment -library "nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_nco_mob_w.v"] -set_global_assignment -library "nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_nco_as_m_dp_cen.v"] -set_global_assignment -library "nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_nco_as_m_cen.v"] -set_global_assignment -library "nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_altqmcpipe.v"] -set_global_assignment -library "nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_gam_dp.v"] -set_global_assignment -library "nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_nco_derot.v"] -set_global_assignment -library "nco" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nco_nco_ii_0_sin_c.hex"] -set_global_assignment -library "nco" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nco_nco_ii_0_cos_c.hex"] -set_global_assignment -library "nco" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nco_nco_ii_0_sin_f.hex"] -set_global_assignment -library "nco" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nco_nco_ii_0_cos_f.hex"] -set_global_assignment -library "nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nco_nco_ii_0.v"] -set_global_assignment -library "nco" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/asj_altq.ocp"] -set_global_assignment -library "nco" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/asj_altqmcash.ocp"] -set_global_assignment -library "nco" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/asj_altqmcpipe.ocp"] - -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_TOOL_NAME "altera_nco_ii" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "nco_nco_ii_0" -library "nco" -name IP_TOOL_ENV "Qsys" diff --git a/FPGA_61.440/db/ip/nco/nco.v b/FPGA_61.440/db/ip/nco/nco.v deleted file mode 100644 index e93ab48..0000000 --- a/FPGA_61.440/db/ip/nco/nco.v +++ /dev/null @@ -1,26 +0,0 @@ -// nco.v - -// Generated using ACDS version 18.1 625 - -`timescale 1 ps / 1 ps -module nco ( - input wire clk, // clk.clk - input wire clken, // in.clken - input wire [21:0] phi_inc_i, // .phi_inc_i - output wire [11:0] fsin_o, // out.fsin_o - output wire [11:0] fcos_o, // .fcos_o - output wire out_valid, // .out_valid - input wire reset_n // rst.reset_n - ); - - nco_nco_ii_0 nco_ii_0 ( - .clk (clk), // clk.clk - .reset_n (reset_n), // rst.reset_n - .clken (clken), // in.clken - .phi_inc_i (phi_inc_i), // .phi_inc_i - .fsin_o (fsin_o), // out.fsin_o - .fcos_o (fcos_o), // .fcos_o - .out_valid (out_valid) // .out_valid - ); - -endmodule diff --git a/FPGA_61.440/db/ip/nco/nco__report.html b/FPGA_61.440/db/ip/nco/nco__report.html deleted file mode 100644 index 6e20e25..0000000 --- a/FPGA_61.440/db/ip/nco/nco__report.html +++ /dev/null @@ -1,241 +0,0 @@ - - - - - datasheet for nco - - - - - - - - -
nco -
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2021.03.31.22:16:18Datasheet
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Overview
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Memory Map
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nco_ii_0

altera_nco_ii v18.1 -
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Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
design_envNATIVE
archtrig
want_sin_and_cosdual_output
numch1
numba1
use_dedicated_multiplierstrue
selected_device_familyCYCLONEIVE
apr22
apri22
mpr12
cordic_archparallel
trig_cycles_per_output1
cycles_per_output1
want_ditherfalse
dpri10
fsamp61.44
freq_out7.1
phi_inc484693
real_freq_out7.1
want_freq_modfalse
aprf32
fmod_pipe1
want_phase_modfalse
aprp16
pmod_pipe1
hyper_optfalse
hyper_opt_selectfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
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Software Assignments

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generation took 0,01 secondsrendering took 0,03 seconds
- - diff --git a/FPGA_61.440/db/ip/nco/nco__report.xml b/FPGA_61.440/db/ip/nco/nco__report.xml deleted file mode 100644 index 95fe4ad..0000000 --- a/FPGA_61.440/db/ip/nco/nco__report.xml +++ /dev/null @@ -1,313 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:nco "nco" - - - - Transform: CustomInstructionTransform - No custom instruction connections, skipping transform - 1 modules, 0 connections]]> - Transform: MMTransform - Transform: InterruptMapperTransform - Transform: InterruptSyncTransform - Transform: InterruptFanoutTransform - Transform: AvalonStreamingTransform - Transform: ResetAdaptation - nco" reuses altera_nco_ii "submodules/nco_nco_ii_0"]]> - queue size: 0 starting:altera_nco_ii "submodules/nco_nco_ii_0" - nco" instantiated altera_nco_ii "nco_ii_0"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:altera_nco_ii "submodules/nco_nco_ii_0" - nco" instantiated altera_nco_ii "nco_ii_0"]]> - - - diff --git a/FPGA_61.440/db/ip/nco/submodules/asj_altq.ocp b/FPGA_61.440/db/ip/nco/submodules/asj_altq.ocp deleted file mode 100644 index 1bd2b88..0000000 Binary files a/FPGA_61.440/db/ip/nco/submodules/asj_altq.ocp and /dev/null differ diff --git a/FPGA_61.440/db/ip/nco/submodules/asj_altqmcash.ocp b/FPGA_61.440/db/ip/nco/submodules/asj_altqmcash.ocp deleted file mode 100644 index ccc465c..0000000 Binary files a/FPGA_61.440/db/ip/nco/submodules/asj_altqmcash.ocp and /dev/null differ diff --git a/FPGA_61.440/db/ip/nco/submodules/asj_altqmcpipe.ocp b/FPGA_61.440/db/ip/nco/submodules/asj_altqmcpipe.ocp deleted file mode 100644 index 9cae72b..0000000 Binary files a/FPGA_61.440/db/ip/nco/submodules/asj_altqmcpipe.ocp and /dev/null differ diff --git a/FPGA_61.440/db/ip/nco/submodules/asj_altqmcpipe.v b/FPGA_61.440/db/ip/nco/submodules/asj_altqmcpipe.v deleted file mode 100644 index 36513b7..0000000 Binary files a/FPGA_61.440/db/ip/nco/submodules/asj_altqmcpipe.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/nco/submodules/asj_gam_dp.v b/FPGA_61.440/db/ip/nco/submodules/asj_gam_dp.v deleted file mode 100644 index 9664a86..0000000 Binary files a/FPGA_61.440/db/ip/nco/submodules/asj_gam_dp.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/nco/submodules/asj_nco_as_m_cen.v b/FPGA_61.440/db/ip/nco/submodules/asj_nco_as_m_cen.v deleted file mode 100644 index 9a264e0..0000000 Binary files a/FPGA_61.440/db/ip/nco/submodules/asj_nco_as_m_cen.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v b/FPGA_61.440/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v deleted file mode 100644 index 7c3b46c..0000000 Binary files a/FPGA_61.440/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/nco/submodules/asj_nco_derot.v b/FPGA_61.440/db/ip/nco/submodules/asj_nco_derot.v deleted file mode 100644 index cf2428b..0000000 Binary files a/FPGA_61.440/db/ip/nco/submodules/asj_nco_derot.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/nco/submodules/asj_nco_isdr.v b/FPGA_61.440/db/ip/nco/submodules/asj_nco_isdr.v deleted file mode 100644 index 0017f76..0000000 Binary files a/FPGA_61.440/db/ip/nco/submodules/asj_nco_isdr.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/nco/submodules/asj_nco_madx_cen.v b/FPGA_61.440/db/ip/nco/submodules/asj_nco_madx_cen.v deleted file mode 100644 index 2590a31..0000000 Binary files a/FPGA_61.440/db/ip/nco/submodules/asj_nco_madx_cen.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/nco/submodules/asj_nco_mady_cen.v b/FPGA_61.440/db/ip/nco/submodules/asj_nco_mady_cen.v deleted file mode 100644 index 20fdefe..0000000 Binary files a/FPGA_61.440/db/ip/nco/submodules/asj_nco_mady_cen.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/nco/submodules/asj_nco_mob_w.v b/FPGA_61.440/db/ip/nco/submodules/asj_nco_mob_w.v deleted file mode 100644 index 39e5e62..0000000 Binary files a/FPGA_61.440/db/ip/nco/submodules/asj_nco_mob_w.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/nco/submodules/nco_nco_ii_0.v b/FPGA_61.440/db/ip/nco/submodules/nco_nco_ii_0.v deleted file mode 100644 index baa21df..0000000 --- a/FPGA_61.440/db/ip/nco/submodules/nco_nco_ii_0.v +++ /dev/null @@ -1,435 +0,0 @@ -// Copyright (C) 1988-2012 Altera Corporation - -// Any megafunction design, and related net list (encrypted or decrypted), -// support information, device programming or simulation file, and any other -// associated documentation or information provided by Altera or a partner -// under Altera's Megafunction Partnership Program may be used only to -// program PLD devices (but not masked PLD devices) from Altera. Any other -// use of such megafunction design, net list, support information, device -// programming or simulation file, or any other related documentation or -// information is prohibited for any other purpose, including, but not -// limited to modification, reverse engineering, de-compiling, or use with -// any other silicon devices, unless such use is explicitly licensed under -// a separate agreement with Altera or a megafunction partner. Title to -// the intellectual property, including patents, copyrights, trademarks, -// trade secrets, or maskworks, embodied in any such megafunction design, -// net list, support information, device programming or simulation file, or -// any other related documentation or information provided by Altera or a -// megafunction partner, remains with Altera, the megafunction partner, or -// their respective licensors. No other licenses, including any licenses -// needed under any third party's intellectual property, are provided herein. - - -module nco_nco_ii_0(clk, reset_n, clken, phi_inc_i, fsin_o, fcos_o, out_valid); - -parameter mpr = 12; -parameter opr = 24; -parameter apr = 22; -parameter apri= 22; -parameter aprf= 32; -parameter aprp= 16; -parameter aprid=27; -parameter dpri= 10; -parameter rdw = 12; -parameter rawc = 11; -parameter rnwc = 2048; -parameter rawf = 11; -parameter rnwf = 2048; -parameter Pn = 1048576; -parameter mxnbc = 24576; -parameter mxnbf = 24576; -parameter rsfc = "nco_nco_ii_0_sin_c.hex"; -parameter rsff = "nco_nco_ii_0_sin_f.hex"; -parameter rcfc = "nco_nco_ii_0_cos_c.hex"; -parameter rcff = "nco_nco_ii_0_cos_f.hex"; -parameter nc = 1; -parameter log2nc =0; -parameter outselinit = 0; -parameter paci0= 0; -parameter paci1= 0; -parameter paci2= 0; -parameter paci3= 0; -parameter paci4= 0; -parameter paci5= 0; -parameter paci6= 0; -parameter paci7= 0; -//parameter numba = 1; -//parameter log2numba = 0; - -input clk; -input reset_n; -input clken; -input [apr-1:0] phi_inc_i; - -output [mpr-1:0] fsin_o; -output [mpr-1:0] fcos_o; -output out_valid; -wire reset; -assign reset = !reset_n; - -wire [apr-1:0] phi_inc_i_w; -wire [apr-1:0] phi_acc_w; -wire [mpr-1:0] rfx_s; -wire [mpr-1:0] rcx_s; -wire [mpr-1:0] rfx_c; -wire [mpr-1:0] rcx_c; -wire [mpr-1:0] rfy_s; -wire [mpr-1:0] rcy_s; -wire [mpr-1:0] rfy_c; -wire [mpr-1:0] rcy_c; -wire [rawc-1:0] raxxx001ms; -wire [rawc-1:0] raxxx001mc; -wire [rawc-1:0] raxxx000m; -wire [rawf-1:0] raxxx000l; -wire [rawc-1:0] raxxx001m; -wire [rawf-1:0] raxxx001l; -wire [opr-1:0] result_i; -wire [opr-1:0] result_r; -wire [mpr-1:0] fsin_o_w; -wire [mpr-1:0] fcos_o_w; -wire out_valid_w; - -//Pipelining for Hyper Retimer starts from here -parameter hyper_pipeline = 0; -integer i; - -reg [1-1:0] reset_reg [3-1:0]; -wire [1-1:0] reset_pipelined; -reg [1-1:0] clken_reg [3-1:0]; -wire [1-1:0] clken_pipelined; -reg [apr-1:0] phi_inc_i_reg [3-1:0]; -wire [apr-1:0] phi_inc_i_pipelined; -reg [1-1:0] out_valid_w_reg [2-1:0]; -wire [1-1:0] out_valid_w_pipelined; -reg [mpr-1:0] fsin_o_w_reg [2-1:0]; -wire [mpr-1:0] fsin_o_w_pipelined; -reg [opr-1:0] result_i_reg [1-1:0]; -wire [opr-1:0] result_i_pipelined; -reg [mpr-1:0] fcos_o_w_reg [2-1:0]; -wire [mpr-1:0] fcos_o_w_pipelined; -reg [opr-1:0] result_r_reg [1-1:0]; -wire [opr-1:0] result_r_pipelined; -reg [mpr-1:0] rcx_c_reg [2-1:0]; -wire [mpr-1:0] rcx_c_pipelined; -reg [mpr-1:0] rfx_c_reg [2-1:0]; -wire [mpr-1:0] rfx_c_pipelined; -reg [mpr-1:0] rcx_s_reg [2-1:0]; -wire [mpr-1:0] rcx_s_pipelined; -reg [mpr-1:0] rfx_s_reg [2-1:0]; -wire [mpr-1:0] rfx_s_pipelined; -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - reset_reg[0] <= reset; - for (i = 1; i < 3; i=i+1) begin - reset_reg[i] <= reset_reg[i-1]; - end - end - assign reset_pipelined = reset_reg[3-1]; - end - else begin - assign reset_pipelined = reset; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - clken_reg[0] <= clken; - for (i = 1; i < 3; i=i+1) begin - clken_reg[i] <= clken_reg[i-1]; - end - end - assign clken_pipelined = clken_reg[3-1]; - end - else begin - assign clken_pipelined = clken; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - phi_inc_i_reg[0] <= phi_inc_i; - for (i = 1; i < 3; i=i+1) begin - phi_inc_i_reg[i] <= phi_inc_i_reg[i-1]; - end - end - assign phi_inc_i_pipelined = phi_inc_i_reg[3-1]; - end - else begin - assign phi_inc_i_pipelined = phi_inc_i; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - out_valid_w_reg[0] <= out_valid_w; - for (i = 1; i < 2; i=i+1) begin - out_valid_w_reg[i] <= out_valid_w_reg[i-1]; - end - end - assign out_valid_w_pipelined = out_valid_w_reg[2-1]; - end - else begin - assign out_valid_w_pipelined = out_valid_w; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - fsin_o_w_reg[0] <= fsin_o_w; - for (i = 1; i < 2; i=i+1) begin - fsin_o_w_reg[i] <= fsin_o_w_reg[i-1]; - end - end - assign fsin_o_w_pipelined = fsin_o_w_reg[2-1]; - end - else begin - assign fsin_o_w_pipelined = fsin_o_w; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - result_i_reg[0] <= result_i; - end - assign result_i_pipelined = result_i_reg[1-1]; - end - else begin - assign result_i_pipelined = result_i; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - fcos_o_w_reg[0] <= fcos_o_w; - for (i = 1; i < 2; i=i+1) begin - fcos_o_w_reg[i] <= fcos_o_w_reg[i-1]; - end - end - assign fcos_o_w_pipelined = fcos_o_w_reg[2-1]; - end - else begin - assign fcos_o_w_pipelined = fcos_o_w; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - result_r_reg[0] <= result_r; - end - assign result_r_pipelined = result_r_reg[1-1]; - end - else begin - assign result_r_pipelined = result_r; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - rcx_c_reg[0] <= rcx_c; - for (i = 1; i < 2; i=i+1) begin - rcx_c_reg[i] <= rcx_c_reg[i-1]; - end - end - assign rcx_c_pipelined = rcx_c_reg[2-1]; - end - else begin - assign rcx_c_pipelined = rcx_c; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - rfx_c_reg[0] <= rfx_c; - for (i = 1; i < 2; i=i+1) begin - rfx_c_reg[i] <= rfx_c_reg[i-1]; - end - end - assign rfx_c_pipelined = rfx_c_reg[2-1]; - end - else begin - assign rfx_c_pipelined = rfx_c; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - rcx_s_reg[0] <= rcx_s; - for (i = 1; i < 2; i=i+1) begin - rcx_s_reg[i] <= rcx_s_reg[i-1]; - end - end - assign rcx_s_pipelined = rcx_s_reg[2-1]; - end - else begin - assign rcx_s_pipelined = rcx_s; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - rfx_s_reg[0] <= rfx_s; - for (i = 1; i < 2; i=i+1) begin - rfx_s_reg[i] <= rfx_s_reg[i-1]; - end - end - assign rfx_s_pipelined = rfx_s_reg[2-1]; - end - else begin - assign rfx_s_pipelined = rfx_s; // pipeline for this signal is disabled - end -endgenerate - - -assign phi_inc_i_w = phi_inc_i_pipelined; - - -asj_altqmcpipe ux000 (.clk(clk), - .reset(reset_pipelined), - .clken(clken_pipelined), - .phi_inc_int(phi_inc_i_w), - .phi_acc_reg(phi_acc_w) - ); - -defparam ux000.nc = nc ; -defparam ux000.apr = apr ; -defparam ux000.lat = 1 ; -defparam ux000.paci0 = paci0 ; -defparam ux000.paci1 = paci1 ; -defparam ux000.paci2 = paci2 ; -defparam ux000.paci3 = paci3 ; -defparam ux000.paci4 = paci4 ; -defparam ux000.paci5 = paci5 ; -defparam ux000.paci6 = paci6 ; -defparam ux000.paci7 = paci7 ; - - -asj_gam_dp ux008( .clk(clk), - .reset(reset_pipelined), - .clken(clken_pipelined), - .phi_acc_w(phi_acc_w[apr-1:apr-rawc-rawf]), - .rom_add_cs(raxxx001ms), - .rom_add_cc(raxxx001mc), - .rom_add_f(raxxx001l) - ); -defparam ux008.rawc = rawc; -defparam ux008.rawf = rawf; -defparam ux008.apr = apri; - - -asj_nco_as_m_dp_cen ux0220(.clk(clk), - .clken (clken_pipelined), - .raxx_a(raxxx001ms[rawc-1:0]), - .raxx_b(raxxx001mc[rawc-1:0]), - .q_a(rcx_s[mpr-1:0]), - .q_b(rcx_c[mpr-1:0]) - ); -defparam ux0220.mpr = mpr; -defparam ux0220.rdw = rdw; -defparam ux0220.raw = rawc; -defparam ux0220.rnw = rnwc; -defparam ux0220.rf = rsfc; -defparam ux0220.dev = "Cyclone IV E"; - -asj_nco_as_m_cen ux0122(.clk(clk), - .clken (clken_pipelined), - .raxx(raxxx001l[rawf-1:0]), - .srw_int_res(rfx_s[mpr-1:0]) - ); -defparam ux0122.mpr = mpr; -defparam ux0122.rdw = rdw; -defparam ux0122.raw = rawf; -defparam ux0122.rnw = rnwf; -defparam ux0122.rf = rsff; -defparam ux0122.dev = "Cyclone IV E"; - -asj_nco_as_m_cen ux0123(.clk(clk), - .clken (clken_pipelined), - .raxx(raxxx001l[rawf-1:0]), - .srw_int_res(rfx_c[mpr-1:0]) - ); -defparam ux0123.mpr = mpr; -defparam ux0123.rdw = rdw; -defparam ux0123.raw = rawf; -defparam ux0123.rnw = rnwf; -defparam ux0123.rf = rcff; -defparam ux0123.dev = "Cyclone IV E"; - -asj_nco_madx_cen m1( - .dataa_0(rcy_c), - .dataa_1(rcy_s), - .datab_0(rfy_c), - .datab_1(rfy_s), - .result(result_r), - .clock0(clk), - .clken(clken_pipelined)); -defparam m1.mpr = mpr; -defparam m1.opr = opr; -// Writing multiplier for 'Cyclone IV E' - -asj_nco_mady_cen m0( - .dataa_0(rcy_s), - .dataa_1(rfy_s), - .datab_0(rfy_c), - .datab_1(rcy_c), - .result(result_i), - .clock0(clk), - .clken(clken_pipelined)); -defparam m0.mpr = mpr; -defparam m0.opr = opr; -// Writing multiplier for 'Cyclone IV E' - -asj_nco_derot ux0136(.crwx_rc(rcx_c_pipelined), - .crwx_rf(rfx_c_pipelined), - .srwx_rc(rcx_s_pipelined), - .srwx_rf(rfx_s_pipelined), - .crwy_rc(rcy_c), - .crwy_rf(rfy_c), - .srwy_rc(rcy_s), - .srwy_rf(rfy_s) - ); -defparam ux0136.mpr = mpr; -defparam ux0136.rxt = rdw; - -asj_nco_mob_w blk0( .clk(clk), - .reset(reset_pipelined), - .clken(clken_pipelined), - .data_in(result_i_pipelined), - .data_out(fsin_o_w)); - -defparam blk0.mpr = mpr; - -asj_nco_mob_w blk1( .clk(clk), - .reset(reset_pipelined), - .clken(clken_pipelined), - .data_in(result_r_pipelined), - .data_out(fcos_o_w)); - -defparam blk1.mpr = mpr; -assign fsin_o = fsin_o_w_pipelined; -assign fcos_o = fcos_o_w_pipelined; - -asj_nco_isdr ux710isdr(.clk(clk), - .reset(reset_pipelined), - .clken(clken_pipelined), - .data_ready(out_valid_w) - ); -defparam ux710isdr.ctc=8; -defparam ux710isdr.cpr=4; -assign out_valid = out_valid_w_pipelined; - - - -endmodule diff --git a/FPGA_61.440/db/ip/nco/submodules/nco_nco_ii_0_cos_c.hex b/FPGA_61.440/db/ip/nco/submodules/nco_nco_ii_0_cos_c.hex deleted file mode 100644 index 45a4a35..0000000 --- a/FPGA_61.440/db/ip/nco/submodules/nco_nco_ii_0_cos_c.hex +++ /dev/null @@ -1,2049 +0,0 @@ -:0200000007fff8 -:0200010007fff7 -:0200020007fff6 -:0200030007fff5 -:0200040007fff4 -:0200050007fff3 -:0200060007fff2 -:0200070007fff1 -:0200080007fef1 -:0200090007fef0 -:02000a0007feef -:02000b0007feee -:02000c0007feed -:02000d0007fded -:02000e0007fdec -:02000f0007fdeb -:0200100007fdea -:0200110007fcea -:0200120007fce9 -:0200130007fce8 -:0200140007fbe8 -:0200150007fbe7 -:0200160007fae7 -:0200170007fae6 -:0200180007f9e6 -:0200190007f9e5 -:02001a0007f8e5 -:02001b0007f8e4 -:02001c0007f7e4 -:02001d0007f7e3 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-:0207df00000612 -:0207e000000611 -:0207e100000610 -:0207e20000060f -:0207e30000060e -:0207e40000060d -:0207e50000060c -:0207e60000060b -:0207e70000060a -:0207e800000609 -:0207e900000608 -:0207ea00000607 -:0207eb00000606 -:0207ec00000605 -:0207ed00000604 -:0207ee00000603 -:0207ef00000602 -:0207f000000601 -:0207f100000600 -:0207f2000006ff -:0207f3000006fe -:0207f4000006fd -:0207f5000006fc -:0207f6000006fb -:0207f7000006fa -:0207f8000006f9 -:0207f9000006f8 -:0207fa000006f7 -:0207fb000006f6 -:0207fc000006f5 -:0207fd000006f4 -:0207fe000006f3 -:0207ff000006f2 -:00000001FF diff --git a/FPGA_61.440/db/ip/rx_cic/rx_cic.bsf b/FPGA_61.440/db/ip/rx_cic/rx_cic.bsf deleted file mode 100644 index 881511c..0000000 --- a/FPGA_61.440/db/ip/rx_cic/rx_cic.bsf +++ /dev/null @@ -1,140 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 2018 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 256 272) - (text "rx_cic" (rect 110 -1 134 11)(font "Arial" (font_size 10))) - (text "inst" (rect 8 256 20 268)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "in_error[1..0]" (rect 0 0 50 12)(font "Arial" (font_size 8))) - (text "in_error[1..0]" (rect 4 61 88 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 80 72)(line_width 3)) - ) - (port - (pt 0 88) - (input) - (text "in_valid" (rect 0 0 29 12)(font "Arial" (font_size 8))) - (text "in_valid" (rect 4 77 52 88)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 80 88)(line_width 1)) - ) - (port - (pt 0 120) - (input) - (text "in_data[22..0]" (rect 0 0 53 12)(font "Arial" (font_size 8))) - (text "in_data[22..0]" (rect 4 109 88 120)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 80 120)(line_width 3)) - ) - (port - (pt 256 120) - (input) - (text "out_ready" (rect 0 0 41 12)(font "Arial" (font_size 8))) - (text "out_ready" (rect 204 109 258 120)(font "Arial" (font_size 8))) - (line (pt 256 120)(pt 176 120)(line_width 1)) - ) - (port - (pt 0 160) - (input) - (text "clken" (rect 0 0 20 12)(font "Arial" (font_size 8))) - (text "clken" (rect 4 149 34 160)(font "Arial" (font_size 8))) - (line (pt 0 160)(pt 80 160)(line_width 1)) - ) - (port - (pt 0 200) - (input) - (text "clk" (rect 0 0 10 12)(font "Arial" (font_size 8))) - (text "clk" (rect 4 189 22 200)(font "Arial" (font_size 8))) - (line (pt 0 200)(pt 80 200)(line_width 1)) - ) - (port - (pt 0 240) - (input) - (text "reset_n" (rect 0 0 30 12)(font "Arial" (font_size 8))) - (text "reset_n" (rect 4 229 46 240)(font "Arial" (font_size 8))) - (line (pt 0 240)(pt 80 240)(line_width 1)) - ) - (port - (pt 0 104) - (output) - (text "in_ready" (rect 0 0 35 12)(font "Arial" (font_size 8))) - (text "in_ready" (rect 4 93 52 104)(font "Arial" (font_size 8))) - (line (pt 0 104)(pt 80 104)(line_width 1)) - ) - (port - (pt 256 72) - (output) - (text "out_data[31..0]" (rect 0 0 57 12)(font "Arial" (font_size 8))) - (text "out_data[31..0]" (rect 183 61 273 72)(font "Arial" (font_size 8))) - (line (pt 256 72)(pt 176 72)(line_width 3)) - ) - (port - (pt 256 88) - (output) - (text "out_error[1..0]" (rect 0 0 56 12)(font "Arial" (font_size 8))) - (text "out_error[1..0]" (rect 186 77 276 88)(font "Arial" (font_size 8))) - (line (pt 256 88)(pt 176 88)(line_width 3)) - ) - (port - (pt 256 104) - (output) - (text "out_valid" (rect 0 0 35 12)(font "Arial" (font_size 8))) - (text "out_valid" (rect 210 93 264 104)(font "Arial" (font_size 8))) - (line (pt 256 104)(pt 176 104)(line_width 1)) - ) - (drawing - (text "av_st_in" (rect 31 43 110 99)(font "Arial" (color 128 0 0)(font_size 9))) - (text "error" (rect 85 67 200 144)(font "Arial" (color 0 0 0))) - (text "valid" (rect 85 83 200 176)(font "Arial" (color 0 0 0))) - (text "ready" (rect 85 99 200 208)(font "Arial" (color 0 0 0))) - (text "in_data" (rect 85 115 212 240)(font "Arial" (color 0 0 0))) - (text "av_st_out" (rect 177 43 408 99)(font "Arial" (color 128 0 0)(font_size 9))) - (text "out_data" (rect 136 67 320 144)(font "Arial" (color 0 0 0))) - (text "error" (rect 151 83 332 176)(font "Arial" (color 0 0 0))) - (text "valid" (rect 153 99 336 208)(font "Arial" (color 0 0 0))) - (text "ready" (rect 148 115 326 240)(font "Arial" (color 0 0 0))) - (text "clken" (rect 51 131 132 275)(font "Arial" (color 128 0 0)(font_size 9))) - (text "clken" (rect 85 155 200 320)(font "Arial" (color 0 0 0))) - (text "clock" (rect 52 171 134 355)(font "Arial" (color 128 0 0)(font_size 9))) - (text "clk" (rect 85 195 188 400)(font "Arial" (color 0 0 0))) - (text "reset" (rect 51 211 132 435)(font "Arial" (color 128 0 0)(font_size 9))) - (text "reset_n" (rect 85 235 212 480)(font "Arial" (color 0 0 0))) - (text " rx_cic " (rect 226 256 500 522)(font "Arial" )) - (line (pt 80 32)(pt 176 32)(line_width 1)) - (line (pt 176 32)(pt 176 256)(line_width 1)) - (line (pt 80 256)(pt 176 256)(line_width 1)) - (line (pt 80 32)(pt 80 256)(line_width 1)) - (line (pt 81 52)(pt 81 124)(line_width 1)) - (line (pt 82 52)(pt 82 124)(line_width 1)) - (line (pt 175 52)(pt 175 124)(line_width 1)) - (line (pt 174 52)(pt 174 124)(line_width 1)) - (line (pt 81 140)(pt 81 164)(line_width 1)) - (line (pt 82 140)(pt 82 164)(line_width 1)) - (line (pt 81 180)(pt 81 204)(line_width 1)) - (line (pt 82 180)(pt 82 204)(line_width 1)) - (line (pt 81 220)(pt 81 244)(line_width 1)) - (line (pt 82 220)(pt 82 244)(line_width 1)) - (line (pt 0 0)(pt 256 0)(line_width 1)) - (line (pt 256 0)(pt 256 272)(line_width 1)) - (line (pt 0 272)(pt 256 272)(line_width 1)) - (line (pt 0 0)(pt 0 272)(line_width 1)) - ) -) diff --git a/FPGA_61.440/db/ip/rx_cic/rx_cic.debuginfo b/FPGA_61.440/db/ip/rx_cic/rx_cic.debuginfo deleted file mode 100644 index df6e441..0000000 --- a/FPGA_61.440/db/ip/rx_cic/rx_cic.debuginfo +++ /dev/null @@ -1,903 +0,0 @@ - - - - - - - com.altera.sopcmodel.ensemble.EClockAdapter - HANDSHAKE - false - true - true - true - - - java.lang.String - EP4CE10E22C8 - false - true - true - true - - - java.lang.String - CYCLONEIVE - false - true - true - true - - - java.lang.String - 8 - false - true - false - true - - - com.altera.sopcmodel.ensemble.Ensemble$EFabricMode - QSYS - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1617214524 - false - true - true - true - - - boolean - false - false - true - false - true - - - com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage - VERILOG - false - false - false - true - - - boolean - true - false - true - true - true - - - com.altera.sopcmodel.definition.BoundaryDefinition - - false - true - false - true - - - int - 1 - false - true - true - true - - - java.lang.String - WOLF-LITE.qpf - false - true - false - true - - - boolean - false - false - true - false - true - - - long - 0 - false - true - false - true - - - java.lang.String - - false - true - false - true - - - long - 0 - false - true - false - true - - - boolean - false - false - true - false - true - - - - - java.lang.String - NATIVE - false - true - false - true - DESIGN_ENVIRONMENT - - - java.lang.String - CYCLONEIVE - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - decimator - false - true - true - true - - - int - 6 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1280 - false - true - true - true - - - int - 8 - false - false - false - true - - - int - 21 - false - false - false - true - - - int - 1280 - true - true - false - true - - - int - 1280 - true - true - false - true - - - int - 1 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 23 - false - true - true - true - - - boolean - true - false - true - true - true - - - java.lang.String - TRUNCATE - false - true - true - true - - - int - 32 - false - true - true - true - - - int - 32 - true - false - false - true - - - boolean - false - true - false - false - true - - - java.lang.String - auto - true - true - true - true - - - java.lang.String - logic_element - false - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - auto - true - true - true - true - - - java.lang.String - logic_element - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - true - false - true - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 85 - true - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clock - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - clken - Input - 1 - clken - - - - - - java.lang.String - clock - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - in_error - Input - 2 - error - - - in_valid - Input - 1 - valid - - - in_ready - Output - 1 - ready - - - in_data - Input - 23 - in_data - - - - - - ui.blockdiagram.direction - OUTPUT - - - java.lang.String - clock - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_data - Output - 32 - out_data - - - out_error - Output - 2 - error - - - out_valid - Output - 1 - valid - - - out_ready - Input - 1 - ready - - - - - 1 - altera_cic_ii - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - CIC - 18.1 - - - 1 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 18.1 - - - 1 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 18.1 - - - 3 - conduit_end - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit - 18.1 - - 18.1 625 - 08626627EDAB00000178897F5422 - diff --git a/FPGA_61.440/db/ip/rx_cic/rx_cic.qip b/FPGA_61.440/db/ip/rx_cic/rx_cic.qip deleted file mode 100644 index 603001e..0000000 --- a/FPGA_61.440/db/ip/rx_cic/rx_cic.qip +++ /dev/null @@ -1,114 +0,0 @@ -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_TOOL_NAME "Qsys" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_TOOL_ENV "Qsys" -set_global_assignment -library "rx_cic" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../../rx_cic.sopcinfo"] -set_global_assignment -entity "rx_cic" -library "rx_cic" -name SLD_INFO "QSYS_NAME rx_cic HAS_SOPCINFO 1 GENERATION_ID 1617214524" -set_global_assignment -library "rx_cic" -name SLD_FILE [file join $::quartus(qip_path) "rx_cic.debuginfo"] -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_QSYS_MODE "STANDALONE" -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -library "rx_cic" -name MISC_FILE [file join $::quartus(qip_path) "../../../rx_cic.qsys"] -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_NAME "cnhfY2lj" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_DISPLAY_NAME "cnhfY2lj" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_REPORT_HIERARCHY "On" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_VERSION "MS4w" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYxNzIxNDUyNA==::QXV0byBHRU5FUkFUSU9OX0lE" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMEUyMkM4::QXV0byBERVZJQ0U=" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19DTE9DS19SQVRF::LTE=::QXV0byBDTE9DS19SQVRF" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19DTE9DS19ET01BSU4=::LTE=::QXV0byBDTE9DS19ET01BSU4=" -set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19SRVNFVF9ET01BSU4=::LTE=::QXV0byBSRVNFVF9ET01BSU4=" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_NAME "cnhfY2ljX2NpY19paV8w" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_DISPLAY_NAME "Q0lD" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIENhc2NhZGVkIEludGVncmF0b3IgQ29tYiBJSQ==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "ZGVzaWduX2Vudg==::TkFUSVZF::ZGVzaWduX2Vudg==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBJViBF::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "RklMVEVSX1RZUEU=::ZGVjaW1hdG9y::RmlsdGVyIHR5cGU=" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "U1RBR0VT::Ng==::TnVtYmVyIG9mIHN0YWdlcw==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "RF9ERUxBWQ==::MQ==::RGlmZmVyZW50aWFsIGRlbGF5" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "VlJDX0VO::MA==::RW5hYmxlIHZhcmlhYmxlIHJhdGUgY2hhbmdlIGZhY3Rvcg==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "UkNGX0ZJWA==::MTI4MA==::UmF0ZSBjaGFuZ2UgZmFjdG9y" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "UkNGX01JTg==::MTI4MA==::UkNGX01JTg==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "UkNGX01BWA==::MTI4MA==::UkNGX01BWA==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SU5URVJGQUNFUw==::MQ==::TnVtYmVyIG9mIGludGVyZmFjZXM=" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q0hfUEVSX0lOVA==::MQ==::TnVtYmVyIG9mIGNoYW5uZWxzIHBlciBpbnRlcmZhY2U=" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SU5fV0lEVEg=::MjM=::SW5wdXQgZGF0YSB3aWR0aA==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q0xLX0VOX1BPUlQ=::dHJ1ZQ==::VXNlIGNsb2NrIGVuYWJsZSBwb3J0" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Uk9VTkRfVFlQRQ==::VFJVTkNBVEU=::T3V0cHV0IFJvdW5kaW5nIE1ldGhvZA==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "UkVRX09VVF9XSURUSA==::MzI=::T3V0cHV0IGRhdGEgd2lkdGg=" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SU5UX01FTQ==::YXV0bw==::SW50ZWdyYXRvciBkYXRhIHN0b3JhZ2UgdHlwZQ==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "UkVRX0lOVF9NRU0=::bG9naWNfZWxlbWVudA==::SW50ZWdyYXRvciBkYXRhIHN0b3JhZ2UgdHlwZQ==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "RElGX1VTRV9NRU0=::ZmFsc2U=::TWFwIGRpZmZlcmVudGlhdG9yIGRhdGEgc3RvcmFnZSB0byBtZW1vcnk=" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "RElGX01FTQ==::YXV0bw==::RGlmZmVyZW50aWF0b3IgZGF0YSBzdG9yYWdlIHR5cGU=" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "UkVRX0RJRl9NRU0=::bG9naWNfZWxlbWVudA==::RGlmZmVyZW50aWF0b3IgZGF0YSBzdG9yYWdlIHR5cGU=" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "UkVRX1BJUEVMSU5F::MA==::UGlwZWxpbmUgc3RhZ2VzIHBlciBpbnRlZ3JhdG9y" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV8wX1dJRFRI::ODU=::Q19TVEFHRV8wX1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV8wX1dJRFRI::ODU=::SV9TVEFHRV8wX1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV8xX1dJRFRI::ODU=::Q19TVEFHRV8xX1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV8xX1dJRFRI::ODU=::SV9TVEFHRV8xX1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV8yX1dJRFRI::ODU=::Q19TVEFHRV8yX1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV8yX1dJRFRI::ODU=::SV9TVEFHRV8yX1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV8zX1dJRFRI::ODU=::Q19TVEFHRV8zX1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV8zX1dJRFRI::ODU=::SV9TVEFHRV8zX1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV80X1dJRFRI::ODU=::Q19TVEFHRV80X1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV80X1dJRFRI::ODU=::SV9TVEFHRV80X1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV81X1dJRFRI::ODU=::Q19TVEFHRV81X1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV81X1dJRFRI::ODU=::SV9TVEFHRV81X1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV82X1dJRFRI::ODU=::Q19TVEFHRV82X1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV82X1dJRFRI::ODU=::SV9TVEFHRV82X1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV83X1dJRFRI::ODU=::Q19TVEFHRV83X1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV83X1dJRFRI::ODU=::SV9TVEFHRV83X1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV84X1dJRFRI::ODU=::Q19TVEFHRV84X1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV84X1dJRFRI::ODU=::SV9TVEFHRV84X1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV85X1dJRFRI::ODU=::Q19TVEFHRV85X1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV85X1dJRFRI::ODU=::SV9TVEFHRV85X1dJRFRI" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV8xMF9XSURUSA==::ODU=::Q19TVEFHRV8xMF9XSURUSA==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV8xMF9XSURUSA==::ODU=::SV9TVEFHRV8xMF9XSURUSA==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV8xMV9XSURUSA==::ODU=::Q19TVEFHRV8xMV9XSURUSA==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV8xMV9XSURUSA==::ODU=::SV9TVEFHRV8xMV9XSURUSA==" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "TUFYX0lfU1RBR0VfV0lEVEg=::ODU=::TUFYX0lfU1RBR0VfV0lEVEg=" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "TUFYX0NfU1RBR0VfV0lEVEg=::ODU=::TUFYX0NfU1RBR0VfV0lEVEg=" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "aHlwZXJfb3B0X3NlbGVjdA==::MA==::T3B0aW1pemUgZm9yIFN0cmF0aXggMTA=" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "aHlwZXJfb3B0::MA==::aHlwZXJfb3B0" - -set_global_assignment -library "rx_cic" -name VERILOG_FILE [file join $::quartus(qip_path) "rx_cic.v"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_math_pkg.vhd"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_text_pkg.vhd"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_lib_pkg.vhd"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_avalon_streaming_small_fifo.vhd"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_avalon_streaming_controller.vhd"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_avalon_streaming_sink.vhd"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_avalon_streaming_source.vhd"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_delay.vhd"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_fastaddsub.vhd"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_fastadd.vhd"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_pipelined_adder.vhd"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_roundsat.vhd"] -set_global_assignment -library "rx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_dsp_cic_common_pkg.sv"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_cic_lib_pkg.vhd"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_differentiator.vhd"] -set_global_assignment -library "rx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_downsample.sv"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_integrator.vhd"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_upsample.vhd"] -set_global_assignment -library "rx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_channel_buffer.vhd"] -set_global_assignment -library "rx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_variable_downsample.sv"] -set_global_assignment -library "rx_cic" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/hyper_pipeline_interface.v"] -set_global_assignment -library "rx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/counter_module.sv"] -set_global_assignment -library "rx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_cic_int_siso.sv"] -set_global_assignment -library "rx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_cic_dec_siso.sv"] -set_global_assignment -library "rx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_cic_int_simo.sv"] -set_global_assignment -library "rx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_cic_dec_miso.sv"] -set_global_assignment -library "rx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_cic_core.sv"] -set_global_assignment -library "rx_cic" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/alt_cic_core.ocp"] -set_global_assignment -library "rx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/rx_cic_cic_ii_0.sv"] - -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_TOOL_NAME "altera_cic_ii" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_TOOL_ENV "Qsys" diff --git a/FPGA_61.440/db/ip/rx_cic/rx_cic.v b/FPGA_61.440/db/ip/rx_cic/rx_cic.v deleted file mode 100644 index 0751cff..0000000 --- a/FPGA_61.440/db/ip/rx_cic/rx_cic.v +++ /dev/null @@ -1,34 +0,0 @@ -// rx_cic.v - -// Generated using ACDS version 18.1 625 - -`timescale 1 ps / 1 ps -module rx_cic ( - input wire [1:0] in_error, // av_st_in.error - input wire in_valid, // .valid - output wire in_ready, // .ready - input wire [22:0] in_data, // .in_data - output wire [31:0] out_data, // av_st_out.out_data - output wire [1:0] out_error, // .error - output wire out_valid, // .valid - input wire out_ready, // .ready - input wire clken, // clken.clken - input wire clk, // clock.clk - input wire reset_n // reset.reset_n - ); - - rx_cic_cic_ii_0 cic_ii_0 ( - .clk (clk), // clock.clk - .reset_n (reset_n), // reset.reset_n - .clken (clken), // clken.clken - .in_error (in_error), // av_st_in.error - .in_valid (in_valid), // .valid - .in_ready (in_ready), // .ready - .in_data (in_data), // .in_data - .out_data (out_data), // av_st_out.out_data - .out_error (out_error), // .error - .out_valid (out_valid), // .valid - .out_ready (out_ready) // .ready - ); - -endmodule diff --git a/FPGA_61.440/db/ip/rx_cic/rx_cic__report.html b/FPGA_61.440/db/ip/rx_cic/rx_cic__report.html deleted file mode 100644 index 8aa8302..0000000 --- a/FPGA_61.440/db/ip/rx_cic/rx_cic__report.html +++ /dev/null @@ -1,349 +0,0 @@ - - - - - datasheet for rx_cic - - - - - - - - -
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2021.03.31.22:15:25Datasheet
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Memory Map
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cic_ii_0

altera_cic_ii v18.1 -
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Parameters

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design_envNATIVE
selected_device_familyCYCLONEIVE
FILTER_TYPEdecimator
STAGES6
D_DELAY1
VRC_EN0
RCF_FIX1280
RCF_LB8
RCF_UB21
RCF_MIN1280
RCF_MAX1280
INTERFACES1
CH_PER_INT1
IN_WIDTH23
CLK_EN_PORTtrue
ROUND_TYPETRUNCATE
REQ_OUT_WIDTH32
OUT_WIDTH32
INT_USE_MEMfalse
INT_MEMauto
REQ_INT_MEMlogic_element
DIF_USE_MEMfalse
DIF_MEMauto
REQ_DIF_MEMlogic_element
REQ_PIPELINE0
PIPELINING0
C_STAGE_0_WIDTH85
I_STAGE_0_WIDTH85
C_STAGE_1_WIDTH85
I_STAGE_1_WIDTH85
C_STAGE_2_WIDTH85
I_STAGE_2_WIDTH85
C_STAGE_3_WIDTH85
I_STAGE_3_WIDTH85
C_STAGE_4_WIDTH85
I_STAGE_4_WIDTH85
C_STAGE_5_WIDTH85
I_STAGE_5_WIDTH85
C_STAGE_6_WIDTH85
I_STAGE_6_WIDTH85
C_STAGE_7_WIDTH85
I_STAGE_7_WIDTH85
C_STAGE_8_WIDTH85
I_STAGE_8_WIDTH85
C_STAGE_9_WIDTH85
I_STAGE_9_WIDTH85
C_STAGE_10_WIDTH85
I_STAGE_10_WIDTH85
C_STAGE_11_WIDTH85
I_STAGE_11_WIDTH85
MAX_I_STAGE_WIDTH85
MAX_C_STAGE_WIDTH85
hyper_opt_select0
hyper_opt0
deviceFamilyUNKNOWN
generateLegacySimfalse
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Software Assignments

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generation took 0,01 secondsrendering took 0,04 seconds
- - diff --git a/FPGA_61.440/db/ip/rx_cic/rx_cic__report.xml b/FPGA_61.440/db/ip/rx_cic/rx_cic__report.xml deleted file mode 100644 index 79464b6..0000000 --- a/FPGA_61.440/db/ip/rx_cic/rx_cic__report.xml +++ /dev/null @@ -1,440 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:rx_cic "rx_cic" - - - - Transform: CustomInstructionTransform - No custom instruction connections, skipping transform - 1 modules, 0 connections]]> - Transform: MMTransform - Transform: InterruptMapperTransform - Transform: InterruptSyncTransform - Transform: InterruptFanoutTransform - Transform: AvalonStreamingTransform - Transform: ResetAdaptation - rx_cic" reuses altera_cic_ii "submodules/rx_cic_cic_ii_0"]]> - queue size: 0 starting:altera_cic_ii "submodules/rx_cic_cic_ii_0" - rx_cic" instantiated altera_cic_ii "cic_ii_0"]]> - - - - - - - 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All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - -------------------------------------------------------------------------- -------------------------------------------------------------------------- --- --- Revision Control Information --- --- $RCSfile: auk_dspip_delay.vhd,v $ --- $Source: /cvs/uksw/dsp_cores/lib/fu/delay/rtl/auk_dspip_delay.vhd,v $ --- --- $Revision: #1 $ --- $Date: 2018/07/18 $ --- Check in by : $Author: psgswbuild $ --- Author : Volker Mauer --- --- Project : common FU library --- --- Description : --- --- This functional unit can be used to insert a delay of specified length. --- The output data at time T will be equivalent to the input data at time --- T-DELAY. The user can select to implement the delay using either LE's --- (registers) or Memory. The type of memory to use is selected by the --- user. --- --- ALTERA Confidential and Proprietary --- Copyright 2006 (c) Altera Corporation --- All rights reserved --- -------------------------------------------------------------------------- -------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library altera_mf; -use altera_mf.altera_mf_components.all; -library work; -use work.auk_dspip_math_pkg.all; - - -entity auk_dspip_delay is - generic ( - WIDTH_g : natural := 8; -- data width - DELAY_g : natural := 8; - -- number of clock cycles the input - -- will be delayed by - MEMORY_TYPE_g : string := "AUTO"; - -- possible values are "m4k", "m512", - -- "register", "mram", "auto", - -- "lutram", "M9K", "M144K". - -- Any other string will be interpreted - -- as "auto" - REGISTER_FIRST_g : natural := 1; - -- if "1", the first delay is guaranteed - -- to be in registers - REGISTER_LAST_g : natural := 1); -- if "1", the last delay is guaranteed - -- to be in registers - port ( - clk : in std_logic; - reset : in std_logic; - enable : in std_logic; -- global clock enable - datain : in std_logic_vector(WIDTH_g-1 downto 0); - dataout : out std_logic_vector(WIDTH_g-1 downto 0) - ); -end entity auk_dspip_delay; - - -architecture rtl of auk_dspip_delay is -begin -- architecture rtl - - - ------------------------------------------------------------------------------ - -- array of registers - ------------------------------------------------------------------------------ - register_fifo : if MEMORY_TYPE_g = "register" or MEMORY_TYPE_g = "REGISTER" or DELAY_g-REGISTER_FIRST_g-REGISTER_LAST_g < 3 generate - type tFIFO_DATA is array (0 to DELAY_g-1) of std_logic_vector(WIDTH_g-1 downto 0); - signal fifo_data : tFIFO_DATA; - begin -- generate register_fifo - - -- purpose: array of registers - -- type : sequential - -- inputs : clk, reset, data_in - -- outputs: data_out - array_of_reg : process (clk, reset) is - begin -- process array_of_reg - if reset = '1' then -- asynchronous reset (active high) - reset_all : for i in 0 to DELAY_g-1 loop - fifo_data(i) <= (others => '0'); - end loop; - elsif rising_edge(clk) then -- rising clock edge - - ------------------------------------------------------------------- - -- memory array - ------------------------------------------------------------------- - - if enable = '1' then - fifo_data(0) <= datain; - if DELAY_g > 1 then - shift_up : for i in 1 to DELAY_g-1 loop - fifo_data(i) <= fifo_data(i-1); - end loop; - end if; - end if; - - end if; - end process array_of_reg; - dataout <= fifo_data(DELAY_g-1); - - - end generate register_fifo; - - ----------------------------------------------------------------------------- - -- memory based delay using altshift_tap - ----------------------------------------------------------------------------- - memory_fifo : if DELAY_g-REGISTER_FIRST_g-REGISTER_LAST_g >= 3 and not(MEMORY_TYPE_g = "register" or MEMORY_TYPE_g = "REGISTER") generate -component altshift_taps - generic ( - lpm_hint : string; - lpm_type : string; - number_of_taps : natural; - tap_distance : natural; - width : natural - ); - port ( - taps : out std_logic_vector (WIDTH_g-1 downto 0); - clken : in std_logic; - clock : in std_logic; - aclr : in std_logic := '0'; - sclr : in std_logic := '0'; - shiftout : out std_logic_vector (WIDTH_g-1 downto 0); - shiftin : in std_logic_vector (WIDTH_g-1 downto 0) - ); - end component; - component scfifo - generic ( - add_ram_output_register : string; - intended_device_family : string; - lpm_numwords : natural; - lpm_showahead : string; - lpm_type : string; - lpm_width : natural; - lpm_widthu : natural; - overflow_checking : string; - underflow_checking : string; - use_eab : string - ); - port ( - rdreq : in std_logic; - clock : in std_logic; - q : out std_logic_vector (WIDTH_g-1 downto 0); - wrreq : in std_logic; - data : in std_logic_vector (WIDTH_g-1 downto 0) - ); - end component; - - constant mem_depth : natural := DELAY_g - REGISTER_FIRST_g - REGISTER_LAST_g; - constant lpm_hint : string := "RAM_BLOCK_TYPE = " & MEMORY_TYPE_g; - - - signal mem_in : std_logic_vector(WIDTH_g-1 downto 0); -- memory input - signal mem_out : std_logic_vector(WIDTH_g-1 downto 0); -- memory_output - signal count_after_reset : unsigned(log2_ceil(mem_depth) downto 0); - signal extended_reset : std_logic; - - begin -- generate memory_fifo - - - - input_stage : if REGISTER_FIRST_g = 1 and (REGISTER_LAST_g = 0 or DELAY_g > 1) generate - begin -- generate input_stage - -- purpose: registers first stage - -- type : sequential - -- inputs : clk, reset, data_in - -- outputs: mem_in - - reg_input : process (clk, reset) is - begin -- process reg_input - if reset = '1' then -- asynchronous reset (active high) - mem_in <= (others => '0'); - elsif rising_edge(clk) then -- rising clock edge - if enable = '1' then - mem_in <= datain; - end if; - end if; - end process reg_input; - end generate input_stage; - - bypass_input_stage : if ((REGISTER_FIRST_g = 0) or - ((REGISTER_FIRST_g = 1) and (REGISTER_LAST_g = 1) and (DELAY_g = 1))) generate - -- captures the case, where the total delay is 1, and input and output - -- register is requested. In this case, the output register is also the - -- input register. Bypassing input register, leaving only output register. - - begin -- generate bypass_input_stage - mem_in <= datain; - end generate bypass_input_stage; - - check_illegal_generic : if REGISTER_FIRST_g > 1 generate - begin -- generate check_illegal_generic - assert false report "Generic REGISTER_FIRST_g in FU : DELAY must be 0 or 1" severity failure; - end generate check_illegal_generic; - - check_illegal_generic_3 : if DELAY_g < 1 generate - begin -- generate check_illegal_generic - assert false report "Generic DELAY_g in FU : DELAY must be at least 1" severity failure; - end generate check_illegal_generic_3; - - --------------------------------------------------------------------------- - -- only instantiate memory if the length of the shift reg is greater than - -- 0. This is to capture the case where the length is 1, and input or - -- output registers have been used. - --------------------------------------------------------------------------- - memory_i : if mem_depth > 0 generate - begin -- generate memory_i - altshift_taps_component : altshift_taps - generic map ( - lpm_hint => lpm_hint, - lpm_type => "altshift_taps", - number_of_taps => 1, - tap_distance => mem_depth, - width => WIDTH_g - ) - port map ( - clken => enable, - clock => clk, - shiftin => mem_in, - taps => mem_out, - shiftout => open - ); - end generate memory_i; - - no_memory_i : if mem_depth < 1 generate - begin -- generate no_memory_i - mem_out <= mem_in; -- bypass memory - end generate no_memory_i; - - - - output_stage : if REGISTER_LAST_g = 1 generate - begin -- generate output_stage - -- purpose: registers first stage - -- type : sequential - -- inputs : clk, reset, data_in - -- outputs: mem_in - reg_output : process (clk, reset) is - begin -- process reg_output - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - elsif rising_edge(clk) then -- rising clock edge - if enable = '1' then - if extended_reset = '1' then - dataout <= (others => '0'); - else - dataout <= mem_out; - end if; - end if; - end if; - end process reg_output; - end generate output_stage; - - bypass_output_stage : if REGISTER_LAST_g = 0 generate - begin -- generate bypass_output_stage - dataout <= mem_out when extended_reset = '0' else - (others => '0'); - end generate bypass_output_stage; - - check_illegal_generic2 : if REGISTER_LAST_g > 1 generate - begin -- generate check_illegal_generic2 - assert false report "Generic REGISTER_LAST_g in FU : DELAY must be 0 or 1" severity failure; - end generate check_illegal_generic2; - - -- purpose: creates an extended reset, that is high for MEM_DEPTH_c clock cycles. - -- This signal is used to 0 out the first MEM_DEPTH values from the delay register. - -- type : sequential - -- inputs : clk, resenable - -- outputs: extended_reset - extend_reset : process (clk, reset) is - begin -- process extended_reset - if reset = '1' then -- asynchronous reset (active high) - extended_reset <= '1'; - count_after_reset <= (others => '0'); - elsif rising_edge(clk) then -- rising clock edge - if enable = '1' then - if count_after_reset < mem_depth then - count_after_reset <= count_after_reset + 1; - extended_reset <= '1'; - else - extended_reset <= '0'; - end if; - end if; - end if; - end process extend_reset; - - end generate memory_fifo; - - -end architecture rtl; diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd b/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd deleted file mode 100644 index 3293d7a..0000000 Binary files a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd and /dev/null differ diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_downsample.sv b/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_downsample.sv deleted file mode 100644 index bdc5d8e..0000000 Binary files a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_downsample.sv and /dev/null differ diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd b/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd deleted file mode 100644 index ec7fa43..0000000 --- a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd +++ /dev/null @@ -1,88 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -entity auk_dspip_fastadd is - generic ( - INWIDTH_g : natural := 18; - LABWIDTH_g : natural := 16); - -- width of lab in selected device ( 10 or 16 in Cyclone, - -- Cylone II, Stratix and Stratix II. Don't know - -- Stratix III yet. - port ( - datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); - datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); - clk : in std_logic; - enable : in std_logic; - reset : in std_logic; - dataout : out std_logic_vector(INWIDTH_g downto 0)); -end entity auk_dspip_fastadd; - - -architecture beh of auk_dspip_fastadd is - - constant LOWWIDTH_c : natural := LABWIDTH_g * (1 + integer(INWIDTH_g/(LABWIDTH_g*2))); - constant asdf : natural := integer(INWIDTH_g/(LABWIDTH_g*2)); - constant asdf2 : natural := 1+integer(INWIDTH_g/(LABWIDTH_g*2)); - constant asdf3 : natural := LABWIDTH_g * (1+integer(INWIDTH_g/(LABWIDTH_g*2))); - - constant HIGHWIDTH_c : natural := INWIDTH_g-LOWWIDTH_c; - - - signal datain1_low : std_logic_vector(LOWWIDTH_c-1 downto 0); - signal datain1_high : std_logic_vector(HIGHWIDTH_c-1 downto 0); - signal datain2_low : std_logic_vector(LOWWIDTH_c-1 downto 0); - signal datain2_high : std_logic_vector(HIGHWIDTH_c-1 downto 0); - signal result_low : std_logic_vector(LOWWIDTH_c downto 0); - signal result_high_cin0 : std_logic_vector(HIGHWIDTH_c downto 0); - signal result_high_cin1 : std_logic_vector(HIGHWIDTH_c downto 0); - - attribute keep : boolean; - attribute keep of result_high_cin0 : signal is true; - attribute keep of result_high_cin1 : signal is true; - -begin -- architecture beh - - datain1_low <= datain1(LOWWIDTH_c-1 downto 0); - datain1_high <= datain1(HIGHWIDTH_c+LOWWIDTH_c-1 downto LOWWIDTH_c); - datain2_low <= datain2(LOWWIDTH_c-1 downto 0); - datain2_high <= datain2(HIGHWIDTH_c+LOWWIDTH_c-1 downto LOWWIDTH_c); - - adder_process : process (clk, reset) is - begin -- process adder_process - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - elsif rising_edge(clk) then -- rising clock edge - if enable = '1' then - if result_low(LOWWIDTH_c) = '1' then - dataout <= result_high_cin1 & result_low(LOWWIDTH_c-1 downto 0); - else - dataout <= result_high_cin0 & result_low(LOWWIDTH_c-1 downto 0); - end if; - end if; - end if; - end process adder_process; - - result_low <= std_logic_vector(unsigned('0' & datain1_low) + unsigned('0' & datain2_low)); - result_high_cin0 <= std_logic_vector(unsigned(datain1_high(HIGHWIDTH_c-1) & datain1_high) + - unsigned(datain2_high(HIGHWIDTH_c-1) & datain2_high)); - result_high_cin1 <= std_logic_vector(unsigned(datain1_high(HIGHWIDTH_c-1) & datain1_high )+ - unsigned(datain2_high(HIGHWIDTH_c-1) & datain2_high )+ - 1); - - -end architecture beh; diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd b/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd deleted file mode 100644 index 312e756..0000000 --- a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd +++ /dev/null @@ -1,160 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - -------------------------------------------------------------------------- -------------------------------------------------------------------------- --- --- Revision Control Information --- --- $RCSfile: $ --- $Source: $ --- --- $Revision: #1 $ --- $Date: 2018/07/18 $ --- Check in by : $Author: psgswbuild $ --- Author : Volker Mauer --- --- Project : auk_dspip_fastaddsub --- --- Description : --- --- This functional unit can be used to perform an addition or subtraction --- in a single clock cycle faster than in a standard adder, by means of a --- carry select structure. --- --- This means that the adder is split into a lower part and an upper part. --- The upper part is implemented twice: Once with the carry_in fixed to '0' --- and once with the carry_in fixed to '1'. The carry_out of the lower part --- is used to control a mux selecting the two possible upper results. --- --- This structucture is useful where the width is so great that the standard --- adder would be slower than the DSP block, and a pipelined adder cannot be --- used, like in accumulators. --- --- There is a device dependency: The width of the lower part, where 1 LE per --- bit is required, should be greater than half the overall width, and --- ideally be selected to fit into labs of the target device. The upper --- half, where 3 LEs per bit are needed, should add the remaining bits. --- --- Given the width and the labwidth, the function will automatically calculate --- the width of lower and upper parts using the following formula: --- --- Wlow = Wlab * ceil(Win / (2*Wlab)) --- Whigh = Win-Wlow --- --- Example: If the adder is 48 bits in, the lab width is 10, we would --- get Wlow = 30, Whigh=18. --- --- ALTERA Confidential and Proprietary --- Copyright 2006 (c) Altera Corporation --- All rights reserved --- -------------------------------------------------------------------------- -------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -entity auk_dspip_fastaddsub is - generic ( - INWIDTH_g : natural := 18; - LABWIDTH_g : natural := 16); - -- width of lab in selected device ( 10 or 16 in Cyclone, - -- Cylone II, Stratix and Stratix II. Don't know - -- Stratix III yet. - port ( - datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); - datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); - add_nsub : in std_logic; - clk : in std_logic; - enable : in std_logic; - reset : in std_logic; - dataout : out std_logic_vector(INWIDTH_g downto 0)); -end entity auk_dspip_fastaddsub; - - -architecture beh of auk_dspip_fastaddsub is - - constant LOWWIDTH_c : natural := LABWIDTH_g * (1 + integer(INWIDTH_g/(LABWIDTH_g*2))); - constant asdf : natural := integer(INWIDTH_g/(LABWIDTH_g*2)); - constant asdf2 : natural := 1+integer(INWIDTH_g/(LABWIDTH_g*2)); - constant asdf3 : natural := LABWIDTH_g * (1+integer(INWIDTH_g/(LABWIDTH_g*2))); - - constant HIGHWIDTH_c : natural := INWIDTH_g-LOWWIDTH_c; - - - signal datain1_low : std_logic_vector(LOWWIDTH_c-1 downto 0); - signal datain1_high : std_logic_vector(HIGHWIDTH_c-1 downto 0); - signal datain2_low : std_logic_vector(LOWWIDTH_c-1 downto 0); - signal datain2_high : std_logic_vector(HIGHWIDTH_c-1 downto 0); - signal result_low : std_logic_vector(LOWWIDTH_c downto 0); - signal result_high_cin0 : std_logic_vector(HIGHWIDTH_c downto 0); - signal result_high_cin1 : std_logic_vector(HIGHWIDTH_c downto 0); - - ----------------------------------------------------------------------------- - -- Synthesis tools have got clever. Need to set "keep" attribute, or the - -- synthesis tool will recognise the structure as a standard adder, and - -- optimise it accordingly. - ----------------------------------------------------------------------------- - attribute keep : boolean; - attribute keep of result_high_cin0 : signal is true; - attribute keep of result_high_cin1 : signal is true; - -begin -- architecture beh - - ----------------------------------------------------------------------------- - -- split inputs into upper and lower halves - ----------------------------------------------------------------------------- - datain1_low <= datain1(LOWWIDTH_c-1 downto 0); - datain1_high <= datain1(HIGHWIDTH_c+LOWWIDTH_c-1 downto LOWWIDTH_c); - datain2_low <= datain2(LOWWIDTH_c-1 downto 0); - datain2_high <= datain2(HIGHWIDTH_c+LOWWIDTH_c-1 downto LOWWIDTH_c); - - ----------------------------------------------------------------------------- - -- perform separate additions/subtractions for upper and lower halves - ----------------------------------------------------------------------------- - result_low <= std_logic_vector(unsigned('0' & datain1_low) + unsigned('0' & datain2_low)) when add_nsub='1' else - std_logic_vector(unsigned('0' & datain1_low) - unsigned('0' & datain2_low)); - result_high_cin0 <= std_logic_vector(unsigned(datain1_high(HIGHWIDTH_c-1) & datain1_high) + - unsigned(datain2_high(HIGHWIDTH_c-1) & datain2_high)) when add_nsub='1' else - std_logic_vector(unsigned(datain1_high(HIGHWIDTH_c-1) & datain1_high) - - unsigned(datain2_high(HIGHWIDTH_c-1) & datain2_high)); - result_high_cin1 <= std_logic_vector(unsigned(datain1_high(HIGHWIDTH_c-1) & datain1_high )+ - unsigned(datain2_high(HIGHWIDTH_c-1) & datain2_high )+ - 1) when add_nsub = '1' else - std_logic_vector(unsigned(datain1_high(HIGHWIDTH_c-1) & datain1_high )- - unsigned(datain2_high(HIGHWIDTH_c-1) & datain2_high )- - 1); - - ----------------------------------------------------------------------------- - -- multiplex (select) the upper half, register selected upper half and lower - -- half. - ----------------------------------------------------------------------------- - adder_process : process (clk, reset) is - begin -- process adder_process - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - elsif rising_edge(clk) then -- rising clock edge - if enable = '1' then - if result_low(LOWWIDTH_c) = '1' then - dataout <= result_high_cin1 & result_low(LOWWIDTH_c-1 downto 0); - else - dataout <= result_high_cin0 & result_low(LOWWIDTH_c-1 downto 0); - end if; - end if; - end if; - end process adder_process; - - -end architecture beh; diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_integrator.vhd b/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_integrator.vhd deleted file mode 100644 index 801c66f..0000000 Binary files a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_integrator.vhd and /dev/null differ diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd b/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd deleted file mode 100644 index 3ee6f10..0000000 --- a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd +++ /dev/null @@ -1,630 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - ---This file is auto-generated by compile_dspip_lib.pl ---Date:06/07/2007 - ---Time:19:15 - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; --- Alex, 02-10-07, this package declaration results in error at built time on a new machine --- -use work.auk_dspip_math_pkg.all; - -package auk_dspip_lib_pkg is ---Component names: ---auk_fifo ---auk_dspip_atlantic_sink ---auk_dspip_atlantic_source ---auk_dspip_interface_controller ---auk_dspip_avalon_streaming_controller ---auk_dspip_avalon_streaming_controller_pe ---auk_dspip_avalon_streaming_sink ---auk_dspip_avalon_streaming_source ---auk_dspip_delay ---auk_dspip_fastadd ---auk_dspip_fastaddsub ---auk_dspip_pipelined_adder ---auk_dspip_fast_accumulator ---auk_dspip_fifo_pfc ---auk_dspip_fpcompiler_alufp ---auk_dspip_fpcompiler_aslf ---auk_dspip_fpcompiler_asrf ---auk_dspip_fpcompiler_castftox ---auk_dspip_fpcompiler_castxtof ---auk_dspip_fpcompiler_clzf ---auk_dspip_fpcompiler_mulfp ---auk_dspip_pfc ---auk_dspip_roundsat - - -component auk_fifo is -generic ( - DATA_WIDTH : natural := 32; - SIZE : natural := 10; - ALMOST_EMPTY_BOUND : natural := 3; - ALMOST_FULL_BOUND : natural := 500 - ); -port ( - clk : in std_logic; - reset : in std_logic; - - read_req : in std_logic; - write_req : in std_logic; - - data_in : in std_logic_vector(DATA_WIDTH-1 DOWNTO 0); - data_out : out std_logic_vector(DATA_WIDTH-1 DOWNTO 0); - - almost_full : out std_logic; - almost_empty : out std_logic; - empty : out std_logic; - full : out std_logic - - ); - -end component auk_fifo; - -component auk_dspip_atlantic_sink is - - generic( - WIDTH : integer := 16; - PACKET_SIZE : natural := 4; - log2packet_size : integer := 2 - ); - port( - clk : in std_logic; - reset_n : in std_logic; - ----------------- DESIGN SIDE SIGNALS - data_available : out std_logic; --goes high when new data is available - data : out std_logic_vector(WIDTH-1 downto 0); - sink_ready_ctrl : in std_logic; --the controller will tell - --the interface whether - --new input can be accepted. - sink_stall : out std_logic; --needs to stall the design - --if no new data is coming - packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only. - --when any of these doesn't behave as - --expected, the error is flagged. - send_sop : out std_logic; -- transmit SOP signal to the design. - -- It only transmits the legal SOP. - send_eop : out std_logic; -- transmit EOP signal to the design. - -- It only transmits the legal EOP. - ----------------- ATLANTIC SIDE SIGNALS - at_sink_ready : out std_logic; --it will be '1' whenever the - --sink_ready_ctrl signal is high. - at_sink_valid : in std_logic; - at_sink_data : in std_logic_vector(WIDTH-1 downto 0); - at_sink_sop : in std_logic := '0'; - at_sink_eop : in std_logic := '0'; - at_sink_error : in std_logic_vector(1 downto 0) --it indicates to the data source - --that the SOP and EOP signals - --are not received as expected. - - ); - -end component auk_dspip_atlantic_sink; - -component auk_dspip_atlantic_source is - generic( - WIDTH : integer := 16; - packet_size : natural := 4; - LOG2packet_size : integer := 2; - multi_channel : BOOLEAN := TRUE - ); - port( - clk : in std_logic; - reset_n : in std_logic; - ----------------- DESIGN SIDE SIGNALS - data : in std_logic_vector (WIDTH-1 downto 0); - data_count : in std_logic_vector (LOG2packet_size-1 downto 0) := (others => '0'); - source_valid_ctrl : in std_logic; --the controller will tell - --the interface whether - --new input can be accepted. - source_stall : out std_logic; --needs to stall the design - --if no new data is coming - packet_error : in std_logic_vector (1 downto 0); - ----------------- ATLANTIC SIDE SIGNALS - at_source_ready : in std_logic; - at_source_valid : out std_logic; - at_source_data : out std_logic_vector (WIDTH-1 downto 0); - at_source_channel : out std_logic_vector (log2packet_size-1 downto 0); - at_source_error : out std_logic_vector (1 downto 0); - at_source_sop : out std_logic; - at_source_eop : out std_logic - ); - --- Declarations - -end component auk_dspip_atlantic_source; - - -component auk_dspip_interface_controller IS - PORT( - clk : in std_logic; - reset : IN std_logic; - ready : in std_logic; - sink_packet_error : IN std_logic_vector (1 DOWNTO 0); - sink_stall : IN std_logic; - source_stall : IN std_logic; - valid : IN std_logic; - reset_design : OUT std_logic; - reset_n : OUT std_logic; - sink_ready_ctrl : OUT std_logic; - source_packet_error : OUT std_logic_vector (1 DOWNTO 0); - source_valid_ctrl : OUT std_logic; - stall : OUT std_logic - ); - --- Declarations - -end component auk_dspip_interface_controller ; - - -component auk_dspip_avalon_streaming_controller is - port( - clk : in std_logic; - clk_en : in std_logic := '1'; - reset_n : in std_logic; - ready : in std_logic; - sink_packet_error : in std_logic_vector (1 downto 0); - sink_stall : in std_logic; - source_stall : in std_logic; - valid : in std_logic; - reset_design : out std_logic; - sink_ready_ctrl : out std_logic; - source_packet_error : out std_logic_vector (1 downto 0); - source_valid_ctrl : out std_logic; - stall : out std_logic - ); - --- Declarations - -end component auk_dspip_avalon_streaming_controller; - -component auk_dspip_avalon_streaming_controller_pe is - generic ( - FIFO_WIDTH_g : natural := 8; - ENABLE_PIPELINE_DEPTH_g : natural := 0; -- this value should match the depth of the enable pipeline in the core - FAMILY_g : string := "Stratix II"; - MEM_TYPE_g : string := "Auto" - ); - port( - clk : in std_logic; - clk_en : in std_logic := '1'; - reset_n : in std_logic; - ready : in std_logic; - sink_packet_error : in std_logic_vector (1 downto 0); - sink_stall : in std_logic; - source_stall : in std_logic; - valid : in std_logic; - reset_design : out std_logic; - sink_ready_ctrl : out std_logic; - source_packet_error : out std_logic_vector (1 downto 0); - source_valid_ctrl : out std_logic; - stall : out std_logic; - data_in : in std_logic_vector(FIFO_WIDTH_g-1 downto 0); - data_out : out std_logic_vector(FIFO_WIDTH_g-1 downto 0); - design_stall : out std_logic - ); - --- Declarations - -end component auk_dspip_avalon_streaming_controller_pe; - -component auk_dspip_avalon_streaming_sink is - - generic( - WIDTH_g : integer := 16; - PACKET_SIZE_g : natural := 4; - FIFO_DEPTH_g : natural := 5; --if PFC mode is selected, this generic - --is used for passing the poly_factor. - MIN_DATA_COUNT_g : natural := 2; - PFC_MODE_g : string := "false"; - SOP_EOP_CALC_g : string := "false"; -- calculate sop and eop rather than - -- reading value from fifo - FAMILY_g : string := "Stratix II"; - MEM_TYPE_g : string := "Auto" - ); - port( - clk : in std_logic; - reset_n : in std_logic; - ----------------- DESIGN SIDE SIGNALS - data : out std_logic_vector(WIDTH_g-1 downto 0); - sink_ready_ctrl : in std_logic; --the controller will tell - --the interface whether - --new input can be accepted. - sink_stall : out std_logic; --needs to stall the design - --if no new data is coming - packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only. - --when any of these doesn't behave as - --expected, the error is flagged. - send_sop : out std_logic; -- transmit SOP signal to the design. - -- It only transmits the legal SOP. - send_eop : out std_logic; -- transmit EOP signal to the design. - -- It only transmits the legal EOP. - ----------------- ATLANTIC SIDE SIGNALS - at_sink_ready : out std_logic; --it will be '1' whenever the - --sink_ready_ctrl signal is high. - at_sink_valid : in std_logic; - at_sink_data : in std_logic_vector(WIDTH_g-1 downto 0); - at_sink_sop : in std_logic := '0'; - at_sink_eop : in std_logic := '0'; - at_sink_error : in std_logic_vector(1 downto 0) := "00" --it indicates - --that there is an error in the packet. - - ); - -end component auk_dspip_avalon_streaming_sink; - -component auk_dspip_avalon_streaming_source is - generic( - WIDTH_g : integer := 16; - PACKET_SIZE_g : natural := 4; - HAVE_COUNTER_g : string := "false"; - COUNTER_LIMIT_g : natural := 4; - MULTI_CHANNEL_g : string := "true" - ); - port( - clk : in std_logic; - reset_n : in std_logic; - ----------------- DESIGN SIDE SIGNALS - data : in std_logic_vector (WIDTH_g-1 downto 0); - data_count : in std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0'); - source_valid_ctrl : in std_logic; - design_stall : in std_logic; - source_stall : out std_logic; - packet_error : in std_logic_vector (1 downto 0); - ----------------- AVALON_STREAMING SIDE SIGNALS - at_source_ready : in std_logic; - at_source_valid : out std_logic; - at_source_data : out std_logic_vector (WIDTH_g-1 downto 0); - at_source_channel : out std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0); - at_source_error : out std_logic_vector (1 downto 0); - at_source_sop : out std_logic; - at_source_eop : out std_logic - ); - --- Declarations - -end component auk_dspip_avalon_streaming_source; - - -component auk_dspip_delay is - generic ( - WIDTH_g : natural := 8; -- data width - DELAY_g : natural := 8; - -- number of clock cycles the input - -- will be delayed by - MEMORY_TYPE_g : string := "AUTO"; - -- possible values are "m4k", "m512", - -- "register", "mram", "auto", - -- "lutram", "M9K", "M144K". - -- Any other string will be interpreted - -- as "auto" - REGISTER_FIRST_g : natural := 1; - -- if "1", the first delay is guaranteed - -- to be in registers - REGISTER_LAST_g : natural := 1); -- if "1", the last delay is guaranteed - -- to be in registers - port ( - clk : in std_logic; - reset : in std_logic; - enable : in std_logic; -- global clock enable - datain : in std_logic_vector(WIDTH_g-1 downto 0); - dataout : out std_logic_vector(WIDTH_g-1 downto 0) - ); -end component auk_dspip_delay; - - -component auk_dspip_fastadd is - generic ( - INWIDTH_g : natural := 18; - LABWIDTH_g : natural := 16); - -- width of lab in selected device ( 10 or 16 in Cyclone, - -- Cylone II, Stratix and Stratix II. Don't know - -- Stratix III yet. - port ( - datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); - datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); - clk : in std_logic; - enable : in std_logic; - reset : in std_logic; - dataout : out std_logic_vector(INWIDTH_g downto 0)); -end component auk_dspip_fastadd; - - -component auk_dspip_fastaddsub is - generic ( - INWIDTH_g : natural := 18; - LABWIDTH_g : natural := 16); - -- width of lab in selected device ( 10 or 16 in Cyclone, - -- Cylone II, Stratix and Stratix II. Don't know - -- Stratix III yet. - port ( - datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); - datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); - add_nsub : in std_logic; - clk : in std_logic; - enable : in std_logic; - reset : in std_logic; - dataout : out std_logic_vector(INWIDTH_g downto 0)); -end component auk_dspip_fastaddsub; - - -component auk_dspip_pipelined_adder is - generic ( - INWIDTH_g : natural := 42; - -- width of lab in selected device ( 10 or 16 in Cyclone, - -- Cylone II, Stratix and Stratix II. - -- Alex : should I use 19 bits for Stratix III? - -- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency. - LABWIDTH_g : natural := 38); - port ( - datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); - datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); - clk : in std_logic; - enable : in std_logic; - reset : in std_logic; - dataout : out std_logic_vector(INWIDTH_g downto 0)); -end component auk_dspip_pipelined_adder; - - -component auk_dspip_fast_accumulator is - generic ( - DATA_WIDTH_g : natural := 42; - -- width of lab in selected device ( 10 or 16 in Cyclone, - -- Cylone II, Stratix and Stratix II. - -- for Stratix III is 20 so labwidth should be set to 18. - -- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency. - LABWIDTH_g : natural := 38; - NUM_OF_CHANNELS_g : natural := 1; - ACCUM_OUT_WIDTH_g : natural := 48; - ACCUM_MEM_TYPE_g : string := "auto"); - port ( - reset : in std_logic; - clk : in std_logic; - enb : in std_logic; - add_to_zero : in std_logic; - datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0); - datao : out std_logic_vector(ACCUM_OUT_WIDTH_g-1 downto 0)); -end component auk_dspip_fast_accumulator; - - -component auk_dspip_fifo_pfc is - generic ( - NUM_CHANNELS_g : integer := 5; - POLY_FACTOR_g : integer := 3; - DATA_WIDTH_g : integer := 16; - ALMOST_FULL_VALUE_g : integer := 2; - RAM_TYPE_g : string := "AUTO"; - CALCULATE_USED_WORDS_ONCE : boolean := true - ); - port ( - - datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0); - datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0); - channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0); - used_w : out std_logic_vector(log2_ceil(POLY_FACTOR_g * NUM_CHANNELS_g)+1 downto 0); - - wrreq : in std_logic; - rdreq : in std_logic; - almost_full : out std_logic; - empty : out std_logic; - sclr : in std_logic; - clk : in std_logic; - reset : in std_logic; - enable : in std_logic - ); -end component auk_dspip_fifo_pfc; -component auk_dspip_fpcompiler_alufp is - port ( - sysclk : in std_logic; - reset : in std_logic; - enable : in std_logic; - addsub : in std_logic; - aa : in std_logic_vector (42 downto 1); - aasat, aazip : in std_logic; - bb : in std_logic_vector (42 downto 1); - bbsat, bbzip : in std_logic; - cc : out std_logic_vector (42 downto 1); - ccsat, cczip : out std_logic - ); -end component auk_dspip_fpcompiler_alufp; -component auk_dspip_fpcompiler_aslf is - port ( - inbus : in std_logic_vector (32 downto 1); - shift : in std_logic_vector (5 downto 1); - - outbus : out std_logic_vector (32 downto 1) - ); -end component auk_dspip_fpcompiler_aslf; -component auk_dspip_fpcompiler_asrf is - port ( - inbus : in std_logic_vector (32 downto 1); - shift : in std_logic_vector (5 downto 1); - - outbus : out std_logic_vector (32 downto 1) - ); -end component auk_dspip_fpcompiler_asrf; - -component auk_dspip_fpcompiler_castftox is - port ( - aa : in std_logic_vector (32 downto 1); - cc : out std_logic_vector (42 downto 1); - ccsat, cczip : out std_logic - ); -end component auk_dspip_fpcompiler_castftox; - -component auk_dspip_fpcompiler_castxtof is - port ( - sysclk : in std_logic; - reset : in std_logic; - enable : in std_logic; - aa : in std_logic_vector (42 downto 1); - aasat, aazip : in std_logic; - cc : out std_logic_vector (32 downto 1) - ); -end component auk_dspip_fpcompiler_castxtof; - -component auk_dspip_fpcompiler_clzf is - port ( - frac : in std_logic_vector (32 downto 1); - count : out std_logic_vector (5 downto 1) - ); -end component auk_dspip_fpcompiler_clzf; -component auk_dspip_fpcompiler_mulfp is - port ( - sysclk : in std_logic; - reset : in std_logic; - enable : in std_logic; - aa : in std_logic_vector (42 downto 1); - aasat, aazip : in std_logic; - bb : in std_logic_vector (42 downto 1); - bbsat, bbzip : in std_logic; - cc : out std_logic_vector (42 downto 1); - ccsat, cczip : out std_logic - ); -end component auk_dspip_fpcompiler_mulfp; - -component auk_dspip_pfc is - generic ( - NUM_CHANNELS_g : integer := 5; - POLY_FACTOR_g : integer := 3; - DATA_WIDTH_g : integer := 16; - RAM_TYPE_g : string := "AUTO" - ); - port ( - - datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0); - datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0); - channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0); - - in_valid : in std_logic; - out_valid : out std_logic; - clk : in std_logic; - reset : in std_logic; - enable : in std_logic - ); -end component auk_dspip_pfc; - - -component auk_dspip_roundsat is - generic ( - IN_WIDTH_g : natural := 8; -- data width - OUT_WIDTH_g : natural := 8; -- data width - LATENCY : natural := 1; - ROUNDING_TYPE_g : string := "TRUNCATE_LOW" - ); - - port ( - clk : in std_logic; - reset : in std_logic; - enable : in std_logic; -- global clock enable - datain : in std_logic_vector(IN_WIDTH_g-1 downto 0); - dataout : out std_logic_vector(OUT_WIDTH_g-1 downto 0)); -end component auk_dspip_roundsat; - -component auk_dspip_avalon_streaming_block_source is - generic ( - MAX_BLK_g : natural; - DATAWIDTH_g : natural; - HYPER_OPTIMIZATION : natural := 0); - port ( - clk : in std_logic; - reset : in std_logic; - in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0); - in_valid : in std_logic; - source_stall : out std_logic; - in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0); - source_valid : out std_logic; - source_ready : in std_logic; - source_sop : out std_logic; - source_eop : out std_logic; - source_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0)); -end component auk_dspip_avalon_streaming_block_source; - -component auk_dspip_avalon_streaming_block_sink is - generic ( - MAX_BLK_g : natural; - STALL_g : natural; - DATAWIDTH_g : natural; - -- this generic is specific for the FFT. - NUM_STAGES_g : natural; - FFT_ARCH : string; - HYPER_OPTIMIZATION : natural := 0); - port ( - clk : in std_logic; - reset : in std_logic; - in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0); - in_sop : in std_logic; - in_eop : in std_logic; - in_inverse : in std_logic; - sink_valid : in std_logic; - sink_ready : out std_logic; - source_stall : in std_logic; - in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0); - processing : in std_logic; - in_error : in std_logic_vector(1 downto 0); - out_error : out std_logic_vector(1 downto 0); - out_valid : out std_logic; - out_sop : out std_logic; - out_eop : out std_logic; - out_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0); - curr_blk : out std_logic_vector(log2_ceil(MAX_BLK_g) downto 0); - -- these are specific to the FFT, no effort has been made to optimize! - curr_pwr_2 : out std_logic; - curr_inverse : out std_logic; - curr_input_sel : out std_logic_vector(NUM_STAGES_g - 1 downto 0)); -end component auk_dspip_avalon_streaming_block_sink; - -component auk_dspip_avalon_streaming_block_sink_fftfprvs is - generic ( - MAX_BLK_g : natural; - STALL_g : natural; - DATAWIDTH_g : natural; - -- this generic is specific for the FFT. - NUM_STAGES_g : natural; - FFT_ARCH : string); - port ( - clk : in std_logic; - reset : in std_logic; - in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0); - in_sop : in std_logic; - in_eop : in std_logic; - in_inverse : in std_logic; - sink_valid : in std_logic; - sink_ready : out std_logic; - source_stall : in std_logic; - in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0); - processing : in std_logic; - in_error : in std_logic_vector(1 downto 0); - out_error : out std_logic_vector(1 downto 0); - out_valid : out std_logic; - out_sop : out std_logic; - out_eop : out std_logic; - out_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0); - curr_blk : out std_logic_vector(log2_ceil(MAX_BLK_g) downto 0); - mlenfor : out std_logic_vector(log2_ceil(4**NUM_STAGES_g) downto 0); - mlentwo : out std_logic_vector(log2_ceil(4**NUM_STAGES_g) downto 0); - -- these are specific to the FFT, no effort has been made to optimize! - curr_pwr_2 : out std_logic; - curr_inverse : out std_logic; - curr_input_sel : out std_logic_vector(NUM_STAGES_g - 1 downto 0)); -end component auk_dspip_avalon_streaming_block_sink_fftfprvs; - - -end package auk_dspip_lib_pkg; diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd b/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd deleted file mode 100644 index 305288c..0000000 --- a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd +++ /dev/null @@ -1,367 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - -------------------------------------------------------------------------- -------------------------------------------------------------------------- --- --- Revision Control Information --- --- $RCSfile: auk_dspip_math_pkg.vhd,v $ --- $Source: /cvs/uksw/dsp_cores/lib/packages/auk_dspip_math_pkg.vhd,v $ --- --- $Revision: #1 $ --- $Date: 2018/07/18 $ --- Check in by : $Author: psgswbuild $ --- Author : DSP_IP --- --- Project : --- --- Description : --- --- Common functions for DSP_IP cores. --- --- --- $Log: auk_dspip_math_pkg.vhd,v $ --- Revision 1.4 2006/07/28 18:52:50 sdemirso --- no compilation errors with the new directory structure --- --- Revision 1.3 2006/07/28 10:27:30 sdemirso --- Header updated --- --- ALTERA Confidential and Proprietary --- Copyright 2006 (c) Altera Corporation --- All rights reserved --- -------------------------------------------------------------------------- -------------------------------------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; -PACKAGE auk_dspip_math_pkg IS - - - ----------------------------------------------------------------------------- - -- NOTE that these log functions are not intended to synthesize directly - -- into hardware, rather they are used to generate constants for - -- synthesized hardware. - ----------------------------------------------------------------------------- - --------------------------------------------------------------------------- - -- LOG2_CEIL Function. - -- Effectively performs log2() followed by ceil() - -- e.g. CEIL_LOG2(255) returns 8 - -- CEIL_LOG2(256) returns 8 - -- CEIL_LOG2(257) returns 9 - --------------------------------------------------------------------------- - function log2_ceil(arg : in integer) return integer; - function log2_ceil_one(arg : in integer) return integer; -- log2_ceil(1)=0 - --------------------------------------------------------------------------- - -- LOG2_FLOOR Function. - -- Effectively performs log2() followed by floor() - -- e.g. CEIL_LOG2(255) returns 7 - -- CEIL_LOG2(256) returns 8 - -- CEIL_LOG2(257) returns 8 - --------------------------------------------------------------------------- - function log2_floor(arg : in integer) return integer; - - ----------------------------------------------------------------------------- - -- SIGN functions - ----------------------------------------------------------------------------- - -- returns the sign bit of a vector - function sign (arg : in signed) return std_logic; - - -- sign extends ARG to size SIZE. - function sign_extend (arg : in signed; size : in positive) return signed; - - -- sign extend one bit - function xt1 (arg : in signed) return signed; - - --------------------------------------------------------------------------- - -- Arithmetic FUNCTIONs. - --------------------------------------------------------------------------- - -- Check integer for odd-ness - function is_odd(arg : integer) return boolean; - - ----------------------------------------------------------------------------- - -- Logical functions - ----------------------------------------------------------------------------- - -- Result of and'ing all of the bits of the vector. - function and_reduce(arg : std_logic_vector) return std_logic; - function and_reduce(arg : unsigned) return std_logic; - - -- Result of or'ing all of the bits of the vector. - function or_reduce(arg : std_logic_vector) return std_logic; - function or_reduce(arg : unsigned) return std_logic; - - -- returns index+1 of the highest asserted bit. - function highest_one(arg : unsigned) return natural; - - -- returns index+1 of the lowest asserted bit. - function lowest_one(arg : unsigned) return natural; - - -- returns the count of number of ones. - function count_ones(arg : unsigned) return natural; - - -- Bit reverse - function bit_reverse(arg : unsigned) return unsigned; - - -- Invert the argument bitwise - function invert(arg : unsigned) return unsigned; - - --Halve towards up - function halve_ceil(arg:natural) return natural; - - function div_ceil(a:natural;b:natural) return natural; - -END PACKAGE auk_dspip_math_pkg; - -package body auk_dspip_math_pkg is - --------------------------------------------------------------------------- - -- LOG2_CEIL Function. - --------------------------------------------------------------------------- - function log2_ceil(arg : in integer) return integer is - variable res : integer; - begin - res := 0; - for i in 0 to 30 loop - if (arg > (2**i)) then - res := i+1; - end if; - end loop; -- i - return res; - end log2_ceil; - --------------------------------------------------------------------------- - -- LOG2_CEIL_ONE Function. - --------------------------------------------------------------------------- - function log2_ceil_one(arg : in integer) return integer is - variable res : integer; - begin - res := 0; - for i in 0 to 30 loop - if (arg > (2**i)) then - res := i+1; - end if; - end loop; -- i - if res = 0 then - res := 1; - end if; - return res; - end log2_ceil_one; - - --------------------------------------------------------------------------- - -- LOG2_FLOOR Function. - ----------------------------------------------------------------------------- - function log2_floor(arg : in integer) return integer is - variable res : integer; - begin - res := 0; - for i in 0 to 30 loop - if (arg >= (2**i)) then - res := i; - end if; - end loop; -- i - return res; - end log2_floor; - - ----------------------------------------------------------------------------- - -- SIGN Function - ----------------------------------------------------------------------------- - function sign (arg : in signed) return std_logic is - variable res : std_logic; - begin - res := arg(arg'left); - return(res); - end sign; - - ----------------------------------------------------------------------------- - -- SIGN_EXTEND Function - ----------------------------------------------------------------------------- - function sign_extend (arg : in signed; size : in positive) return signed is - variable res : signed(size-1 downto 0); - begin - if arg'length > size then - assert arg'length < size report "WARNING, can't sign extend" severity warning; - end if; - for i in arg'length to size-1 loop - res(i) := arg(arg'left); - end loop; -- i - res(arg'length-1 downto 0) := arg; - return(res); - end sign_extend; - - ----------------------------------------------------------------------------- - -- XT1 Function - ----------------------------------------------------------------------------- - function xt1 (arg : in signed) return signed is - variable res : signed(arg'length downto 0); - begin - res := arg(arg'left) & arg; - return(res); - end xt1; - - ----------------------------------------------------------------------------- - -- IS_ODD Function - ----------------------------------------------------------------------------- - function is_odd(arg : integer) return boolean is - begin - return ((arg mod 2) = 1); - end is_odd; - - - ----------------------------------------------------------------------------- - -- AND_REDUCE Function - ----------------------------------------------------------------------------- - function and_reduce(arg : std_logic_vector) return std_logic is - variable res : std_logic; - begin - res := '1'; - for i in arg'range loop - res := res and arg(i); - end loop; - return res; - end; - - function and_reduce(arg : unsigned) return std_logic is - variable res : std_logic; - begin - res := '1'; - for i in arg'range loop - res := res and arg(i); - end loop; - return res; - end; - - - ----------------------------------------------------------------------------- - -- OR_REDUCE Function - ----------------------------------------------------------------------------- - function or_reduce(arg : unsigned) return std_logic is - variable res : std_logic; - begin - res := '0'; - for i in arg'range loop - res := res or arg(i); - end loop; - return res; - end; - - function or_reduce(arg : std_logic_vector) return std_logic is - variable res : std_logic; - begin - res := '0'; - for i in arg'range loop - res := res or arg(i); - end loop; - return res; - end; - - --------------------------------------------------------------------------- - -- HIGHEST_ONE Function. - --------------------------------------------------------------------------- - -- Returns index+1 of the highest asserted bit, or 0 if no bit set. - -- Vector is evaluated from left to right, not high to low! - function highest_one(arg : unsigned) return natural is - begin - for i in arg'range loop - if arg(i) = '1' then - return i+1; - end if; - end loop; - return 0; - end; - - ----------------------------------------------------------------------------- - -- LOWEST_ONE Function - ----------------------------------------------------------------------------- - -- Returns index+1 of the lowest asserted bit, or 0 if no bit set. - -- Vector is evaluated from left to right, not high to low! - function lowest_one(arg : unsigned) return natural is - begin - for i in 0 to arg'length-1 loop - if (arg(i) = '1') then - return(i+1); - end if; - end loop; - return(0); - end; - - ----------------------------------------------------------------------------- - -- COUNT_ONES - --------------------------------------------------------------------------- - -- Returns the count of the number of ones. - function count_ones(arg : unsigned) return natural is - variable count : integer; - begin - count := 0; - for i in 0 to arg'length-1 loop - if (arg(i) = '1') then - count := count + 1; - end if; - end loop; - return count; - end; - - ----------------------------------------------------------------------------- - -- BIT_REVERSE function - ----------------------------------------------------------------------------- - function bit_reverse(arg : unsigned) return unsigned is - variable res : unsigned(arg'range); - begin - for i in arg'range loop - res(i) := arg(arg'high - i); - end loop; - return(res); - end; - - ----------------------------------------------------------------------------- - -- INVERT Function - ----------------------------------------------------------------------------- - function invert(arg : unsigned) - return unsigned -- (word'high downto 0) - is - variable res : unsigned(arg'high downto 0); - begin - - for i in arg'range loop - res(i) := not arg(i); - end loop; - return (res); - end invert; - - ----------------------------------------------------------------------------- - -- HALVE_CEIL Function - ----------------------------------------------------------------------------- - function halve_ceil(arg : natural) return natural is - variable res : natural; - begin - if is_odd(arg) then - res := (arg+1)/2; - else - res := arg/2; - end if; - return (res); - end halve_ceil; - -------------------------------------------------------------------------------- --- DIV_CEIL function -------------------------------------------------------------------------------- - function div_ceil(a : natural; b : natural) return natural is - variable res : natural := a/b; - begin - if res*b /= a then - res := res +1; - end if; - return res; - end div_ceil; - -end package body auk_dspip_math_pkg; diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd b/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd deleted file mode 100644 index 54149f3..0000000 --- a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd +++ /dev/null @@ -1,309 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - -------------------------------------------------------------------------- -------------------------------------------------------------------------- --- --- Revision Control Information --- --- $RCSfile: auk_dspip_fast_accumulator.vhd,v $ --- $Source: /cvs/uksw/dsp_cores/lib/fu/fast_accum/rtl/auk_dspip_fast_accumulator.vhd,v $ --- --- $Revision: #1 $ --- $Date: 2018/07/18 $ --- Check in by : $Author: psgswbuild $ --- Author : Alex Diaz-Manero --- --- Project : FIR --- --- Description : --- --- Fast pipelined Accumulator for fast filters --- --- --- $Log: auk_dspip_fast_accumulator.vhd,v $ --- Revision 1.2 2007/10/09 19:08:16 admanero --- slight mod to avoid propagation of X through Sum at MSB bits --- --- Revision 1.1 2007/09/24 16:59:34 admanero --- first revision of fast (pipelined) accumulator. --- --- --- ALTERA Confidential and Proprietary --- Copyright 2007 (c) Altera Corporation --- All rights reserved --- -------------------------------------------------------------------------- -------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.auk_dspip_math_pkg.all; ---use auk_dspip_lib.auk_dspip_lib_pkg.all; - - -entity auk_dspip_pipelined_adder is - generic ( - -- This adder assumes that both operands datain1 and datain2 are of the same data width - -- if that is not the case and the shorter word is (sign) expanded to the size of the bigger then - -- a penalty is incurred in the pipelined implementation. - -- But for the time being I only need the same size :-) So don't make your life too difficult - INWIDTH_g : natural := 42; - -- width of lab in selected device ( 10 or 16 in Cyclone, - -- Cylone II, Stratix and Stratix II. - -- Alex : should I use 19 bits for Stratix III? - -- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency. - -- Shall I have family generic to set labwidth? - LABWIDTH_g : natural := 38); - port ( - datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); - datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); - clk : in std_logic; - enable : in std_logic; - reset : in std_logic; - dataout : out std_logic_vector(INWIDTH_g downto 0)); -end auk_dspip_pipelined_adder; - - -architecture rtl of auk_dspip_pipelined_adder is - - type NATURAL_ARRAY is array(NATURAL RANGE <>) of NATURAL; - - -- IN_OR_OUT is 0 for IN and 1 for ADD (OUT) - function calc_number_of_stages(FULL_WIDTH, LABWIDTH, IN_OR_OUT : natural) return natural is - variable tmp : natural; - variable result : natural; - begin - tmp := FULL_WIDTH; - result := 0; - while tmp > LABWIDTH+IN_OR_OUT loop - tmp := tmp - LABWIDTH; - result := result + 1; - end loop; - - return result; - end calc_number_of_stages; - - - function calc_width_of_stages(FULL_WIDTH, LABWIDTH, IN_OR_OUT : natural) return natural_array is - Constant STAGES_c : natural := calc_number_of_stages(FULL_WIDTH, LABWIDTH, IN_OR_OUT); - variable tmp : natural; - variable result : natural_array(stages_c downto 0); - begin - tmp := FULL_WIDTH; - for I in 0 to STAGES_c loop - if I=STAGES_c then - result(I) := tmp; - else - result(I) := LABWIDTH; - tmp := tmp - LABWIDTH; - end if; - end loop; - return result; - - end calc_width_of_stages; - --- This stages_c will be either 0, 1 or 2. Rarely it will be 3. --- 39 "divided" by 19 still should yield just 1 (2 stages). but for 40 it should 2 (3 stages) --- So, it should be a function not a just a division. --- For an adder, for simplicity, shouldn't I have the same stages for input and output? Well, leave it like this anyways - Constant STAGES_ADD_c : natural := calc_number_of_stages(INWIDTH_g+1, LABWIDTH_g, 1); --ACCUM_OUT_WIDTH_g / LABWIDTH_g; - Constant WIDTH_STAGES_ADD_c : natural_array(STAGES_ADD_c downto 0) := calc_width_of_stages(INWIDTH_g+1, LABWIDTH_g, 1); - Constant STAGES_IN_c : natural := calc_number_of_stages(INWIDTH_g, LABWIDTH_g, 0); - Constant WIDTH_STAGES_IN_c : natural_array(STAGES_IN_c downto 0) := calc_width_of_stages(INWIDTH_g, LABWIDTH_g, 0); - - type TRIANGLE_DELAY_t is array (natural range<>, natural range<>) of std_logic_vector(LABWIDTH_g-1 downto 0); - type TRIANGLE_DELAY_P1_t is array (natural range<>, natural range<>) of std_logic_vector(LABWIDTH_g downto 0); - type COLUMN_VECTOR_t is array (natural range<>) of std_logic_vector(LABWIDTH_g downto 0); - - signal input1_side_data_scaled_delay_q : TRIANGLE_DELAY_t(STAGES_IN_c downto 0, STAGES_IN_c downto 0); - signal input1_side_data_scaled_delay_d : TRIANGLE_DELAY_t(STAGES_IN_c downto 0, STAGES_IN_c downto 0); - signal input2_side_data_scaled_delay_q : TRIANGLE_DELAY_t(STAGES_IN_c downto 0, STAGES_IN_c downto 0); - signal input2_side_data_scaled_delay_d : TRIANGLE_DELAY_t(STAGES_IN_c downto 0, STAGES_IN_c downto 0); - signal output_side_data_scaled_delay_q : TRIANGLE_DELAY_P1_t(STAGES_ADD_c downto 0, STAGES_ADD_c downto 0); - signal output_side_data_scaled_delay_d : TRIANGLE_DELAY_P1_t(STAGES_ADD_c downto 0, STAGES_ADD_c downto 0); - signal datai1_int : COLUMN_VECTOR_t(STAGES_ADD_c downto 0); - signal datai2_int : COLUMN_VECTOR_t(STAGES_ADD_c downto 0); - signal datao_int : COLUMN_VECTOR_t(STAGES_ADD_c downto 0); - signal cout_cin_d : std_logic_vector(STAGES_ADD_c+1 downto 0); - signal cout_cin_q : std_logic_vector(STAGES_ADD_c+1 downto 0); - signal enb : std_logic; - - -begin - - enb <= enable; - - ifg4: if STAGES_ADD_c>0 generate - reg2 : process(clk, reset) is - begin - if reset = '1' then - cout_cin_q(STAGES_ADD_c+1 downto 1) <= (others => '0'); - elsif rising_edge(clk) then - if enb = '1' then - cout_cin_q(STAGES_ADD_c+1 downto 1) <= cout_cin_d(STAGES_ADD_c+1 downto 1); - end if; - end if; - end process reg2; - end generate ifg4; - - cout_cin_q(0) <= '0'; - - fg1: for J in 0 to STAGES_IN_c generate - - fg1c: for I in 0 to STAGES_IN_c generate - ifg6b: if I <= 1 generate - input1_side_data_scaled_delay_d(I, J)(WIDTH_STAGES_IN_c(J)-1 downto 0) <= datain1(WIDTH_STAGES_IN_c(J)-1 + J*LABWIDTH_g downto J*LABWIDTH_g); - input2_side_data_scaled_delay_d(I, J)(WIDTH_STAGES_IN_c(J)-1 downto 0) <= datain2(WIDTH_STAGES_IN_c(J)-1 + J*LABWIDTH_g downto J*LABWIDTH_g); - end generate ifg6b; - ifg7b: if I > 1 generate - input1_side_data_scaled_delay_d(I, J)(LABWIDTH_g-1 downto 0) <= input1_side_data_scaled_delay_q(I-1, J)(LABWIDTH_g-1 downto 0); - input2_side_data_scaled_delay_d(I, J)(LABWIDTH_g-1 downto 0) <= input2_side_data_scaled_delay_q(I-1, J)(LABWIDTH_g-1 downto 0); - end generate ifg7b; - end generate fg1c; - - end generate fg1; - - reg : process(clk, reset) is - begin - if reset = '1' then - loop1: for I in 1 to STAGES_IN_c loop - loop2: for J in I to STAGES_IN_c loop - input1_side_data_scaled_delay_q(I, J) <= (others => '0'); - input2_side_data_scaled_delay_q(I, J) <= (others => '0'); - end loop loop2; - end loop loop1; - elsif rising_edge(clk) then - if enb = '1' then - loop3: for I in 1 to STAGES_IN_c loop - loop4: for J in I to STAGES_IN_c loop - input1_side_data_scaled_delay_q(I, J) <= input1_side_data_scaled_delay_d(I, J); - input2_side_data_scaled_delay_q(I, J) <= input2_side_data_scaled_delay_d(I, J); - end loop loop4; - end loop loop3; - end if; - end if; - end process reg; - - adding: process(cout_cin_q, datai1_int, datai2_int) - variable tmp_debug_s : signed(LABWIDTH_g downto 0); - variable tmp_debug_u : unsigned(LABWIDTH_g downto 0); - begin - --Only the upper most chunk sum is signed, the other chunks ought to be unsigned - for I in 0 to STAGES_ADD_c loop - if I=STAGES_ADD_c then - if cout_cin_q(I)='1' then - --datao_int(I) <= signed(datai_int(I)) + signed(datas_int(I)) + natural(1); - tmp_debug_s(WIDTH_STAGES_ADD_c(I)-1 downto 0) := signed(datai1_int(I)(WIDTH_STAGES_ADD_c(I)-1 downto 0)) + signed(datai2_int(I)(WIDTH_STAGES_ADD_c(I)-1 downto 0)) + natural(1); - else - --datao_int(I) <= signed(datai_int(I)) + signed(datas_int(I)) + natural(0); - tmp_debug_s(WIDTH_STAGES_ADD_c(I)-1 downto 0) := signed(datai1_int(I)(WIDTH_STAGES_ADD_c(I)-1 downto 0)) + signed(datai2_int(I)(WIDTH_STAGES_ADD_c(I)-1 downto 0)) + natural(0); - end if; - - datao_int(I) <= std_logic_vector(tmp_debug_s); - cout_cin_d(I+1) <= tmp_debug_s(LABWIDTH_g); - else - if cout_cin_q(I)='1' then - --datao_int(I) <= unsigned(datai_int(I)) + unsigned(datas_int(I)) + natural(1); - tmp_debug_u := unsigned(datai1_int(I)) + unsigned(datai2_int(I)) + natural(1); - else - --datao_int(I) <= unsigned(datai_int(I)) + unsigned(datas_int(I)) + natural(0); - tmp_debug_u := unsigned(datai1_int(I)) + unsigned(datai2_int(I)) + natural(0); - end if; - datao_int(I) <= std_logic_vector(tmp_debug_u); - cout_cin_d(I+1) <= tmp_debug_u(LABWIDTH_g); - end if; - end loop; - end process adding; - - - --Always STAGES_ADD_c >= STAGES_IN_c - --when it is greater it needs special handling - fg1b: for I in 0 to STAGES_ADD_c generate - - --I need to split STAGES_ADD_c from STAGES_IN_c - fg2: for J in 0 to I generate - ifg1a: if J=0 and I=0 generate - --In reality the chunks below the MSB are unsigned. Only the upper most (MSB) chunk is signed - -- - datai1_int(I)(WIDTH_STAGES_IN_c(I) downto 0) <= std_logic_vector('0' & input1_side_data_scaled_delay_d(0, 0)(WIDTH_STAGES_IN_c(I)-1 downto 0)); - datai2_int(I)(WIDTH_STAGES_IN_c(I) downto 0) <= std_logic_vector('0' & input2_side_data_scaled_delay_d(0, 0)(WIDTH_STAGES_IN_c(I)-1 downto 0)); - end generate ifg1a; - ifg1: if J=I and I0 and J>0 generate - --In reality the chunks below the MSB are unsigned. Only the upper most (MSB) chunk is signed - datai1_int(I)(WIDTH_STAGES_IN_c(I) downto 0) <= std_logic_vector('0' & input1_side_data_scaled_delay_q(I, J)(WIDTH_STAGES_IN_c(I)-1 downto 0)); - datai2_int(I)(WIDTH_STAGES_IN_c(I) downto 0) <= std_logic_vector('0' & input2_side_data_scaled_delay_q(I, J)(WIDTH_STAGES_IN_c(I)-1 downto 0)); - end generate ifg1; - -------- - --Could it be possible to have STAGES_ADD_c > STAGES_IN_c ? yes, it could => sign extension stages needed herefor datai_int - ifg2a: if J=I and I>=STAGES_IN_c and I STAGES_IN_c) - datai1_int(I)(LABWIDTH_g downto 0) <= std_logic_vector(sign_extend(signed(input1_side_data_scaled_delay_q(STAGES_IN_c, J)(WIDTH_STAGES_IN_c(STAGES_IN_c)-1 downto 0)), LABWIDTH_g+1)); - datai2_int(I)(LABWIDTH_g downto 0) <= std_logic_vector(sign_extend(signed(input2_side_data_scaled_delay_q(STAGES_IN_c, J)(WIDTH_STAGES_IN_c(STAGES_IN_c)-1 downto 0)), LABWIDTH_g+1)); - --this last chunk doesn't need sign extension, it would need it if we wanted carry out (i.e. for overflow) - end generate ifg2a; - -------- - -- Only the MSB chunk needs to be signed. Question: Is there a need for a pipelined accumulator with unsigned data? - ifg2: if J=I and I=STAGES_ADD_c generate - datai1_int(I)(LABWIDTH_g downto 0) <= std_logic_vector(sign_extend(signed(input1_side_data_scaled_delay_q(STAGES_IN_c, J)(WIDTH_STAGES_IN_c(STAGES_IN_c)-1 downto 0)), LABWIDTH_g+1)); - datai2_int(I)(LABWIDTH_g downto 0) <= std_logic_vector(sign_extend(signed(input2_side_data_scaled_delay_q(STAGES_IN_c, J)(WIDTH_STAGES_IN_c(STAGES_IN_c)-1 downto 0)), LABWIDTH_g+1)); - --this last chunk doesn't need sign extension, it would need it if we wanted carry out (i.e. for overflow) - end generate ifg2; - end generate fg2; - - - -- output connection, MSB chunk from _d the remainder from _q - ifg3: if I=STAGES_ADD_c generate - dataout(WIDTH_STAGES_ADD_c(I)-1+LABWIDTH_g*I downto LABWIDTH_g*I) <= output_side_data_scaled_delay_d(STAGES_ADD_c-I, I)(WIDTH_STAGES_ADD_c(I)-1 downto 0); - end generate ifg3; - ifg4: if I 1 generate - output_side_data_scaled_delay_d(I, J)(LABWIDTH_g-1 downto 0) <= output_side_data_scaled_delay_q(I-1, J)(LABWIDTH_g-1 downto 0); - end generate ifg7; - end generate fg3b; - - end generate fg3a; - -- - reg_o : process(clk, reset) is - begin - if reset = '1' then - loop1: for I in 1 to STAGES_ADD_c loop - loop2: for J in 0 to STAGES_ADD_c-I loop - output_side_data_scaled_delay_q(I, J) <= (others => '0'); - end loop loop2; - end loop loop1; - elsif rising_edge(clk) then - if enb = '1' then - loop3: for I in 1 to STAGES_ADD_c loop - loop4: for J in 0 to STAGES_ADD_c-I loop - output_side_data_scaled_delay_q(I, J) <= output_side_data_scaled_delay_d(I, J); - end loop loop4; - end loop loop3; - end if; - end if; - end process reg_o; - -end rtl; - diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd b/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd deleted file mode 100644 index 70665a2..0000000 --- a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd +++ /dev/null @@ -1,438 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - -------------------------------------------------------------------------- -------------------------------------------------------------------------- --- --- Revision Control Information --- --- $RCSfile: auk_dspip_roundsat.vhd,v $ --- $Source: /cvs/uksw/dsp_cores/lib/fu/roundsat/rtl/auk_dspip_roundsat.vhd,v $ --- --- $Revision: #1 $ --- $Date: 2018/07/18 $ --- Check in by : $Author: psgswbuild $ --- Author : Volker Mauer --- --- Project : common FU library --- --- Description : --- --- This functional unit can be used to implement various forms of --- rounding, saturation and truncation. --- --- ALTERA Confidential and Proprietary --- Copyright 2006 (c) Altera Corporation --- All rights reserved --- -------------------------------------------------------------------------- -------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -entity auk_dspip_roundsat is - generic ( - IN_WIDTH_g : natural := 8; -- data width - OUT_WIDTH_g : natural := 8; -- data width - ROUNDING_TYPE_g : string := "TRUNCATE_LOW"; - LATENCY : natural := 1 - ); - - port ( - clk : in std_logic; - reset : in std_logic; - enable : in std_logic; -- global clock enable - datain : in std_logic_vector(IN_WIDTH_g-1 downto 0); - dataout : out std_logic_vector(OUT_WIDTH_g-1 downto 0)); -end entity auk_dspip_roundsat; - -architecture beh of auk_dspip_roundsat is - -begin -- architecture beh - - ----------------------------------------------------------------------------- - -- truncate low - ----------------------------------------------------------------------------- - trunc_low: if ROUNDING_TYPE_g = "TRUNCATE_LOW" generate - begin -- generate trunc_low - trunc_low_p: process (clk) is - begin -- process trunc_low_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - dataout <= datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g); - end if; - end if; - end if; - end process trunc_low_p; - end generate trunc_low; - - ----------------------------------------------------------------------------- - -- truncate high - ----------------------------------------------------------------------------- - trunc_high: if ROUNDING_TYPE_g = "TRUNCATE_HIGH" generate - begin -- generate trunc_high - trunc_high_p: process (clk) is - begin -- process trunc_high_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - dataout <= datain(OUT_WIDTH_g-1 downto 0); - end if; - end if; - end if; - end process trunc_high_p; - end generate trunc_high; - - ----------------------------------------------------------------------------- - -- saturation - ----------------------------------------------------------------------------- - sat : if ROUNDING_TYPE_g = "SATURATE" generate - begin -- generate sat - sat_p : process (clk) is - begin -- process sat_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- synchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - if signed(datain) > 2**(OUT_WIDTH_g-1)-1 then - dataout <= std_logic_vector(to_signed(2**(OUT_WIDTH_g-1)-1, OUT_WIDTH_g)); - elsif signed(datain) < -2**(OUT_WIDTH_g-1) then - dataout <= std_logic_vector(to_signed(-2**(OUT_WIDTH_g-1), OUT_WIDTH_g)); - else - dataout <= datain(OUT_WIDTH_g-1 downto 0); - end if; - end if; - end if; - end if; - end process sat_p; - end generate sat; - - ----------------------------------------------------------------------------- - -- symmetrical saturation - ----------------------------------------------------------------------------- - satsym : if ROUNDING_TYPE_g = "SATURATE_SYM" generate - begin -- generate satsym - satsym_p : process (clk) is - begin -- process satsym_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - if signed(datain) > 2**(OUT_WIDTH_g-1)-1 then - dataout <= std_logic_vector(to_signed(2**(OUT_WIDTH_g-1)-1, OUT_WIDTH_g)); - elsif signed(datain) < -2**(OUT_WIDTH_g-1)+1 then - dataout <= std_logic_vector(to_signed(-2**(OUT_WIDTH_g-1)+1, OUT_WIDTH_g)); - else - dataout <= datain(OUT_WIDTH_g-1 downto 0); - end if; - end if; - end if; - end if; - end process satsym_p; - end generate satsym; - - ----------------------------------------------------------------------------- - -- simple rounding (always rounds up) - ----------------------------------------------------------------------------- - round : if ROUNDING_TYPE_g = "ROUND_UP" generate - - signal RB : std_logic; -- rounding bit (MSB of discarded bit) - - begin -- generate round - ----------------------------------------------------------------------------- - -- get relevant bits - ----------------------------------------------------------------------------- - RB <= datain(IN_WIDTH_g-OUT_WIDTH_g-1); - - round_p : process (clk) is - begin -- process round_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - if RB = '1' then - dataout <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g))+1); - else - dataout <= datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g); - end if; - end if; - end if; - end if; - end process round_p; - end generate round; - - ----------------------------------------------------------------------------- - -- round towards 0 - ----------------------------------------------------------------------------- - round0 : if ROUNDING_TYPE_g = "ROUND0" generate - signal SB : std_logic; -- sign bit - begin -- generate round0 - - SB <= datain(IN_WIDTH_g-1); - - round0_p : process (clk) is - variable OR_accu : std_logic := '0'; - begin -- process round0_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - OR_accu := '0'; - for i in 0 to IN_WIDTH_g-OUT_WIDTH_g-1 loop - OR_accu := OR_accu or datain(i); - end loop; -- i - if SB = '1' and OR_accu = '1' then - dataout <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g))+1); - else - dataout <= datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g); - end if; - end if; - end if; - end if; - end process round0_p; - end generate round0; - - ----------------------------------------------------------------------------- - -- round away from 0 - ----------------------------------------------------------------------------- - round_up_sym : if ROUNDING_TYPE_g = "ROUND_UP_SYM" generate - signal SB : std_logic; -- sign bit - signal SB_delayed : std_logic; -- sign bit, delayed - signal RB : std_logic; -- rounding bit (MSB of discarded bit) - signal dataout_temp : std_logic_vector(OUT_WIDTH_g-1 downto 0); - -- internal, readable version of dataoout - - begin -- generate round_up_sym - - SB <= datain(IN_WIDTH_g-1); - RB <= datain(IN_WIDTH_g-OUT_WIDTH_g-1); - - round_up_sym_p : process (clk) is - variable OR_accu : std_logic := '0'; - begin -- process round_up_sym_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout_temp <= (others => '0'); - SB_delayed <= '0'; - else - if enable = '1' then - SB_delayed <= SB; - OR_accu := '0'; - for i in 0 to IN_WIDTH_g-OUT_WIDTH_g-1 loop - OR_accu := OR_accu or datain(i); - end loop; -- i - if (SB = '0' and RB = '1') or (SB = '1' and RB='1' and OR_accu='1') then - dataout_temp <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g))+1); - else - dataout_temp <= datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g); - end if; - end if; - end if; - end if; - end process round_up_sym_p; - - dataout <= dataout_temp; - - assert not(SB_delayed = '0' and dataout_temp(OUT_WIDTH_g-1 downto OUT_WIDTH_g-2)="10") report "Overflow during rounding, dataout invalid. This condition occurs when ROUND_UP_SYM is selected for rounding, and a large integer appears at the input. Please consider changing rounding mode to CONVERGENT rounding, where overflows cannot happen, or apply SATURATION first." severity warning; - - end generate round_up_sym; - - ----------------------------------------------------------------------------- - -- convergent rounding - ----------------------------------------------------------------------------- - conv_round_1 : if ROUNDING_TYPE_g = "CONV_ROUND" and LATENCY = 1 generate - signal LSB : std_logic; -- least significant retained bit - signal RB : std_logic; -- rounding bit (MSB of discarded bit) - - begin -- generate conv_round - - ----------------------------------------------------------------------------- - -- get relevant bits - ----------------------------------------------------------------------------- - RB <= datain(IN_WIDTH_g-OUT_WIDTH_g-1); - LSB <= datain(IN_WIDTH_g-OUT_WIDTH_g); - - conv_round_p1 : process (clk) is - variable OR_accu : std_logic := '0'; - begin -- process conv_round_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - OR_accu := '0'; - for i in 0 to IN_WIDTH_g-OUT_WIDTH_g-2 loop - OR_accu := OR_accu or datain(i); - end loop; -- i - if RB = '1' and (LSB = '1' or OR_accu = '1') then - dataout <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g))+1); - else - dataout <= datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g); - end if; - end if; - end if; - end if; - end process conv_round_p1; - end generate conv_round_1; - - - conv_round_2 : if ROUNDING_TYPE_g = "CONV_ROUND" and LATENCY = 2 generate - signal LSB : std_logic; -- least significant retained bit - signal RB : std_logic; -- rounding bit (MSB of discarded bit) - signal datareg : std_logic_vector(IN_WIDTH_g-1 downto 0); - signal OR_accu : std_logic; - - begin -- generate conv_round - - ----------------------------------------------------------------------------- - -- get relevant bits - ----------------------------------------------------------------------------- - - conv_round_p : process(clk) is - variable OR_Temp : std_logic := '0'; - begin - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - RB <= '0'; - LSB <= '0'; - OR_accu <= '0'; - datareg <= (others =>'0'); - else - if enable = '1' then - OR_Temp := '0'; - for i in 0 to IN_WIDTH_g-OUT_WIDTH_g-2 loop - OR_Temp := OR_Temp or datain(i); - end loop; -- - RB <= datain(IN_WIDTH_g-OUT_WIDTH_g-1); - LSB <= datain(IN_WIDTH_g-OUT_WIDTH_g); - OR_accu <= OR_Temp; - datareg <= datain; - end if; - end if; - end if; - end process conv_round_p; - - conv_round_p2 : process (clk) is - begin -- process conv_round_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - if RB = '1' and (LSB = '1' or OR_accu = '1') then - dataout <= std_logic_vector(signed(datareg(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g))+1); - else - dataout <= datareg(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g); - end if; - end if; - end if; - end if; - end process conv_round_p2; - end generate conv_round_2; - - -conv_round_3 : if ROUNDING_TYPE_g = "CONV_ROUND" and LATENCY = 3 generate - signal LSB,LSB_R : std_logic; -- least significant retained bit - signal RB,RB_R : std_logic; -- rounding bit (MSB of discarded bit) - signal datareg, datareg_2 : std_logic_vector(IN_WIDTH_g-1 downto 0); - signal OR_accu_1, OR_accu_2 : std_logic; - signal OR_accu : std_logic; - - begin -- generate conv_round - - ----------------------------------------------------------------------------- - -- get relevant bits - ----------------------------------------------------------------------------- - - conv_round_p : process(clk) is - variable OR_Temp_2,OR_Temp_1 : std_logic := '0'; - begin - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - RB <= '0'; - LSB <= '0'; - RB_R <= '0'; - LSB_R <= '0'; - OR_accu_1 <= '0'; - OR_accu_2 <= '0'; - datareg <= (others =>'0'); - else - if enable = '1' then - OR_Temp_1 := '0'; - OR_Temp_2 := '0'; - for i in 0 to (IN_WIDTH_g-OUT_WIDTH_g-2)/2 loop - OR_Temp_1 := OR_Temp_1 or datain(i); - end loop; -- - for i in ((IN_WIDTH_g-OUT_WIDTH_g-2)/2)+1 to (IN_WIDTH_g-OUT_WIDTH_g-2) loop - OR_Temp_2 := OR_Temp_2 or datain(i); - end loop; -- RB <= datain(IN_WIDTH_g-OUT_WIDTH_g-1); - LSB <= datain(IN_WIDTH_g-OUT_WIDTH_g); - LSB_R <= LSB; - RB <= datain(IN_WIDTH_g-OUT_WIDTH_g-1); - RB_R <= RB; - OR_accu_1 <= OR_Temp_1; - OR_accu_2 <= OR_Temp_2; - OR_accu <= OR_accu_1 or OR_accu_2; - datareg <= datain; - datareg_2 <= datareg; - end if; - end if; - end if; - end process conv_round_p; - - conv_round_p2 : process (clk) is - begin -- process conv_round_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - if RB_R = '1' and (LSB_R = '1' or OR_accu = '1') then - dataout <= std_logic_vector(signed(datareg_2(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g))+1); - else - dataout <= datareg_2(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g); - end if; - end if; - end if; - end if; - end process conv_round_p2; - end generate conv_round_3; - ----------------------------------------------------------------------------- - -- error checking: - -- Have we got a valid rounding mode? - -- Is the input greater than the output? - ----------------------------------------------------------------------------- - assert (ROUNDING_TYPE_g = "SATURATE" or - ROUNDING_TYPE_g = "SATURATE_SYM" or - ROUNDING_TYPE_g = "ROUND_UP" or - ROUNDING_TYPE_g = "ROUND0" or - ROUNDING_TYPE_g = "ROUND_UP_SYM" or - ROUNDING_TYPE_g = "CONV_ROUND" or - ROUNDING_TYPE_g = "TRUNCATE_LOW" or - ROUNDING_TYPE_g = "TRUNCATE_HIGH" - ) report "Please check your rounding type and its spelling. Currently, we only support SATURATE, SATURATE_SYM, ROUND_UP, ROUND0, CONV_ROUND, TRUNCATE_LOW, TRUNCATE_HIGH" severity error; - assert (((LATENCY = 1) or (ROUNDING_TYPE_g = "CONV_ROUND" and (LATENCY = 3 or LATENCY = 2)))) report "Please check your Latency. Currently we only support latency for all modes and 2 latency for convergent round" severity error; - - -end architecture beh; diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd b/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd deleted file mode 100644 index c792d98..0000000 --- a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd +++ /dev/null @@ -1,121 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - -------------------------------------------------------------------------- -------------------------------------------------------------------------- --- --- Revision Control Information --- --- $RCSfile: auk_dspip_text_pkg.vhd,v $ --- $Source: /cvs/uksw/dsp_cores/lib/packages/auk_dspip_text_pkg.vhd,v $ --- --- $Revision: #1 $ --- $Date: 2018/07/18 $ --- Check in by : $Author: psgswbuild $ --- Author : DSP_IP --- --- Project : --- --- Description : --- --- Common functions for DSP_IP cores. --- --- --- $Log: auk_dspip_text_pkg.vhd,v $ --- Revision 1.2 2007/05/04 15:33:11 sdemirso --- merge from 7.1 --- --- Revision 1.1 2007/02/01 17:29:45 kmarks --- Initial commit --- --- Revision 1.5 2006/08/17 10:13:02 sdemirso --- log2_ceil_one function added --- --- Revision 1.4 2006/07/28 18:52:50 sdemirso --- no compilation errors with the new directory structure --- --- Revision 1.3 2006/07/28 10:27:30 sdemirso --- Header updated --- --- ALTERA Confidential and Proprietary --- Copyright 2006 (c) Altera Corporation --- All rights reserved --- -------------------------------------------------------------------------- -------------------------------------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; -PACKAGE auk_dspip_text_pkg IS - - - ----------------------------------------------------------------------------- - -- NOTE that these log functions are not intended to synthesize directly - -- into hardware, rather they are used to generate constants for - -- synthesized hardware. - ----------------------------------------------------------------------------- - type array_natural_t is array (natural range <>) of integer; - - function parse_string_array (str : string; size : natural) return array_natural_t; - - function str_to_int (str : string; base : string) return integer; - -END PACKAGE auk_dspip_text_pkg; - -package body auk_dspip_text_pkg is - --------------------------------------------------------------------------- - -- str_to_int Function. Only parses positive decimal values - --------------------------------------------------------------------------- - function str_to_int(str : string; base : string) return integer is - variable res : integer; - variable base_cnt : integer; - begin - res := 0; - base_cnt:=1; - for i in str'length downto 1 loop - if str(i) /= ' ' then - res := res + (character'pos(str(i)) - character'pos('0'))*base_cnt; - base_cnt:=base_cnt*10; - end if; - end loop; -- i - return res; - end str_to_int; - - --------------------------------------------------------------------------- - -- parse_string_array Function. - --------------------------------------------------------------------------- - function parse_string_array(str : string; size : natural) return array_natural_t is - variable this_str : string(1 to 32); - variable cnt_char : natural; -- how many characters have we seen - variable cnt_str : natural:=0; - variable res : array_natural_t(0 to size-1); - begin - this_str := (others => ' '); - cnt_char := 1; - for i in str'left to str'right loop - if str(i) = ',' then - res(cnt_str) := str_to_int(this_str, "DEC"); - cnt_char := 1; - cnt_str := cnt_str + 1; - this_str := (others => ' '); - else - this_str(cnt_char) := str(i); - cnt_char := cnt_char+1; - end if; - end loop; -- i - res(cnt_str) := str_to_int(this_str, "DEC"); - return res; - end parse_string_array; - - end package body auk_dspip_text_pkg; diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_upsample.vhd b/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_upsample.vhd deleted file mode 100644 index fdfa848..0000000 Binary files a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_upsample.vhd and /dev/null differ diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_variable_downsample.sv b/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_variable_downsample.sv deleted file mode 100644 index 76d2504..0000000 Binary files a/FPGA_61.440/db/ip/rx_cic/submodules/auk_dspip_variable_downsample.sv and /dev/null differ diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/counter_module.sv b/FPGA_61.440/db/ip/rx_cic/submodules/counter_module.sv deleted file mode 100644 index 4385698..0000000 Binary files a/FPGA_61.440/db/ip/rx_cic/submodules/counter_module.sv and /dev/null differ diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/hyper_pipeline_interface.v b/FPGA_61.440/db/ip/rx_cic/submodules/hyper_pipeline_interface.v deleted file mode 100644 index a9bd59a..0000000 Binary files a/FPGA_61.440/db/ip/rx_cic/submodules/hyper_pipeline_interface.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv b/FPGA_61.440/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv deleted file mode 100644 index 21c96d1..0000000 --- a/FPGA_61.440/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv +++ /dev/null @@ -1,217 +0,0 @@ -// (C) 2001-2018 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - - -module rx_cic_cic_ii_0 ( - in_data, - out_ready, - in_valid, - clk, - clken, - reset_n, - in_ready, - in_error, - out_error, - out_data, - out_valid - ); - - parameter DEVICE_FAMILY = "Cyclone IV E"; - - - - parameter FILTER_TYPE = "decimator"; - parameter STAGES = 6; - parameter D_DELAY = 1; - parameter VRC_EN = 0; - parameter RCF_MAX = 1280; - parameter RCF_MIN = 1280; - parameter INTERFACES = 1; - parameter CH_PER_INT = 1; - parameter INT_USE_MEM = "false"; - parameter INT_MEM = "auto"; - parameter DIF_USE_MEM = "false"; - parameter DIF_MEM = "auto"; - parameter IN_WIDTH = 23; - parameter OUT_WIDTH = 32; - parameter ROUND_TYPE = "TRUNCATE"; - parameter PIPELINING = 0; - - - parameter C_STAGE_0_WIDTH = 85; - parameter C_STAGE_1_WIDTH = 85; - parameter C_STAGE_2_WIDTH = 85; - parameter C_STAGE_3_WIDTH = 85; - parameter C_STAGE_4_WIDTH = 85; - parameter C_STAGE_5_WIDTH = 85; - parameter C_STAGE_6_WIDTH = 85; - parameter C_STAGE_7_WIDTH = 85; - parameter C_STAGE_8_WIDTH = 85; - parameter C_STAGE_9_WIDTH = 85; - parameter C_STAGE_10_WIDTH = 85; - parameter C_STAGE_11_WIDTH = 85; - parameter MAX_C_STAGE_WIDTH = 85; - - parameter I_STAGE_0_WIDTH = 85; - parameter I_STAGE_1_WIDTH = 85; - parameter I_STAGE_2_WIDTH = 85; - parameter I_STAGE_3_WIDTH = 85; - parameter I_STAGE_4_WIDTH = 85; - parameter I_STAGE_5_WIDTH = 85; - parameter I_STAGE_6_WIDTH = 85; - parameter I_STAGE_7_WIDTH = 85; - parameter I_STAGE_8_WIDTH = 85; - parameter I_STAGE_9_WIDTH = 85; - parameter I_STAGE_10_WIDTH = 85; - parameter I_STAGE_11_WIDTH = 85; - parameter MAX_I_STAGE_WIDTH = 85; - - localparam TOTAL_CHANNELS = CH_PER_INT*INTERFACES; - - localparam INTERFACES_IN = (FILTER_TYPE=="decimator" & INTERFACES > 1) ? INTERFACES : 1 ; - localparam INTERFACES_OUT = (FILTER_TYPE=="interpolator" & INTERFACES > 1) ? INTERFACES : 1 ; - localparam CHANNEL_SIZE_OUT = (FILTER_TYPE=="interpolator" & INTERFACES > 1) ? CH_PER_INT : TOTAL_CHANNELS ; - localparam CHANNEL_SIZE_IN = (FILTER_TYPE=="decimator" & INTERFACES > 1) ? CH_PER_INT : TOTAL_CHANNELS ; - localparam CHANNEL_OUT_WIDTH = (CHANNEL_SIZE_OUT > 1) ? $clog2(CHANNEL_SIZE_OUT) : 1; - localparam NUMBER_OF_CHANNELS = INTERFACES*CH_PER_INT; - localparam RATE_FACTOR_WIDTH = $clog2(RCF_MAX+1); - localparam CHANNEL_WIDTH = $clog2(TOTAL_CHANNELS); - localparam COUNTER_FS_MAX = RCF_MAX*NUMBER_OF_CHANNELS; - - //latency calculations - //localparam COMB_STAGE_LATENCY = 1; - //localparam COMB_SECTION_LATENCY = COMB_STAGE_LATENCY*STAGES; - //localparam INT_SECTION_LATENCY = (~INT_USE_MEM & PIPELINING > 1) ? PIPELINING*STAGES: STAGES*NUMBER_OF_CHANNELS; - //localparam MUX_LATENCY = NUMBER_OF_CHANNELS*(INTERFACES-1)+1; - //localparam DEC_SISO_LATENCY = COMB_SECTION_LATENCY + INT_SECTION_LATENCY; - //localparam INT_SISO_LATENCY = COMB_SECTION_LATENCY + INT_SECTION_LATENCY; - //localparam DEC_MISO_LATENCY = COMB_SECTION_LATENCY+INT_SECTION_LATENCY+2; - //localparam INT_SIMO_LATENCY = COMB_SECTION_LATENCY+INT_SECTION_LATENCY+MUX_LATENCY ; - //localparam S_LATENCY = (FILTER_TYPE == "decimator") ? DEC_SISO_LATENCY : INT_SISO_LATENCY; - //localparam M_LATENCY = (FILTER_TYPE == "decimator") ? DEC_MISO_LATENCY : INT_SIMO_LATENCY; - //localparam TOTAL_LATENCY = (INTERFACES > 1) ? M_LATENCY : S_LATENCY; - //localparam CLOCKS_PER_SAMPLE = RCF_MIN/INTERFACES; - - - - - - - - - - - -input clk; -input clken; -input reset_n; -logic [RATE_FACTOR_WIDTH-1:0] rate; -logic in_startofpacket; -logic in_endofpacket; -output in_ready; -input in_valid; -logic [CHANNEL_OUT_WIDTH-1:0] out_channel; -logic out_startofpacket; -logic out_endofpacket; -input [1:0] in_error; -output [1:0] out_error; -input out_ready; -output out_valid; -input [IN_WIDTH-1:0] in_data; -output [OUT_WIDTH-1:0] out_data; - -wire [IN_WIDTH-1:0] din [INTERFACES_IN-1:0]; -wire [OUT_WIDTH-1:0] dout [INTERFACES_OUT-1:0]; - - - - - -assign din[0] = in_data; - -assign out_data = dout[0]; -assign in_startofpacket = 1'b1; -assign in_endofpacket = 1'b1; -assign rate = '0; - - - - alt_cic_core #( - .DEVICE_FAMILY (DEVICE_FAMILY), - .FILTER_TYPE (FILTER_TYPE), - .STAGES (STAGES), - .D_DELAY (D_DELAY), - .VRC_EN (VRC_EN), - .RCF_MAX (RCF_MAX), - .RCF_MIN (RCF_MIN), - .INTERFACES (INTERFACES), - .CH_PER_INT (CH_PER_INT), - .INT_USE_MEM (INT_USE_MEM), - .INT_MEM (INT_MEM), - .DIF_USE_MEM (DIF_USE_MEM), - .DIF_MEM (DIF_MEM), - .IN_WIDTH (IN_WIDTH), - .OUT_WIDTH (OUT_WIDTH), - .ROUND_TYPE (ROUND_TYPE), - .PIPELINING (PIPELINING), - - .C_STAGE_0_WIDTH(C_STAGE_0_WIDTH), - .C_STAGE_1_WIDTH(C_STAGE_1_WIDTH), - .C_STAGE_2_WIDTH(C_STAGE_2_WIDTH), - .C_STAGE_3_WIDTH(C_STAGE_3_WIDTH), - .C_STAGE_4_WIDTH(C_STAGE_4_WIDTH), - .C_STAGE_5_WIDTH(C_STAGE_5_WIDTH), - .C_STAGE_6_WIDTH(C_STAGE_6_WIDTH), - .C_STAGE_7_WIDTH(C_STAGE_7_WIDTH), - .C_STAGE_8_WIDTH(C_STAGE_8_WIDTH), - .C_STAGE_9_WIDTH(C_STAGE_9_WIDTH), - .C_STAGE_10_WIDTH(C_STAGE_10_WIDTH), - .C_STAGE_11_WIDTH(C_STAGE_11_WIDTH), - .MAX_C_STAGE_WIDTH(MAX_C_STAGE_WIDTH), - - .I_STAGE_0_WIDTH(I_STAGE_0_WIDTH), - .I_STAGE_1_WIDTH(I_STAGE_1_WIDTH), - .I_STAGE_2_WIDTH(I_STAGE_2_WIDTH), - .I_STAGE_3_WIDTH(I_STAGE_3_WIDTH), - .I_STAGE_4_WIDTH(I_STAGE_4_WIDTH), - .I_STAGE_5_WIDTH(I_STAGE_5_WIDTH), - .I_STAGE_6_WIDTH(I_STAGE_6_WIDTH), - .I_STAGE_7_WIDTH(I_STAGE_7_WIDTH), - .I_STAGE_8_WIDTH(I_STAGE_8_WIDTH), - .I_STAGE_9_WIDTH(I_STAGE_9_WIDTH), - .I_STAGE_10_WIDTH(I_STAGE_10_WIDTH), - .I_STAGE_11_WIDTH(I_STAGE_11_WIDTH), - .MAX_I_STAGE_WIDTH(MAX_I_STAGE_WIDTH) - ) core ( - .clk(clk), - .clken(clken), - .reset_n(reset_n), - .rate(rate), - .in_startofpacket(in_startofpacket), - .in_endofpacket(in_endofpacket), - .in_data(din), - .in_ready(in_ready), - .in_valid(in_valid), - .out_channel(out_channel), - .out_startofpacket(out_startofpacket), - .out_endofpacket(out_endofpacket), - .in_error(in_error), - .out_error(out_error), - .out_ready(out_ready), - .out_data(dout), - .out_valid(out_valid) - ); - defparam core.HYPER_PIPELINE = 0; - - -endmodule diff --git a/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab.qip b/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab.qip deleted file mode 100644 index 55585fc..0000000 --- a/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab.qip +++ /dev/null @@ -1,91 +0,0 @@ -set_global_assignment -entity "alt_sld_fab" -library "alt_sld_fab" -name IP_TOOL_NAME "Qsys" -set_global_assignment -entity "alt_sld_fab" -library "alt_sld_fab" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "alt_sld_fab" -library "alt_sld_fab" -name IP_TOOL_ENV "Qsys" -set_global_assignment -library "alt_sld_fab" -name SOPCINFO_FILE [file join $::quartus(qip_path) "alt_sld_fab.sopcinfo"] -set_global_assignment -entity "alt_sld_fab" -library "alt_sld_fab" -name SLD_INFO "QSYS_NAME alt_sld_fab HAS_SOPCINFO 1" -set_global_assignment -entity "alt_sld_fab" -library "alt_sld_fab" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E" -set_global_assignment -entity "alt_sld_fab" -library "alt_sld_fab" -name IP_GENERATED_DEVICE_FAMILY "{Device Agnostic}" -set_global_assignment -entity "alt_sld_fab" -library "alt_sld_fab" -name IP_QSYS_MODE "UNKNOWN" -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -entity "alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_NAME "YWx0X3NsZF9mYWI=" -set_global_assignment -entity "alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_DISPLAY_NAME "YWx0X3NsZF9mYWI=" -set_global_assignment -entity "alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_INTERNAL "On" -set_global_assignment -entity "alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_VERSION "MS4w" -set_global_assignment -entity "alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_NAME "YWx0X3NsZF9mYWJfYWx0X3NsZF9mYWI=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_DISPLAY_NAME "VG9wIGxldmVsIGdlbmVyYXRlZCBpbnN0cnVtZW50YXRpb24gZmFicmlj" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_INTERNAL "On" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "REVTSUdOX0hBU0g=::ZDkyZDczODJlYzBlMTA0N2EyYmY=::REVTSUdOX0hBU0g=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "Tk9ERV9DT1VOVA==::MQ==::Tk9ERV9DT1VOVA==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "TUFYX1dJRFRI::Mjc=::TUFYX1dJRFRI" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "U0VUVElOR1M=::e2ZhYnJpYyBzbGQgZGlyIGFnZW50IG1mcl9jb2RlIDExMCB0eXBlX2NvZGUgOSB2ZXJzaW9uIDAgaW5zdGFuY2UgMCBpcl93aWR0aCA0IHBzaWcgOWI2NzkxOWV9::U0VUVElOR1M=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "Q0xPQ0tT::e2lkIHt9IH0=::Q0xPQ0tT" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "RVBfSU5GT1M=::e2hwYXRoIHtERUJVRzpEQkdfQURDfGFsdHNvdXJjZV9wcm9iZV90b3A6aW5fc3lzdGVtX3NvdXJjZXNfcHJvYmVzXzB8YWx0c291cmNlX3Byb2JlOmlzc3BfaW1wbH0gfQ==::RVBfSU5GT1M=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "TUlSUk9S::MA==::TUlSUk9S" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "VE9QX0hVQg==::MQ==::VE9QX0hVQg==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "Q09NUE9TRURfU0VUVElOR1M=::e2ZhYnJpYyBzbGQgZGlyIGFnZW50IG1mcl9jb2RlIDExMCB0eXBlX2NvZGUgOSB2ZXJzaW9uIDAgaW5zdGFuY2UgMCBpcl93aWR0aCA0IGJyaWRnZV9hZ2VudCAwIHByZWZlcl9ob3N0IHt9IH0=::Q09NUE9TRURfU0VUVElOR1M=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBJViBF::REVWSUNFX0ZBTUlMWQ==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::VW5rbm93bg==::QXV0byBERVZJQ0U=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::VW5rbm93bg==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_ident" -library "alt_sld_fab" -name IP_COMPONENT_NAME "YWx0X3NsZF9mYWJfYWx0X3NsZF9mYWJfaWRlbnQ=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_ident" -library "alt_sld_fab" -name IP_COMPONENT_DISPLAY_NAME "Q29ubmVjdGlvbiBpZGVudGlmaWNhdGlvbiBodWI=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_ident" -library "alt_sld_fab" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_ident" -library "alt_sld_fab" -name IP_COMPONENT_INTERNAL "On" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_ident" -library "alt_sld_fab" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_ident" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "REVTSUdOX0hBU0g=::ZDkyZDczODJlYzBlMTA0N2EyYmY=::REVTSUdOX0hBU0g=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_ident" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "Q09VTlQ=::MQ==::Q09VTlQ=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_ident" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "U0VUVElOR1M=::e3dpZHRoIDQgbGF0ZW5jeSAwfQ==::U0VUVElOR1M=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_NAME "YWx0X3NsZF9mYWJfYWx0X3NsZF9mYWJfc2xkZmFicmlj" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFNMRCBKVEFHIEh1Yg==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_INTERNAL "On" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFNMRCBKVEFHIEh1YiAtLSBUaGlzIFRDTCBjb21wb25lbnQgd2lsbCBjb250YWluIHRoZSBzbGRfanRhZ19odWI=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBJViBF::REVWSUNFX0ZBTUlMWQ==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "U0VUVElOR1M=::e21mcl9jb2RlIDExMCB0eXBlX2NvZGUgOSB2ZXJzaW9uIDAgaW5zdGFuY2UgMCBpcl93aWR0aCA0IGJyaWRnZV9hZ2VudCAwIHByZWZlcl9ob3N0IHt9IH0=::U0VUVElOR1M=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "Q09VTlQ=::MQ==::Q09VTlQ=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "Tl9TRUxfQklUUw==::MQ==::Tl9TRUxfQklUUw==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "Tl9OT0RFX0lSX0JJVFM=::NA==::Tl9OT0RFX0lSX0JJVFM=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "Tk9ERV9JTkZP::MDAwMDAwMDAwMTAwMTAwMDAxMTAxMTEwMDAwMDAwMDA=::Tk9ERV9JTkZP" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "Q09NUElMQVRJT05fTU9ERQ==::MA==::Q09NUElMQVRJT05fTU9ERQ==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "QlJPQURDQVNUX0ZFQVRVUkU=::MA==::QlJPQURDQVNUX0ZFQVRVUkU=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfSVJfQ0FQVFVSRV9GRUFUVVJF::MQ==::Rk9SQ0VfSVJfQ0FQVFVSRV9GRUFUVVJF" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "Rk9SQ0VfUFJFXzFfNF9GRUFUVVJF::MA==::Rk9SQ0VfUFJFXzFfNF9GRUFUVVJF" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "TkVHRURHRV9URE9fTEFUQ0g=::MQ==::TkVHRURHRV9URE9fTEFUQ0g=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1NPRlRfQ09SRV9DT05UUk9MTEVS::MA==::RU5BQkxFX1NPRlRfQ09SRV9DT05UUk9MTEVS" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "VE9QX0hVQg==::MQ==::VE9QX0hVQg==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "Q09OTl9JTkRFWA==::MA==::Q09OTl9JTkRFWA==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_splitter" -library "alt_sld_fab" -name IP_COMPONENT_NAME "YWx0X3NsZF9mYWJfYWx0X3NsZF9mYWJfc3BsaXR0ZXI=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_splitter" -library "alt_sld_fab" -name IP_COMPONENT_DISPLAY_NAME "U3BsaXR0ZXIgZm9yIGRlYnVnIGZhYnJpYw==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_splitter" -library "alt_sld_fab" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_splitter" -library "alt_sld_fab" -name IP_COMPONENT_INTERNAL "On" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_splitter" -library "alt_sld_fab" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_splitter" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "RlJBR01FTlRT::e3tuYW1lIGNsb2NrIHR5cGUgY2xvY2sgZGlyIGVuZCBwb3J0cyB7IHt0Y2sgY2xrIGluIDEgMH0gfSB9IHtuYW1lIG5vZGUgdHlwZSBjb25kdWl0IGRpciBlbmQgcG9ydHMgeyB7dG1zIHRtcyBpbiAxIDF9IHt0ZGkgdGRpIGluIDEgMn0ge3RkbyB0ZG8gb3V0IDEgMH0ge2VuYSBlbmEgaW4gMSAzfSB7dXNyMSB1c3IxIGluIDEgNH0ge2NsciBjbHIgaW4gMSA1fSB7Y2xybiBjbHJuIGluIDEgNn0ge2p0YWdfc3RhdGVfdGxyIGp0YWdfc3RhdGVfdGxyIGluIDEgN30ge2p0YWdfc3RhdGVfcnRpIGp0YWdfc3RhdGVfcnRpIGluIDEgOH0ge2p0YWdfc3RhdGVfc2RycyBqdGFnX3N0YXRlX3NkcnMgaW4gMSA5fSB7anRhZ19zdGF0ZV9jZHIganRhZ19zdGF0ZV9jZHIgaW4gMSAxMH0ge2p0YWdfc3RhdGVfc2RyIGp0YWdfc3RhdGVfc2RyIGluIDEgMTF9IHtqdGFnX3N0YXRlX2UxZHIganRhZ19zdGF0ZV9lMWRyIGluIDEgMTJ9IHtqdGFnX3N0YXRlX3BkciBqdGFnX3N0YXRlX3BkciBpbiAxIDEzfSB7anRhZ19zdGF0ZV9lMmRyIGp0YWdfc3RhdGVfZTJkciBpbiAxIDE0fSB7anRhZ19zdGF0ZV91ZHIganRhZ19zdGF0ZV91ZHIgaW4gMSAxNX0ge2p0YWdfc3RhdGVfc2lycyBqdGFnX3N0YXRlX3NpcnMgaW4gMSAxNn0ge2p0YWdfc3RhdGVfY2lyIGp0YWdfc3RhdGVfY2lyIGluIDEgMTd9IHtqdGFnX3N0YXRlX3NpciBqdGFnX3N0YXRlX3NpciBpbiAxIDE4fSB7anRhZ19zdGF0ZV9lMWlyIGp0YWdfc3RhdGVfZTFpciBpbiAxIDE5fSB7anRhZ19zdGF0ZV9waXIganRhZ19zdGF0ZV9waXIgaW4gMSAyMH0ge2p0YWdfc3RhdGVfZTJpciBqdGFnX3N0YXRlX2UyaXIgaW4gMSAyMX0ge2p0YWdfc3RhdGVfdWlyIGp0YWdfc3RhdGVfdWlyIGluIDEgMjJ9IHtpcl9pbiBpcl9pbiBpbiA0IDIzfSB7aXJxIGlycSBvdXQgMSAxfSB7aXJfb3V0IGlyX291dCBvdXQgNCAyfSB9IGNsb2NrIGNsb2NrIGFzc2lnbiB7ZGVidWcuY29udHJvbGxlZEJ5IHtsaW5rXzB9IH0gbW9kdWxlYXNzaWduIHtkZWJ1Zy52aXJ0dWFsSW50ZXJmYWNlLmxpbmtfMCB7ZGVidWcuZW5kcG9pbnRMaW5rIHtmYWJyaWMgc2xkIGluZGV4IDF9IH0gfSB9IH0=::RlJBR01FTlRT" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_splitter" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "QUREX0lOVEVSRkFDRV9BU0dO::MA==::QUREX0lOVEVSRkFDRV9BU0dO" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_presplit" -library "alt_sld_fab" -name IP_COMPONENT_NAME "YWx0X3NsZF9mYWJfYWx0X3NsZF9mYWJfcHJlc3BsaXQ=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_presplit" -library "alt_sld_fab" -name IP_COMPONENT_DISPLAY_NAME "U3BsaXR0ZXIgZm9yIGRlYnVnIGZhYnJpYw==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_presplit" -library "alt_sld_fab" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_presplit" -library "alt_sld_fab" -name IP_COMPONENT_INTERNAL "On" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_presplit" -library "alt_sld_fab" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_presplit" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "TUFYX1dJRFRI::Mjc=::TUFYX1dJRFRI" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_presplit" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "U0VORF9XSURUSFM=::Ng==::U0VORF9XSURUSFM=" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_presplit" -library "alt_sld_fab" -name IP_COMPONENT_PARAMETER "UkVDRUlWRV9XSURUSFM=::Mjc=::UkVDRUlWRV9XSURUSFM=" - -set_global_assignment -library "alt_sld_fab" -name VERILOG_FILE [file join $::quartus(qip_path) "alt_sld_fab.v"] -set_global_assignment -library "alt_sld_fab" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_sld_fab_alt_sld_fab.v"] -set_global_assignment -library "alt_sld_fab" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_sld_fab_alt_sld_fab_ident.sv"] -set_global_assignment -library "alt_sld_fab" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd"] -set_global_assignment -library "alt_sld_fab" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_sld_fab_alt_sld_fab_splitter.sv"] -set_global_assignment -library "alt_sld_fab" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_sld_fab_alt_sld_fab_presplit.sv"] - -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_TOOL_NAME "alt_sld_fab" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab" -library "alt_sld_fab" -name IP_TOOL_ENV "Qsys" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_TOOL_NAME "altera_sld_jtag_hub" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "alt_sld_fab_alt_sld_fab_sldfabric" -library "alt_sld_fab" -name IP_TOOL_ENV "Qsys" diff --git a/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab.sopcinfo b/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab.sopcinfo deleted file mode 100644 index fa3c872..0000000 --- a/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab.sopcinfo +++ /dev/null @@ -1,2138 +0,0 @@ - - - - - - - java.lang.String - CYCLONEIVE - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - - false - true - false - true - DEVICE - - - java.lang.String - - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.String - Cyclone IV E - false - true - false - true - DEVICE_FAMILY - - - boolean - false - false - true - true - true - - - - - java.lang.String - d92d7382ec0e1047a2bf - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 27 - false - true - true - true - - - java.lang.String - {fabric sld dir agent mfr_code 110 type_code 9 version 0 instance 0 ir_width 4 psig 9b67919e} - false - true - true - true - - - java.lang.String - {id {} } - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - {hpath {DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl} } - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - java.lang.String - {fabric sld dir agent mfr_code 110 type_code 9 version 0 instance 0 ir_width 4 bridge_agent 0 prefer_host {} } - true - true - true - true - - - java.lang.String - CYCLONEIVE - false - true - true - true - DEVICE_FAMILY - - - java.lang.String - Unknown - false - true - false - true - DEVICE - - - java.lang.String - Unknown - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - nodes_send - Input - 27 - send - - - nodes_receive - Output - 27 - receive - - - - - - debug.hostConnection - type jtag connidx ext - - - debug.providesServices - deviceConn - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - hub_tck - Input - 1 - tck - - - hub_tms - Input - 1 - tms - - - hub_tdi - Input - 1 - tdi - - - hub_tdo - Output - 1 - tdo - - - - - - - debug.isTransparent - true - - - int - 27 - false - true - true - true - - - java.lang.String - 6 - false - true - true - true - - - java.lang.String - 27 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - send - Input - 27 - send - - - receive - Output - 27 - receive - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - send_0 - Output - 6 - send_0 - - - receive_0 - Input - 27 - receive_0 - - - - - - - debug.isTransparent - true - - - debug.virtualInterface.link_0 - debug.endpointLink {fabric sld index 1} - - - java.lang.String - {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 4 23} {irq irq out 1 1} {ir_out ir_out out 4 2} } clock clock assign {debug.controlledBy {link_0} } moduleassign {debug.virtualInterface.link_0 {debug.endpointLink {fabric sld index 1} } } } } - false - true - true - true - - - java.lang.String - - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - send_0 - Input - 6 - send_0 - - - receive_0 - Output - 27 - receive_0 - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - tck_0 - Input - 1 - clk - - - - - - debug.controlledBy - link_0 - - - java.lang.String - clock_0 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - tms_0 - Input - 1 - tms - - - tdi_0 - Input - 1 - tdi - - - tdo_0 - Output - 1 - tdo - - - ena_0 - Input - 1 - ena - - - usr1_0 - Input - 1 - usr1 - - - clr_0 - Input - 1 - clr - - - clrn_0 - Input - 1 - clrn - - - jtag_state_tlr_0 - Input - 1 - jtag_state_tlr - - - jtag_state_rti_0 - Input - 1 - jtag_state_rti - - - jtag_state_sdrs_0 - Input - 1 - jtag_state_sdrs - - - jtag_state_cdr_0 - Input - 1 - jtag_state_cdr - - - jtag_state_sdr_0 - Input - 1 - jtag_state_sdr - - - jtag_state_e1dr_0 - Input - 1 - jtag_state_e1dr - - - jtag_state_pdr_0 - Input - 1 - jtag_state_pdr - - - jtag_state_e2dr_0 - Input - 1 - jtag_state_e2dr - - - jtag_state_udr_0 - Input - 1 - jtag_state_udr - - - jtag_state_sirs_0 - Input - 1 - jtag_state_sirs - - - jtag_state_cir_0 - Input - 1 - jtag_state_cir - - - jtag_state_sir_0 - Input - 1 - jtag_state_sir - - - jtag_state_e1ir_0 - Input - 1 - jtag_state_e1ir - - - jtag_state_pir_0 - Input - 1 - jtag_state_pir - - - jtag_state_e2ir_0 - Input - 1 - jtag_state_e2ir - - - jtag_state_uir_0 - Input - 1 - jtag_state_uir - - - ir_in_0 - Input - 4 - ir_in - - - irq_0 - Output - 1 - irq - - - ir_out_0 - Output - 4 - ir_out - - - - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - debug.hostConnection - type jtag connidx ext - - - debug.providesServices - deviceConn - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - ext_tck - Input - 1 - tck - - - ext_tms - Input - 1 - tms - - - ext_tdi - Input - 1 - tdi - - - ext_tdo - Output - 1 - tdo - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - int_tck - Output - 1 - clk - - - false - alt_sld_fab_sldfabric - clock - alt_sld_fab_sldfabric.clock - - - - - - debug.controlledBy - pins - - - java.lang.String - clock - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - int_tms - Output - 1 - tms - - - int_tdi - Output - 1 - tdi - - - int_tdo - Input - 1 - tdo - - - - - - - java.lang.String - CYCLONEIVE - false - true - true - true - DEVICE_FAMILY - - - java.lang.String - {mfr_code 110 type_code 9 version 0 instance 0 ir_width 4 bridge_agent 0 prefer_host {} } - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 1 - true - true - true - true - - - int - 4 - true - true - true - true - - - java.lang.String - 00000000010010000110111000000000 - true - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - true - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - true - true - true - true - - - int - 1 - true - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - jsm_tck - Input - 1 - clk - - - - - - debug.connIndex - 0 - - - java.lang.String - clock - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - jsm_tms - Input - 1 - tms - - - hub_tdi - Input - 1 - tdi - - - hub_tdo - Output - 1 - tdo - - - - - - java.lang.String - - false - true - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - node_raw_tck_0 - Output - 1 - clk - - - false - alt_sld_fab_splitter - clock_0 - alt_sld_fab_splitter.clock_0 - - - - - - debug.controlledBy - node - - - debug.encodedSldId - 4746752 - - - debug.providesServices - sld - - - java.lang.String - clock_0 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - node_ir_in_1d_0 - Output - 4 - ir_in - - - node_ir_out_1d_0 - Input - 4 - ir_out - - - node_tdo_0 - Input - 1 - tdo - - - node_irq_0 - Input - 1 - irq - - - node_raw_tms_0 - Output - 1 - tms - - - node_tdi_0 - Output - 1 - tdi - - - node_clr_0 - Output - 1 - clr - - - node_clrn_0 - Output - 1 - clrn - - - node_usr1_0 - Output - 1 - usr1 - - - node_ena_0 - Output - 1 - ena - - - node_jtag_state_tlr_0 - Output - 1 - jtag_state_tlr - - - node_jtag_state_rti_0 - Output - 1 - jtag_state_rti - - - node_jtag_state_sdrs_0 - Output - 1 - jtag_state_sdrs - - - node_jtag_state_cdr_0 - Output - 1 - jtag_state_cdr - - - node_jtag_state_sdr_0 - Output - 1 - jtag_state_sdr - - - node_jtag_state_e1dr_0 - Output - 1 - jtag_state_e1dr - - - node_jtag_state_pdr_0 - Output - 1 - jtag_state_pdr - - - node_jtag_state_e2dr_0 - Output - 1 - jtag_state_e2dr - - - node_jtag_state_udr_0 - Output - 1 - jtag_state_udr - - - node_jtag_state_sirs_0 - Output - 1 - jtag_state_sirs - - - node_jtag_state_cir_0 - Output - 1 - jtag_state_cir - - - node_jtag_state_sir_0 - Output - 1 - jtag_state_sir - - - node_jtag_state_e1ir_0 - Output - 1 - jtag_state_e1ir - - - node_jtag_state_pir_0 - Output - 1 - jtag_state_pir - - - node_jtag_state_e2ir_0 - Output - 1 - jtag_state_e2ir - - - node_jtag_state_uir_0 - Output - 1 - jtag_state_uir - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - ident_writedata - Output - 4 - writedata - - - ident_address - Output - 5 - address - - - ident_readdata - Input - 4 - readdata - - - - - - - java.lang.String - d92d7382ec0e1047a2bf - false - true - true - true - - - int - 1 - false - true - true - true - - - java.lang.String - {width 4 latency 0} - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - address_0 - Input - 5 - address - - - contrib_0 - Input - 4 - writedata - - - rdata_0 - Output - 4 - readdata - - - - - - com.altera.entityinterfaces.IPort - - false - true - true - true - - - int - 0 - false - true - true - true - - - com.altera.entityinterfaces.IPort - - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - alt_sld_fab_presplit - pass - alt_sld_fab_splitter - nodes - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - alt_sld_fab_jtagpins - clock - alt_sld_fab_sldfabric - clock - - - - com.altera.entityinterfaces.IPort - - false - true - true - true - - - int - 0 - false - true - true - true - - - com.altera.entityinterfaces.IPort - - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - alt_sld_fab_jtagpins - node - alt_sld_fab_sldfabric - node - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - alt_sld_fab_sldfabric - clock_0 - alt_sld_fab_splitter - clock_0 - - - - com.altera.entityinterfaces.IPort - - false - true - true - true - - - int - 0 - false - true - true - true - - - com.altera.entityinterfaces.IPort - - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - alt_sld_fab_sldfabric - node_0 - alt_sld_fab_splitter - node_0 - - - - com.altera.entityinterfaces.IPort - - false - true - true - true - - - int - 0 - false - true - true - true - - - com.altera.entityinterfaces.IPort - - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - alt_sld_fab_sldfabric - ident - alt_sld_fab_ident - ident_0 - - - 1 - alt_sld_fab - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Top level generated instrumentation fabric - 18.1 - - - 12 - conduit_end - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit - 18.1 - - - 1 - altera_super_splitter - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Splitter for debug fabric - 18.1 - - - 1 - altera_sld_splitter - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Splitter for debug fabric - 18.1 - - - 2 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 18.1 - - - 1 - altera_jtag_pins_bridge - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - altera_jtag_pins_bridge - 18.1 - - - 2 - clock_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Output - 18.1 - - - 1 - altera_sld_jtag_hub - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Altera SLD JTAG Hub - 18.1 - - - 1 - altera_connection_identification_hub - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Connection identification hub - 18.1 - - - 4 - conduit - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Conduit Connection - 18.1 - - - 2 - clock - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Clock Connection - 18.1 - - 18.1 625 - - diff --git a/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab.v b/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab.v deleted file mode 100644 index df4c395..0000000 Binary files a/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab__report.html b/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab__report.html deleted file mode 100644 index d956f5b..0000000 --- a/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab__report.html +++ /dev/null @@ -1,537 +0,0 @@ - - - - - datasheet for alt_sld_fab - - - - - - - - -
alt_sld_fab -
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2021.03.31.22:18:29Datasheet
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Overview
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Memory Map
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alt_sld_fab

alt_sld_fab v18.1 -
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Parameters

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DESIGN_HASHd92d7382ec0e1047a2bf
NODE_COUNT1
MAX_WIDTH27
SETTINGS{fabric sld dir agent mfr_code 110 type_code 9 version 0 instance 0 ir_width 4 psig 9b67919e}
CLOCKS{id {} }
AGENTS
EP_INFOS{hpath {DEBUG:DBG_ADC|altsource_probe_top:in_system_sources_probes_0|altsource_probe:issp_impl} }
MIRROR0
TOP_HUB1
COMPOSED_SETTINGS{fabric sld dir agent mfr_code 110 type_code 9 version 0 instance 0 ir_width 4 bridge_agent 0 prefer_host {} }
DEVICE_FAMILYCYCLONEIVE
AUTO_DEVICEUnknown
AUTO_DEVICE_SPEEDGRADEUnknown
deviceFamilyUNKNOWN
generateLegacySimfalse
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Software Assignments

(none)
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alt_sld_fab_presplit

altera_super_splitter v18.1 -
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Parameters

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MAX_WIDTH27
SEND_WIDTHS6
RECEIVE_WIDTHS27
deviceFamilyUNKNOWN
generateLegacySimfalse
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Software Assignments

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alt_sld_fab_splitter

altera_sld_splitter v18.1 -
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- alt_sld_fab_presplit - pass  alt_sld_fab_splitter
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- alt_sld_fab_sldfabric - clock_0  
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node_0  
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Parameters

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FRAGMENTS{{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 4 23} {irq irq out 1 1} {ir_out ir_out out 4 2} } clock clock assign {debug.controlledBy {link_0} } moduleassign {debug.virtualInterface.link_0 {debug.endpointLink {fabric sld index 1} } } } }
EXAMPLE
ADD_INTERFACE_ASGN0
deviceFamilyUNKNOWN
generateLegacySimfalse
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Software Assignments

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alt_sld_fab_jtagpins

altera_jtag_pins_bridge v18.1 -
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Parameters

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deviceFamilyUNKNOWN
generateLegacySimfalse
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Software Assignments

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alt_sld_fab_sldfabric

altera_sld_jtag_hub v18.1 -
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- alt_sld_fab_jtagpins - clock  alt_sld_fab_sldfabric
  clock
node  
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clock_0   - alt_sld_fab_splitter -
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node_0  
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ident   - alt_sld_fab_ident -
  ident_0
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Parameters

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DEVICE_FAMILYCYCLONEIVE
SETTINGS{mfr_code 110 type_code 9 version 0 instance 0 ir_width 4 bridge_agent 0 prefer_host {} }
COUNT1
N_SEL_BITS1
N_NODE_IR_BITS4
NODE_INFO00000000010010000110111000000000
COMPILATION_MODE0
BROADCAST_FEATURE0
FORCE_IR_CAPTURE_FEATURE1
FORCE_PRE_1_4_FEATURE0
NEGEDGE_TDO_LATCH1
ENABLE_SOFT_CORE_CONTROLLER0
TOP_HUB1
CONN_INDEX0
deviceFamilyUNKNOWN
generateLegacySimfalse
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Software Assignments

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alt_sld_fab_ident

altera_connection_identification_hub v18.1 -
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- alt_sld_fab_sldfabric - ident  alt_sld_fab_ident
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Parameters

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DESIGN_HASHd92d7382ec0e1047a2bf
COUNT1
SETTINGS{width 4 latency 0}
deviceFamilyUNKNOWN
generateLegacySimfalse
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Software Assignments

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generation took 0,01 secondsrendering took 0,05 seconds
- - diff --git a/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab__report.xml b/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab__report.xml deleted file mode 100644 index 9d34fe6..0000000 --- a/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab__report.xml +++ /dev/null @@ -1,371 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:alt_sld_fab "alt_sld_fab" - - - - Transform: CustomInstructionTransform - No custom instruction connections, skipping transform - 1 modules, 0 connections]]> - Transform: MMTransform - Transform: InterruptMapperTransform - Transform: InterruptSyncTransform - Transform: InterruptFanoutTransform - Transform: AvalonStreamingTransform - Transform: ResetAdaptation - alt_sld_fab" reuses alt_sld_fab "submodules/alt_sld_fab_alt_sld_fab"]]> - queue size: 0 starting:alt_sld_fab "submodules/alt_sld_fab_alt_sld_fab" - - - - Transform: CustomInstructionTransform - No custom instruction connections, skipping transform - 5 modules, 6 connections]]> - Transform: MMTransform - Transform: InterruptMapperTransform - Transform: InterruptSyncTransform - Transform: InterruptFanoutTransform - Transform: AvalonStreamingTransform - Transform: ResetAdaptation - alt_sld_fab" reuses altera_super_splitter "submodules/alt_sld_fab_alt_sld_fab_presplit"]]> - alt_sld_fab" reuses altera_sld_splitter "submodules/alt_sld_fab_alt_sld_fab_splitter"]]> - alt_sld_fab" reuses altera_sld_jtag_hub "submodules/alt_sld_fab_alt_sld_fab_sldfabric"]]> - alt_sld_fab" reuses altera_connection_identification_hub "submodules/alt_sld_fab_alt_sld_fab_ident"]]> - alt_sld_fab" instantiated alt_sld_fab "alt_sld_fab"]]> - queue size: 3 starting:altera_super_splitter "submodules/alt_sld_fab_alt_sld_fab_presplit" - alt_sld_fab" instantiated altera_super_splitter "presplit"]]> - queue size: 2 starting:altera_sld_splitter "submodules/alt_sld_fab_alt_sld_fab_splitter" - alt_sld_fab" instantiated altera_sld_splitter "splitter"]]> - queue size: 1 starting:altera_sld_jtag_hub "submodules/alt_sld_fab_alt_sld_fab_sldfabric" - alt_sld_fab" instantiated altera_sld_jtag_hub "sldfabric"]]> - queue size: 0 starting:altera_connection_identification_hub "submodules/alt_sld_fab_alt_sld_fab_ident" - alt_sld_fab" instantiated altera_connection_identification_hub "ident"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:alt_sld_fab "submodules/alt_sld_fab_alt_sld_fab" - - - - Transform: CustomInstructionTransform - No custom instruction connections, skipping transform - 5 modules, 6 connections]]> - Transform: MMTransform - Transform: InterruptMapperTransform - Transform: InterruptSyncTransform - Transform: InterruptFanoutTransform - Transform: AvalonStreamingTransform - Transform: ResetAdaptation - alt_sld_fab" reuses altera_super_splitter "submodules/alt_sld_fab_alt_sld_fab_presplit"]]> - alt_sld_fab" reuses altera_sld_splitter "submodules/alt_sld_fab_alt_sld_fab_splitter"]]> - alt_sld_fab" reuses altera_sld_jtag_hub "submodules/alt_sld_fab_alt_sld_fab_sldfabric"]]> - alt_sld_fab" reuses altera_connection_identification_hub "submodules/alt_sld_fab_alt_sld_fab_ident"]]> - alt_sld_fab" instantiated alt_sld_fab "alt_sld_fab"]]> - queue size: 3 starting:altera_super_splitter "submodules/alt_sld_fab_alt_sld_fab_presplit" - alt_sld_fab" instantiated altera_super_splitter "presplit"]]> - queue size: 2 starting:altera_sld_splitter "submodules/alt_sld_fab_alt_sld_fab_splitter" - alt_sld_fab" instantiated altera_sld_splitter "splitter"]]> - queue size: 1 starting:altera_sld_jtag_hub "submodules/alt_sld_fab_alt_sld_fab_sldfabric" - alt_sld_fab" instantiated altera_sld_jtag_hub "sldfabric"]]> - queue size: 0 starting:altera_connection_identification_hub "submodules/alt_sld_fab_alt_sld_fab_ident" - alt_sld_fab" instantiated altera_connection_identification_hub "ident"]]> - - - - - - - - - - - - - - - - - queue size: 3 starting:altera_super_splitter "submodules/alt_sld_fab_alt_sld_fab_presplit" - alt_sld_fab" instantiated altera_super_splitter "presplit"]]> - - - - - - - - - - - - - - - - - queue size: 2 starting:altera_sld_splitter "submodules/alt_sld_fab_alt_sld_fab_splitter" - alt_sld_fab" instantiated altera_sld_splitter "splitter"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 1 starting:altera_sld_jtag_hub "submodules/alt_sld_fab_alt_sld_fab_sldfabric" - alt_sld_fab" instantiated altera_sld_jtag_hub "sldfabric"]]> - - - - - - - - - - - - - - - - - queue size: 0 starting:altera_connection_identification_hub "submodules/alt_sld_fab_alt_sld_fab_ident" - alt_sld_fab" instantiated altera_connection_identification_hub "ident"]]> - - - diff --git a/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab_wrapper_hw.tcl b/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab_wrapper_hw.tcl deleted file mode 100644 index 3146ddb..0000000 Binary files a/FPGA_61.440/db/ip/sld0b974a4e/alt_sld_fab_wrapper_hw.tcl and /dev/null differ diff --git a/FPGA_61.440/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v b/FPGA_61.440/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v deleted file mode 100644 index eb92ea0..0000000 Binary files a/FPGA_61.440/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv b/FPGA_61.440/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv deleted file mode 100644 index 456b458..0000000 --- a/FPGA_61.440/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv +++ /dev/null @@ -1,91 +0,0 @@ -// (C) 2001-2018 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/main/ip/altera_connection_identification_hub/altera_connection_identification_hub.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2012/05/24 $ -// $Author: adraper $ - -// ------------------------------------------------------- -// Altera Identification hub -// -// Parameters -// DESIGN_HASH : d92d7382ec0e1047a2bf -// COUNT : 1 -// ROM_WIDTHS : 4 -// LATENCIES : 0 -// -// ------------------------------------------------------- - - -`timescale 1 ns / 1 ns - -module alt_sld_fab_alt_sld_fab_ident -( - input [4:0] address_0, - input [3:0] contrib_0, - output [3:0] rdata_0, - output [3:0] mixed -); - - -wire [127:0] data_0 = { mixed, 12'h0, 32'h0, 80'hd92d7382ec0e1047a2bf }; - -reg [3:0] result_0; -always @(address_0 or data_0) begin - case (address_0) - 0: result_0 <= data_0[0+:4]; - 1: result_0 <= data_0[4+:4]; - 2: result_0 <= data_0[8+:4]; - 3: result_0 <= data_0[12+:4]; - 4: result_0 <= data_0[16+:4]; - 5: result_0 <= data_0[20+:4]; - 6: result_0 <= data_0[24+:4]; - 7: result_0 <= data_0[28+:4]; - 8: result_0 <= data_0[32+:4]; - 9: result_0 <= data_0[36+:4]; - 10: result_0 <= data_0[40+:4]; - 11: result_0 <= data_0[44+:4]; - 12: result_0 <= data_0[48+:4]; - 13: result_0 <= data_0[52+:4]; - 14: result_0 <= data_0[56+:4]; - 15: result_0 <= data_0[60+:4]; - 16: result_0 <= data_0[64+:4]; - 17: result_0 <= data_0[68+:4]; - 18: result_0 <= data_0[72+:4]; - 19: result_0 <= data_0[76+:4]; - 20: result_0 <= data_0[80+:4]; - 21: result_0 <= data_0[84+:4]; - 22: result_0 <= data_0[88+:4]; - 23: result_0 <= data_0[92+:4]; - 24: result_0 <= data_0[96+:4]; - 25: result_0 <= data_0[100+:4]; - 26: result_0 <= data_0[104+:4]; - 27: result_0 <= data_0[108+:4]; - 28: result_0 <= data_0[112+:4]; - 29: result_0 <= data_0[116+:4]; - 30: result_0 <= data_0[120+:4]; - 31: result_0 <= data_0[124+:4]; - default: result_0 <= 0; - endcase -end -assign rdata_0 = result_0; - -// TODO: Cut timing paths into and out of mixed - -assign mixed = - contrib_0 ^ - 4'h0; - -endmodule - diff --git a/FPGA_61.440/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv b/FPGA_61.440/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv deleted file mode 100644 index 699c238..0000000 Binary files a/FPGA_61.440/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv and /dev/null differ diff --git a/FPGA_61.440/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd b/FPGA_61.440/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd deleted file mode 100644 index 978ba06..0000000 Binary files a/FPGA_61.440/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd and /dev/null differ diff --git a/FPGA_61.440/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_splitter.sv b/FPGA_61.440/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_splitter.sv deleted file mode 100644 index 93a5cc0..0000000 Binary files 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diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd deleted file mode 100644 index 6749efc..0000000 Binary files a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd deleted file mode 100644 index 1177239..0000000 Binary files a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_cic_lib_pkg.vhd b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_cic_lib_pkg.vhd deleted file mode 100644 index 7433b82..0000000 Binary files a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_cic_lib_pkg.vhd and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_delay.vhd b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_delay.vhd deleted file mode 100644 index f8e1c1a..0000000 --- a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_delay.vhd +++ /dev/null @@ -1,308 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - -------------------------------------------------------------------------- -------------------------------------------------------------------------- --- --- Revision Control Information --- --- $RCSfile: auk_dspip_delay.vhd,v $ --- $Source: /cvs/uksw/dsp_cores/lib/fu/delay/rtl/auk_dspip_delay.vhd,v $ --- --- $Revision: #1 $ --- $Date: 2018/07/18 $ --- Check in by : $Author: psgswbuild $ --- Author : Volker Mauer --- --- Project : common FU library --- --- Description : --- --- This functional unit can be used to insert a delay of specified length. --- The output data at time T will be equivalent to the input data at time --- T-DELAY. The user can select to implement the delay using either LE's --- (registers) or Memory. The type of memory to use is selected by the --- user. --- --- ALTERA Confidential and Proprietary --- Copyright 2006 (c) Altera Corporation --- All rights reserved --- -------------------------------------------------------------------------- -------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library altera_mf; -use altera_mf.altera_mf_components.all; -library work; -use work.auk_dspip_math_pkg.all; - - -entity auk_dspip_delay is - generic ( - WIDTH_g : natural := 8; -- data width - DELAY_g : natural := 8; - -- number of clock cycles the input - -- will be delayed by - MEMORY_TYPE_g : string := "AUTO"; - -- possible values are "m4k", "m512", - -- "register", "mram", "auto", - -- "lutram", "M9K", "M144K". - -- Any other string will be interpreted - -- as "auto" - REGISTER_FIRST_g : natural := 1; - -- if "1", the first delay is guaranteed - -- to be in registers - REGISTER_LAST_g : natural := 1); -- if "1", the last delay is guaranteed - -- to be in registers - port ( - clk : in std_logic; - reset : in std_logic; - enable : in std_logic; -- global clock enable - datain : in std_logic_vector(WIDTH_g-1 downto 0); - dataout : out std_logic_vector(WIDTH_g-1 downto 0) - ); -end entity auk_dspip_delay; - - -architecture rtl of auk_dspip_delay is -begin -- architecture rtl - - - ------------------------------------------------------------------------------ - -- array of registers - ------------------------------------------------------------------------------ - register_fifo : if MEMORY_TYPE_g = "register" or MEMORY_TYPE_g = "REGISTER" or DELAY_g-REGISTER_FIRST_g-REGISTER_LAST_g < 3 generate - type tFIFO_DATA is array (0 to DELAY_g-1) of std_logic_vector(WIDTH_g-1 downto 0); - signal fifo_data : tFIFO_DATA; - begin -- generate register_fifo - - -- purpose: array of registers - -- type : sequential - -- inputs : clk, reset, data_in - -- outputs: data_out - array_of_reg : process (clk, reset) is - begin -- process array_of_reg - if reset = '1' then -- asynchronous reset (active high) - reset_all : for i in 0 to DELAY_g-1 loop - fifo_data(i) <= (others => '0'); - end loop; - elsif rising_edge(clk) then -- rising clock edge - - ------------------------------------------------------------------- - -- memory array - ------------------------------------------------------------------- - - if enable = '1' then - fifo_data(0) <= datain; - if DELAY_g > 1 then - shift_up : for i in 1 to DELAY_g-1 loop - fifo_data(i) <= fifo_data(i-1); - end loop; - end if; - end if; - - end if; - end process array_of_reg; - dataout <= fifo_data(DELAY_g-1); - - - end generate register_fifo; - - ----------------------------------------------------------------------------- - -- memory based delay using altshift_tap - ----------------------------------------------------------------------------- - memory_fifo : if DELAY_g-REGISTER_FIRST_g-REGISTER_LAST_g >= 3 and not(MEMORY_TYPE_g = "register" or MEMORY_TYPE_g = "REGISTER") generate -component altshift_taps - generic ( - lpm_hint : string; - lpm_type : string; - number_of_taps : natural; - tap_distance : natural; - width : natural - ); - port ( - taps : out std_logic_vector (WIDTH_g-1 downto 0); - clken : in std_logic; - clock : in std_logic; - aclr : in std_logic := '0'; - sclr : in std_logic := '0'; - shiftout : out std_logic_vector (WIDTH_g-1 downto 0); - shiftin : in std_logic_vector (WIDTH_g-1 downto 0) - ); - end component; - component scfifo - generic ( - add_ram_output_register : string; - intended_device_family : string; - lpm_numwords : natural; - lpm_showahead : string; - lpm_type : string; - lpm_width : natural; - lpm_widthu : natural; - overflow_checking : string; - underflow_checking : string; - use_eab : string - ); - port ( - rdreq : in std_logic; - clock : in std_logic; - q : out std_logic_vector (WIDTH_g-1 downto 0); - wrreq : in std_logic; - data : in std_logic_vector (WIDTH_g-1 downto 0) - ); - end component; - - constant mem_depth : natural := DELAY_g - REGISTER_FIRST_g - REGISTER_LAST_g; - constant lpm_hint : string := "RAM_BLOCK_TYPE = " & MEMORY_TYPE_g; - - - signal mem_in : std_logic_vector(WIDTH_g-1 downto 0); -- memory input - signal mem_out : std_logic_vector(WIDTH_g-1 downto 0); -- memory_output - signal count_after_reset : unsigned(log2_ceil(mem_depth) downto 0); - signal extended_reset : std_logic; - - begin -- generate memory_fifo - - - - input_stage : if REGISTER_FIRST_g = 1 and (REGISTER_LAST_g = 0 or DELAY_g > 1) generate - begin -- generate input_stage - -- purpose: registers first stage - -- type : sequential - -- inputs : clk, reset, data_in - -- outputs: mem_in - - reg_input : process (clk, reset) is - begin -- process reg_input - if reset = '1' then -- asynchronous reset (active high) - mem_in <= (others => '0'); - elsif rising_edge(clk) then -- rising clock edge - if enable = '1' then - mem_in <= datain; - end if; - end if; - end process reg_input; - end generate input_stage; - - bypass_input_stage : if ((REGISTER_FIRST_g = 0) or - ((REGISTER_FIRST_g = 1) and (REGISTER_LAST_g = 1) and (DELAY_g = 1))) generate - -- captures the case, where the total delay is 1, and input and output - -- register is requested. In this case, the output register is also the - -- input register. Bypassing input register, leaving only output register. - - begin -- generate bypass_input_stage - mem_in <= datain; - end generate bypass_input_stage; - - check_illegal_generic : if REGISTER_FIRST_g > 1 generate - begin -- generate check_illegal_generic - assert false report "Generic REGISTER_FIRST_g in FU : DELAY must be 0 or 1" severity failure; - end generate check_illegal_generic; - - check_illegal_generic_3 : if DELAY_g < 1 generate - begin -- generate check_illegal_generic - assert false report "Generic DELAY_g in FU : DELAY must be at least 1" severity failure; - end generate check_illegal_generic_3; - - --------------------------------------------------------------------------- - -- only instantiate memory if the length of the shift reg is greater than - -- 0. This is to capture the case where the length is 1, and input or - -- output registers have been used. - --------------------------------------------------------------------------- - memory_i : if mem_depth > 0 generate - begin -- generate memory_i - altshift_taps_component : altshift_taps - generic map ( - lpm_hint => lpm_hint, - lpm_type => "altshift_taps", - number_of_taps => 1, - tap_distance => mem_depth, - width => WIDTH_g - ) - port map ( - clken => enable, - clock => clk, - shiftin => mem_in, - taps => mem_out, - shiftout => open - ); - end generate memory_i; - - no_memory_i : if mem_depth < 1 generate - begin -- generate no_memory_i - mem_out <= mem_in; -- bypass memory - end generate no_memory_i; - - - - output_stage : if REGISTER_LAST_g = 1 generate - begin -- generate output_stage - -- purpose: registers first stage - -- type : sequential - -- inputs : clk, reset, data_in - -- outputs: mem_in - reg_output : process (clk, reset) is - begin -- process reg_output - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - elsif rising_edge(clk) then -- rising clock edge - if enable = '1' then - if extended_reset = '1' then - dataout <= (others => '0'); - else - dataout <= mem_out; - end if; - end if; - end if; - end process reg_output; - end generate output_stage; - - bypass_output_stage : if REGISTER_LAST_g = 0 generate - begin -- generate bypass_output_stage - dataout <= mem_out when extended_reset = '0' else - (others => '0'); - end generate bypass_output_stage; - - check_illegal_generic2 : if REGISTER_LAST_g > 1 generate - begin -- generate check_illegal_generic2 - assert false report "Generic REGISTER_LAST_g in FU : DELAY must be 0 or 1" severity failure; - end generate check_illegal_generic2; - - -- purpose: creates an extended reset, that is high for MEM_DEPTH_c clock cycles. - -- This signal is used to 0 out the first MEM_DEPTH values from the delay register. - -- type : sequential - -- inputs : clk, resenable - -- outputs: extended_reset - extend_reset : process (clk, reset) is - begin -- process extended_reset - if reset = '1' then -- asynchronous reset (active high) - extended_reset <= '1'; - count_after_reset <= (others => '0'); - elsif rising_edge(clk) then -- rising clock edge - if enable = '1' then - if count_after_reset < mem_depth then - count_after_reset <= count_after_reset + 1; - extended_reset <= '1'; - else - extended_reset <= '0'; - end if; - end if; - end if; - end process extend_reset; - - end generate memory_fifo; - - -end architecture rtl; diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd deleted file mode 100644 index 3293d7a..0000000 Binary files a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_downsample.sv b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_downsample.sv deleted file mode 100644 index bdc5d8e..0000000 Binary files a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_downsample.sv and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd deleted file mode 100644 index ec7fa43..0000000 --- a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd +++ /dev/null @@ -1,88 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -entity auk_dspip_fastadd is - generic ( - INWIDTH_g : natural := 18; - LABWIDTH_g : natural := 16); - -- width of lab in selected device ( 10 or 16 in Cyclone, - -- Cylone II, Stratix and Stratix II. Don't know - -- Stratix III yet. - port ( - datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); - datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); - clk : in std_logic; - enable : in std_logic; - reset : in std_logic; - dataout : out std_logic_vector(INWIDTH_g downto 0)); -end entity auk_dspip_fastadd; - - -architecture beh of auk_dspip_fastadd is - - constant LOWWIDTH_c : natural := LABWIDTH_g * (1 + integer(INWIDTH_g/(LABWIDTH_g*2))); - constant asdf : natural := integer(INWIDTH_g/(LABWIDTH_g*2)); - constant asdf2 : natural := 1+integer(INWIDTH_g/(LABWIDTH_g*2)); - constant asdf3 : natural := LABWIDTH_g * (1+integer(INWIDTH_g/(LABWIDTH_g*2))); - - constant HIGHWIDTH_c : natural := INWIDTH_g-LOWWIDTH_c; - - - signal datain1_low : std_logic_vector(LOWWIDTH_c-1 downto 0); - signal datain1_high : std_logic_vector(HIGHWIDTH_c-1 downto 0); - signal datain2_low : std_logic_vector(LOWWIDTH_c-1 downto 0); - signal datain2_high : std_logic_vector(HIGHWIDTH_c-1 downto 0); - signal result_low : std_logic_vector(LOWWIDTH_c downto 0); - signal result_high_cin0 : std_logic_vector(HIGHWIDTH_c downto 0); - signal result_high_cin1 : std_logic_vector(HIGHWIDTH_c downto 0); - - attribute keep : boolean; - attribute keep of result_high_cin0 : signal is true; - attribute keep of result_high_cin1 : signal is true; - -begin -- architecture beh - - datain1_low <= datain1(LOWWIDTH_c-1 downto 0); - datain1_high <= datain1(HIGHWIDTH_c+LOWWIDTH_c-1 downto LOWWIDTH_c); - datain2_low <= datain2(LOWWIDTH_c-1 downto 0); - datain2_high <= datain2(HIGHWIDTH_c+LOWWIDTH_c-1 downto LOWWIDTH_c); - - adder_process : process (clk, reset) is - begin -- process adder_process - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - elsif rising_edge(clk) then -- rising clock edge - if enable = '1' then - if result_low(LOWWIDTH_c) = '1' then - dataout <= result_high_cin1 & result_low(LOWWIDTH_c-1 downto 0); - else - dataout <= result_high_cin0 & result_low(LOWWIDTH_c-1 downto 0); - end if; - end if; - end if; - end process adder_process; - - result_low <= std_logic_vector(unsigned('0' & datain1_low) + unsigned('0' & datain2_low)); - result_high_cin0 <= std_logic_vector(unsigned(datain1_high(HIGHWIDTH_c-1) & datain1_high) + - unsigned(datain2_high(HIGHWIDTH_c-1) & datain2_high)); - result_high_cin1 <= std_logic_vector(unsigned(datain1_high(HIGHWIDTH_c-1) & datain1_high )+ - unsigned(datain2_high(HIGHWIDTH_c-1) & datain2_high )+ - 1); - - -end architecture beh; diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd deleted file mode 100644 index 312e756..0000000 --- a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd +++ /dev/null @@ -1,160 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - -------------------------------------------------------------------------- -------------------------------------------------------------------------- --- --- Revision Control Information --- --- $RCSfile: $ --- $Source: $ --- --- $Revision: #1 $ --- $Date: 2018/07/18 $ --- Check in by : $Author: psgswbuild $ --- Author : Volker Mauer --- --- Project : auk_dspip_fastaddsub --- --- Description : --- --- This functional unit can be used to perform an addition or subtraction --- in a single clock cycle faster than in a standard adder, by means of a --- carry select structure. --- --- This means that the adder is split into a lower part and an upper part. --- The upper part is implemented twice: Once with the carry_in fixed to '0' --- and once with the carry_in fixed to '1'. The carry_out of the lower part --- is used to control a mux selecting the two possible upper results. --- --- This structucture is useful where the width is so great that the standard --- adder would be slower than the DSP block, and a pipelined adder cannot be --- used, like in accumulators. --- --- There is a device dependency: The width of the lower part, where 1 LE per --- bit is required, should be greater than half the overall width, and --- ideally be selected to fit into labs of the target device. The upper --- half, where 3 LEs per bit are needed, should add the remaining bits. --- --- Given the width and the labwidth, the function will automatically calculate --- the width of lower and upper parts using the following formula: --- --- Wlow = Wlab * ceil(Win / (2*Wlab)) --- Whigh = Win-Wlow --- --- Example: If the adder is 48 bits in, the lab width is 10, we would --- get Wlow = 30, Whigh=18. --- --- ALTERA Confidential and Proprietary --- Copyright 2006 (c) Altera Corporation --- All rights reserved --- -------------------------------------------------------------------------- -------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -entity auk_dspip_fastaddsub is - generic ( - INWIDTH_g : natural := 18; - LABWIDTH_g : natural := 16); - -- width of lab in selected device ( 10 or 16 in Cyclone, - -- Cylone II, Stratix and Stratix II. Don't know - -- Stratix III yet. - port ( - datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); - datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); - add_nsub : in std_logic; - clk : in std_logic; - enable : in std_logic; - reset : in std_logic; - dataout : out std_logic_vector(INWIDTH_g downto 0)); -end entity auk_dspip_fastaddsub; - - -architecture beh of auk_dspip_fastaddsub is - - constant LOWWIDTH_c : natural := LABWIDTH_g * (1 + integer(INWIDTH_g/(LABWIDTH_g*2))); - constant asdf : natural := integer(INWIDTH_g/(LABWIDTH_g*2)); - constant asdf2 : natural := 1+integer(INWIDTH_g/(LABWIDTH_g*2)); - constant asdf3 : natural := LABWIDTH_g * (1+integer(INWIDTH_g/(LABWIDTH_g*2))); - - constant HIGHWIDTH_c : natural := INWIDTH_g-LOWWIDTH_c; - - - signal datain1_low : std_logic_vector(LOWWIDTH_c-1 downto 0); - signal datain1_high : std_logic_vector(HIGHWIDTH_c-1 downto 0); - signal datain2_low : std_logic_vector(LOWWIDTH_c-1 downto 0); - signal datain2_high : std_logic_vector(HIGHWIDTH_c-1 downto 0); - signal result_low : std_logic_vector(LOWWIDTH_c downto 0); - signal result_high_cin0 : std_logic_vector(HIGHWIDTH_c downto 0); - signal result_high_cin1 : std_logic_vector(HIGHWIDTH_c downto 0); - - ----------------------------------------------------------------------------- - -- Synthesis tools have got clever. Need to set "keep" attribute, or the - -- synthesis tool will recognise the structure as a standard adder, and - -- optimise it accordingly. - ----------------------------------------------------------------------------- - attribute keep : boolean; - attribute keep of result_high_cin0 : signal is true; - attribute keep of result_high_cin1 : signal is true; - -begin -- architecture beh - - ----------------------------------------------------------------------------- - -- split inputs into upper and lower halves - ----------------------------------------------------------------------------- - datain1_low <= datain1(LOWWIDTH_c-1 downto 0); - datain1_high <= datain1(HIGHWIDTH_c+LOWWIDTH_c-1 downto LOWWIDTH_c); - datain2_low <= datain2(LOWWIDTH_c-1 downto 0); - datain2_high <= datain2(HIGHWIDTH_c+LOWWIDTH_c-1 downto LOWWIDTH_c); - - ----------------------------------------------------------------------------- - -- perform separate additions/subtractions for upper and lower halves - ----------------------------------------------------------------------------- - result_low <= std_logic_vector(unsigned('0' & datain1_low) + unsigned('0' & datain2_low)) when add_nsub='1' else - std_logic_vector(unsigned('0' & datain1_low) - unsigned('0' & datain2_low)); - result_high_cin0 <= std_logic_vector(unsigned(datain1_high(HIGHWIDTH_c-1) & datain1_high) + - unsigned(datain2_high(HIGHWIDTH_c-1) & datain2_high)) when add_nsub='1' else - std_logic_vector(unsigned(datain1_high(HIGHWIDTH_c-1) & datain1_high) - - unsigned(datain2_high(HIGHWIDTH_c-1) & datain2_high)); - result_high_cin1 <= std_logic_vector(unsigned(datain1_high(HIGHWIDTH_c-1) & datain1_high )+ - unsigned(datain2_high(HIGHWIDTH_c-1) & datain2_high )+ - 1) when add_nsub = '1' else - std_logic_vector(unsigned(datain1_high(HIGHWIDTH_c-1) & datain1_high )- - unsigned(datain2_high(HIGHWIDTH_c-1) & datain2_high )- - 1); - - ----------------------------------------------------------------------------- - -- multiplex (select) the upper half, register selected upper half and lower - -- half. - ----------------------------------------------------------------------------- - adder_process : process (clk, reset) is - begin -- process adder_process - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - elsif rising_edge(clk) then -- rising clock edge - if enable = '1' then - if result_low(LOWWIDTH_c) = '1' then - dataout <= result_high_cin1 & result_low(LOWWIDTH_c-1 downto 0); - else - dataout <= result_high_cin0 & result_low(LOWWIDTH_c-1 downto 0); - end if; - end if; - end if; - end process adder_process; - - -end architecture beh; diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_integrator.vhd b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_integrator.vhd deleted file mode 100644 index 801c66f..0000000 Binary files a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_integrator.vhd and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd deleted file mode 100644 index 3ee6f10..0000000 --- a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd +++ /dev/null @@ -1,630 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - ---This file is auto-generated by compile_dspip_lib.pl ---Date:06/07/2007 - ---Time:19:15 - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; --- Alex, 02-10-07, this package declaration results in error at built time on a new machine --- -use work.auk_dspip_math_pkg.all; - -package auk_dspip_lib_pkg is ---Component names: ---auk_fifo ---auk_dspip_atlantic_sink ---auk_dspip_atlantic_source ---auk_dspip_interface_controller ---auk_dspip_avalon_streaming_controller ---auk_dspip_avalon_streaming_controller_pe ---auk_dspip_avalon_streaming_sink ---auk_dspip_avalon_streaming_source ---auk_dspip_delay ---auk_dspip_fastadd ---auk_dspip_fastaddsub ---auk_dspip_pipelined_adder ---auk_dspip_fast_accumulator ---auk_dspip_fifo_pfc ---auk_dspip_fpcompiler_alufp ---auk_dspip_fpcompiler_aslf ---auk_dspip_fpcompiler_asrf ---auk_dspip_fpcompiler_castftox ---auk_dspip_fpcompiler_castxtof ---auk_dspip_fpcompiler_clzf ---auk_dspip_fpcompiler_mulfp ---auk_dspip_pfc ---auk_dspip_roundsat - - -component auk_fifo is -generic ( - DATA_WIDTH : natural := 32; - SIZE : natural := 10; - ALMOST_EMPTY_BOUND : natural := 3; - ALMOST_FULL_BOUND : natural := 500 - ); -port ( - clk : in std_logic; - reset : in std_logic; - - read_req : in std_logic; - write_req : in std_logic; - - data_in : in std_logic_vector(DATA_WIDTH-1 DOWNTO 0); - data_out : out std_logic_vector(DATA_WIDTH-1 DOWNTO 0); - - almost_full : out std_logic; - almost_empty : out std_logic; - empty : out std_logic; - full : out std_logic - - ); - -end component auk_fifo; - -component auk_dspip_atlantic_sink is - - generic( - WIDTH : integer := 16; - PACKET_SIZE : natural := 4; - log2packet_size : integer := 2 - ); - port( - clk : in std_logic; - reset_n : in std_logic; - ----------------- DESIGN SIDE SIGNALS - data_available : out std_logic; --goes high when new data is available - data : out std_logic_vector(WIDTH-1 downto 0); - sink_ready_ctrl : in std_logic; --the controller will tell - --the interface whether - --new input can be accepted. - sink_stall : out std_logic; --needs to stall the design - --if no new data is coming - packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only. - --when any of these doesn't behave as - --expected, the error is flagged. - send_sop : out std_logic; -- transmit SOP signal to the design. - -- It only transmits the legal SOP. - send_eop : out std_logic; -- transmit EOP signal to the design. - -- It only transmits the legal EOP. - ----------------- ATLANTIC SIDE SIGNALS - at_sink_ready : out std_logic; --it will be '1' whenever the - --sink_ready_ctrl signal is high. - at_sink_valid : in std_logic; - at_sink_data : in std_logic_vector(WIDTH-1 downto 0); - at_sink_sop : in std_logic := '0'; - at_sink_eop : in std_logic := '0'; - at_sink_error : in std_logic_vector(1 downto 0) --it indicates to the data source - --that the SOP and EOP signals - --are not received as expected. - - ); - -end component auk_dspip_atlantic_sink; - -component auk_dspip_atlantic_source is - generic( - WIDTH : integer := 16; - packet_size : natural := 4; - LOG2packet_size : integer := 2; - multi_channel : BOOLEAN := TRUE - ); - port( - clk : in std_logic; - reset_n : in std_logic; - ----------------- DESIGN SIDE SIGNALS - data : in std_logic_vector (WIDTH-1 downto 0); - data_count : in std_logic_vector (LOG2packet_size-1 downto 0) := (others => '0'); - source_valid_ctrl : in std_logic; --the controller will tell - --the interface whether - --new input can be accepted. - source_stall : out std_logic; --needs to stall the design - --if no new data is coming - packet_error : in std_logic_vector (1 downto 0); - ----------------- ATLANTIC SIDE SIGNALS - at_source_ready : in std_logic; - at_source_valid : out std_logic; - at_source_data : out std_logic_vector (WIDTH-1 downto 0); - at_source_channel : out std_logic_vector (log2packet_size-1 downto 0); - at_source_error : out std_logic_vector (1 downto 0); - at_source_sop : out std_logic; - at_source_eop : out std_logic - ); - --- Declarations - -end component auk_dspip_atlantic_source; - - -component auk_dspip_interface_controller IS - PORT( - clk : in std_logic; - reset : IN std_logic; - ready : in std_logic; - sink_packet_error : IN std_logic_vector (1 DOWNTO 0); - sink_stall : IN std_logic; - source_stall : IN std_logic; - valid : IN std_logic; - reset_design : OUT std_logic; - reset_n : OUT std_logic; - sink_ready_ctrl : OUT std_logic; - source_packet_error : OUT std_logic_vector (1 DOWNTO 0); - source_valid_ctrl : OUT std_logic; - stall : OUT std_logic - ); - --- Declarations - -end component auk_dspip_interface_controller ; - - -component auk_dspip_avalon_streaming_controller is - port( - clk : in std_logic; - clk_en : in std_logic := '1'; - reset_n : in std_logic; - ready : in std_logic; - sink_packet_error : in std_logic_vector (1 downto 0); - sink_stall : in std_logic; - source_stall : in std_logic; - valid : in std_logic; - reset_design : out std_logic; - sink_ready_ctrl : out std_logic; - source_packet_error : out std_logic_vector (1 downto 0); - source_valid_ctrl : out std_logic; - stall : out std_logic - ); - --- Declarations - -end component auk_dspip_avalon_streaming_controller; - -component auk_dspip_avalon_streaming_controller_pe is - generic ( - FIFO_WIDTH_g : natural := 8; - ENABLE_PIPELINE_DEPTH_g : natural := 0; -- this value should match the depth of the enable pipeline in the core - FAMILY_g : string := "Stratix II"; - MEM_TYPE_g : string := "Auto" - ); - port( - clk : in std_logic; - clk_en : in std_logic := '1'; - reset_n : in std_logic; - ready : in std_logic; - sink_packet_error : in std_logic_vector (1 downto 0); - sink_stall : in std_logic; - source_stall : in std_logic; - valid : in std_logic; - reset_design : out std_logic; - sink_ready_ctrl : out std_logic; - source_packet_error : out std_logic_vector (1 downto 0); - source_valid_ctrl : out std_logic; - stall : out std_logic; - data_in : in std_logic_vector(FIFO_WIDTH_g-1 downto 0); - data_out : out std_logic_vector(FIFO_WIDTH_g-1 downto 0); - design_stall : out std_logic - ); - --- Declarations - -end component auk_dspip_avalon_streaming_controller_pe; - -component auk_dspip_avalon_streaming_sink is - - generic( - WIDTH_g : integer := 16; - PACKET_SIZE_g : natural := 4; - FIFO_DEPTH_g : natural := 5; --if PFC mode is selected, this generic - --is used for passing the poly_factor. - MIN_DATA_COUNT_g : natural := 2; - PFC_MODE_g : string := "false"; - SOP_EOP_CALC_g : string := "false"; -- calculate sop and eop rather than - -- reading value from fifo - FAMILY_g : string := "Stratix II"; - MEM_TYPE_g : string := "Auto" - ); - port( - clk : in std_logic; - reset_n : in std_logic; - ----------------- DESIGN SIDE SIGNALS - data : out std_logic_vector(WIDTH_g-1 downto 0); - sink_ready_ctrl : in std_logic; --the controller will tell - --the interface whether - --new input can be accepted. - sink_stall : out std_logic; --needs to stall the design - --if no new data is coming - packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only. - --when any of these doesn't behave as - --expected, the error is flagged. - send_sop : out std_logic; -- transmit SOP signal to the design. - -- It only transmits the legal SOP. - send_eop : out std_logic; -- transmit EOP signal to the design. - -- It only transmits the legal EOP. - ----------------- ATLANTIC SIDE SIGNALS - at_sink_ready : out std_logic; --it will be '1' whenever the - --sink_ready_ctrl signal is high. - at_sink_valid : in std_logic; - at_sink_data : in std_logic_vector(WIDTH_g-1 downto 0); - at_sink_sop : in std_logic := '0'; - at_sink_eop : in std_logic := '0'; - at_sink_error : in std_logic_vector(1 downto 0) := "00" --it indicates - --that there is an error in the packet. - - ); - -end component auk_dspip_avalon_streaming_sink; - -component auk_dspip_avalon_streaming_source is - generic( - WIDTH_g : integer := 16; - PACKET_SIZE_g : natural := 4; - HAVE_COUNTER_g : string := "false"; - COUNTER_LIMIT_g : natural := 4; - MULTI_CHANNEL_g : string := "true" - ); - port( - clk : in std_logic; - reset_n : in std_logic; - ----------------- DESIGN SIDE SIGNALS - data : in std_logic_vector (WIDTH_g-1 downto 0); - data_count : in std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0'); - source_valid_ctrl : in std_logic; - design_stall : in std_logic; - source_stall : out std_logic; - packet_error : in std_logic_vector (1 downto 0); - ----------------- AVALON_STREAMING SIDE SIGNALS - at_source_ready : in std_logic; - at_source_valid : out std_logic; - at_source_data : out std_logic_vector (WIDTH_g-1 downto 0); - at_source_channel : out std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0); - at_source_error : out std_logic_vector (1 downto 0); - at_source_sop : out std_logic; - at_source_eop : out std_logic - ); - --- Declarations - -end component auk_dspip_avalon_streaming_source; - - -component auk_dspip_delay is - generic ( - WIDTH_g : natural := 8; -- data width - DELAY_g : natural := 8; - -- number of clock cycles the input - -- will be delayed by - MEMORY_TYPE_g : string := "AUTO"; - -- possible values are "m4k", "m512", - -- "register", "mram", "auto", - -- "lutram", "M9K", "M144K". - -- Any other string will be interpreted - -- as "auto" - REGISTER_FIRST_g : natural := 1; - -- if "1", the first delay is guaranteed - -- to be in registers - REGISTER_LAST_g : natural := 1); -- if "1", the last delay is guaranteed - -- to be in registers - port ( - clk : in std_logic; - reset : in std_logic; - enable : in std_logic; -- global clock enable - datain : in std_logic_vector(WIDTH_g-1 downto 0); - dataout : out std_logic_vector(WIDTH_g-1 downto 0) - ); -end component auk_dspip_delay; - - -component auk_dspip_fastadd is - generic ( - INWIDTH_g : natural := 18; - LABWIDTH_g : natural := 16); - -- width of lab in selected device ( 10 or 16 in Cyclone, - -- Cylone II, Stratix and Stratix II. Don't know - -- Stratix III yet. - port ( - datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); - datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); - clk : in std_logic; - enable : in std_logic; - reset : in std_logic; - dataout : out std_logic_vector(INWIDTH_g downto 0)); -end component auk_dspip_fastadd; - - -component auk_dspip_fastaddsub is - generic ( - INWIDTH_g : natural := 18; - LABWIDTH_g : natural := 16); - -- width of lab in selected device ( 10 or 16 in Cyclone, - -- Cylone II, Stratix and Stratix II. Don't know - -- Stratix III yet. - port ( - datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); - datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); - add_nsub : in std_logic; - clk : in std_logic; - enable : in std_logic; - reset : in std_logic; - dataout : out std_logic_vector(INWIDTH_g downto 0)); -end component auk_dspip_fastaddsub; - - -component auk_dspip_pipelined_adder is - generic ( - INWIDTH_g : natural := 42; - -- width of lab in selected device ( 10 or 16 in Cyclone, - -- Cylone II, Stratix and Stratix II. - -- Alex : should I use 19 bits for Stratix III? - -- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency. - LABWIDTH_g : natural := 38); - port ( - datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); - datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); - clk : in std_logic; - enable : in std_logic; - reset : in std_logic; - dataout : out std_logic_vector(INWIDTH_g downto 0)); -end component auk_dspip_pipelined_adder; - - -component auk_dspip_fast_accumulator is - generic ( - DATA_WIDTH_g : natural := 42; - -- width of lab in selected device ( 10 or 16 in Cyclone, - -- Cylone II, Stratix and Stratix II. - -- for Stratix III is 20 so labwidth should be set to 18. - -- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency. - LABWIDTH_g : natural := 38; - NUM_OF_CHANNELS_g : natural := 1; - ACCUM_OUT_WIDTH_g : natural := 48; - ACCUM_MEM_TYPE_g : string := "auto"); - port ( - reset : in std_logic; - clk : in std_logic; - enb : in std_logic; - add_to_zero : in std_logic; - datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0); - datao : out std_logic_vector(ACCUM_OUT_WIDTH_g-1 downto 0)); -end component auk_dspip_fast_accumulator; - - -component auk_dspip_fifo_pfc is - generic ( - NUM_CHANNELS_g : integer := 5; - POLY_FACTOR_g : integer := 3; - DATA_WIDTH_g : integer := 16; - ALMOST_FULL_VALUE_g : integer := 2; - RAM_TYPE_g : string := "AUTO"; - CALCULATE_USED_WORDS_ONCE : boolean := true - ); - port ( - - datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0); - datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0); - channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0); - used_w : out std_logic_vector(log2_ceil(POLY_FACTOR_g * NUM_CHANNELS_g)+1 downto 0); - - wrreq : in std_logic; - rdreq : in std_logic; - almost_full : out std_logic; - empty : out std_logic; - sclr : in std_logic; - clk : in std_logic; - reset : in std_logic; - enable : in std_logic - ); -end component auk_dspip_fifo_pfc; -component auk_dspip_fpcompiler_alufp is - port ( - sysclk : in std_logic; - reset : in std_logic; - enable : in std_logic; - addsub : in std_logic; - aa : in std_logic_vector (42 downto 1); - aasat, aazip : in std_logic; - bb : in std_logic_vector (42 downto 1); - bbsat, bbzip : in std_logic; - cc : out std_logic_vector (42 downto 1); - ccsat, cczip : out std_logic - ); -end component auk_dspip_fpcompiler_alufp; -component auk_dspip_fpcompiler_aslf is - port ( - inbus : in std_logic_vector (32 downto 1); - shift : in std_logic_vector (5 downto 1); - - outbus : out std_logic_vector (32 downto 1) - ); -end component auk_dspip_fpcompiler_aslf; -component auk_dspip_fpcompiler_asrf is - port ( - inbus : in std_logic_vector (32 downto 1); - shift : in std_logic_vector (5 downto 1); - - outbus : out std_logic_vector (32 downto 1) - ); -end component auk_dspip_fpcompiler_asrf; - -component auk_dspip_fpcompiler_castftox is - port ( - aa : in std_logic_vector (32 downto 1); - cc : out std_logic_vector (42 downto 1); - ccsat, cczip : out std_logic - ); -end component auk_dspip_fpcompiler_castftox; - -component auk_dspip_fpcompiler_castxtof is - port ( - sysclk : in std_logic; - reset : in std_logic; - enable : in std_logic; - aa : in std_logic_vector (42 downto 1); - aasat, aazip : in std_logic; - cc : out std_logic_vector (32 downto 1) - ); -end component auk_dspip_fpcompiler_castxtof; - -component auk_dspip_fpcompiler_clzf is - port ( - frac : in std_logic_vector (32 downto 1); - count : out std_logic_vector (5 downto 1) - ); -end component auk_dspip_fpcompiler_clzf; -component auk_dspip_fpcompiler_mulfp is - port ( - sysclk : in std_logic; - reset : in std_logic; - enable : in std_logic; - aa : in std_logic_vector (42 downto 1); - aasat, aazip : in std_logic; - bb : in std_logic_vector (42 downto 1); - bbsat, bbzip : in std_logic; - cc : out std_logic_vector (42 downto 1); - ccsat, cczip : out std_logic - ); -end component auk_dspip_fpcompiler_mulfp; - -component auk_dspip_pfc is - generic ( - NUM_CHANNELS_g : integer := 5; - POLY_FACTOR_g : integer := 3; - DATA_WIDTH_g : integer := 16; - RAM_TYPE_g : string := "AUTO" - ); - port ( - - datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0); - datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0); - channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0); - - in_valid : in std_logic; - out_valid : out std_logic; - clk : in std_logic; - reset : in std_logic; - enable : in std_logic - ); -end component auk_dspip_pfc; - - -component auk_dspip_roundsat is - generic ( - IN_WIDTH_g : natural := 8; -- data width - OUT_WIDTH_g : natural := 8; -- data width - LATENCY : natural := 1; - ROUNDING_TYPE_g : string := "TRUNCATE_LOW" - ); - - port ( - clk : in std_logic; - reset : in std_logic; - enable : in std_logic; -- global clock enable - datain : in std_logic_vector(IN_WIDTH_g-1 downto 0); - dataout : out std_logic_vector(OUT_WIDTH_g-1 downto 0)); -end component auk_dspip_roundsat; - -component auk_dspip_avalon_streaming_block_source is - generic ( - MAX_BLK_g : natural; - DATAWIDTH_g : natural; - HYPER_OPTIMIZATION : natural := 0); - port ( - clk : in std_logic; - reset : in std_logic; - in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0); - in_valid : in std_logic; - source_stall : out std_logic; - in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0); - source_valid : out std_logic; - source_ready : in std_logic; - source_sop : out std_logic; - source_eop : out std_logic; - source_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0)); -end component auk_dspip_avalon_streaming_block_source; - -component auk_dspip_avalon_streaming_block_sink is - generic ( - MAX_BLK_g : natural; - STALL_g : natural; - DATAWIDTH_g : natural; - -- this generic is specific for the FFT. - NUM_STAGES_g : natural; - FFT_ARCH : string; - HYPER_OPTIMIZATION : natural := 0); - port ( - clk : in std_logic; - reset : in std_logic; - in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0); - in_sop : in std_logic; - in_eop : in std_logic; - in_inverse : in std_logic; - sink_valid : in std_logic; - sink_ready : out std_logic; - source_stall : in std_logic; - in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0); - processing : in std_logic; - in_error : in std_logic_vector(1 downto 0); - out_error : out std_logic_vector(1 downto 0); - out_valid : out std_logic; - out_sop : out std_logic; - out_eop : out std_logic; - out_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0); - curr_blk : out std_logic_vector(log2_ceil(MAX_BLK_g) downto 0); - -- these are specific to the FFT, no effort has been made to optimize! - curr_pwr_2 : out std_logic; - curr_inverse : out std_logic; - curr_input_sel : out std_logic_vector(NUM_STAGES_g - 1 downto 0)); -end component auk_dspip_avalon_streaming_block_sink; - -component auk_dspip_avalon_streaming_block_sink_fftfprvs is - generic ( - MAX_BLK_g : natural; - STALL_g : natural; - DATAWIDTH_g : natural; - -- this generic is specific for the FFT. - NUM_STAGES_g : natural; - FFT_ARCH : string); - port ( - clk : in std_logic; - reset : in std_logic; - in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0); - in_sop : in std_logic; - in_eop : in std_logic; - in_inverse : in std_logic; - sink_valid : in std_logic; - sink_ready : out std_logic; - source_stall : in std_logic; - in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0); - processing : in std_logic; - in_error : in std_logic_vector(1 downto 0); - out_error : out std_logic_vector(1 downto 0); - out_valid : out std_logic; - out_sop : out std_logic; - out_eop : out std_logic; - out_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0); - curr_blk : out std_logic_vector(log2_ceil(MAX_BLK_g) downto 0); - mlenfor : out std_logic_vector(log2_ceil(4**NUM_STAGES_g) downto 0); - mlentwo : out std_logic_vector(log2_ceil(4**NUM_STAGES_g) downto 0); - -- these are specific to the FFT, no effort has been made to optimize! - curr_pwr_2 : out std_logic; - curr_inverse : out std_logic; - curr_input_sel : out std_logic_vector(NUM_STAGES_g - 1 downto 0)); -end component auk_dspip_avalon_streaming_block_sink_fftfprvs; - - -end package auk_dspip_lib_pkg; diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd deleted file mode 100644 index 305288c..0000000 --- a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd +++ /dev/null @@ -1,367 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - -------------------------------------------------------------------------- -------------------------------------------------------------------------- --- --- Revision Control Information --- --- $RCSfile: auk_dspip_math_pkg.vhd,v $ --- $Source: /cvs/uksw/dsp_cores/lib/packages/auk_dspip_math_pkg.vhd,v $ --- --- $Revision: #1 $ --- $Date: 2018/07/18 $ --- Check in by : $Author: psgswbuild $ --- Author : DSP_IP --- --- Project : --- --- Description : --- --- Common functions for DSP_IP cores. --- --- --- $Log: auk_dspip_math_pkg.vhd,v $ --- Revision 1.4 2006/07/28 18:52:50 sdemirso --- no compilation errors with the new directory structure --- --- Revision 1.3 2006/07/28 10:27:30 sdemirso --- Header updated --- --- ALTERA Confidential and Proprietary --- Copyright 2006 (c) Altera Corporation --- All rights reserved --- -------------------------------------------------------------------------- -------------------------------------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; -PACKAGE auk_dspip_math_pkg IS - - - ----------------------------------------------------------------------------- - -- NOTE that these log functions are not intended to synthesize directly - -- into hardware, rather they are used to generate constants for - -- synthesized hardware. - ----------------------------------------------------------------------------- - --------------------------------------------------------------------------- - -- LOG2_CEIL Function. - -- Effectively performs log2() followed by ceil() - -- e.g. CEIL_LOG2(255) returns 8 - -- CEIL_LOG2(256) returns 8 - -- CEIL_LOG2(257) returns 9 - --------------------------------------------------------------------------- - function log2_ceil(arg : in integer) return integer; - function log2_ceil_one(arg : in integer) return integer; -- log2_ceil(1)=0 - --------------------------------------------------------------------------- - -- LOG2_FLOOR Function. - -- Effectively performs log2() followed by floor() - -- e.g. CEIL_LOG2(255) returns 7 - -- CEIL_LOG2(256) returns 8 - -- CEIL_LOG2(257) returns 8 - --------------------------------------------------------------------------- - function log2_floor(arg : in integer) return integer; - - ----------------------------------------------------------------------------- - -- SIGN functions - ----------------------------------------------------------------------------- - -- returns the sign bit of a vector - function sign (arg : in signed) return std_logic; - - -- sign extends ARG to size SIZE. - function sign_extend (arg : in signed; size : in positive) return signed; - - -- sign extend one bit - function xt1 (arg : in signed) return signed; - - --------------------------------------------------------------------------- - -- Arithmetic FUNCTIONs. - --------------------------------------------------------------------------- - -- Check integer for odd-ness - function is_odd(arg : integer) return boolean; - - ----------------------------------------------------------------------------- - -- Logical functions - ----------------------------------------------------------------------------- - -- Result of and'ing all of the bits of the vector. - function and_reduce(arg : std_logic_vector) return std_logic; - function and_reduce(arg : unsigned) return std_logic; - - -- Result of or'ing all of the bits of the vector. - function or_reduce(arg : std_logic_vector) return std_logic; - function or_reduce(arg : unsigned) return std_logic; - - -- returns index+1 of the highest asserted bit. - function highest_one(arg : unsigned) return natural; - - -- returns index+1 of the lowest asserted bit. - function lowest_one(arg : unsigned) return natural; - - -- returns the count of number of ones. - function count_ones(arg : unsigned) return natural; - - -- Bit reverse - function bit_reverse(arg : unsigned) return unsigned; - - -- Invert the argument bitwise - function invert(arg : unsigned) return unsigned; - - --Halve towards up - function halve_ceil(arg:natural) return natural; - - function div_ceil(a:natural;b:natural) return natural; - -END PACKAGE auk_dspip_math_pkg; - -package body auk_dspip_math_pkg is - --------------------------------------------------------------------------- - -- LOG2_CEIL Function. - --------------------------------------------------------------------------- - function log2_ceil(arg : in integer) return integer is - variable res : integer; - begin - res := 0; - for i in 0 to 30 loop - if (arg > (2**i)) then - res := i+1; - end if; - end loop; -- i - return res; - end log2_ceil; - --------------------------------------------------------------------------- - -- LOG2_CEIL_ONE Function. - --------------------------------------------------------------------------- - function log2_ceil_one(arg : in integer) return integer is - variable res : integer; - begin - res := 0; - for i in 0 to 30 loop - if (arg > (2**i)) then - res := i+1; - end if; - end loop; -- i - if res = 0 then - res := 1; - end if; - return res; - end log2_ceil_one; - - --------------------------------------------------------------------------- - -- LOG2_FLOOR Function. - ----------------------------------------------------------------------------- - function log2_floor(arg : in integer) return integer is - variable res : integer; - begin - res := 0; - for i in 0 to 30 loop - if (arg >= (2**i)) then - res := i; - end if; - end loop; -- i - return res; - end log2_floor; - - ----------------------------------------------------------------------------- - -- SIGN Function - ----------------------------------------------------------------------------- - function sign (arg : in signed) return std_logic is - variable res : std_logic; - begin - res := arg(arg'left); - return(res); - end sign; - - ----------------------------------------------------------------------------- - -- SIGN_EXTEND Function - ----------------------------------------------------------------------------- - function sign_extend (arg : in signed; size : in positive) return signed is - variable res : signed(size-1 downto 0); - begin - if arg'length > size then - assert arg'length < size report "WARNING, can't sign extend" severity warning; - end if; - for i in arg'length to size-1 loop - res(i) := arg(arg'left); - end loop; -- i - res(arg'length-1 downto 0) := arg; - return(res); - end sign_extend; - - ----------------------------------------------------------------------------- - -- XT1 Function - ----------------------------------------------------------------------------- - function xt1 (arg : in signed) return signed is - variable res : signed(arg'length downto 0); - begin - res := arg(arg'left) & arg; - return(res); - end xt1; - - ----------------------------------------------------------------------------- - -- IS_ODD Function - ----------------------------------------------------------------------------- - function is_odd(arg : integer) return boolean is - begin - return ((arg mod 2) = 1); - end is_odd; - - - ----------------------------------------------------------------------------- - -- AND_REDUCE Function - ----------------------------------------------------------------------------- - function and_reduce(arg : std_logic_vector) return std_logic is - variable res : std_logic; - begin - res := '1'; - for i in arg'range loop - res := res and arg(i); - end loop; - return res; - end; - - function and_reduce(arg : unsigned) return std_logic is - variable res : std_logic; - begin - res := '1'; - for i in arg'range loop - res := res and arg(i); - end loop; - return res; - end; - - - ----------------------------------------------------------------------------- - -- OR_REDUCE Function - ----------------------------------------------------------------------------- - function or_reduce(arg : unsigned) return std_logic is - variable res : std_logic; - begin - res := '0'; - for i in arg'range loop - res := res or arg(i); - end loop; - return res; - end; - - function or_reduce(arg : std_logic_vector) return std_logic is - variable res : std_logic; - begin - res := '0'; - for i in arg'range loop - res := res or arg(i); - end loop; - return res; - end; - - --------------------------------------------------------------------------- - -- HIGHEST_ONE Function. - --------------------------------------------------------------------------- - -- Returns index+1 of the highest asserted bit, or 0 if no bit set. - -- Vector is evaluated from left to right, not high to low! - function highest_one(arg : unsigned) return natural is - begin - for i in arg'range loop - if arg(i) = '1' then - return i+1; - end if; - end loop; - return 0; - end; - - ----------------------------------------------------------------------------- - -- LOWEST_ONE Function - ----------------------------------------------------------------------------- - -- Returns index+1 of the lowest asserted bit, or 0 if no bit set. - -- Vector is evaluated from left to right, not high to low! - function lowest_one(arg : unsigned) return natural is - begin - for i in 0 to arg'length-1 loop - if (arg(i) = '1') then - return(i+1); - end if; - end loop; - return(0); - end; - - ----------------------------------------------------------------------------- - -- COUNT_ONES - --------------------------------------------------------------------------- - -- Returns the count of the number of ones. - function count_ones(arg : unsigned) return natural is - variable count : integer; - begin - count := 0; - for i in 0 to arg'length-1 loop - if (arg(i) = '1') then - count := count + 1; - end if; - end loop; - return count; - end; - - ----------------------------------------------------------------------------- - -- BIT_REVERSE function - ----------------------------------------------------------------------------- - function bit_reverse(arg : unsigned) return unsigned is - variable res : unsigned(arg'range); - begin - for i in arg'range loop - res(i) := arg(arg'high - i); - end loop; - return(res); - end; - - ----------------------------------------------------------------------------- - -- INVERT Function - ----------------------------------------------------------------------------- - function invert(arg : unsigned) - return unsigned -- (word'high downto 0) - is - variable res : unsigned(arg'high downto 0); - begin - - for i in arg'range loop - res(i) := not arg(i); - end loop; - return (res); - end invert; - - ----------------------------------------------------------------------------- - -- HALVE_CEIL Function - ----------------------------------------------------------------------------- - function halve_ceil(arg : natural) return natural is - variable res : natural; - begin - if is_odd(arg) then - res := (arg+1)/2; - else - res := arg/2; - end if; - return (res); - end halve_ceil; - -------------------------------------------------------------------------------- --- DIV_CEIL function -------------------------------------------------------------------------------- - function div_ceil(a : natural; b : natural) return natural is - variable res : natural := a/b; - begin - if res*b /= a then - res := res +1; - end if; - return res; - end div_ceil; - -end package body auk_dspip_math_pkg; diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd deleted file mode 100644 index 54149f3..0000000 --- a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd +++ /dev/null @@ -1,309 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - -------------------------------------------------------------------------- -------------------------------------------------------------------------- --- --- Revision Control Information --- --- $RCSfile: auk_dspip_fast_accumulator.vhd,v $ --- $Source: /cvs/uksw/dsp_cores/lib/fu/fast_accum/rtl/auk_dspip_fast_accumulator.vhd,v $ --- --- $Revision: #1 $ --- $Date: 2018/07/18 $ --- Check in by : $Author: psgswbuild $ --- Author : Alex Diaz-Manero --- --- Project : FIR --- --- Description : --- --- Fast pipelined Accumulator for fast filters --- --- --- $Log: auk_dspip_fast_accumulator.vhd,v $ --- Revision 1.2 2007/10/09 19:08:16 admanero --- slight mod to avoid propagation of X through Sum at MSB bits --- --- Revision 1.1 2007/09/24 16:59:34 admanero --- first revision of fast (pipelined) accumulator. --- --- --- ALTERA Confidential and Proprietary --- Copyright 2007 (c) Altera Corporation --- All rights reserved --- -------------------------------------------------------------------------- -------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.auk_dspip_math_pkg.all; ---use auk_dspip_lib.auk_dspip_lib_pkg.all; - - -entity auk_dspip_pipelined_adder is - generic ( - -- This adder assumes that both operands datain1 and datain2 are of the same data width - -- if that is not the case and the shorter word is (sign) expanded to the size of the bigger then - -- a penalty is incurred in the pipelined implementation. - -- But for the time being I only need the same size :-) So don't make your life too difficult - INWIDTH_g : natural := 42; - -- width of lab in selected device ( 10 or 16 in Cyclone, - -- Cylone II, Stratix and Stratix II. - -- Alex : should I use 19 bits for Stratix III? - -- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency. - -- Shall I have family generic to set labwidth? - LABWIDTH_g : natural := 38); - port ( - datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); - datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); - clk : in std_logic; - enable : in std_logic; - reset : in std_logic; - dataout : out std_logic_vector(INWIDTH_g downto 0)); -end auk_dspip_pipelined_adder; - - -architecture rtl of auk_dspip_pipelined_adder is - - type NATURAL_ARRAY is array(NATURAL RANGE <>) of NATURAL; - - -- IN_OR_OUT is 0 for IN and 1 for ADD (OUT) - function calc_number_of_stages(FULL_WIDTH, LABWIDTH, IN_OR_OUT : natural) return natural is - variable tmp : natural; - variable result : natural; - begin - tmp := FULL_WIDTH; - result := 0; - while tmp > LABWIDTH+IN_OR_OUT loop - tmp := tmp - LABWIDTH; - result := result + 1; - end loop; - - return result; - end calc_number_of_stages; - - - function calc_width_of_stages(FULL_WIDTH, LABWIDTH, IN_OR_OUT : natural) return natural_array is - Constant STAGES_c : natural := calc_number_of_stages(FULL_WIDTH, LABWIDTH, IN_OR_OUT); - variable tmp : natural; - variable result : natural_array(stages_c downto 0); - begin - tmp := FULL_WIDTH; - for I in 0 to STAGES_c loop - if I=STAGES_c then - result(I) := tmp; - else - result(I) := LABWIDTH; - tmp := tmp - LABWIDTH; - end if; - end loop; - return result; - - end calc_width_of_stages; - --- This stages_c will be either 0, 1 or 2. Rarely it will be 3. --- 39 "divided" by 19 still should yield just 1 (2 stages). but for 40 it should 2 (3 stages) --- So, it should be a function not a just a division. --- For an adder, for simplicity, shouldn't I have the same stages for input and output? Well, leave it like this anyways - Constant STAGES_ADD_c : natural := calc_number_of_stages(INWIDTH_g+1, LABWIDTH_g, 1); --ACCUM_OUT_WIDTH_g / LABWIDTH_g; - Constant WIDTH_STAGES_ADD_c : natural_array(STAGES_ADD_c downto 0) := calc_width_of_stages(INWIDTH_g+1, LABWIDTH_g, 1); - Constant STAGES_IN_c : natural := calc_number_of_stages(INWIDTH_g, LABWIDTH_g, 0); - Constant WIDTH_STAGES_IN_c : natural_array(STAGES_IN_c downto 0) := calc_width_of_stages(INWIDTH_g, LABWIDTH_g, 0); - - type TRIANGLE_DELAY_t is array (natural range<>, natural range<>) of std_logic_vector(LABWIDTH_g-1 downto 0); - type TRIANGLE_DELAY_P1_t is array (natural range<>, natural range<>) of std_logic_vector(LABWIDTH_g downto 0); - type COLUMN_VECTOR_t is array (natural range<>) of std_logic_vector(LABWIDTH_g downto 0); - - signal input1_side_data_scaled_delay_q : TRIANGLE_DELAY_t(STAGES_IN_c downto 0, STAGES_IN_c downto 0); - signal input1_side_data_scaled_delay_d : TRIANGLE_DELAY_t(STAGES_IN_c downto 0, STAGES_IN_c downto 0); - signal input2_side_data_scaled_delay_q : TRIANGLE_DELAY_t(STAGES_IN_c downto 0, STAGES_IN_c downto 0); - signal input2_side_data_scaled_delay_d : TRIANGLE_DELAY_t(STAGES_IN_c downto 0, STAGES_IN_c downto 0); - signal output_side_data_scaled_delay_q : TRIANGLE_DELAY_P1_t(STAGES_ADD_c downto 0, STAGES_ADD_c downto 0); - signal output_side_data_scaled_delay_d : TRIANGLE_DELAY_P1_t(STAGES_ADD_c downto 0, STAGES_ADD_c downto 0); - signal datai1_int : COLUMN_VECTOR_t(STAGES_ADD_c downto 0); - signal datai2_int : COLUMN_VECTOR_t(STAGES_ADD_c downto 0); - signal datao_int : COLUMN_VECTOR_t(STAGES_ADD_c downto 0); - signal cout_cin_d : std_logic_vector(STAGES_ADD_c+1 downto 0); - signal cout_cin_q : std_logic_vector(STAGES_ADD_c+1 downto 0); - signal enb : std_logic; - - -begin - - enb <= enable; - - ifg4: if STAGES_ADD_c>0 generate - reg2 : process(clk, reset) is - begin - if reset = '1' then - cout_cin_q(STAGES_ADD_c+1 downto 1) <= (others => '0'); - elsif rising_edge(clk) then - if enb = '1' then - cout_cin_q(STAGES_ADD_c+1 downto 1) <= cout_cin_d(STAGES_ADD_c+1 downto 1); - end if; - end if; - end process reg2; - end generate ifg4; - - cout_cin_q(0) <= '0'; - - fg1: for J in 0 to STAGES_IN_c generate - - fg1c: for I in 0 to STAGES_IN_c generate - ifg6b: if I <= 1 generate - input1_side_data_scaled_delay_d(I, J)(WIDTH_STAGES_IN_c(J)-1 downto 0) <= datain1(WIDTH_STAGES_IN_c(J)-1 + J*LABWIDTH_g downto J*LABWIDTH_g); - input2_side_data_scaled_delay_d(I, J)(WIDTH_STAGES_IN_c(J)-1 downto 0) <= datain2(WIDTH_STAGES_IN_c(J)-1 + J*LABWIDTH_g downto J*LABWIDTH_g); - end generate ifg6b; - ifg7b: if I > 1 generate - input1_side_data_scaled_delay_d(I, J)(LABWIDTH_g-1 downto 0) <= input1_side_data_scaled_delay_q(I-1, J)(LABWIDTH_g-1 downto 0); - input2_side_data_scaled_delay_d(I, J)(LABWIDTH_g-1 downto 0) <= input2_side_data_scaled_delay_q(I-1, J)(LABWIDTH_g-1 downto 0); - end generate ifg7b; - end generate fg1c; - - end generate fg1; - - reg : process(clk, reset) is - begin - if reset = '1' then - loop1: for I in 1 to STAGES_IN_c loop - loop2: for J in I to STAGES_IN_c loop - input1_side_data_scaled_delay_q(I, J) <= (others => '0'); - input2_side_data_scaled_delay_q(I, J) <= (others => '0'); - end loop loop2; - end loop loop1; - elsif rising_edge(clk) then - if enb = '1' then - loop3: for I in 1 to STAGES_IN_c loop - loop4: for J in I to STAGES_IN_c loop - input1_side_data_scaled_delay_q(I, J) <= input1_side_data_scaled_delay_d(I, J); - input2_side_data_scaled_delay_q(I, J) <= input2_side_data_scaled_delay_d(I, J); - end loop loop4; - end loop loop3; - end if; - end if; - end process reg; - - adding: process(cout_cin_q, datai1_int, datai2_int) - variable tmp_debug_s : signed(LABWIDTH_g downto 0); - variable tmp_debug_u : unsigned(LABWIDTH_g downto 0); - begin - --Only the upper most chunk sum is signed, the other chunks ought to be unsigned - for I in 0 to STAGES_ADD_c loop - if I=STAGES_ADD_c then - if cout_cin_q(I)='1' then - --datao_int(I) <= signed(datai_int(I)) + signed(datas_int(I)) + natural(1); - tmp_debug_s(WIDTH_STAGES_ADD_c(I)-1 downto 0) := signed(datai1_int(I)(WIDTH_STAGES_ADD_c(I)-1 downto 0)) + signed(datai2_int(I)(WIDTH_STAGES_ADD_c(I)-1 downto 0)) + natural(1); - else - --datao_int(I) <= signed(datai_int(I)) + signed(datas_int(I)) + natural(0); - tmp_debug_s(WIDTH_STAGES_ADD_c(I)-1 downto 0) := signed(datai1_int(I)(WIDTH_STAGES_ADD_c(I)-1 downto 0)) + signed(datai2_int(I)(WIDTH_STAGES_ADD_c(I)-1 downto 0)) + natural(0); - end if; - - datao_int(I) <= std_logic_vector(tmp_debug_s); - cout_cin_d(I+1) <= tmp_debug_s(LABWIDTH_g); - else - if cout_cin_q(I)='1' then - --datao_int(I) <= unsigned(datai_int(I)) + unsigned(datas_int(I)) + natural(1); - tmp_debug_u := unsigned(datai1_int(I)) + unsigned(datai2_int(I)) + natural(1); - else - --datao_int(I) <= unsigned(datai_int(I)) + unsigned(datas_int(I)) + natural(0); - tmp_debug_u := unsigned(datai1_int(I)) + unsigned(datai2_int(I)) + natural(0); - end if; - datao_int(I) <= std_logic_vector(tmp_debug_u); - cout_cin_d(I+1) <= tmp_debug_u(LABWIDTH_g); - end if; - end loop; - end process adding; - - - --Always STAGES_ADD_c >= STAGES_IN_c - --when it is greater it needs special handling - fg1b: for I in 0 to STAGES_ADD_c generate - - --I need to split STAGES_ADD_c from STAGES_IN_c - fg2: for J in 0 to I generate - ifg1a: if J=0 and I=0 generate - --In reality the chunks below the MSB are unsigned. Only the upper most (MSB) chunk is signed - -- - datai1_int(I)(WIDTH_STAGES_IN_c(I) downto 0) <= std_logic_vector('0' & input1_side_data_scaled_delay_d(0, 0)(WIDTH_STAGES_IN_c(I)-1 downto 0)); - datai2_int(I)(WIDTH_STAGES_IN_c(I) downto 0) <= std_logic_vector('0' & input2_side_data_scaled_delay_d(0, 0)(WIDTH_STAGES_IN_c(I)-1 downto 0)); - end generate ifg1a; - ifg1: if J=I and I0 and J>0 generate - --In reality the chunks below the MSB are unsigned. Only the upper most (MSB) chunk is signed - datai1_int(I)(WIDTH_STAGES_IN_c(I) downto 0) <= std_logic_vector('0' & input1_side_data_scaled_delay_q(I, J)(WIDTH_STAGES_IN_c(I)-1 downto 0)); - datai2_int(I)(WIDTH_STAGES_IN_c(I) downto 0) <= std_logic_vector('0' & input2_side_data_scaled_delay_q(I, J)(WIDTH_STAGES_IN_c(I)-1 downto 0)); - end generate ifg1; - -------- - --Could it be possible to have STAGES_ADD_c > STAGES_IN_c ? yes, it could => sign extension stages needed herefor datai_int - ifg2a: if J=I and I>=STAGES_IN_c and I STAGES_IN_c) - datai1_int(I)(LABWIDTH_g downto 0) <= std_logic_vector(sign_extend(signed(input1_side_data_scaled_delay_q(STAGES_IN_c, J)(WIDTH_STAGES_IN_c(STAGES_IN_c)-1 downto 0)), LABWIDTH_g+1)); - datai2_int(I)(LABWIDTH_g downto 0) <= std_logic_vector(sign_extend(signed(input2_side_data_scaled_delay_q(STAGES_IN_c, J)(WIDTH_STAGES_IN_c(STAGES_IN_c)-1 downto 0)), LABWIDTH_g+1)); - --this last chunk doesn't need sign extension, it would need it if we wanted carry out (i.e. for overflow) - end generate ifg2a; - -------- - -- Only the MSB chunk needs to be signed. Question: Is there a need for a pipelined accumulator with unsigned data? - ifg2: if J=I and I=STAGES_ADD_c generate - datai1_int(I)(LABWIDTH_g downto 0) <= std_logic_vector(sign_extend(signed(input1_side_data_scaled_delay_q(STAGES_IN_c, J)(WIDTH_STAGES_IN_c(STAGES_IN_c)-1 downto 0)), LABWIDTH_g+1)); - datai2_int(I)(LABWIDTH_g downto 0) <= std_logic_vector(sign_extend(signed(input2_side_data_scaled_delay_q(STAGES_IN_c, J)(WIDTH_STAGES_IN_c(STAGES_IN_c)-1 downto 0)), LABWIDTH_g+1)); - --this last chunk doesn't need sign extension, it would need it if we wanted carry out (i.e. for overflow) - end generate ifg2; - end generate fg2; - - - -- output connection, MSB chunk from _d the remainder from _q - ifg3: if I=STAGES_ADD_c generate - dataout(WIDTH_STAGES_ADD_c(I)-1+LABWIDTH_g*I downto LABWIDTH_g*I) <= output_side_data_scaled_delay_d(STAGES_ADD_c-I, I)(WIDTH_STAGES_ADD_c(I)-1 downto 0); - end generate ifg3; - ifg4: if I 1 generate - output_side_data_scaled_delay_d(I, J)(LABWIDTH_g-1 downto 0) <= output_side_data_scaled_delay_q(I-1, J)(LABWIDTH_g-1 downto 0); - end generate ifg7; - end generate fg3b; - - end generate fg3a; - -- - reg_o : process(clk, reset) is - begin - if reset = '1' then - loop1: for I in 1 to STAGES_ADD_c loop - loop2: for J in 0 to STAGES_ADD_c-I loop - output_side_data_scaled_delay_q(I, J) <= (others => '0'); - end loop loop2; - end loop loop1; - elsif rising_edge(clk) then - if enb = '1' then - loop3: for I in 1 to STAGES_ADD_c loop - loop4: for J in 0 to STAGES_ADD_c-I loop - output_side_data_scaled_delay_q(I, J) <= output_side_data_scaled_delay_d(I, J); - end loop loop4; - end loop loop3; - end if; - end if; - end process reg_o; - -end rtl; - diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd deleted file mode 100644 index 70665a2..0000000 --- a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd +++ /dev/null @@ -1,438 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - -------------------------------------------------------------------------- -------------------------------------------------------------------------- --- --- Revision Control Information --- --- $RCSfile: auk_dspip_roundsat.vhd,v $ --- $Source: /cvs/uksw/dsp_cores/lib/fu/roundsat/rtl/auk_dspip_roundsat.vhd,v $ --- --- $Revision: #1 $ --- $Date: 2018/07/18 $ --- Check in by : $Author: psgswbuild $ --- Author : Volker Mauer --- --- Project : common FU library --- --- Description : --- --- This functional unit can be used to implement various forms of --- rounding, saturation and truncation. --- --- ALTERA Confidential and Proprietary --- Copyright 2006 (c) Altera Corporation --- All rights reserved --- -------------------------------------------------------------------------- -------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -entity auk_dspip_roundsat is - generic ( - IN_WIDTH_g : natural := 8; -- data width - OUT_WIDTH_g : natural := 8; -- data width - ROUNDING_TYPE_g : string := "TRUNCATE_LOW"; - LATENCY : natural := 1 - ); - - port ( - clk : in std_logic; - reset : in std_logic; - enable : in std_logic; -- global clock enable - datain : in std_logic_vector(IN_WIDTH_g-1 downto 0); - dataout : out std_logic_vector(OUT_WIDTH_g-1 downto 0)); -end entity auk_dspip_roundsat; - -architecture beh of auk_dspip_roundsat is - -begin -- architecture beh - - ----------------------------------------------------------------------------- - -- truncate low - ----------------------------------------------------------------------------- - trunc_low: if ROUNDING_TYPE_g = "TRUNCATE_LOW" generate - begin -- generate trunc_low - trunc_low_p: process (clk) is - begin -- process trunc_low_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - dataout <= datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g); - end if; - end if; - end if; - end process trunc_low_p; - end generate trunc_low; - - ----------------------------------------------------------------------------- - -- truncate high - ----------------------------------------------------------------------------- - trunc_high: if ROUNDING_TYPE_g = "TRUNCATE_HIGH" generate - begin -- generate trunc_high - trunc_high_p: process (clk) is - begin -- process trunc_high_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - dataout <= datain(OUT_WIDTH_g-1 downto 0); - end if; - end if; - end if; - end process trunc_high_p; - end generate trunc_high; - - ----------------------------------------------------------------------------- - -- saturation - ----------------------------------------------------------------------------- - sat : if ROUNDING_TYPE_g = "SATURATE" generate - begin -- generate sat - sat_p : process (clk) is - begin -- process sat_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- synchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - if signed(datain) > 2**(OUT_WIDTH_g-1)-1 then - dataout <= std_logic_vector(to_signed(2**(OUT_WIDTH_g-1)-1, OUT_WIDTH_g)); - elsif signed(datain) < -2**(OUT_WIDTH_g-1) then - dataout <= std_logic_vector(to_signed(-2**(OUT_WIDTH_g-1), OUT_WIDTH_g)); - else - dataout <= datain(OUT_WIDTH_g-1 downto 0); - end if; - end if; - end if; - end if; - end process sat_p; - end generate sat; - - ----------------------------------------------------------------------------- - -- symmetrical saturation - ----------------------------------------------------------------------------- - satsym : if ROUNDING_TYPE_g = "SATURATE_SYM" generate - begin -- generate satsym - satsym_p : process (clk) is - begin -- process satsym_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - if signed(datain) > 2**(OUT_WIDTH_g-1)-1 then - dataout <= std_logic_vector(to_signed(2**(OUT_WIDTH_g-1)-1, OUT_WIDTH_g)); - elsif signed(datain) < -2**(OUT_WIDTH_g-1)+1 then - dataout <= std_logic_vector(to_signed(-2**(OUT_WIDTH_g-1)+1, OUT_WIDTH_g)); - else - dataout <= datain(OUT_WIDTH_g-1 downto 0); - end if; - end if; - end if; - end if; - end process satsym_p; - end generate satsym; - - ----------------------------------------------------------------------------- - -- simple rounding (always rounds up) - ----------------------------------------------------------------------------- - round : if ROUNDING_TYPE_g = "ROUND_UP" generate - - signal RB : std_logic; -- rounding bit (MSB of discarded bit) - - begin -- generate round - ----------------------------------------------------------------------------- - -- get relevant bits - ----------------------------------------------------------------------------- - RB <= datain(IN_WIDTH_g-OUT_WIDTH_g-1); - - round_p : process (clk) is - begin -- process round_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - if RB = '1' then - dataout <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g))+1); - else - dataout <= datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g); - end if; - end if; - end if; - end if; - end process round_p; - end generate round; - - ----------------------------------------------------------------------------- - -- round towards 0 - ----------------------------------------------------------------------------- - round0 : if ROUNDING_TYPE_g = "ROUND0" generate - signal SB : std_logic; -- sign bit - begin -- generate round0 - - SB <= datain(IN_WIDTH_g-1); - - round0_p : process (clk) is - variable OR_accu : std_logic := '0'; - begin -- process round0_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - OR_accu := '0'; - for i in 0 to IN_WIDTH_g-OUT_WIDTH_g-1 loop - OR_accu := OR_accu or datain(i); - end loop; -- i - if SB = '1' and OR_accu = '1' then - dataout <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g))+1); - else - dataout <= datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g); - end if; - end if; - end if; - end if; - end process round0_p; - end generate round0; - - ----------------------------------------------------------------------------- - -- round away from 0 - ----------------------------------------------------------------------------- - round_up_sym : if ROUNDING_TYPE_g = "ROUND_UP_SYM" generate - signal SB : std_logic; -- sign bit - signal SB_delayed : std_logic; -- sign bit, delayed - signal RB : std_logic; -- rounding bit (MSB of discarded bit) - signal dataout_temp : std_logic_vector(OUT_WIDTH_g-1 downto 0); - -- internal, readable version of dataoout - - begin -- generate round_up_sym - - SB <= datain(IN_WIDTH_g-1); - RB <= datain(IN_WIDTH_g-OUT_WIDTH_g-1); - - round_up_sym_p : process (clk) is - variable OR_accu : std_logic := '0'; - begin -- process round_up_sym_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout_temp <= (others => '0'); - SB_delayed <= '0'; - else - if enable = '1' then - SB_delayed <= SB; - OR_accu := '0'; - for i in 0 to IN_WIDTH_g-OUT_WIDTH_g-1 loop - OR_accu := OR_accu or datain(i); - end loop; -- i - if (SB = '0' and RB = '1') or (SB = '1' and RB='1' and OR_accu='1') then - dataout_temp <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g))+1); - else - dataout_temp <= datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g); - end if; - end if; - end if; - end if; - end process round_up_sym_p; - - dataout <= dataout_temp; - - assert not(SB_delayed = '0' and dataout_temp(OUT_WIDTH_g-1 downto OUT_WIDTH_g-2)="10") report "Overflow during rounding, dataout invalid. This condition occurs when ROUND_UP_SYM is selected for rounding, and a large integer appears at the input. Please consider changing rounding mode to CONVERGENT rounding, where overflows cannot happen, or apply SATURATION first." severity warning; - - end generate round_up_sym; - - ----------------------------------------------------------------------------- - -- convergent rounding - ----------------------------------------------------------------------------- - conv_round_1 : if ROUNDING_TYPE_g = "CONV_ROUND" and LATENCY = 1 generate - signal LSB : std_logic; -- least significant retained bit - signal RB : std_logic; -- rounding bit (MSB of discarded bit) - - begin -- generate conv_round - - ----------------------------------------------------------------------------- - -- get relevant bits - ----------------------------------------------------------------------------- - RB <= datain(IN_WIDTH_g-OUT_WIDTH_g-1); - LSB <= datain(IN_WIDTH_g-OUT_WIDTH_g); - - conv_round_p1 : process (clk) is - variable OR_accu : std_logic := '0'; - begin -- process conv_round_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - OR_accu := '0'; - for i in 0 to IN_WIDTH_g-OUT_WIDTH_g-2 loop - OR_accu := OR_accu or datain(i); - end loop; -- i - if RB = '1' and (LSB = '1' or OR_accu = '1') then - dataout <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g))+1); - else - dataout <= datain(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g); - end if; - end if; - end if; - end if; - end process conv_round_p1; - end generate conv_round_1; - - - conv_round_2 : if ROUNDING_TYPE_g = "CONV_ROUND" and LATENCY = 2 generate - signal LSB : std_logic; -- least significant retained bit - signal RB : std_logic; -- rounding bit (MSB of discarded bit) - signal datareg : std_logic_vector(IN_WIDTH_g-1 downto 0); - signal OR_accu : std_logic; - - begin -- generate conv_round - - ----------------------------------------------------------------------------- - -- get relevant bits - ----------------------------------------------------------------------------- - - conv_round_p : process(clk) is - variable OR_Temp : std_logic := '0'; - begin - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - RB <= '0'; - LSB <= '0'; - OR_accu <= '0'; - datareg <= (others =>'0'); - else - if enable = '1' then - OR_Temp := '0'; - for i in 0 to IN_WIDTH_g-OUT_WIDTH_g-2 loop - OR_Temp := OR_Temp or datain(i); - end loop; -- - RB <= datain(IN_WIDTH_g-OUT_WIDTH_g-1); - LSB <= datain(IN_WIDTH_g-OUT_WIDTH_g); - OR_accu <= OR_Temp; - datareg <= datain; - end if; - end if; - end if; - end process conv_round_p; - - conv_round_p2 : process (clk) is - begin -- process conv_round_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - if RB = '1' and (LSB = '1' or OR_accu = '1') then - dataout <= std_logic_vector(signed(datareg(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g))+1); - else - dataout <= datareg(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g); - end if; - end if; - end if; - end if; - end process conv_round_p2; - end generate conv_round_2; - - -conv_round_3 : if ROUNDING_TYPE_g = "CONV_ROUND" and LATENCY = 3 generate - signal LSB,LSB_R : std_logic; -- least significant retained bit - signal RB,RB_R : std_logic; -- rounding bit (MSB of discarded bit) - signal datareg, datareg_2 : std_logic_vector(IN_WIDTH_g-1 downto 0); - signal OR_accu_1, OR_accu_2 : std_logic; - signal OR_accu : std_logic; - - begin -- generate conv_round - - ----------------------------------------------------------------------------- - -- get relevant bits - ----------------------------------------------------------------------------- - - conv_round_p : process(clk) is - variable OR_Temp_2,OR_Temp_1 : std_logic := '0'; - begin - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - RB <= '0'; - LSB <= '0'; - RB_R <= '0'; - LSB_R <= '0'; - OR_accu_1 <= '0'; - OR_accu_2 <= '0'; - datareg <= (others =>'0'); - else - if enable = '1' then - OR_Temp_1 := '0'; - OR_Temp_2 := '0'; - for i in 0 to (IN_WIDTH_g-OUT_WIDTH_g-2)/2 loop - OR_Temp_1 := OR_Temp_1 or datain(i); - end loop; -- - for i in ((IN_WIDTH_g-OUT_WIDTH_g-2)/2)+1 to (IN_WIDTH_g-OUT_WIDTH_g-2) loop - OR_Temp_2 := OR_Temp_2 or datain(i); - end loop; -- RB <= datain(IN_WIDTH_g-OUT_WIDTH_g-1); - LSB <= datain(IN_WIDTH_g-OUT_WIDTH_g); - LSB_R <= LSB; - RB <= datain(IN_WIDTH_g-OUT_WIDTH_g-1); - RB_R <= RB; - OR_accu_1 <= OR_Temp_1; - OR_accu_2 <= OR_Temp_2; - OR_accu <= OR_accu_1 or OR_accu_2; - datareg <= datain; - datareg_2 <= datareg; - end if; - end if; - end if; - end process conv_round_p; - - conv_round_p2 : process (clk) is - begin -- process conv_round_p - if rising_edge(clk) then -- rising clock edge - if reset = '1' then -- asynchronous reset (active high) - dataout <= (others => '0'); - else - if enable = '1' then - if RB_R = '1' and (LSB_R = '1' or OR_accu = '1') then - dataout <= std_logic_vector(signed(datareg_2(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g))+1); - else - dataout <= datareg_2(IN_WIDTH_g-1 downto IN_WIDTH_g-OUT_WIDTH_g); - end if; - end if; - end if; - end if; - end process conv_round_p2; - end generate conv_round_3; - ----------------------------------------------------------------------------- - -- error checking: - -- Have we got a valid rounding mode? - -- Is the input greater than the output? - ----------------------------------------------------------------------------- - assert (ROUNDING_TYPE_g = "SATURATE" or - ROUNDING_TYPE_g = "SATURATE_SYM" or - ROUNDING_TYPE_g = "ROUND_UP" or - ROUNDING_TYPE_g = "ROUND0" or - ROUNDING_TYPE_g = "ROUND_UP_SYM" or - ROUNDING_TYPE_g = "CONV_ROUND" or - ROUNDING_TYPE_g = "TRUNCATE_LOW" or - ROUNDING_TYPE_g = "TRUNCATE_HIGH" - ) report "Please check your rounding type and its spelling. Currently, we only support SATURATE, SATURATE_SYM, ROUND_UP, ROUND0, CONV_ROUND, TRUNCATE_LOW, TRUNCATE_HIGH" severity error; - assert (((LATENCY = 1) or (ROUNDING_TYPE_g = "CONV_ROUND" and (LATENCY = 3 or LATENCY = 2)))) report "Please check your Latency. Currently we only support latency for all modes and 2 latency for convergent round" severity error; - - -end architecture beh; diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd deleted file mode 100644 index c792d98..0000000 --- a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd +++ /dev/null @@ -1,121 +0,0 @@ --- (C) 2001-2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions and other --- software and tools, and its AMPP partner logic functions, and any output --- files from any of the foregoing (including device programming or simulation --- files), and any associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License Subscription --- Agreement, Intel FPGA IP License Agreement, or other applicable --- license agreement, including, without limitation, that your use is for the --- sole purpose of programming logic devices manufactured by Intel and sold by --- Intel or its authorized distributors. Please refer to the applicable --- agreement for further details. - - -------------------------------------------------------------------------- -------------------------------------------------------------------------- --- --- Revision Control Information --- --- $RCSfile: auk_dspip_text_pkg.vhd,v $ --- $Source: /cvs/uksw/dsp_cores/lib/packages/auk_dspip_text_pkg.vhd,v $ --- --- $Revision: #1 $ --- $Date: 2018/07/18 $ --- Check in by : $Author: psgswbuild $ --- Author : DSP_IP --- --- Project : --- --- Description : --- --- Common functions for DSP_IP cores. --- --- --- $Log: auk_dspip_text_pkg.vhd,v $ --- Revision 1.2 2007/05/04 15:33:11 sdemirso --- merge from 7.1 --- --- Revision 1.1 2007/02/01 17:29:45 kmarks --- Initial commit --- --- Revision 1.5 2006/08/17 10:13:02 sdemirso --- log2_ceil_one function added --- --- Revision 1.4 2006/07/28 18:52:50 sdemirso --- no compilation errors with the new directory structure --- --- Revision 1.3 2006/07/28 10:27:30 sdemirso --- Header updated --- --- ALTERA Confidential and Proprietary --- Copyright 2006 (c) Altera Corporation --- All rights reserved --- -------------------------------------------------------------------------- -------------------------------------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; -PACKAGE auk_dspip_text_pkg IS - - - ----------------------------------------------------------------------------- - -- NOTE that these log functions are not intended to synthesize directly - -- into hardware, rather they are used to generate constants for - -- synthesized hardware. - ----------------------------------------------------------------------------- - type array_natural_t is array (natural range <>) of integer; - - function parse_string_array (str : string; size : natural) return array_natural_t; - - function str_to_int (str : string; base : string) return integer; - -END PACKAGE auk_dspip_text_pkg; - -package body auk_dspip_text_pkg is - --------------------------------------------------------------------------- - -- str_to_int Function. Only parses positive decimal values - --------------------------------------------------------------------------- - function str_to_int(str : string; base : string) return integer is - variable res : integer; - variable base_cnt : integer; - begin - res := 0; - base_cnt:=1; - for i in str'length downto 1 loop - if str(i) /= ' ' then - res := res + (character'pos(str(i)) - character'pos('0'))*base_cnt; - base_cnt:=base_cnt*10; - end if; - end loop; -- i - return res; - end str_to_int; - - --------------------------------------------------------------------------- - -- parse_string_array Function. - --------------------------------------------------------------------------- - function parse_string_array(str : string; size : natural) return array_natural_t is - variable this_str : string(1 to 32); - variable cnt_char : natural; -- how many characters have we seen - variable cnt_str : natural:=0; - variable res : array_natural_t(0 to size-1); - begin - this_str := (others => ' '); - cnt_char := 1; - for i in str'left to str'right loop - if str(i) = ',' then - res(cnt_str) := str_to_int(this_str, "DEC"); - cnt_char := 1; - cnt_str := cnt_str + 1; - this_str := (others => ' '); - else - this_str(cnt_char) := str(i); - cnt_char := cnt_char+1; - end if; - end loop; -- i - res(cnt_str) := str_to_int(this_str, "DEC"); - return res; - end parse_string_array; - - end package body auk_dspip_text_pkg; diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_upsample.vhd b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_upsample.vhd deleted file mode 100644 index fdfa848..0000000 Binary files a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_upsample.vhd and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_variable_downsample.sv b/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_variable_downsample.sv deleted file mode 100644 index 76d2504..0000000 Binary files a/FPGA_61.440/db/ip/tx_cic/submodules/auk_dspip_variable_downsample.sv and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/counter_module.sv b/FPGA_61.440/db/ip/tx_cic/submodules/counter_module.sv deleted file mode 100644 index 4385698..0000000 Binary files a/FPGA_61.440/db/ip/tx_cic/submodules/counter_module.sv and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/hyper_pipeline_interface.v b/FPGA_61.440/db/ip/tx_cic/submodules/hyper_pipeline_interface.v deleted file mode 100644 index a9bd59a..0000000 Binary files a/FPGA_61.440/db/ip/tx_cic/submodules/hyper_pipeline_interface.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv b/FPGA_61.440/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv deleted file mode 100644 index 0e99d24..0000000 --- a/FPGA_61.440/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv +++ /dev/null @@ -1,217 +0,0 @@ -// (C) 2001-2018 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - - -module tx_cic_cic_ii_0 ( - in_data, - out_ready, - in_valid, - clk, - clken, - reset_n, - in_ready, - in_error, - out_error, - out_data, - out_valid - ); - - parameter DEVICE_FAMILY = "Cyclone IV E"; - - - - parameter FILTER_TYPE = "interpolator"; - parameter STAGES = 6; - parameter D_DELAY = 1; - parameter VRC_EN = 0; - parameter RCF_MAX = 3200; - parameter RCF_MIN = 3200; - parameter INTERFACES = 1; - parameter CH_PER_INT = 1; - parameter INT_USE_MEM = "false"; - parameter INT_MEM = "auto"; - parameter DIF_USE_MEM = "false"; - parameter DIF_MEM = "auto"; - parameter IN_WIDTH = 16; - parameter OUT_WIDTH = 16; - parameter ROUND_TYPE = "TRUNCATE"; - parameter PIPELINING = 0; - - - parameter C_STAGE_0_WIDTH = 75; - parameter C_STAGE_1_WIDTH = 75; - parameter C_STAGE_2_WIDTH = 75; - parameter C_STAGE_3_WIDTH = 75; - parameter C_STAGE_4_WIDTH = 75; - parameter C_STAGE_5_WIDTH = 75; - parameter C_STAGE_6_WIDTH = 75; - parameter C_STAGE_7_WIDTH = 75; - parameter C_STAGE_8_WIDTH = 75; - parameter C_STAGE_9_WIDTH = 75; - parameter C_STAGE_10_WIDTH = 75; - parameter C_STAGE_11_WIDTH = 75; - parameter MAX_C_STAGE_WIDTH = 75; - - parameter I_STAGE_0_WIDTH = 75; - parameter I_STAGE_1_WIDTH = 75; - parameter I_STAGE_2_WIDTH = 75; - parameter I_STAGE_3_WIDTH = 75; - parameter I_STAGE_4_WIDTH = 75; - parameter I_STAGE_5_WIDTH = 75; - parameter I_STAGE_6_WIDTH = 75; - parameter I_STAGE_7_WIDTH = 75; - parameter I_STAGE_8_WIDTH = 75; - parameter I_STAGE_9_WIDTH = 75; - parameter I_STAGE_10_WIDTH = 75; - parameter I_STAGE_11_WIDTH = 75; - parameter MAX_I_STAGE_WIDTH = 75; - - localparam TOTAL_CHANNELS = CH_PER_INT*INTERFACES; - - localparam INTERFACES_IN = (FILTER_TYPE=="decimator" & INTERFACES > 1) ? INTERFACES : 1 ; - localparam INTERFACES_OUT = (FILTER_TYPE=="interpolator" & INTERFACES > 1) ? INTERFACES : 1 ; - localparam CHANNEL_SIZE_OUT = (FILTER_TYPE=="interpolator" & INTERFACES > 1) ? CH_PER_INT : TOTAL_CHANNELS ; - localparam CHANNEL_SIZE_IN = (FILTER_TYPE=="decimator" & INTERFACES > 1) ? CH_PER_INT : TOTAL_CHANNELS ; - localparam CHANNEL_OUT_WIDTH = (CHANNEL_SIZE_OUT > 1) ? $clog2(CHANNEL_SIZE_OUT) : 1; - localparam NUMBER_OF_CHANNELS = INTERFACES*CH_PER_INT; - localparam RATE_FACTOR_WIDTH = $clog2(RCF_MAX+1); - localparam CHANNEL_WIDTH = $clog2(TOTAL_CHANNELS); - localparam COUNTER_FS_MAX = RCF_MAX*NUMBER_OF_CHANNELS; - - //latency calculations - //localparam COMB_STAGE_LATENCY = 1; - //localparam COMB_SECTION_LATENCY = COMB_STAGE_LATENCY*STAGES; - //localparam INT_SECTION_LATENCY = (~INT_USE_MEM & PIPELINING > 1) ? PIPELINING*STAGES: STAGES*NUMBER_OF_CHANNELS; - //localparam MUX_LATENCY = NUMBER_OF_CHANNELS*(INTERFACES-1)+1; - //localparam DEC_SISO_LATENCY = COMB_SECTION_LATENCY + INT_SECTION_LATENCY; - //localparam INT_SISO_LATENCY = COMB_SECTION_LATENCY + INT_SECTION_LATENCY; - //localparam DEC_MISO_LATENCY = COMB_SECTION_LATENCY+INT_SECTION_LATENCY+2; - //localparam INT_SIMO_LATENCY = COMB_SECTION_LATENCY+INT_SECTION_LATENCY+MUX_LATENCY ; - //localparam S_LATENCY = (FILTER_TYPE == "decimator") ? DEC_SISO_LATENCY : INT_SISO_LATENCY; - //localparam M_LATENCY = (FILTER_TYPE == "decimator") ? DEC_MISO_LATENCY : INT_SIMO_LATENCY; - //localparam TOTAL_LATENCY = (INTERFACES > 1) ? M_LATENCY : S_LATENCY; - //localparam CLOCKS_PER_SAMPLE = RCF_MIN/INTERFACES; - - - - - - - - - - - -input clk; -input clken; -input reset_n; -logic [RATE_FACTOR_WIDTH-1:0] rate; -logic in_startofpacket; -logic in_endofpacket; -output in_ready; -input in_valid; -logic [CHANNEL_OUT_WIDTH-1:0] out_channel; -logic out_startofpacket; -logic out_endofpacket; -input [1:0] in_error; -output [1:0] out_error; -input out_ready; -output out_valid; -input [IN_WIDTH-1:0] in_data; -output [OUT_WIDTH-1:0] out_data; - -wire [IN_WIDTH-1:0] din [INTERFACES_IN-1:0]; -wire [OUT_WIDTH-1:0] dout [INTERFACES_OUT-1:0]; - - - - - -assign din[0] = in_data; - -assign out_data = dout[0]; -assign in_startofpacket = 1'b1; -assign in_endofpacket = 1'b1; -assign rate = '0; - - - - alt_cic_core #( - .DEVICE_FAMILY (DEVICE_FAMILY), - .FILTER_TYPE (FILTER_TYPE), - .STAGES (STAGES), - .D_DELAY (D_DELAY), - .VRC_EN (VRC_EN), - .RCF_MAX (RCF_MAX), - .RCF_MIN (RCF_MIN), - .INTERFACES (INTERFACES), - .CH_PER_INT (CH_PER_INT), - .INT_USE_MEM (INT_USE_MEM), - .INT_MEM (INT_MEM), - .DIF_USE_MEM (DIF_USE_MEM), - .DIF_MEM (DIF_MEM), - .IN_WIDTH (IN_WIDTH), - .OUT_WIDTH (OUT_WIDTH), - .ROUND_TYPE (ROUND_TYPE), - .PIPELINING (PIPELINING), - - .C_STAGE_0_WIDTH(C_STAGE_0_WIDTH), - .C_STAGE_1_WIDTH(C_STAGE_1_WIDTH), - .C_STAGE_2_WIDTH(C_STAGE_2_WIDTH), - .C_STAGE_3_WIDTH(C_STAGE_3_WIDTH), - .C_STAGE_4_WIDTH(C_STAGE_4_WIDTH), - .C_STAGE_5_WIDTH(C_STAGE_5_WIDTH), - .C_STAGE_6_WIDTH(C_STAGE_6_WIDTH), - .C_STAGE_7_WIDTH(C_STAGE_7_WIDTH), - .C_STAGE_8_WIDTH(C_STAGE_8_WIDTH), - .C_STAGE_9_WIDTH(C_STAGE_9_WIDTH), - .C_STAGE_10_WIDTH(C_STAGE_10_WIDTH), - .C_STAGE_11_WIDTH(C_STAGE_11_WIDTH), - .MAX_C_STAGE_WIDTH(MAX_C_STAGE_WIDTH), - - .I_STAGE_0_WIDTH(I_STAGE_0_WIDTH), - .I_STAGE_1_WIDTH(I_STAGE_1_WIDTH), - .I_STAGE_2_WIDTH(I_STAGE_2_WIDTH), - .I_STAGE_3_WIDTH(I_STAGE_3_WIDTH), - .I_STAGE_4_WIDTH(I_STAGE_4_WIDTH), - .I_STAGE_5_WIDTH(I_STAGE_5_WIDTH), - .I_STAGE_6_WIDTH(I_STAGE_6_WIDTH), - .I_STAGE_7_WIDTH(I_STAGE_7_WIDTH), - .I_STAGE_8_WIDTH(I_STAGE_8_WIDTH), - .I_STAGE_9_WIDTH(I_STAGE_9_WIDTH), - .I_STAGE_10_WIDTH(I_STAGE_10_WIDTH), - .I_STAGE_11_WIDTH(I_STAGE_11_WIDTH), - .MAX_I_STAGE_WIDTH(MAX_I_STAGE_WIDTH) - ) core ( - .clk(clk), - .clken(clken), - .reset_n(reset_n), - .rate(rate), - .in_startofpacket(in_startofpacket), - .in_endofpacket(in_endofpacket), - .in_data(din), - .in_ready(in_ready), - .in_valid(in_valid), - .out_channel(out_channel), - .out_startofpacket(out_startofpacket), - .out_endofpacket(out_endofpacket), - .in_error(in_error), - .out_error(out_error), - .out_ready(out_ready), - .out_data(dout), - .out_valid(out_valid) - ); - defparam core.HYPER_PIPELINE = 0; - - -endmodule diff --git a/FPGA_61.440/db/ip/tx_cic/tx_cic.bsf b/FPGA_61.440/db/ip/tx_cic/tx_cic.bsf deleted file mode 100644 index 9da2ed1..0000000 --- a/FPGA_61.440/db/ip/tx_cic/tx_cic.bsf +++ /dev/null @@ -1,129 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 2018 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 256 232) - (text "tx_cic" (rect 111 -1 134 11)(font "Arial" (font_size 10))) - (text "inst" (rect 8 216 20 228)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "in_error[1..0]" (rect 0 0 50 12)(font "Arial" (font_size 8))) - (text "in_error[1..0]" (rect 4 61 88 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 80 72)(line_width 3)) - ) - (port - (pt 0 88) - (input) - (text "in_valid" (rect 0 0 29 12)(font "Arial" (font_size 8))) - (text "in_valid" (rect 4 77 52 88)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 80 88)(line_width 1)) - ) - (port - (pt 0 120) - (input) - (text "in_data[15..0]" (rect 0 0 51 12)(font "Arial" (font_size 8))) - (text "in_data[15..0]" (rect 4 109 88 120)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 80 120)(line_width 3)) - ) - (port - (pt 256 120) - (input) - (text "out_ready" (rect 0 0 41 12)(font "Arial" (font_size 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false - true - - - com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage - VERILOG - false - false - false - true - - - boolean - true - false - true - true - true - - - com.altera.sopcmodel.definition.BoundaryDefinition - - false - true - false - true - - - int - 1 - false - true - true - true - - - java.lang.String - WOLF-LITE.qpf - false - true - false - true - - - boolean - false - false - true - false - true - - - long - 0 - false - true - false - true - - - java.lang.String - - false - true - false - true - - - long - 0 - false - true - false - true - - - boolean - false - false - true - false - true - - - - - java.lang.String - NATIVE - false - true - false - true - DESIGN_ENVIRONMENT - - - java.lang.String - CYCLONEIVE - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - interpolator - false - true - true - true - - - int - 6 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 3200 - false - true - true - true - - - int - 8 - false - false - false - true - - - int - 21 - false - false - false - true - - - int - 3200 - true - true - false - true - - - int - 3200 - true - true - false - true - - - int - 1 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 16 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - TRUNCATE - false - true - true - true - - - int - 16 - false - true - true - true - - - int - 16 - true - false - false - true - - - boolean - false - true - false - false - true - - - java.lang.String - auto - true - true - true - true - - - java.lang.String - logic_element - false - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - auto - true - true - true - true - - - java.lang.String - logic_element - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - true - false - true - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 75 - true - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clock - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - java.lang.String - clock - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - in_error - Input - 2 - error - - - in_valid - Input - 1 - valid - - - in_ready - Output - 1 - ready - - - in_data - Input - 16 - in_data - - - - - - ui.blockdiagram.direction - OUTPUT - - - java.lang.String - clock - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_data - Output - 16 - out_data - - - out_error - Output - 2 - error - - - out_valid - Output - 1 - valid - - - out_ready - Input - 1 - ready - - - - - 1 - altera_cic_ii - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - CIC - 18.1 - - - 1 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 18.1 - - - 1 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 18.1 - - - 2 - conduit_end - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit - 18.1 - - 18.1 625 - 08626627EDAB00000178897F8C06 - diff --git a/FPGA_61.440/db/ip/tx_cic/tx_cic.qip b/FPGA_61.440/db/ip/tx_cic/tx_cic.qip deleted file mode 100644 index d45e441..0000000 --- a/FPGA_61.440/db/ip/tx_cic/tx_cic.qip +++ /dev/null @@ -1,114 +0,0 @@ -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_TOOL_NAME "Qsys" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_TOOL_ENV "Qsys" -set_global_assignment -library "tx_cic" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../../tx_cic.sopcinfo"] -set_global_assignment -entity "tx_cic" -library "tx_cic" -name SLD_INFO "QSYS_NAME tx_cic HAS_SOPCINFO 1 GENERATION_ID 1617214539" -set_global_assignment -library "tx_cic" -name SLD_FILE [file join $::quartus(qip_path) "tx_cic.debuginfo"] -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_QSYS_MODE "STANDALONE" -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -library "tx_cic" -name MISC_FILE [file join $::quartus(qip_path) "../../../tx_cic.qsys"] -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_COMPONENT_NAME "dHhfY2lj" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_COMPONENT_DISPLAY_NAME "dHhfY2lj" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_COMPONENT_REPORT_HIERARCHY "On" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_COMPONENT_VERSION "MS4w" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYxNzIxNDUzOQ==::QXV0byBHRU5FUkFUSU9OX0lE" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMEUyMkM4::QXV0byBERVZJQ0U=" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19DTE9DS19SQVRF::LTE=::QXV0byBDTE9DS19SQVRF" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19DTE9DS19ET01BSU4=::LTE=::QXV0byBDTE9DS19ET01BSU4=" -set_global_assignment -entity "tx_cic" -library "tx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19SRVNFVF9ET01BSU4=::LTE=::QXV0byBSRVNFVF9ET01BSU4=" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_NAME "dHhfY2ljX2NpY19paV8w" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_DISPLAY_NAME "Q0lD" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIENhc2NhZGVkIEludGVncmF0b3IgQ29tYiBJSQ==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "ZGVzaWduX2Vudg==::TkFUSVZF::ZGVzaWduX2Vudg==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBJViBF::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "RklMVEVSX1RZUEU=::aW50ZXJwb2xhdG9y::RmlsdGVyIHR5cGU=" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "U1RBR0VT::Ng==::TnVtYmVyIG9mIHN0YWdlcw==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "RF9ERUxBWQ==::MQ==::RGlmZmVyZW50aWFsIGRlbGF5" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "VlJDX0VO::MA==::RW5hYmxlIHZhcmlhYmxlIHJhdGUgY2hhbmdlIGZhY3Rvcg==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "UkNGX0ZJWA==::MzIwMA==::UmF0ZSBjaGFuZ2UgZmFjdG9y" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "UkNGX01JTg==::MzIwMA==::UkNGX01JTg==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "UkNGX01BWA==::MzIwMA==::UkNGX01BWA==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SU5URVJGQUNFUw==::MQ==::TnVtYmVyIG9mIGludGVyZmFjZXM=" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Q0hfUEVSX0lOVA==::MQ==::TnVtYmVyIG9mIGNoYW5uZWxzIHBlciBpbnRlcmZhY2U=" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SU5fV0lEVEg=::MTY=::SW5wdXQgZGF0YSB3aWR0aA==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Q0xLX0VOX1BPUlQ=::ZmFsc2U=::VXNlIGNsb2NrIGVuYWJsZSBwb3J0" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Uk9VTkRfVFlQRQ==::VFJVTkNBVEU=::T3V0cHV0IFJvdW5kaW5nIE1ldGhvZA==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "UkVRX09VVF9XSURUSA==::MTY=::T3V0cHV0IGRhdGEgd2lkdGg=" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SU5UX01FTQ==::YXV0bw==::SW50ZWdyYXRvciBkYXRhIHN0b3JhZ2UgdHlwZQ==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "UkVRX0lOVF9NRU0=::bG9naWNfZWxlbWVudA==::SW50ZWdyYXRvciBkYXRhIHN0b3JhZ2UgdHlwZQ==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "RElGX1VTRV9NRU0=::ZmFsc2U=::TWFwIGRpZmZlcmVudGlhdG9yIGRhdGEgc3RvcmFnZSB0byBtZW1vcnk=" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "RElGX01FTQ==::YXV0bw==::RGlmZmVyZW50aWF0b3IgZGF0YSBzdG9yYWdlIHR5cGU=" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "UkVRX0RJRl9NRU0=::bG9naWNfZWxlbWVudA==::RGlmZmVyZW50aWF0b3IgZGF0YSBzdG9yYWdlIHR5cGU=" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "UkVRX1BJUEVMSU5F::MA==::UGlwZWxpbmUgc3RhZ2VzIHBlciBpbnRlZ3JhdG9y" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV8wX1dJRFRI::NzU=::Q19TVEFHRV8wX1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV8wX1dJRFRI::NzU=::SV9TVEFHRV8wX1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV8xX1dJRFRI::NzU=::Q19TVEFHRV8xX1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV8xX1dJRFRI::NzU=::SV9TVEFHRV8xX1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV8yX1dJRFRI::NzU=::Q19TVEFHRV8yX1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV8yX1dJRFRI::NzU=::SV9TVEFHRV8yX1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV8zX1dJRFRI::NzU=::Q19TVEFHRV8zX1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV8zX1dJRFRI::NzU=::SV9TVEFHRV8zX1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV80X1dJRFRI::NzU=::Q19TVEFHRV80X1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV80X1dJRFRI::NzU=::SV9TVEFHRV80X1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV81X1dJRFRI::NzU=::Q19TVEFHRV81X1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV81X1dJRFRI::NzU=::SV9TVEFHRV81X1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV82X1dJRFRI::NzU=::Q19TVEFHRV82X1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV82X1dJRFRI::NzU=::SV9TVEFHRV82X1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV83X1dJRFRI::NzU=::Q19TVEFHRV83X1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV83X1dJRFRI::NzU=::SV9TVEFHRV83X1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV84X1dJRFRI::NzU=::Q19TVEFHRV84X1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV84X1dJRFRI::NzU=::SV9TVEFHRV84X1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV85X1dJRFRI::NzU=::Q19TVEFHRV85X1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV85X1dJRFRI::NzU=::SV9TVEFHRV85X1dJRFRI" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV8xMF9XSURUSA==::NzU=::Q19TVEFHRV8xMF9XSURUSA==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV8xMF9XSURUSA==::NzU=::SV9TVEFHRV8xMF9XSURUSA==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "Q19TVEFHRV8xMV9XSURUSA==::NzU=::Q19TVEFHRV8xMV9XSURUSA==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "SV9TVEFHRV8xMV9XSURUSA==::NzU=::SV9TVEFHRV8xMV9XSURUSA==" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "TUFYX0lfU1RBR0VfV0lEVEg=::NzU=::TUFYX0lfU1RBR0VfV0lEVEg=" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "TUFYX0NfU1RBR0VfV0lEVEg=::NzU=::TUFYX0NfU1RBR0VfV0lEVEg=" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "aHlwZXJfb3B0X3NlbGVjdA==::MA==::T3B0aW1pemUgZm9yIFN0cmF0aXggMTA=" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_COMPONENT_PARAMETER "aHlwZXJfb3B0::MA==::aHlwZXJfb3B0" - -set_global_assignment -library "tx_cic" -name VERILOG_FILE [file join $::quartus(qip_path) "tx_cic.v"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_math_pkg.vhd"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_text_pkg.vhd"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_lib_pkg.vhd"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_avalon_streaming_small_fifo.vhd"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_avalon_streaming_controller.vhd"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_avalon_streaming_sink.vhd"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_avalon_streaming_source.vhd"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_delay.vhd"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_fastaddsub.vhd"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_fastadd.vhd"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_pipelined_adder.vhd"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_roundsat.vhd"] -set_global_assignment -library "tx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_dsp_cic_common_pkg.sv"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_cic_lib_pkg.vhd"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_differentiator.vhd"] -set_global_assignment -library "tx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_downsample.sv"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_integrator.vhd"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_upsample.vhd"] -set_global_assignment -library "tx_cic" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_channel_buffer.vhd"] -set_global_assignment -library "tx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/auk_dspip_variable_downsample.sv"] -set_global_assignment -library "tx_cic" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/hyper_pipeline_interface.v"] -set_global_assignment -library "tx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/counter_module.sv"] -set_global_assignment -library "tx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_cic_int_siso.sv"] -set_global_assignment -library "tx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_cic_dec_siso.sv"] -set_global_assignment -library "tx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_cic_int_simo.sv"] -set_global_assignment -library "tx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_cic_dec_miso.sv"] -set_global_assignment -library "tx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/alt_cic_core.sv"] -set_global_assignment -library "tx_cic" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/alt_cic_core.ocp"] -set_global_assignment -library "tx_cic" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/tx_cic_cic_ii_0.sv"] - -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_TOOL_NAME "altera_cic_ii" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "tx_cic_cic_ii_0" -library "tx_cic" -name IP_TOOL_ENV "Qsys" diff --git a/FPGA_61.440/db/ip/tx_cic/tx_cic.v b/FPGA_61.440/db/ip/tx_cic/tx_cic.v deleted file mode 100644 index d78f193..0000000 --- a/FPGA_61.440/db/ip/tx_cic/tx_cic.v +++ /dev/null @@ -1,33 +0,0 @@ -// tx_cic.v - -// Generated using ACDS version 18.1 625 - -`timescale 1 ps / 1 ps -module tx_cic ( - input wire [1:0] in_error, // av_st_in.error - input wire in_valid, // .valid - output wire in_ready, // .ready - input wire [15:0] in_data, // .in_data - output wire [15:0] out_data, // av_st_out.out_data - output wire [1:0] out_error, // .error - output wire out_valid, // .valid - input wire out_ready, // .ready - input wire clk, // clock.clk - input wire reset_n // reset.reset_n - ); - - tx_cic_cic_ii_0 cic_ii_0 ( - .clk (clk), // clock.clk - .reset_n (reset_n), // reset.reset_n - .in_error (in_error), // av_st_in.error - .in_valid (in_valid), // .valid - .in_ready (in_ready), // .ready - .in_data (in_data), // .in_data - .out_data (out_data), // av_st_out.out_data - .out_error (out_error), // .error - .out_valid (out_valid), // .valid - .out_ready (out_ready), // .ready - .clken (1'b1) // (terminated) - ); - -endmodule diff --git a/FPGA_61.440/db/ip/tx_cic/tx_cic__report.html b/FPGA_61.440/db/ip/tx_cic/tx_cic__report.html deleted file mode 100644 index cd2ed26..0000000 --- a/FPGA_61.440/db/ip/tx_cic/tx_cic__report.html +++ /dev/null @@ -1,349 +0,0 @@ - - - - - datasheet for tx_cic - - - - - - - - -
tx_cic -
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2021.03.31.22:15:40Datasheet
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Overview
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Memory Map
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cic_ii_0

altera_cic_ii v18.1 -
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Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
design_envNATIVE
selected_device_familyCYCLONEIVE
FILTER_TYPEinterpolator
STAGES6
D_DELAY1
VRC_EN0
RCF_FIX3200
RCF_LB8
RCF_UB21
RCF_MIN3200
RCF_MAX3200
INTERFACES1
CH_PER_INT1
IN_WIDTH16
CLK_EN_PORTfalse
ROUND_TYPETRUNCATE
REQ_OUT_WIDTH16
OUT_WIDTH16
INT_USE_MEMfalse
INT_MEMauto
REQ_INT_MEMlogic_element
DIF_USE_MEMfalse
DIF_MEMauto
REQ_DIF_MEMlogic_element
REQ_PIPELINE0
PIPELINING0
C_STAGE_0_WIDTH75
I_STAGE_0_WIDTH75
C_STAGE_1_WIDTH75
I_STAGE_1_WIDTH75
C_STAGE_2_WIDTH75
I_STAGE_2_WIDTH75
C_STAGE_3_WIDTH75
I_STAGE_3_WIDTH75
C_STAGE_4_WIDTH75
I_STAGE_4_WIDTH75
C_STAGE_5_WIDTH75
I_STAGE_5_WIDTH75
C_STAGE_6_WIDTH75
I_STAGE_6_WIDTH75
C_STAGE_7_WIDTH75
I_STAGE_7_WIDTH75
C_STAGE_8_WIDTH75
I_STAGE_8_WIDTH75
C_STAGE_9_WIDTH75
I_STAGE_9_WIDTH75
C_STAGE_10_WIDTH75
I_STAGE_10_WIDTH75
C_STAGE_11_WIDTH75
I_STAGE_11_WIDTH75
MAX_I_STAGE_WIDTH75
MAX_C_STAGE_WIDTH75
hyper_opt_select0
hyper_opt0
deviceFamilyUNKNOWN
generateLegacySimfalse
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Software Assignments

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generation took 0,01 secondsrendering took 0,04 seconds
- - diff --git a/FPGA_61.440/db/ip/tx_cic/tx_cic__report.xml b/FPGA_61.440/db/ip/tx_cic/tx_cic__report.xml deleted file mode 100644 index 1dd3a5e..0000000 --- a/FPGA_61.440/db/ip/tx_cic/tx_cic__report.xml +++ /dev/null @@ -1,435 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:tx_cic "tx_cic" - - - - Transform: CustomInstructionTransform - No custom instruction connections, skipping transform - 1 modules, 0 connections]]> - Transform: MMTransform - Transform: InterruptMapperTransform - Transform: InterruptSyncTransform - Transform: InterruptFanoutTransform - Transform: AvalonStreamingTransform - Transform: ResetAdaptation - tx_cic" reuses altera_cic_ii "submodules/tx_cic_cic_ii_0"]]> - queue size: 0 starting:altera_cic_ii "submodules/tx_cic_cic_ii_0" - tx_cic" instantiated altera_cic_ii "cic_ii_0"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:altera_cic_ii "submodules/tx_cic_cic_ii_0" - tx_cic" instantiated altera_cic_ii "cic_ii_0"]]> - - - diff --git a/FPGA_61.440/db/ip/tx_nco/submodules/asj_altq.ocp b/FPGA_61.440/db/ip/tx_nco/submodules/asj_altq.ocp deleted file mode 100644 index 1bd2b88..0000000 Binary files a/FPGA_61.440/db/ip/tx_nco/submodules/asj_altq.ocp and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_nco/submodules/asj_altqmcash.ocp b/FPGA_61.440/db/ip/tx_nco/submodules/asj_altqmcash.ocp deleted file mode 100644 index ccc465c..0000000 Binary files a/FPGA_61.440/db/ip/tx_nco/submodules/asj_altqmcash.ocp and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_nco/submodules/asj_altqmcpipe.ocp b/FPGA_61.440/db/ip/tx_nco/submodules/asj_altqmcpipe.ocp deleted file mode 100644 index 9cae72b..0000000 Binary files a/FPGA_61.440/db/ip/tx_nco/submodules/asj_altqmcpipe.ocp and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_nco/submodules/asj_altqmcpipe.v b/FPGA_61.440/db/ip/tx_nco/submodules/asj_altqmcpipe.v deleted file mode 100644 index 36513b7..0000000 Binary files a/FPGA_61.440/db/ip/tx_nco/submodules/asj_altqmcpipe.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_nco/submodules/asj_gam_dp.v b/FPGA_61.440/db/ip/tx_nco/submodules/asj_gam_dp.v deleted file mode 100644 index 9664a86..0000000 Binary files a/FPGA_61.440/db/ip/tx_nco/submodules/asj_gam_dp.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v b/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v deleted file mode 100644 index 9a264e0..0000000 Binary files a/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v b/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v deleted file mode 100644 index 7c3b46c..0000000 Binary files a/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_derot.v b/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_derot.v deleted file mode 100644 index cf2428b..0000000 Binary files a/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_derot.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_isdr.v b/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_isdr.v deleted file mode 100644 index 0017f76..0000000 Binary files a/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_isdr.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_madx_cen.v b/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_madx_cen.v deleted file mode 100644 index 2590a31..0000000 Binary files a/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_madx_cen.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_mady_cen.v b/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_mady_cen.v deleted file mode 100644 index 20fdefe..0000000 Binary files a/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_mady_cen.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_mob_w.v b/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_mob_w.v deleted file mode 100644 index 39e5e62..0000000 Binary files a/FPGA_61.440/db/ip/tx_nco/submodules/asj_nco_mob_w.v and /dev/null differ diff --git a/FPGA_61.440/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v b/FPGA_61.440/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v deleted file mode 100644 index 7aedc86..0000000 --- a/FPGA_61.440/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v +++ /dev/null @@ -1,435 +0,0 @@ -// Copyright (C) 1988-2012 Altera Corporation - -// Any megafunction design, and related net list (encrypted or decrypted), -// support information, device programming or simulation file, and any other -// associated documentation or information provided by Altera or a partner -// under Altera's Megafunction Partnership Program may be used only to -// program PLD devices (but not masked PLD devices) from Altera. Any other -// use of such megafunction design, net list, support information, device -// programming or simulation file, or any other related documentation or -// information is prohibited for any other purpose, including, but not -// limited to modification, reverse engineering, de-compiling, or use with -// any other silicon devices, unless such use is explicitly licensed under -// a separate agreement with Altera or a megafunction partner. Title to -// the intellectual property, including patents, copyrights, trademarks, -// trade secrets, or maskworks, embodied in any such megafunction design, -// net list, support information, device programming or simulation file, or -// any other related documentation or information provided by Altera or a -// megafunction partner, remains with Altera, the megafunction partner, or -// their respective licensors. No other licenses, including any licenses -// needed under any third party's intellectual property, are provided herein. - - -module tx_nco_nco_ii_0(clk, reset_n, clken, phi_inc_i, fsin_o, fcos_o, out_valid); - -parameter mpr = 16; -parameter opr = 32; -parameter apr = 22; -parameter apri= 22; -parameter aprf= 32; -parameter aprp= 16; -parameter aprid=27; -parameter dpri= 4; -parameter rdw = 16; -parameter rawc = 11; -parameter rnwc = 2048; -parameter rawf = 11; -parameter rnwf = 2048; -parameter Pn = 1048576; -parameter mxnbc = 32768; -parameter mxnbf = 32768; -parameter rsfc = "tx_nco_nco_ii_0_sin_c.hex"; -parameter rsff = "tx_nco_nco_ii_0_sin_f.hex"; -parameter rcfc = "tx_nco_nco_ii_0_cos_c.hex"; -parameter rcff = "tx_nco_nco_ii_0_cos_f.hex"; -parameter nc = 1; -parameter log2nc =0; -parameter outselinit = 0; -parameter paci0= 0; -parameter paci1= 0; -parameter paci2= 0; -parameter paci3= 0; -parameter paci4= 0; -parameter paci5= 0; -parameter paci6= 0; -parameter paci7= 0; -//parameter numba = 1; -//parameter log2numba = 0; - -input clk; -input reset_n; -input clken; -input [apr-1:0] phi_inc_i; - -output [mpr-1:0] fsin_o; -output [mpr-1:0] fcos_o; -output out_valid; -wire reset; -assign reset = !reset_n; - -wire [apr-1:0] phi_inc_i_w; -wire [apr-1:0] phi_acc_w; -wire [mpr-1:0] rfx_s; -wire [mpr-1:0] rcx_s; -wire [mpr-1:0] rfx_c; -wire [mpr-1:0] rcx_c; -wire [mpr-1:0] rfy_s; -wire [mpr-1:0] rcy_s; -wire [mpr-1:0] rfy_c; -wire [mpr-1:0] rcy_c; -wire [rawc-1:0] raxxx001ms; -wire [rawc-1:0] raxxx001mc; -wire [rawc-1:0] raxxx000m; -wire [rawf-1:0] raxxx000l; -wire [rawc-1:0] raxxx001m; -wire [rawf-1:0] raxxx001l; -wire [opr-1:0] result_i; -wire [opr-1:0] result_r; -wire [mpr-1:0] fsin_o_w; -wire [mpr-1:0] fcos_o_w; -wire out_valid_w; - -//Pipelining for Hyper Retimer starts from here -parameter hyper_pipeline = 0; -integer i; - -reg [1-1:0] reset_reg [3-1:0]; -wire [1-1:0] reset_pipelined; -reg [1-1:0] clken_reg [3-1:0]; -wire [1-1:0] clken_pipelined; -reg [apr-1:0] phi_inc_i_reg [3-1:0]; -wire [apr-1:0] phi_inc_i_pipelined; -reg [1-1:0] out_valid_w_reg [2-1:0]; -wire [1-1:0] out_valid_w_pipelined; -reg [mpr-1:0] fsin_o_w_reg [2-1:0]; -wire [mpr-1:0] fsin_o_w_pipelined; -reg [opr-1:0] result_i_reg [1-1:0]; -wire [opr-1:0] result_i_pipelined; -reg [mpr-1:0] fcos_o_w_reg [2-1:0]; -wire [mpr-1:0] fcos_o_w_pipelined; -reg [opr-1:0] result_r_reg [1-1:0]; -wire [opr-1:0] result_r_pipelined; -reg [mpr-1:0] rcx_c_reg [2-1:0]; -wire [mpr-1:0] rcx_c_pipelined; -reg [mpr-1:0] rfx_c_reg [2-1:0]; -wire [mpr-1:0] rfx_c_pipelined; -reg [mpr-1:0] rcx_s_reg [2-1:0]; -wire [mpr-1:0] rcx_s_pipelined; -reg [mpr-1:0] rfx_s_reg [2-1:0]; -wire [mpr-1:0] rfx_s_pipelined; -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - reset_reg[0] <= reset; - for (i = 1; i < 3; i=i+1) begin - reset_reg[i] <= reset_reg[i-1]; - end - end - assign reset_pipelined = reset_reg[3-1]; - end - else begin - assign reset_pipelined = reset; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - clken_reg[0] <= clken; - for (i = 1; i < 3; i=i+1) begin - clken_reg[i] <= clken_reg[i-1]; - end - end - assign clken_pipelined = clken_reg[3-1]; - end - else begin - assign clken_pipelined = clken; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - phi_inc_i_reg[0] <= phi_inc_i; - for (i = 1; i < 3; i=i+1) begin - phi_inc_i_reg[i] <= phi_inc_i_reg[i-1]; - end - end - assign phi_inc_i_pipelined = phi_inc_i_reg[3-1]; - end - else begin - assign phi_inc_i_pipelined = phi_inc_i; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - out_valid_w_reg[0] <= out_valid_w; - for (i = 1; i < 2; i=i+1) begin - out_valid_w_reg[i] <= out_valid_w_reg[i-1]; - end - end - assign out_valid_w_pipelined = out_valid_w_reg[2-1]; - end - else begin - assign out_valid_w_pipelined = out_valid_w; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - fsin_o_w_reg[0] <= fsin_o_w; - for (i = 1; i < 2; i=i+1) begin - fsin_o_w_reg[i] <= fsin_o_w_reg[i-1]; - end - end - assign fsin_o_w_pipelined = fsin_o_w_reg[2-1]; - end - else begin - assign fsin_o_w_pipelined = fsin_o_w; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - result_i_reg[0] <= result_i; - end - assign result_i_pipelined = result_i_reg[1-1]; - end - else begin - assign result_i_pipelined = result_i; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - fcos_o_w_reg[0] <= fcos_o_w; - for (i = 1; i < 2; i=i+1) begin - fcos_o_w_reg[i] <= fcos_o_w_reg[i-1]; - end - end - assign fcos_o_w_pipelined = fcos_o_w_reg[2-1]; - end - else begin - assign fcos_o_w_pipelined = fcos_o_w; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - result_r_reg[0] <= result_r; - end - assign result_r_pipelined = result_r_reg[1-1]; - end - else begin - assign result_r_pipelined = result_r; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - rcx_c_reg[0] <= rcx_c; - for (i = 1; i < 2; i=i+1) begin - rcx_c_reg[i] <= rcx_c_reg[i-1]; - end - end - assign rcx_c_pipelined = rcx_c_reg[2-1]; - end - else begin - assign rcx_c_pipelined = rcx_c; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - rfx_c_reg[0] <= rfx_c; - for (i = 1; i < 2; i=i+1) begin - rfx_c_reg[i] <= rfx_c_reg[i-1]; - end - end - assign rfx_c_pipelined = rfx_c_reg[2-1]; - end - else begin - assign rfx_c_pipelined = rfx_c; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - rcx_s_reg[0] <= rcx_s; - for (i = 1; i < 2; i=i+1) begin - rcx_s_reg[i] <= rcx_s_reg[i-1]; - end - end - assign rcx_s_pipelined = rcx_s_reg[2-1]; - end - else begin - assign rcx_s_pipelined = rcx_s; // pipeline for this signal is disabled - end -endgenerate -// Pipeline block -generate - if (hyper_pipeline == 1) begin - always @ (posedge clk) begin - rfx_s_reg[0] <= rfx_s; - for (i = 1; i < 2; i=i+1) begin - rfx_s_reg[i] <= rfx_s_reg[i-1]; - end - end - assign rfx_s_pipelined = rfx_s_reg[2-1]; - end - else begin - assign rfx_s_pipelined = rfx_s; // pipeline for this signal is disabled - end -endgenerate - - -assign phi_inc_i_w = phi_inc_i_pipelined; - - -asj_altqmcpipe ux000 (.clk(clk), - .reset(reset_pipelined), - .clken(clken_pipelined), - .phi_inc_int(phi_inc_i_w), - .phi_acc_reg(phi_acc_w) - ); - -defparam ux000.nc = nc ; -defparam ux000.apr = apr ; -defparam ux000.lat = 1 ; -defparam ux000.paci0 = paci0 ; -defparam ux000.paci1 = paci1 ; -defparam ux000.paci2 = paci2 ; -defparam ux000.paci3 = paci3 ; -defparam ux000.paci4 = paci4 ; -defparam ux000.paci5 = paci5 ; -defparam ux000.paci6 = paci6 ; -defparam ux000.paci7 = paci7 ; - - -asj_gam_dp ux008( .clk(clk), - .reset(reset_pipelined), - .clken(clken_pipelined), - .phi_acc_w(phi_acc_w[apr-1:apr-rawc-rawf]), - .rom_add_cs(raxxx001ms), - .rom_add_cc(raxxx001mc), - .rom_add_f(raxxx001l) - ); -defparam ux008.rawc = rawc; -defparam ux008.rawf = rawf; -defparam ux008.apr = apri; - - -asj_nco_as_m_dp_cen ux0220(.clk(clk), - .clken (clken_pipelined), - .raxx_a(raxxx001ms[rawc-1:0]), - .raxx_b(raxxx001mc[rawc-1:0]), - .q_a(rcx_s[mpr-1:0]), - .q_b(rcx_c[mpr-1:0]) - ); -defparam ux0220.mpr = mpr; -defparam ux0220.rdw = rdw; -defparam ux0220.raw = rawc; -defparam ux0220.rnw = rnwc; -defparam ux0220.rf = rsfc; -defparam ux0220.dev = "Cyclone IV E"; - -asj_nco_as_m_cen ux0122(.clk(clk), - .clken (clken_pipelined), - .raxx(raxxx001l[rawf-1:0]), - .srw_int_res(rfx_s[mpr-1:0]) - ); -defparam ux0122.mpr = mpr; -defparam ux0122.rdw = rdw; -defparam ux0122.raw = rawf; -defparam ux0122.rnw = rnwf; -defparam ux0122.rf = rsff; -defparam ux0122.dev = "Cyclone IV E"; - -asj_nco_as_m_cen ux0123(.clk(clk), - .clken (clken_pipelined), - .raxx(raxxx001l[rawf-1:0]), - .srw_int_res(rfx_c[mpr-1:0]) - ); -defparam ux0123.mpr = mpr; -defparam ux0123.rdw = rdw; -defparam ux0123.raw = rawf; -defparam ux0123.rnw = rnwf; -defparam ux0123.rf = rcff; -defparam ux0123.dev = "Cyclone IV E"; - -asj_nco_madx_cen m1( - .dataa_0(rcy_c), - .dataa_1(rcy_s), - .datab_0(rfy_c), - .datab_1(rfy_s), - .result(result_r), - .clock0(clk), - .clken(clken_pipelined)); -defparam m1.mpr = mpr; -defparam m1.opr = opr; -// Writing multiplier for 'Cyclone IV E' - -asj_nco_mady_cen m0( - .dataa_0(rcy_s), - .dataa_1(rfy_s), - .datab_0(rfy_c), - .datab_1(rcy_c), - .result(result_i), - .clock0(clk), - .clken(clken_pipelined)); -defparam m0.mpr = mpr; -defparam m0.opr = opr; -// Writing multiplier for 'Cyclone IV E' - -asj_nco_derot ux0136(.crwx_rc(rcx_c_pipelined), - .crwx_rf(rfx_c_pipelined), - .srwx_rc(rcx_s_pipelined), - .srwx_rf(rfx_s_pipelined), - .crwy_rc(rcy_c), - .crwy_rf(rfy_c), - .srwy_rc(rcy_s), - .srwy_rf(rfy_s) - ); -defparam ux0136.mpr = mpr; -defparam ux0136.rxt = rdw; - -asj_nco_mob_w blk0( .clk(clk), - .reset(reset_pipelined), - .clken(clken_pipelined), - .data_in(result_i_pipelined), - .data_out(fsin_o_w)); - -defparam blk0.mpr = mpr; - -asj_nco_mob_w blk1( .clk(clk), - .reset(reset_pipelined), - .clken(clken_pipelined), - .data_in(result_r_pipelined), - .data_out(fcos_o_w)); - -defparam blk1.mpr = mpr; -assign fsin_o = fsin_o_w_pipelined; -assign fcos_o = fcos_o_w_pipelined; - -asj_nco_isdr ux710isdr(.clk(clk), - .reset(reset_pipelined), - .clken(clken_pipelined), - .data_ready(out_valid_w) - ); -defparam ux710isdr.ctc=8; -defparam ux710isdr.cpr=4; -assign out_valid = out_valid_w_pipelined; - - - -endmodule diff --git a/FPGA_61.440/db/ip/tx_nco/submodules/tx_nco_nco_ii_0_cos_c.hex b/FPGA_61.440/db/ip/tx_nco/submodules/tx_nco_nco_ii_0_cos_c.hex deleted file mode 100644 index d0d114c..0000000 --- a/FPGA_61.440/db/ip/tx_nco/submodules/tx_nco_nco_ii_0_cos_c.hex +++ /dev/null @@ -1,2049 +0,0 @@ -:020000007fff80 -:020001007fff7f -:020002007ffe7f -:020003007ffe7e -:020004007ffd7e -:020005007ffb7f -:020006007ff980 -:020007007ff781 -:020008007ff582 -:020009007ff383 -:02000a007ff085 -:02000b007fec88 -:02000c007fe98a -:02000d007fe58d -:02000e007fe190 -:02000f007fdc94 -:020010007fd897 -:020011007fd29c -:020012007fcda0 -:020013007fc7a5 -:020014007fc1aa -:020015007fbbaf -:020016007fb4b5 -:020017007fadbb -:020018007fa6c1 -:020019007f9fc7 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file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 2018 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 256 200) - (text "tx_nco" (rect 109 -1 136 11)(font "Arial" (font_size 10))) - (text "inst" (rect 8 184 20 196)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "clk" (rect 0 0 10 12)(font "Arial" (font_size 8))) - (text "clk" (rect 4 61 22 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 80 72)(line_width 1)) - ) - (port - (pt 0 112) - (input) - (text "clken" (rect 0 0 20 12)(font "Arial" (font_size 8))) - (text "clken" (rect 4 101 34 112)(font "Arial" (font_size 8))) - (line (pt 0 112)(pt 80 112)(line_width 1)) - ) - (port - (pt 0 128) - (input) - (text "phi_inc_i[21..0]" (rect 0 0 57 12)(font "Arial" (font_size 8))) - (text "phi_inc_i[21..0]" (rect 4 117 100 128)(font "Arial" (font_size 8))) - (line (pt 0 128)(pt 80 128)(line_width 3)) - ) - (port - (pt 0 168) - (input) - (text "reset_n" (rect 0 0 30 12)(font "Arial" (font_size 8))) - (text "reset_n" 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false - true - false - true - - - int - 1617214553 - false - true - true - true - - - boolean - false - false - true - false - true - - - com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage - VERILOG - false - false - false - true - - - boolean - true - false - true - true - true - - - com.altera.sopcmodel.definition.BoundaryDefinition - - false - true - false - true - - - int - 1 - false - true - true - true - - - java.lang.String - WOLF-LITE.qpf - false - true - false - true - - - boolean - false - false - true - false - true - - - long - 0 - false - true - false - true - - - java.lang.String - - false - true - false - true - - - long - 0 - false - true - false - true - - - boolean - false - false - true - false - true - - - - - java.lang.String - NATIVE - false - true - false - true - DESIGN_ENVIRONMENT - - - java.lang.String - trig - false - true - true - true - - - java.lang.String - dual_output - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - true - false - true - true - true - - - java.lang.String - CYCLONEIVE - false - true - true - true - DEVICE_FAMILY - - - int - 22 - false - true - true - true - - - int - 22 - false - true - true - true - - - int - 16 - false - true - true - true - - - java.lang.String - parallel - false - true - false - true - - - int - 1 - false - true - true - true - - - int - 1 - true - true - false - true - - - boolean - false - false - true - true - true - - - int - 4 - false - false - true - true - - - double - 153.6 - false - true - true - true - - - double - 7.1 - false - true - true - true - - - long - 193877 - true - true - true - true - - - double - 7.1 - true - true - true - true - - - boolean - false - false - true - true - true - - - int - 32 - false - false - true - true - - - int - 1 - false - false - true - true - - - boolean - false - false - true - true - true - - - int - 16 - false - false - true - true - - - int - 1 - false - false - true - true - - - boolean - false - true - true - false - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - rst - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - clken - Input - 1 - clken - - - phi_inc_i - Input - 22 - phi_inc_i - - - - - - ui.blockdiagram.direction - OUTPUT - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - rst - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - fsin_o - Output - 16 - fsin_o - - - fcos_o - Output - 16 - fcos_o - - - out_valid - Output - 1 - out_valid - - - - - 1 - altera_nco_ii - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - NCO - 18.1 - - - 1 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 18.1 - - - 1 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 18.1 - - - 2 - conduit_end - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit - 18.1 - - 18.1 625 - 08626627EDAB00000178897FC659 - diff --git a/FPGA_61.440/db/ip/tx_nco/tx_nco.qip b/FPGA_61.440/db/ip/tx_nco/tx_nco.qip deleted file mode 100644 index 79d404b..0000000 --- a/FPGA_61.440/db/ip/tx_nco/tx_nco.qip +++ /dev/null @@ -1,75 +0,0 @@ -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_TOOL_NAME "Qsys" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_TOOL_ENV "Qsys" -set_global_assignment -library "tx_nco" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../../tx_nco.sopcinfo"] -set_global_assignment -entity "tx_nco" -library "tx_nco" -name SLD_INFO "QSYS_NAME tx_nco HAS_SOPCINFO 1 GENERATION_ID 1617214553" -set_global_assignment -library "tx_nco" -name SLD_FILE [file join $::quartus(qip_path) "tx_nco.debuginfo"] -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_QSYS_MODE "STANDALONE" -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -library "tx_nco" -name MISC_FILE [file join $::quartus(qip_path) "../../../tx_nco.qsys"] -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_COMPONENT_NAME "dHhfbmNv" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_COMPONENT_DISPLAY_NAME "dHhfbmNv" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_COMPONENT_REPORT_HIERARCHY "On" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_COMPONENT_VERSION "MS4w" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYxNzIxNDU1Mw==::QXV0byBHRU5FUkFUSU9OX0lE" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMEUyMkM4::QXV0byBERVZJQ0U=" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4=" -set_global_assignment -entity "tx_nco" -library "tx_nco" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4=" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_NAME "dHhfbmNvX25jb19paV8w" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_DISPLAY_NAME "TkNP" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_VERSION "MTguMQ==" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIE51bWVyaWNhbGx5IENvbnRyb2xsZWQgT3NjaWxsYXRvcg==" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "ZGVzaWduX2Vudg==::TkFUSVZF::ZGVzaWduX2Vudg==" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "YXJjaA==::dHJpZw==::R2VuZXJhdGlvbiBBbGdvcml0aG0=" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "d2FudF9zaW5fYW5kX2Nvcw==::ZHVhbF9vdXRwdXQ=::T3V0cHV0cw==" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "bnVtY2g=::MQ==::TnVtYmVyIG9mIENoYW5uZWxz" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "bnVtYmE=::MQ==::TnVtYmVyIG9mIEJhbmRz" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "dXNlX2RlZGljYXRlZF9tdWx0aXBsaWVycw==::dHJ1ZQ==::VXNlIGRlZGljYXRlZCBtdWx0aXBsaWVycw==" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBJViBF::RGV2aWNlIEZhbWlseQ==" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "YXBy::MjI=::UGhhc2UgQWNjdW11bGF0b3IgUHJlY2lzaW9u" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "YXByaQ==::MjI=::QW5ndWxhciBSZXNvbHV0aW9u" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "bXBy::MTY=::TWFnbml0dWRlIFJlc29sdXRpb24=" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "Y29yZGljX2FyY2g=::cGFyYWxsZWw=::Q09SRElDIEFyY2hpdGVjdHVyZQ==" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "dHJpZ19jeWNsZXNfcGVyX291dHB1dA==::MQ==::Q2xvY2sgY3ljbGVzIHBlciBvdXRwdXQ=" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "Y3ljbGVzX3Blcl9vdXRwdXQ=::MQ==::Q2xvY2sgY3ljbGVzIHBlciBvdXRwdXQ=" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "d2FudF9kaXRoZXI=::ZmFsc2U=::SW1wbGVtZW50IFBoYXNlIERpdGhlcmluZw==" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "ZnNhbXA=::MTUzLjY=::Q2xvY2sgUmF0ZQ==" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "ZnJlcV9vdXQ=::Ny4x::RGVzaXJlZCBPdXRwdXQgRnJlcXVlbmN5" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "cGhpX2luYw==::MTkzODc3::UGhhc2UgSW5jcmVtZW50IFZhbHVl" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "cmVhbF9mcmVxX291dA==::Ny4x::UmVhbCBPdXRwdXQgRnJlcXVlbmN5" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "d2FudF9mcmVxX21vZA==::ZmFsc2U=::RnJlcXVlbmN5IE1vZHVsYXRpb24gSW5wdXQ=" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "d2FudF9waGFzZV9tb2Q=::ZmFsc2U=::UGhhc2UgTW9kdWxhdGlvbiBJbnB1dA==" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "aHlwZXJfb3B0::ZmFsc2U=::aHlwZXJfb3B0" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_COMPONENT_PARAMETER "aHlwZXJfb3B0X3NlbGVjdA==::ZmFsc2U=::T3B0aW1pemUgZm9yIFN0cmF0aXggMTA=" - -set_global_assignment -library "tx_nco" -name VERILOG_FILE [file join $::quartus(qip_path) "tx_nco.v"] -set_global_assignment -library "tx_nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_nco_madx_cen.v"] -set_global_assignment -library "tx_nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_nco_mady_cen.v"] -set_global_assignment -library "tx_nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_nco_isdr.v"] -set_global_assignment -library "tx_nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_nco_mob_w.v"] -set_global_assignment -library "tx_nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_nco_as_m_dp_cen.v"] -set_global_assignment -library "tx_nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_nco_as_m_cen.v"] -set_global_assignment -library "tx_nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_altqmcpipe.v"] -set_global_assignment -library "tx_nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_gam_dp.v"] -set_global_assignment -library "tx_nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/asj_nco_derot.v"] -set_global_assignment -library "tx_nco" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/tx_nco_nco_ii_0_sin_c.hex"] -set_global_assignment -library "tx_nco" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/tx_nco_nco_ii_0_cos_c.hex"] -set_global_assignment -library "tx_nco" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/tx_nco_nco_ii_0_sin_f.hex"] -set_global_assignment -library "tx_nco" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/tx_nco_nco_ii_0_cos_f.hex"] -set_global_assignment -library "tx_nco" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/tx_nco_nco_ii_0.v"] -set_global_assignment -library "tx_nco" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/asj_altq.ocp"] -set_global_assignment -library "tx_nco" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/asj_altqmcash.ocp"] -set_global_assignment -library "tx_nco" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/asj_altqmcpipe.ocp"] - -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_TOOL_NAME "altera_nco_ii" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_TOOL_VERSION "18.1" -set_global_assignment -entity "tx_nco_nco_ii_0" -library "tx_nco" -name IP_TOOL_ENV "Qsys" diff --git a/FPGA_61.440/db/ip/tx_nco/tx_nco.v b/FPGA_61.440/db/ip/tx_nco/tx_nco.v deleted file mode 100644 index 65ad20e..0000000 --- a/FPGA_61.440/db/ip/tx_nco/tx_nco.v +++ /dev/null @@ -1,26 +0,0 @@ -// tx_nco.v - -// Generated using ACDS version 18.1 625 - -`timescale 1 ps / 1 ps -module tx_nco ( - input wire clk, // clk.clk - input wire clken, // in.clken - input wire [21:0] phi_inc_i, // .phi_inc_i - output wire [15:0] fsin_o, // out.fsin_o - output wire [15:0] fcos_o, // .fcos_o - output wire out_valid, // .out_valid - input wire reset_n // rst.reset_n - ); - - tx_nco_nco_ii_0 nco_ii_0 ( - .clk (clk), // clk.clk - .reset_n (reset_n), // rst.reset_n - .clken (clken), // in.clken - .phi_inc_i (phi_inc_i), // .phi_inc_i - .fsin_o (fsin_o), // out.fsin_o - .fcos_o (fcos_o), // .fcos_o - .out_valid (out_valid) // .out_valid - ); - -endmodule diff --git a/FPGA_61.440/db/ip/tx_nco/tx_nco__report.html b/FPGA_61.440/db/ip/tx_nco/tx_nco__report.html deleted file mode 100644 index 1f6221f..0000000 --- a/FPGA_61.440/db/ip/tx_nco/tx_nco__report.html +++ /dev/null @@ -1,241 +0,0 @@ - - - - - datasheet for tx_nco - - - - - - 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tx_nco -
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2021.03.31.22:15:54Datasheet
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Overview
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Memory Map
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nco_ii_0

altera_nco_ii v18.1 -
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Parameters

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
design_envNATIVE
archtrig
want_sin_and_cosdual_output
numch1
numba1
use_dedicated_multiplierstrue
selected_device_familyCYCLONEIVE
apr22
apri22
mpr16
cordic_archparallel
trig_cycles_per_output1
cycles_per_output1
want_ditherfalse
dpri4
fsamp153.6
freq_out7.1
phi_inc193877
real_freq_out7.1
want_freq_modfalse
aprf32
fmod_pipe1
want_phase_modfalse
aprp16
pmod_pipe1
hyper_optfalse
hyper_opt_selectfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
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Software Assignments

(none)
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generation took 0,01 secondsrendering took 0,04 seconds
- - diff --git a/FPGA_61.440/db/ip/tx_nco/tx_nco__report.xml b/FPGA_61.440/db/ip/tx_nco/tx_nco__report.xml deleted file mode 100644 index 101ab8c..0000000 --- a/FPGA_61.440/db/ip/tx_nco/tx_nco__report.xml +++ /dev/null @@ -1,313 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:tx_nco "tx_nco" - - - - Transform: CustomInstructionTransform - No custom instruction connections, skipping transform - 1 modules, 0 connections]]> - Transform: MMTransform - Transform: InterruptMapperTransform - Transform: InterruptSyncTransform - Transform: InterruptFanoutTransform - Transform: AvalonStreamingTransform - Transform: ResetAdaptation - tx_nco" reuses altera_nco_ii "submodules/tx_nco_nco_ii_0"]]> - queue size: 0 starting:altera_nco_ii "submodules/tx_nco_nco_ii_0" - tx_nco" instantiated altera_nco_ii "nco_ii_0"]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - queue size: 0 starting:altera_nco_ii "submodules/tx_nco_nco_ii_0" - tx_nco" instantiated altera_nco_ii "nco_ii_0"]]> - - - diff --git a/FPGA_61.440/db/lpm_constant_9k6.tdf b/FPGA_61.440/db/lpm_constant_9k6.tdf deleted file mode 100644 index af49d63..0000000 --- a/FPGA_61.440/db/lpm_constant_9k6.tdf +++ /dev/null @@ -1,30 +0,0 @@ ---lpm_constant ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=2000 LPM_WIDTH=14 result ---VERSION_BEGIN 18.1 cbx_lpm_constant 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - - ---synthesis_resources = -SUBDESIGN lpm_constant_9k6 -( - result[13..0] : output; -) - -BEGIN - result[] = B"10000000000000"; -END; ---VALID FILE diff --git a/FPGA_61.440/db/mult_36t.tdf b/FPGA_61.440/db/mult_36t.tdf deleted file mode 100644 index 369aa7f..0000000 --- a/FPGA_61.440/db/mult_36t.tdf +++ /dev/null @@ -1,58 +0,0 @@ ---lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" INPUT_A_IS_CONSTANT="NO" INPUT_B_IS_CONSTANT="NO" LPM_REPRESENTATION="SIGNED" LPM_WIDTHA=16 LPM_WIDTHB=16 LPM_WIDTHP=32 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_mult 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_padd 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb) -WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock) -RETURNS ( dataout[dataa_width+datab_width-1..0]); -FUNCTION cycloneive_mac_out (aclr, clk, dataa[dataa_width-1..0], ena) -WITH ( dataa_width = 0, output_clock) -RETURNS ( dataout[dataa_width-1..0]); - ---synthesis_resources = dsp_9bit 2 -SUBDESIGN mult_36t -( - dataa[15..0] : input; - datab[15..0] : input; - result[31..0] : output; -) -VARIABLE - mac_mult1 : cycloneive_mac_mult - WITH ( - dataa_clock = "none", - dataa_width = 16, - datab_clock = "none", - datab_width = 16, - signa_clock = "none", - signb_clock = "none" - ); - mac_out2 : cycloneive_mac_out - WITH ( - dataa_width = 32, - output_clock = "none" - ); - -BEGIN - mac_mult1.dataa[] = ( dataa[]); - mac_mult1.datab[] = ( datab[]); - mac_mult1.signa = B"1"; - mac_mult1.signb = B"1"; - mac_out2.dataa[] = mac_mult1.dataout[]; - result[31..0] = mac_out2.dataout[31..0]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/mult_abt.tdf b/FPGA_61.440/db/mult_abt.tdf deleted file mode 100644 index 0ae7d65..0000000 --- a/FPGA_61.440/db/mult_abt.tdf +++ /dev/null @@ -1,65 +0,0 @@ ---lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" LPM_PIPELINE=1 LPM_REPRESENTATION="SIGNED" LPM_WIDTHA=16 LPM_WIDTHB=16 LPM_WIDTHP=32 MAXIMIZE_SPEED=9 clken clock dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_mult 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_padd 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb) -WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock) -RETURNS ( dataout[dataa_width+datab_width-1..0]); -FUNCTION cycloneive_mac_out (aclr, clk, dataa[dataa_width-1..0], ena) -WITH ( dataa_width = 0, output_clock) -RETURNS ( dataout[dataa_width-1..0]); - ---synthesis_resources = dsp_9bit 2 -SUBDESIGN mult_abt -( - clken : input; - clock : input; - dataa[15..0] : input; - datab[15..0] : input; - result[31..0] : output; -) -VARIABLE - mac_mult1 : cycloneive_mac_mult - WITH ( - dataa_clock = "none", - dataa_width = 16, - datab_clock = "none", - datab_width = 16, - signa_clock = "none", - signb_clock = "none" - ); - mac_out2 : cycloneive_mac_out - WITH ( - dataa_width = 32, - output_clock = "0" - ); - aclr : NODE; - -BEGIN - mac_mult1.dataa[] = ( dataa[]); - mac_mult1.datab[] = ( datab[]); - mac_mult1.signa = B"1"; - mac_mult1.signb = B"1"; - mac_out2.aclr = aclr; - mac_out2.clk = clock; - mac_out2.dataa[] = mac_mult1.dataout[]; - mac_out2.ena = clken; - aclr = GND; - result[31..0] = mac_out2.dataout[31..0]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/mult_jnp.tdf b/FPGA_61.440/db/mult_jnp.tdf deleted file mode 100644 index 9ccc20a..0000000 --- a/FPGA_61.440/db/mult_jnp.tdf +++ /dev/null @@ -1,65 +0,0 @@ ---lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" LPM_PIPELINE=1 LPM_REPRESENTATION="SIGNED" LPM_WIDTHA=12 LPM_WIDTHB=12 LPM_WIDTHP=24 MAXIMIZE_SPEED=5 clken clock dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_mult 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_padd 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb) -WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock) -RETURNS ( dataout[dataa_width+datab_width-1..0]); -FUNCTION cycloneive_mac_out (aclr, clk, dataa[dataa_width-1..0], ena) -WITH ( dataa_width = 0, output_clock) -RETURNS ( dataout[dataa_width-1..0]); - ---synthesis_resources = dsp_9bit 2 -SUBDESIGN mult_jnp -( - clken : input; - clock : input; - dataa[11..0] : input; - datab[11..0] : input; - result[23..0] : output; -) -VARIABLE - mac_mult1 : cycloneive_mac_mult - WITH ( - dataa_clock = "none", - dataa_width = 12, - datab_clock = "none", - datab_width = 12, - signa_clock = "none", - signb_clock = "none" - ); - mac_out2 : cycloneive_mac_out - WITH ( - dataa_width = 24, - output_clock = "0" - ); - aclr : NODE; - -BEGIN - mac_mult1.dataa[] = ( dataa[]); - mac_mult1.datab[] = ( datab[]); - mac_mult1.signa = B"1"; - mac_mult1.signb = B"1"; - mac_out2.aclr = aclr; - mac_out2.clk = clock; - mac_out2.dataa[] = mac_mult1.dataout[]; - mac_out2.ena = clken; - aclr = GND; - result[23..0] = mac_out2.dataout[23..0]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/mult_lcu.tdf b/FPGA_61.440/db/mult_lcu.tdf deleted file mode 100644 index a05c744..0000000 --- a/FPGA_61.440/db/mult_lcu.tdf +++ /dev/null @@ -1,68 +0,0 @@ ---lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" LPM_PIPELINE=2 LPM_REPRESENTATION="SIGNED" LPM_WIDTHA=15 LPM_WIDTHB=8 LPM_WIDTHP=23 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 aclr clock dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_mult 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_padd 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb) -WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock) -RETURNS ( dataout[dataa_width+datab_width-1..0]); -FUNCTION cycloneive_mac_out (aclr, clk, dataa[dataa_width-1..0], ena) -WITH ( dataa_width = 0, output_clock) -RETURNS ( dataout[dataa_width-1..0]); - ---synthesis_resources = dsp_9bit 2 -SUBDESIGN mult_lcu -( - aclr : input; - clock : input; - dataa[14..0] : input; - datab[7..0] : input; - result[22..0] : output; -) -VARIABLE - mac_mult1 : cycloneive_mac_mult - WITH ( - dataa_clock = "0", - dataa_width = 15, - datab_clock = "0", - datab_width = 8, - signa_clock = "none", - signb_clock = "none" - ); - mac_out2 : cycloneive_mac_out - WITH ( - dataa_width = 23, - output_clock = "0" - ); - clken : NODE; - -BEGIN - mac_mult1.aclr = aclr; - mac_mult1.clk = clock; - mac_mult1.dataa[] = ( dataa[]); - mac_mult1.datab[] = ( datab[]); - mac_mult1.ena = clken; - mac_mult1.signa = B"1"; - mac_mult1.signb = B"1"; - mac_out2.aclr = aclr; - mac_out2.clk = clock; - mac_out2.dataa[] = mac_mult1.dataout[]; - mac_out2.ena = clken; - clken = VCC; - result[22..0] = mac_out2.dataout[22..0]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/mult_ncu.tdf b/FPGA_61.440/db/mult_ncu.tdf deleted file mode 100644 index 1d78a37..0000000 --- a/FPGA_61.440/db/mult_ncu.tdf +++ /dev/null @@ -1,68 +0,0 @@ ---lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" LPM_PIPELINE=2 LPM_REPRESENTATION="SIGNED" LPM_WIDTHA=8 LPM_WIDTHB=16 LPM_WIDTHP=24 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 aclr clock dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_mult 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_padd 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb) -WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock) -RETURNS ( dataout[dataa_width+datab_width-1..0]); -FUNCTION cycloneive_mac_out (aclr, clk, dataa[dataa_width-1..0], ena) -WITH ( dataa_width = 0, output_clock) -RETURNS ( dataout[dataa_width-1..0]); - ---synthesis_resources = dsp_9bit 2 -SUBDESIGN mult_ncu -( - aclr : input; - clock : input; - dataa[7..0] : input; - datab[15..0] : input; - result[23..0] : output; -) -VARIABLE - mac_mult1 : cycloneive_mac_mult - WITH ( - dataa_clock = "0", - dataa_width = 8, - datab_clock = "0", - datab_width = 16, - signa_clock = "none", - signb_clock = "none" - ); - mac_out2 : cycloneive_mac_out - WITH ( - dataa_width = 24, - output_clock = "0" - ); - clken : NODE; - -BEGIN - mac_mult1.aclr = aclr; - mac_mult1.clk = clock; - mac_mult1.dataa[] = ( dataa[]); - mac_mult1.datab[] = ( datab[]); - mac_mult1.ena = clken; - mac_mult1.signa = B"1"; - mac_mult1.signb = B"1"; - mac_out2.aclr = aclr; - mac_out2.clk = clock; - mac_out2.dataa[] = mac_mult1.dataout[]; - mac_out2.ena = clken; - clken = VCC; - result[23..0] = mac_out2.dataout[23..0]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/mult_rcu.tdf b/FPGA_61.440/db/mult_rcu.tdf deleted file mode 100644 index a730cf5..0000000 --- a/FPGA_61.440/db/mult_rcu.tdf +++ /dev/null @@ -1,68 +0,0 @@ ---lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" LPM_PIPELINE=2 LPM_REPRESENTATION="SIGNED" LPM_WIDTHA=18 LPM_WIDTHB=8 LPM_WIDTHP=26 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 aclr clock dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_mult 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_padd 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb) -WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock) -RETURNS ( dataout[dataa_width+datab_width-1..0]); -FUNCTION cycloneive_mac_out (aclr, clk, dataa[dataa_width-1..0], ena) -WITH ( dataa_width = 0, output_clock) -RETURNS ( dataout[dataa_width-1..0]); - ---synthesis_resources = dsp_9bit 2 -SUBDESIGN mult_rcu -( - aclr : input; - clock : input; - dataa[17..0] : input; - datab[7..0] : input; - result[25..0] : output; -) -VARIABLE - mac_mult1 : cycloneive_mac_mult - WITH ( - dataa_clock = "0", - dataa_width = 18, - datab_clock = "0", - datab_width = 8, - signa_clock = "none", - signb_clock = "none" - ); - mac_out2 : cycloneive_mac_out - WITH ( - dataa_width = 26, - output_clock = "0" - ); - clken : NODE; - -BEGIN - mac_mult1.aclr = aclr; - mac_mult1.clk = clock; - mac_mult1.dataa[] = ( dataa[]); - mac_mult1.datab[] = ( datab[]); - mac_mult1.ena = clken; - mac_mult1.signa = B"1"; - mac_mult1.signb = B"1"; - mac_out2.aclr = aclr; - mac_out2.clk = clock; - mac_out2.dataa[] = mac_mult1.dataout[]; - mac_out2.ena = clken; - clken = VCC; - result[25..0] = mac_out2.dataout[25..0]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/mult_t5t.tdf b/FPGA_61.440/db/mult_t5t.tdf deleted file mode 100644 index a6d402f..0000000 --- a/FPGA_61.440/db/mult_t5t.tdf +++ /dev/null @@ -1,58 +0,0 @@ ---lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" INPUT_A_IS_CONSTANT="NO" INPUT_B_IS_CONSTANT="NO" LPM_REPRESENTATION="SIGNED" LPM_WIDTHA=12 LPM_WIDTHB=12 LPM_WIDTHP=24 LPM_WIDTHS=1 MAXIMIZE_SPEED=6 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_mult 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_padd 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION cycloneive_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb) -WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock) -RETURNS ( dataout[dataa_width+datab_width-1..0]); -FUNCTION cycloneive_mac_out (aclr, clk, dataa[dataa_width-1..0], ena) -WITH ( dataa_width = 0, output_clock) -RETURNS ( dataout[dataa_width-1..0]); - ---synthesis_resources = dsp_9bit 2 -SUBDESIGN mult_t5t -( - dataa[11..0] : input; - datab[11..0] : input; - result[23..0] : output; -) -VARIABLE - mac_mult1 : cycloneive_mac_mult - WITH ( - dataa_clock = "none", - dataa_width = 12, - datab_clock = "none", - datab_width = 12, - signa_clock = "none", - signb_clock = "none" - ); - mac_out2 : cycloneive_mac_out - WITH ( - dataa_width = 24, - output_clock = "none" - ); - -BEGIN - mac_mult1.dataa[] = ( dataa[]); - mac_mult1.datab[] = ( datab[]); - mac_mult1.signa = B"1"; - mac_mult1.signb = B"1"; - mac_out2.dataa[] = mac_mult1.dataout[]; - result[23..0] = mac_out2.dataout[23..0]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/mux_rob.tdf b/FPGA_61.440/db/mux_rob.tdf deleted file mode 100644 index de8d90e..0000000 --- a/FPGA_61.440/db/mux_rob.tdf +++ /dev/null @@ -1,207 +0,0 @@ ---lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_SIZE=4 LPM_WIDTH=85 LPM_WIDTHS=2 data result sel ---VERSION_BEGIN 18.1 cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - - ---synthesis_resources = lut 170 -SUBDESIGN mux_rob -( - data[339..0] : input; - result[84..0] : output; - sel[1..0] : input; -) -VARIABLE - result_node[84..0] : WIRE; - sel_node[1..0] : WIRE; - w_data1002w[3..0] : WIRE; - w_data1027w[3..0] : WIRE; - w_data102w[3..0] : WIRE; - w_data1052w[3..0] : WIRE; - w_data1077w[3..0] : WIRE; - w_data1102w[3..0] : WIRE; - w_data1127w[3..0] : WIRE; - w_data1152w[3..0] : WIRE; - w_data1177w[3..0] : WIRE; - w_data1202w[3..0] : WIRE; - w_data1227w[3..0] : WIRE; - w_data1252w[3..0] : WIRE; - w_data1277w[3..0] : WIRE; - w_data127w[3..0] : WIRE; - w_data1302w[3..0] : WIRE; - w_data1327w[3..0] : WIRE; - w_data1352w[3..0] : WIRE; - w_data1377w[3..0] : WIRE; - w_data1402w[3..0] : WIRE; - w_data1427w[3..0] : WIRE; - w_data1452w[3..0] : WIRE; - w_data1477w[3..0] : WIRE; - w_data1502w[3..0] : WIRE; - w_data1527w[3..0] : WIRE; - w_data152w[3..0] : WIRE; - w_data1552w[3..0] : WIRE; - w_data1577w[3..0] : WIRE; - w_data1602w[3..0] : WIRE; - w_data1627w[3..0] : WIRE; - w_data1652w[3..0] : WIRE; - w_data1677w[3..0] : WIRE; - w_data1702w[3..0] : WIRE; - w_data1727w[3..0] : WIRE; - w_data1752w[3..0] : WIRE; - w_data1777w[3..0] : WIRE; - w_data177w[3..0] : WIRE; - w_data1802w[3..0] : WIRE; - w_data1827w[3..0] : WIRE; - w_data1852w[3..0] : WIRE; - w_data1877w[3..0] : WIRE; - w_data1902w[3..0] : WIRE; - w_data1927w[3..0] : WIRE; - w_data1952w[3..0] : WIRE; - w_data1977w[3..0] : WIRE; - w_data2002w[3..0] : WIRE; - w_data2027w[3..0] : WIRE; - w_data202w[3..0] : WIRE; - w_data2052w[3..0] : WIRE; - w_data2077w[3..0] : WIRE; - w_data2102w[3..0] : WIRE; - w_data2127w[3..0] : WIRE; - w_data227w[3..0] : WIRE; - w_data22w[3..0] : WIRE; - w_data252w[3..0] : WIRE; - w_data277w[3..0] : WIRE; - w_data302w[3..0] : WIRE; - w_data327w[3..0] : WIRE; - w_data352w[3..0] : WIRE; - w_data377w[3..0] : WIRE; - w_data402w[3..0] : WIRE; - w_data427w[3..0] : WIRE; - w_data452w[3..0] : WIRE; - w_data477w[3..0] : WIRE; - w_data502w[3..0] : WIRE; - w_data527w[3..0] : WIRE; - w_data52w[3..0] : WIRE; - w_data552w[3..0] : WIRE; - w_data577w[3..0] : WIRE; - w_data602w[3..0] : WIRE; - w_data627w[3..0] : WIRE; - w_data652w[3..0] : WIRE; - w_data677w[3..0] : WIRE; - w_data702w[3..0] : WIRE; - w_data727w[3..0] : WIRE; - w_data752w[3..0] : WIRE; - w_data777w[3..0] : WIRE; - w_data77w[3..0] : WIRE; - w_data802w[3..0] : WIRE; - w_data827w[3..0] : WIRE; - w_data852w[3..0] : WIRE; - w_data877w[3..0] : WIRE; - w_data902w[3..0] : WIRE; - w_data927w[3..0] : WIRE; - w_data952w[3..0] : WIRE; - w_data977w[3..0] : WIRE; - -BEGIN - result[] = result_node[]; - result_node[] = ( (((w_data2127w[1..1] & sel_node[0..0]) & (! (((w_data2127w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2127w[2..2]))))) # ((((w_data2127w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2127w[2..2]))) & (w_data2127w[3..3] # (! sel_node[0..0])))), (((w_data2102w[1..1] & sel_node[0..0]) & (! (((w_data2102w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2102w[2..2]))))) # ((((w_data2102w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2102w[2..2]))) & (w_data2102w[3..3] # (! sel_node[0..0])))), (((w_data2077w[1..1] & sel_node[0..0]) & (! (((w_data2077w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2077w[2..2]))))) # ((((w_data2077w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2077w[2..2]))) & (w_data2077w[3..3] # (! sel_node[0..0])))), (((w_data2052w[1..1] & sel_node[0..0]) & (! (((w_data2052w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2052w[2..2]))))) # ((((w_data2052w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2052w[2..2]))) & (w_data2052w[3..3] # (! sel_node[0..0])))), (((w_data2027w[1..1] & sel_node[0..0]) & (! (((w_data2027w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2027w[2..2]))))) # ((((w_data2027w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2027w[2..2]))) & (w_data2027w[3..3] # (! sel_node[0..0])))), (((w_data2002w[1..1] & sel_node[0..0]) & (! (((w_data2002w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2002w[2..2]))))) # ((((w_data2002w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2002w[2..2]))) & (w_data2002w[3..3] # (! sel_node[0..0])))), (((w_data1977w[1..1] & sel_node[0..0]) & (! (((w_data1977w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1977w[2..2]))))) # ((((w_data1977w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1977w[2..2]))) & (w_data1977w[3..3] # (! sel_node[0..0])))), (((w_data1952w[1..1] & sel_node[0..0]) & (! (((w_data1952w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1952w[2..2]))))) # ((((w_data1952w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1952w[2..2]))) & (w_data1952w[3..3] # (! sel_node[0..0])))), (((w_data1927w[1..1] & sel_node[0..0]) & (! (((w_data1927w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1927w[2..2]))))) # ((((w_data1927w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1927w[2..2]))) & (w_data1927w[3..3] # (! sel_node[0..0])))), (((w_data1902w[1..1] & sel_node[0..0]) & (! (((w_data1902w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1902w[2..2]))))) # ((((w_data1902w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1902w[2..2]))) & (w_data1902w[3..3] # (! sel_node[0..0])))), (((w_data1877w[1..1] & sel_node[0..0]) & (! (((w_data1877w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1877w[2..2]))))) # ((((w_data1877w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1877w[2..2]))) & (w_data1877w[3..3] # (! sel_node[0..0])))), (((w_data1852w[1..1] & sel_node[0..0]) & (! (((w_data1852w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1852w[2..2]))))) # ((((w_data1852w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1852w[2..2]))) & (w_data1852w[3..3] # (! sel_node[0..0])))), (((w_data1827w[1..1] & sel_node[0..0]) & (! (((w_data1827w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1827w[2..2]))))) # ((((w_data1827w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1827w[2..2]))) & (w_data1827w[3..3] # (! sel_node[0..0])))), (((w_data1802w[1..1] & sel_node[0..0]) & (! (((w_data1802w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1802w[2..2]))))) # ((((w_data1802w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1802w[2..2]))) & (w_data1802w[3..3] # (! sel_node[0..0])))), (((w_data1777w[1..1] & sel_node[0..0]) & (! (((w_data1777w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1777w[2..2]))))) # ((((w_data1777w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1777w[2..2]))) & (w_data1777w[3..3] # (! sel_node[0..0])))), (((w_data1752w[1..1] & sel_node[0..0]) & (! (((w_data1752w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1752w[2..2]))))) # ((((w_data1752w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1752w[2..2]))) & (w_data1752w[3..3] # (! sel_node[0..0])))), (((w_data1727w[1..1] & sel_node[0..0]) & (! (((w_data1727w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1727w[2..2]))))) # ((((w_data1727w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1727w[2..2]))) & (w_data1727w[3..3] # (! sel_node[0..0])))), (((w_data1702w[1..1] & sel_node[0..0]) & (! (((w_data1702w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1702w[2..2]))))) # ((((w_data1702w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1702w[2..2]))) & (w_data1702w[3..3] # (! sel_node[0..0])))), (((w_data1677w[1..1] & sel_node[0..0]) & (! (((w_data1677w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1677w[2..2]))))) # ((((w_data1677w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1677w[2..2]))) & (w_data1677w[3..3] # (! sel_node[0..0])))), (((w_data1652w[1..1] & sel_node[0..0]) & (! (((w_data1652w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1652w[2..2]))))) # ((((w_data1652w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1652w[2..2]))) & (w_data1652w[3..3] # (! sel_node[0..0])))), (((w_data1627w[1..1] & sel_node[0..0]) & (! (((w_data1627w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1627w[2..2]))))) # ((((w_data1627w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1627w[2..2]))) & (w_data1627w[3..3] # (! sel_node[0..0])))), (((w_data1602w[1..1] & sel_node[0..0]) & (! (((w_data1602w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1602w[2..2]))))) # ((((w_data1602w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1602w[2..2]))) & (w_data1602w[3..3] # (! sel_node[0..0])))), (((w_data1577w[1..1] & sel_node[0..0]) & (! (((w_data1577w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1577w[2..2]))))) # ((((w_data1577w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1577w[2..2]))) & (w_data1577w[3..3] # (! sel_node[0..0])))), (((w_data1552w[1..1] & sel_node[0..0]) & (! (((w_data1552w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1552w[2..2]))))) # ((((w_data1552w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1552w[2..2]))) & (w_data1552w[3..3] # (! sel_node[0..0])))), (((w_data1527w[1..1] & sel_node[0..0]) & (! (((w_data1527w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1527w[2..2]))))) # ((((w_data1527w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1527w[2..2]))) & (w_data1527w[3..3] # (! sel_node[0..0])))), (((w_data1502w[1..1] & sel_node[0..0]) & (! (((w_data1502w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1502w[2..2]))))) # ((((w_data1502w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1502w[2..2]))) & (w_data1502w[3..3] # (! sel_node[0..0])))), (((w_data1477w[1..1] & sel_node[0..0]) & (! (((w_data1477w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1477w[2..2]))))) # ((((w_data1477w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1477w[2..2]))) & (w_data1477w[3..3] # (! sel_node[0..0])))), (((w_data1452w[1..1] & sel_node[0..0]) & (! (((w_data1452w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1452w[2..2]))))) # ((((w_data1452w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1452w[2..2]))) & (w_data1452w[3..3] # (! sel_node[0..0])))), (((w_data1427w[1..1] & sel_node[0..0]) & (! (((w_data1427w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1427w[2..2]))))) # ((((w_data1427w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1427w[2..2]))) & (w_data1427w[3..3] # (! sel_node[0..0])))), (((w_data1402w[1..1] & sel_node[0..0]) & (! (((w_data1402w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1402w[2..2]))))) # ((((w_data1402w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1402w[2..2]))) & (w_data1402w[3..3] # (! sel_node[0..0])))), (((w_data1377w[1..1] & sel_node[0..0]) & (! (((w_data1377w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1377w[2..2]))))) # ((((w_data1377w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1377w[2..2]))) & (w_data1377w[3..3] # (! sel_node[0..0])))), (((w_data1352w[1..1] & sel_node[0..0]) & (! (((w_data1352w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1352w[2..2]))))) # ((((w_data1352w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1352w[2..2]))) & (w_data1352w[3..3] # (! sel_node[0..0])))), (((w_data1327w[1..1] & sel_node[0..0]) & (! (((w_data1327w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1327w[2..2]))))) # ((((w_data1327w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1327w[2..2]))) & (w_data1327w[3..3] # (! sel_node[0..0])))), (((w_data1302w[1..1] & sel_node[0..0]) & (! (((w_data1302w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1302w[2..2]))))) # ((((w_data1302w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1302w[2..2]))) & (w_data1302w[3..3] # (! sel_node[0..0])))), (((w_data1277w[1..1] & sel_node[0..0]) & (! (((w_data1277w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1277w[2..2]))))) # ((((w_data1277w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1277w[2..2]))) & (w_data1277w[3..3] # (! sel_node[0..0])))), (((w_data1252w[1..1] & sel_node[0..0]) & (! (((w_data1252w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1252w[2..2]))))) # ((((w_data1252w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1252w[2..2]))) & (w_data1252w[3..3] # (! sel_node[0..0])))), (((w_data1227w[1..1] & sel_node[0..0]) & (! (((w_data1227w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1227w[2..2]))))) # ((((w_data1227w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1227w[2..2]))) & (w_data1227w[3..3] # (! sel_node[0..0])))), (((w_data1202w[1..1] & sel_node[0..0]) & (! (((w_data1202w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1202w[2..2]))))) # ((((w_data1202w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1202w[2..2]))) & (w_data1202w[3..3] # (! sel_node[0..0])))), (((w_data1177w[1..1] & sel_node[0..0]) & (! (((w_data1177w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1177w[2..2]))))) # ((((w_data1177w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1177w[2..2]))) & (w_data1177w[3..3] # (! sel_node[0..0])))), (((w_data1152w[1..1] & sel_node[0..0]) & (! (((w_data1152w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1152w[2..2]))))) # ((((w_data1152w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1152w[2..2]))) & (w_data1152w[3..3] # (! sel_node[0..0])))), (((w_data1127w[1..1] & sel_node[0..0]) & (! (((w_data1127w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1127w[2..2]))))) # ((((w_data1127w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1127w[2..2]))) & (w_data1127w[3..3] # (! sel_node[0..0])))), (((w_data1102w[1..1] & sel_node[0..0]) & (! (((w_data1102w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1102w[2..2]))))) # ((((w_data1102w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1102w[2..2]))) & (w_data1102w[3..3] # (! sel_node[0..0])))), (((w_data1077w[1..1] & sel_node[0..0]) & (! (((w_data1077w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1077w[2..2]))))) # ((((w_data1077w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1077w[2..2]))) & (w_data1077w[3..3] # (! sel_node[0..0])))), (((w_data1052w[1..1] & sel_node[0..0]) & (! (((w_data1052w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1052w[2..2]))))) # ((((w_data1052w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1052w[2..2]))) & (w_data1052w[3..3] # (! sel_node[0..0])))), (((w_data1027w[1..1] & sel_node[0..0]) & (! (((w_data1027w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1027w[2..2]))))) # ((((w_data1027w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1027w[2..2]))) & (w_data1027w[3..3] # (! sel_node[0..0])))), (((w_data1002w[1..1] & sel_node[0..0]) & (! (((w_data1002w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1002w[2..2]))))) # ((((w_data1002w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1002w[2..2]))) & (w_data1002w[3..3] # (! sel_node[0..0])))), (((w_data977w[1..1] & sel_node[0..0]) & (! (((w_data977w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data977w[2..2]))))) # ((((w_data977w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data977w[2..2]))) & (w_data977w[3..3] # (! sel_node[0..0])))), (((w_data952w[1..1] & sel_node[0..0]) & (! (((w_data952w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data952w[2..2]))))) # ((((w_data952w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data952w[2..2]))) & (w_data952w[3..3] # (! sel_node[0..0])))), (((w_data927w[1..1] & sel_node[0..0]) & (! (((w_data927w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data927w[2..2]))))) # ((((w_data927w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data927w[2..2]))) & (w_data927w[3..3] # (! sel_node[0..0])))), (((w_data902w[1..1] & sel_node[0..0]) & (! (((w_data902w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data902w[2..2]))))) # ((((w_data902w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data902w[2..2]))) & (w_data902w[3..3] # (! sel_node[0..0])))), (((w_data877w[1..1] & sel_node[0..0]) & (! (((w_data877w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data877w[2..2]))))) # ((((w_data877w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data877w[2..2]))) & (w_data877w[3..3] # (! sel_node[0..0])))), (((w_data852w[1..1] & sel_node[0..0]) & (! (((w_data852w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data852w[2..2]))))) # ((((w_data852w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data852w[2..2]))) & (w_data852w[3..3] # (! sel_node[0..0])))), (((w_data827w[1..1] & sel_node[0..0]) & (! (((w_data827w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data827w[2..2]))))) # ((((w_data827w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data827w[2..2]))) & (w_data827w[3..3] # (! sel_node[0..0])))), (((w_data802w[1..1] & sel_node[0..0]) & (! (((w_data802w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data802w[2..2]))))) # ((((w_data802w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data802w[2..2]))) & (w_data802w[3..3] # (! sel_node[0..0])))), (((w_data777w[1..1] & sel_node[0..0]) & (! (((w_data777w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data777w[2..2]))))) # ((((w_data777w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data777w[2..2]))) & (w_data777w[3..3] # (! sel_node[0..0])))), (((w_data752w[1..1] & sel_node[0..0]) & (! (((w_data752w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data752w[2..2]))))) # ((((w_data752w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data752w[2..2]))) & (w_data752w[3..3] # (! sel_node[0..0])))), (((w_data727w[1..1] & sel_node[0..0]) & (! (((w_data727w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data727w[2..2]))))) # ((((w_data727w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data727w[2..2]))) & (w_data727w[3..3] # (! sel_node[0..0])))), (((w_data702w[1..1] & sel_node[0..0]) & (! (((w_data702w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data702w[2..2]))))) # ((((w_data702w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data702w[2..2]))) & (w_data702w[3..3] # (! sel_node[0..0])))), (((w_data677w[1..1] & sel_node[0..0]) & (! (((w_data677w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data677w[2..2]))))) # ((((w_data677w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data677w[2..2]))) & (w_data677w[3..3] # (! sel_node[0..0])))), (((w_data652w[1..1] & sel_node[0..0]) & (! (((w_data652w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data652w[2..2]))))) # ((((w_data652w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data652w[2..2]))) & (w_data652w[3..3] # (! sel_node[0..0])))), (((w_data627w[1..1] & sel_node[0..0]) & (! (((w_data627w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data627w[2..2]))))) # ((((w_data627w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data627w[2..2]))) & (w_data627w[3..3] # (! sel_node[0..0])))), (((w_data602w[1..1] & sel_node[0..0]) & (! (((w_data602w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data602w[2..2]))))) # ((((w_data602w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data602w[2..2]))) & (w_data602w[3..3] # (! sel_node[0..0])))), (((w_data577w[1..1] & sel_node[0..0]) & (! (((w_data577w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data577w[2..2]))))) # ((((w_data577w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data577w[2..2]))) & (w_data577w[3..3] # (! sel_node[0..0])))), (((w_data552w[1..1] & sel_node[0..0]) & (! (((w_data552w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data552w[2..2]))))) # ((((w_data552w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data552w[2..2]))) & (w_data552w[3..3] # (! sel_node[0..0])))), (((w_data527w[1..1] & sel_node[0..0]) & (! (((w_data527w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data527w[2..2]))))) # ((((w_data527w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data527w[2..2]))) & (w_data527w[3..3] # (! sel_node[0..0])))), (((w_data502w[1..1] & sel_node[0..0]) & (! (((w_data502w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data502w[2..2]))))) # ((((w_data502w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data502w[2..2]))) & (w_data502w[3..3] # (! sel_node[0..0])))), (((w_data477w[1..1] & sel_node[0..0]) & (! (((w_data477w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data477w[2..2]))))) # ((((w_data477w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data477w[2..2]))) & (w_data477w[3..3] # (! sel_node[0..0])))), (((w_data452w[1..1] & sel_node[0..0]) & (! (((w_data452w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data452w[2..2]))))) # ((((w_data452w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data452w[2..2]))) & (w_data452w[3..3] # (! sel_node[0..0])))), (((w_data427w[1..1] & sel_node[0..0]) & (! (((w_data427w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data427w[2..2]))))) # ((((w_data427w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data427w[2..2]))) & (w_data427w[3..3] # (! sel_node[0..0])))), (((w_data402w[1..1] & sel_node[0..0]) & (! (((w_data402w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data402w[2..2]))))) # ((((w_data402w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data402w[2..2]))) & (w_data402w[3..3] # (! sel_node[0..0])))), (((w_data377w[1..1] & sel_node[0..0]) & (! (((w_data377w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data377w[2..2]))))) # ((((w_data377w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data377w[2..2]))) & (w_data377w[3..3] # (! sel_node[0..0])))), (((w_data352w[1..1] & sel_node[0..0]) & (! (((w_data352w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data352w[2..2]))))) # ((((w_data352w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data352w[2..2]))) & (w_data352w[3..3] # (! sel_node[0..0])))), (((w_data327w[1..1] & sel_node[0..0]) & (! (((w_data327w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data327w[2..2]))))) # ((((w_data327w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data327w[2..2]))) & (w_data327w[3..3] # (! sel_node[0..0])))), (((w_data302w[1..1] & sel_node[0..0]) & (! (((w_data302w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data302w[2..2]))))) # ((((w_data302w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data302w[2..2]))) & (w_data302w[3..3] # (! sel_node[0..0])))), (((w_data277w[1..1] & sel_node[0..0]) & (! (((w_data277w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data277w[2..2]))))) # ((((w_data277w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data277w[2..2]))) & (w_data277w[3..3] # (! sel_node[0..0])))), (((w_data252w[1..1] & sel_node[0..0]) & (! (((w_data252w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data252w[2..2]))))) # ((((w_data252w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data252w[2..2]))) & (w_data252w[3..3] # (! sel_node[0..0])))), (((w_data227w[1..1] & sel_node[0..0]) & (! (((w_data227w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data227w[2..2]))))) # ((((w_data227w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data227w[2..2]))) & (w_data227w[3..3] # (! sel_node[0..0])))), (((w_data202w[1..1] & sel_node[0..0]) & (! (((w_data202w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data202w[2..2]))))) # ((((w_data202w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data202w[2..2]))) & (w_data202w[3..3] # (! sel_node[0..0])))), (((w_data177w[1..1] & sel_node[0..0]) & (! (((w_data177w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data177w[2..2]))))) # ((((w_data177w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data177w[2..2]))) & (w_data177w[3..3] # (! sel_node[0..0])))), (((w_data152w[1..1] & sel_node[0..0]) & (! (((w_data152w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data152w[2..2]))))) # ((((w_data152w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data152w[2..2]))) & (w_data152w[3..3] # (! sel_node[0..0])))), (((w_data127w[1..1] & sel_node[0..0]) & (! (((w_data127w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data127w[2..2]))))) # ((((w_data127w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data127w[2..2]))) & (w_data127w[3..3] # (! sel_node[0..0])))), (((w_data102w[1..1] & sel_node[0..0]) & (! (((w_data102w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data102w[2..2]))))) # ((((w_data102w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data102w[2..2]))) & (w_data102w[3..3] # (! sel_node[0..0])))), (((w_data77w[1..1] & sel_node[0..0]) & (! (((w_data77w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data77w[2..2]))))) # ((((w_data77w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data77w[2..2]))) & (w_data77w[3..3] # (! sel_node[0..0])))), (((w_data52w[1..1] & sel_node[0..0]) & (! (((w_data52w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data52w[2..2]))))) # ((((w_data52w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data52w[2..2]))) & (w_data52w[3..3] # (! sel_node[0..0])))), (((w_data22w[1..1] & sel_node[0..0]) & (! (((w_data22w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data22w[2..2]))))) # ((((w_data22w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data22w[2..2]))) & (w_data22w[3..3] # (! sel_node[0..0]))))); - sel_node[] = ( sel[1..0]); - w_data1002w[] = ( data[294..294], data[209..209], data[124..124], data[39..39]); - w_data1027w[] = ( data[295..295], data[210..210], data[125..125], data[40..40]); - w_data102w[] = ( data[258..258], data[173..173], data[88..88], data[3..3]); - w_data1052w[] = ( data[296..296], data[211..211], data[126..126], data[41..41]); - w_data1077w[] = ( data[297..297], data[212..212], data[127..127], data[42..42]); - w_data1102w[] = ( data[298..298], data[213..213], data[128..128], data[43..43]); - w_data1127w[] = ( data[299..299], data[214..214], data[129..129], data[44..44]); - w_data1152w[] = ( data[300..300], data[215..215], data[130..130], data[45..45]); - w_data1177w[] = ( data[301..301], data[216..216], data[131..131], data[46..46]); - w_data1202w[] = ( data[302..302], data[217..217], data[132..132], data[47..47]); - w_data1227w[] = ( data[303..303], data[218..218], data[133..133], data[48..48]); - w_data1252w[] = ( data[304..304], data[219..219], data[134..134], data[49..49]); - w_data1277w[] = ( data[305..305], data[220..220], data[135..135], data[50..50]); - w_data127w[] = ( data[259..259], data[174..174], data[89..89], data[4..4]); - w_data1302w[] = ( data[306..306], data[221..221], data[136..136], data[51..51]); - w_data1327w[] = ( data[307..307], data[222..222], data[137..137], data[52..52]); - w_data1352w[] = ( data[308..308], data[223..223], data[138..138], data[53..53]); - w_data1377w[] = ( data[309..309], data[224..224], data[139..139], data[54..54]); - w_data1402w[] = ( data[310..310], data[225..225], data[140..140], data[55..55]); - w_data1427w[] = ( data[311..311], data[226..226], data[141..141], data[56..56]); - w_data1452w[] = ( data[312..312], data[227..227], data[142..142], data[57..57]); - w_data1477w[] = ( data[313..313], data[228..228], data[143..143], data[58..58]); - w_data1502w[] = ( data[314..314], data[229..229], data[144..144], data[59..59]); - w_data1527w[] = ( data[315..315], data[230..230], data[145..145], data[60..60]); - w_data152w[] = ( data[260..260], data[175..175], data[90..90], data[5..5]); - w_data1552w[] = ( data[316..316], data[231..231], data[146..146], data[61..61]); - w_data1577w[] = ( data[317..317], data[232..232], data[147..147], data[62..62]); - w_data1602w[] = ( data[318..318], data[233..233], data[148..148], data[63..63]); - w_data1627w[] = ( data[319..319], data[234..234], data[149..149], data[64..64]); - w_data1652w[] = ( data[320..320], data[235..235], data[150..150], data[65..65]); - w_data1677w[] = ( data[321..321], data[236..236], data[151..151], data[66..66]); - w_data1702w[] = ( data[322..322], data[237..237], data[152..152], data[67..67]); - w_data1727w[] = ( data[323..323], data[238..238], data[153..153], data[68..68]); - w_data1752w[] = ( data[324..324], data[239..239], data[154..154], data[69..69]); - w_data1777w[] = ( data[325..325], data[240..240], data[155..155], data[70..70]); - w_data177w[] = ( data[261..261], data[176..176], data[91..91], data[6..6]); - w_data1802w[] = ( data[326..326], data[241..241], data[156..156], data[71..71]); - w_data1827w[] = ( data[327..327], data[242..242], data[157..157], data[72..72]); - w_data1852w[] = ( data[328..328], data[243..243], data[158..158], data[73..73]); - w_data1877w[] = ( data[329..329], data[244..244], data[159..159], data[74..74]); - w_data1902w[] = ( data[330..330], data[245..245], data[160..160], data[75..75]); - w_data1927w[] = ( data[331..331], data[246..246], data[161..161], data[76..76]); - w_data1952w[] = ( data[332..332], data[247..247], data[162..162], data[77..77]); - w_data1977w[] = ( data[333..333], data[248..248], data[163..163], data[78..78]); - w_data2002w[] = ( data[334..334], data[249..249], data[164..164], data[79..79]); - w_data2027w[] = ( data[335..335], data[250..250], data[165..165], data[80..80]); - w_data202w[] = ( data[262..262], data[177..177], data[92..92], data[7..7]); - w_data2052w[] = ( data[336..336], data[251..251], data[166..166], data[81..81]); - w_data2077w[] = ( data[337..337], data[252..252], data[167..167], data[82..82]); - w_data2102w[] = ( data[338..338], data[253..253], data[168..168], data[83..83]); - w_data2127w[] = ( data[339..339], data[254..254], data[169..169], data[84..84]); - w_data227w[] = ( data[263..263], data[178..178], data[93..93], data[8..8]); - w_data22w[] = ( data[255..255], data[170..170], data[85..85], data[0..0]); - w_data252w[] = ( data[264..264], data[179..179], data[94..94], data[9..9]); - w_data277w[] = ( data[265..265], data[180..180], data[95..95], data[10..10]); - w_data302w[] = ( data[266..266], data[181..181], data[96..96], data[11..11]); - w_data327w[] = ( data[267..267], data[182..182], data[97..97], data[12..12]); - w_data352w[] = ( data[268..268], data[183..183], data[98..98], data[13..13]); - w_data377w[] = ( data[269..269], data[184..184], data[99..99], data[14..14]); - w_data402w[] = ( data[270..270], data[185..185], data[100..100], data[15..15]); - w_data427w[] = ( data[271..271], data[186..186], data[101..101], data[16..16]); - w_data452w[] = ( data[272..272], data[187..187], data[102..102], data[17..17]); - w_data477w[] = ( data[273..273], data[188..188], data[103..103], data[18..18]); - w_data502w[] = ( data[274..274], data[189..189], data[104..104], data[19..19]); - w_data527w[] = ( data[275..275], data[190..190], data[105..105], data[20..20]); - w_data52w[] = ( data[256..256], data[171..171], data[86..86], data[1..1]); - w_data552w[] = ( data[276..276], data[191..191], data[106..106], data[21..21]); - w_data577w[] = ( data[277..277], data[192..192], data[107..107], data[22..22]); - w_data602w[] = ( data[278..278], data[193..193], data[108..108], data[23..23]); - w_data627w[] = ( data[279..279], data[194..194], data[109..109], data[24..24]); - w_data652w[] = ( data[280..280], data[195..195], data[110..110], data[25..25]); - w_data677w[] = ( data[281..281], data[196..196], data[111..111], data[26..26]); - w_data702w[] = ( data[282..282], data[197..197], data[112..112], data[27..27]); - w_data727w[] = ( data[283..283], data[198..198], data[113..113], data[28..28]); - w_data752w[] = ( data[284..284], data[199..199], data[114..114], data[29..29]); - w_data777w[] = ( data[285..285], data[200..200], data[115..115], data[30..30]); - w_data77w[] = ( data[257..257], data[172..172], data[87..87], data[2..2]); - w_data802w[] = ( data[286..286], data[201..201], data[116..116], data[31..31]); - w_data827w[] = ( data[287..287], data[202..202], data[117..117], data[32..32]); - w_data852w[] = ( data[288..288], data[203..203], data[118..118], data[33..33]); - w_data877w[] = ( data[289..289], data[204..204], data[119..119], data[34..34]); - w_data902w[] = ( data[290..290], data[205..205], data[120..120], data[35..35]); - w_data927w[] = ( data[291..291], data[206..206], data[121..121], data[36..36]); - w_data952w[] = ( data[292..292], data[207..207], data[122..122], data[37..37]); - w_data977w[] = ( data[293..293], data[208..208], data[123..123], data[38..38]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/mux_rsc.tdf b/FPGA_61.440/db/mux_rsc.tdf deleted file mode 100644 index 004e944..0000000 --- a/FPGA_61.440/db/mux_rsc.tdf +++ /dev/null @@ -1,65 +0,0 @@ ---lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone IV E" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=2 LPM_WIDTH=14 LPM_WIDTHS=1 data result sel ---VERSION_BEGIN 18.1 cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - - ---synthesis_resources = lut 14 -SUBDESIGN mux_rsc -( - data[27..0] : input; - result[13..0] : output; - sel[0..0] : input; -) -VARIABLE - result_node[13..0] : WIRE; - sel_node[0..0] : WIRE; - w_data102w[1..0] : WIRE; - w_data114w[1..0] : WIRE; - w_data126w[1..0] : WIRE; - w_data138w[1..0] : WIRE; - w_data150w[1..0] : WIRE; - w_data162w[1..0] : WIRE; - w_data18w[1..0] : WIRE; - w_data30w[1..0] : WIRE; - w_data42w[1..0] : WIRE; - w_data4w[1..0] : WIRE; - w_data54w[1..0] : WIRE; - w_data66w[1..0] : WIRE; - w_data78w[1..0] : WIRE; - w_data90w[1..0] : WIRE; - -BEGIN - result[] = result_node[]; - result_node[] = ( ((sel_node[] & w_data162w[1..1]) # ((! sel_node[]) & w_data162w[0..0])), ((sel_node[] & w_data150w[1..1]) # ((! sel_node[]) & w_data150w[0..0])), ((sel_node[] & w_data138w[1..1]) # ((! sel_node[]) & w_data138w[0..0])), ((sel_node[] & w_data126w[1..1]) # ((! sel_node[]) & w_data126w[0..0])), ((sel_node[] & w_data114w[1..1]) # ((! sel_node[]) & w_data114w[0..0])), ((sel_node[] & w_data102w[1..1]) # ((! sel_node[]) & w_data102w[0..0])), ((sel_node[] & w_data90w[1..1]) # ((! sel_node[]) & w_data90w[0..0])), ((sel_node[] & w_data78w[1..1]) # ((! sel_node[]) & w_data78w[0..0])), ((sel_node[] & w_data66w[1..1]) # ((! sel_node[]) & w_data66w[0..0])), ((sel_node[] & w_data54w[1..1]) # ((! sel_node[]) & w_data54w[0..0])), ((sel_node[] & w_data42w[1..1]) # ((! sel_node[]) & w_data42w[0..0])), ((sel_node[] & w_data30w[1..1]) # ((! sel_node[]) & w_data30w[0..0])), ((sel_node[] & w_data18w[1..1]) # ((! sel_node[]) & w_data18w[0..0])), ((sel_node[] & w_data4w[1..1]) # ((! sel_node[]) & w_data4w[0..0]))); - sel_node[] = ( sel[0..0]); - w_data102w[] = ( data[22..22], data[8..8]); - w_data114w[] = ( data[23..23], data[9..9]); - w_data126w[] = ( data[24..24], data[10..10]); - w_data138w[] = ( data[25..25], data[11..11]); - w_data150w[] = ( data[26..26], data[12..12]); - w_data162w[] = ( data[27..27], data[13..13]); - w_data18w[] = ( data[15..15], data[1..1]); - w_data30w[] = ( data[16..16], data[2..2]); - w_data42w[] = ( data[17..17], data[3..3]); - w_data4w[] = ( data[14..14], data[0..0]); - w_data54w[] = ( data[18..18], data[4..4]); - w_data66w[] = ( data[19..19], data[5..5]); - w_data78w[] = ( data[20..20], data[6..6]); - w_data90w[] = ( data[21..21], data[7..7]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/mux_sob.tdf b/FPGA_61.440/db/mux_sob.tdf deleted file mode 100644 index 9f0acb0..0000000 --- a/FPGA_61.440/db/mux_sob.tdf +++ /dev/null @@ -1,209 +0,0 @@ ---lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_SIZE=4 LPM_WIDTH=86 LPM_WIDTHS=2 data result sel ---VERSION_BEGIN 18.1 cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - - ---synthesis_resources = lut 172 -SUBDESIGN mux_sob -( - data[343..0] : input; - result[85..0] : output; - sel[1..0] : input; -) -VARIABLE - result_node[85..0] : WIRE; - sel_node[1..0] : WIRE; - w_data1015w[3..0] : WIRE; - w_data1040w[3..0] : WIRE; - w_data1065w[3..0] : WIRE; - w_data1090w[3..0] : WIRE; - w_data1115w[3..0] : WIRE; - w_data1140w[3..0] : WIRE; - w_data115w[3..0] : WIRE; - w_data1165w[3..0] : WIRE; - w_data1190w[3..0] : WIRE; - w_data1215w[3..0] : WIRE; - w_data1240w[3..0] : WIRE; - w_data1265w[3..0] : WIRE; - w_data1290w[3..0] : WIRE; - w_data1315w[3..0] : WIRE; - w_data1340w[3..0] : WIRE; - w_data1365w[3..0] : WIRE; - w_data1390w[3..0] : WIRE; - w_data140w[3..0] : WIRE; - w_data1415w[3..0] : WIRE; - w_data1440w[3..0] : WIRE; - w_data1465w[3..0] : WIRE; - w_data1490w[3..0] : WIRE; - w_data1515w[3..0] : WIRE; - w_data1540w[3..0] : WIRE; - w_data1565w[3..0] : WIRE; - w_data1590w[3..0] : WIRE; - w_data1615w[3..0] : WIRE; - w_data1640w[3..0] : WIRE; - w_data165w[3..0] : WIRE; - w_data1665w[3..0] : WIRE; - w_data1690w[3..0] : WIRE; - w_data1715w[3..0] : WIRE; - w_data1740w[3..0] : WIRE; - w_data1765w[3..0] : WIRE; - w_data1790w[3..0] : WIRE; - w_data1815w[3..0] : WIRE; - w_data1840w[3..0] : WIRE; - w_data1865w[3..0] : WIRE; - w_data1890w[3..0] : WIRE; - w_data190w[3..0] : WIRE; - w_data1915w[3..0] : WIRE; - w_data1940w[3..0] : WIRE; - w_data1965w[3..0] : WIRE; - w_data1990w[3..0] : WIRE; - w_data2015w[3..0] : WIRE; - w_data2040w[3..0] : WIRE; - w_data2065w[3..0] : WIRE; - w_data2090w[3..0] : WIRE; - w_data2115w[3..0] : WIRE; - w_data2140w[3..0] : WIRE; - w_data215w[3..0] : WIRE; - w_data2165w[3..0] : WIRE; - w_data2190w[3..0] : WIRE; - w_data240w[3..0] : WIRE; - w_data265w[3..0] : WIRE; - w_data290w[3..0] : WIRE; - w_data315w[3..0] : WIRE; - w_data340w[3..0] : WIRE; - w_data365w[3..0] : WIRE; - w_data390w[3..0] : WIRE; - w_data415w[3..0] : WIRE; - w_data440w[3..0] : WIRE; - w_data465w[3..0] : WIRE; - w_data490w[3..0] : WIRE; - w_data515w[3..0] : WIRE; - w_data540w[3..0] : WIRE; - w_data565w[3..0] : WIRE; - w_data590w[3..0] : WIRE; - w_data60w[3..0] : WIRE; - w_data615w[3..0] : WIRE; - w_data640w[3..0] : WIRE; - w_data665w[3..0] : WIRE; - w_data690w[3..0] : WIRE; - w_data715w[3..0] : WIRE; - w_data740w[3..0] : WIRE; - w_data765w[3..0] : WIRE; - w_data790w[3..0] : WIRE; - w_data815w[3..0] : WIRE; - w_data840w[3..0] : WIRE; - w_data865w[3..0] : WIRE; - w_data890w[3..0] : WIRE; - w_data90w[3..0] : WIRE; - w_data915w[3..0] : WIRE; - w_data940w[3..0] : WIRE; - w_data965w[3..0] : WIRE; - w_data990w[3..0] : WIRE; - -BEGIN - result[] = result_node[]; - result_node[] = ( (((w_data2190w[1..1] & sel_node[0..0]) & (! (((w_data2190w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2190w[2..2]))))) # ((((w_data2190w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2190w[2..2]))) & (w_data2190w[3..3] # (! sel_node[0..0])))), (((w_data2165w[1..1] & sel_node[0..0]) & (! (((w_data2165w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2165w[2..2]))))) # ((((w_data2165w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2165w[2..2]))) & (w_data2165w[3..3] # (! sel_node[0..0])))), (((w_data2140w[1..1] & sel_node[0..0]) & (! (((w_data2140w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2140w[2..2]))))) # ((((w_data2140w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2140w[2..2]))) & (w_data2140w[3..3] # (! sel_node[0..0])))), (((w_data2115w[1..1] & sel_node[0..0]) & (! (((w_data2115w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2115w[2..2]))))) # ((((w_data2115w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2115w[2..2]))) & (w_data2115w[3..3] # (! sel_node[0..0])))), (((w_data2090w[1..1] & sel_node[0..0]) & (! (((w_data2090w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2090w[2..2]))))) # ((((w_data2090w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2090w[2..2]))) & (w_data2090w[3..3] # (! sel_node[0..0])))), (((w_data2065w[1..1] & sel_node[0..0]) & (! (((w_data2065w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2065w[2..2]))))) # ((((w_data2065w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2065w[2..2]))) & (w_data2065w[3..3] # (! sel_node[0..0])))), (((w_data2040w[1..1] & sel_node[0..0]) & (! (((w_data2040w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2040w[2..2]))))) # ((((w_data2040w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2040w[2..2]))) & (w_data2040w[3..3] # (! sel_node[0..0])))), (((w_data2015w[1..1] & sel_node[0..0]) & (! (((w_data2015w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2015w[2..2]))))) # ((((w_data2015w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data2015w[2..2]))) & (w_data2015w[3..3] # (! sel_node[0..0])))), (((w_data1990w[1..1] & sel_node[0..0]) & (! (((w_data1990w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1990w[2..2]))))) # ((((w_data1990w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1990w[2..2]))) & (w_data1990w[3..3] # (! sel_node[0..0])))), (((w_data1965w[1..1] & sel_node[0..0]) & (! (((w_data1965w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1965w[2..2]))))) # ((((w_data1965w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1965w[2..2]))) & (w_data1965w[3..3] # (! sel_node[0..0])))), (((w_data1940w[1..1] & sel_node[0..0]) & (! (((w_data1940w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1940w[2..2]))))) # ((((w_data1940w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1940w[2..2]))) & (w_data1940w[3..3] # (! sel_node[0..0])))), (((w_data1915w[1..1] & sel_node[0..0]) & (! (((w_data1915w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1915w[2..2]))))) # ((((w_data1915w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1915w[2..2]))) & (w_data1915w[3..3] # (! sel_node[0..0])))), (((w_data1890w[1..1] & sel_node[0..0]) & (! (((w_data1890w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1890w[2..2]))))) # ((((w_data1890w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1890w[2..2]))) & (w_data1890w[3..3] # (! sel_node[0..0])))), (((w_data1865w[1..1] & sel_node[0..0]) & (! (((w_data1865w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1865w[2..2]))))) # ((((w_data1865w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1865w[2..2]))) & (w_data1865w[3..3] # (! sel_node[0..0])))), (((w_data1840w[1..1] & sel_node[0..0]) & (! (((w_data1840w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1840w[2..2]))))) # ((((w_data1840w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1840w[2..2]))) & (w_data1840w[3..3] # (! sel_node[0..0])))), (((w_data1815w[1..1] & sel_node[0..0]) & (! (((w_data1815w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1815w[2..2]))))) # ((((w_data1815w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1815w[2..2]))) & (w_data1815w[3..3] # (! sel_node[0..0])))), (((w_data1790w[1..1] & sel_node[0..0]) & (! (((w_data1790w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1790w[2..2]))))) # ((((w_data1790w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1790w[2..2]))) & (w_data1790w[3..3] # (! sel_node[0..0])))), (((w_data1765w[1..1] & sel_node[0..0]) & (! (((w_data1765w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1765w[2..2]))))) # ((((w_data1765w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1765w[2..2]))) & (w_data1765w[3..3] # (! sel_node[0..0])))), (((w_data1740w[1..1] & sel_node[0..0]) & (! (((w_data1740w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1740w[2..2]))))) # ((((w_data1740w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1740w[2..2]))) & (w_data1740w[3..3] # (! sel_node[0..0])))), (((w_data1715w[1..1] & sel_node[0..0]) & (! (((w_data1715w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1715w[2..2]))))) # ((((w_data1715w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1715w[2..2]))) & (w_data1715w[3..3] # (! sel_node[0..0])))), (((w_data1690w[1..1] & sel_node[0..0]) & (! (((w_data1690w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1690w[2..2]))))) # ((((w_data1690w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1690w[2..2]))) & (w_data1690w[3..3] # (! sel_node[0..0])))), (((w_data1665w[1..1] & sel_node[0..0]) & (! (((w_data1665w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1665w[2..2]))))) # ((((w_data1665w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1665w[2..2]))) & (w_data1665w[3..3] # (! sel_node[0..0])))), (((w_data1640w[1..1] & sel_node[0..0]) & (! (((w_data1640w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1640w[2..2]))))) # ((((w_data1640w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1640w[2..2]))) & (w_data1640w[3..3] # (! sel_node[0..0])))), (((w_data1615w[1..1] & sel_node[0..0]) & (! (((w_data1615w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1615w[2..2]))))) # ((((w_data1615w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1615w[2..2]))) & (w_data1615w[3..3] # (! sel_node[0..0])))), (((w_data1590w[1..1] & sel_node[0..0]) & (! (((w_data1590w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1590w[2..2]))))) # ((((w_data1590w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1590w[2..2]))) & (w_data1590w[3..3] # (! sel_node[0..0])))), (((w_data1565w[1..1] & sel_node[0..0]) & (! (((w_data1565w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1565w[2..2]))))) # ((((w_data1565w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1565w[2..2]))) & (w_data1565w[3..3] # (! sel_node[0..0])))), (((w_data1540w[1..1] & sel_node[0..0]) & (! (((w_data1540w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1540w[2..2]))))) # ((((w_data1540w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1540w[2..2]))) & (w_data1540w[3..3] # (! sel_node[0..0])))), (((w_data1515w[1..1] & sel_node[0..0]) & (! (((w_data1515w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1515w[2..2]))))) # ((((w_data1515w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1515w[2..2]))) & (w_data1515w[3..3] # (! sel_node[0..0])))), (((w_data1490w[1..1] & sel_node[0..0]) & (! (((w_data1490w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1490w[2..2]))))) # ((((w_data1490w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1490w[2..2]))) & (w_data1490w[3..3] # (! sel_node[0..0])))), (((w_data1465w[1..1] & sel_node[0..0]) & (! (((w_data1465w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1465w[2..2]))))) # ((((w_data1465w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1465w[2..2]))) & (w_data1465w[3..3] # (! sel_node[0..0])))), (((w_data1440w[1..1] & sel_node[0..0]) & (! (((w_data1440w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1440w[2..2]))))) # ((((w_data1440w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1440w[2..2]))) & (w_data1440w[3..3] # (! sel_node[0..0])))), (((w_data1415w[1..1] & sel_node[0..0]) & (! (((w_data1415w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1415w[2..2]))))) # ((((w_data1415w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1415w[2..2]))) & (w_data1415w[3..3] # (! sel_node[0..0])))), (((w_data1390w[1..1] & sel_node[0..0]) & (! (((w_data1390w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1390w[2..2]))))) # ((((w_data1390w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1390w[2..2]))) & (w_data1390w[3..3] # (! sel_node[0..0])))), (((w_data1365w[1..1] & sel_node[0..0]) & (! (((w_data1365w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1365w[2..2]))))) # ((((w_data1365w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1365w[2..2]))) & (w_data1365w[3..3] # (! sel_node[0..0])))), (((w_data1340w[1..1] & sel_node[0..0]) & (! (((w_data1340w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1340w[2..2]))))) # ((((w_data1340w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1340w[2..2]))) & (w_data1340w[3..3] # (! sel_node[0..0])))), (((w_data1315w[1..1] & sel_node[0..0]) & (! (((w_data1315w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1315w[2..2]))))) # ((((w_data1315w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1315w[2..2]))) & (w_data1315w[3..3] # (! sel_node[0..0])))), (((w_data1290w[1..1] & sel_node[0..0]) & (! (((w_data1290w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1290w[2..2]))))) # ((((w_data1290w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1290w[2..2]))) & (w_data1290w[3..3] # (! sel_node[0..0])))), (((w_data1265w[1..1] & sel_node[0..0]) & (! (((w_data1265w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1265w[2..2]))))) # ((((w_data1265w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1265w[2..2]))) & (w_data1265w[3..3] # (! sel_node[0..0])))), (((w_data1240w[1..1] & sel_node[0..0]) & (! (((w_data1240w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1240w[2..2]))))) # ((((w_data1240w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1240w[2..2]))) & (w_data1240w[3..3] # (! sel_node[0..0])))), (((w_data1215w[1..1] & sel_node[0..0]) & (! (((w_data1215w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1215w[2..2]))))) # ((((w_data1215w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1215w[2..2]))) & (w_data1215w[3..3] # (! sel_node[0..0])))), (((w_data1190w[1..1] & sel_node[0..0]) & (! (((w_data1190w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1190w[2..2]))))) # ((((w_data1190w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1190w[2..2]))) & (w_data1190w[3..3] # (! sel_node[0..0])))), (((w_data1165w[1..1] & sel_node[0..0]) & (! (((w_data1165w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1165w[2..2]))))) # ((((w_data1165w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1165w[2..2]))) & (w_data1165w[3..3] # (! sel_node[0..0])))), (((w_data1140w[1..1] & sel_node[0..0]) & (! (((w_data1140w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1140w[2..2]))))) # ((((w_data1140w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1140w[2..2]))) & (w_data1140w[3..3] # (! sel_node[0..0])))), (((w_data1115w[1..1] & sel_node[0..0]) & (! (((w_data1115w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1115w[2..2]))))) # ((((w_data1115w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1115w[2..2]))) & (w_data1115w[3..3] # (! sel_node[0..0])))), (((w_data1090w[1..1] & sel_node[0..0]) & (! (((w_data1090w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1090w[2..2]))))) # ((((w_data1090w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1090w[2..2]))) & (w_data1090w[3..3] # (! sel_node[0..0])))), (((w_data1065w[1..1] & sel_node[0..0]) & (! (((w_data1065w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1065w[2..2]))))) # ((((w_data1065w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1065w[2..2]))) & (w_data1065w[3..3] # (! sel_node[0..0])))), (((w_data1040w[1..1] & sel_node[0..0]) & (! (((w_data1040w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1040w[2..2]))))) # ((((w_data1040w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1040w[2..2]))) & (w_data1040w[3..3] # (! sel_node[0..0])))), (((w_data1015w[1..1] & sel_node[0..0]) & (! (((w_data1015w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1015w[2..2]))))) # ((((w_data1015w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data1015w[2..2]))) & (w_data1015w[3..3] # (! sel_node[0..0])))), (((w_data990w[1..1] & sel_node[0..0]) & (! (((w_data990w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data990w[2..2]))))) # ((((w_data990w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data990w[2..2]))) & (w_data990w[3..3] # (! sel_node[0..0])))), (((w_data965w[1..1] & sel_node[0..0]) & (! (((w_data965w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data965w[2..2]))))) # ((((w_data965w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data965w[2..2]))) & (w_data965w[3..3] # (! sel_node[0..0])))), (((w_data940w[1..1] & sel_node[0..0]) & (! (((w_data940w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data940w[2..2]))))) # ((((w_data940w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data940w[2..2]))) & (w_data940w[3..3] # (! sel_node[0..0])))), (((w_data915w[1..1] & sel_node[0..0]) & (! (((w_data915w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data915w[2..2]))))) # ((((w_data915w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data915w[2..2]))) & (w_data915w[3..3] # (! sel_node[0..0])))), (((w_data890w[1..1] & sel_node[0..0]) & (! (((w_data890w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data890w[2..2]))))) # ((((w_data890w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data890w[2..2]))) & (w_data890w[3..3] # (! sel_node[0..0])))), (((w_data865w[1..1] & sel_node[0..0]) & (! (((w_data865w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data865w[2..2]))))) # ((((w_data865w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data865w[2..2]))) & (w_data865w[3..3] # (! sel_node[0..0])))), (((w_data840w[1..1] & sel_node[0..0]) & (! (((w_data840w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data840w[2..2]))))) # ((((w_data840w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data840w[2..2]))) & (w_data840w[3..3] # (! sel_node[0..0])))), (((w_data815w[1..1] & sel_node[0..0]) & (! (((w_data815w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data815w[2..2]))))) # ((((w_data815w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data815w[2..2]))) & (w_data815w[3..3] # (! sel_node[0..0])))), (((w_data790w[1..1] & sel_node[0..0]) & (! (((w_data790w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data790w[2..2]))))) # ((((w_data790w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data790w[2..2]))) & (w_data790w[3..3] # (! sel_node[0..0])))), (((w_data765w[1..1] & sel_node[0..0]) & (! (((w_data765w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data765w[2..2]))))) # ((((w_data765w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data765w[2..2]))) & (w_data765w[3..3] # (! sel_node[0..0])))), (((w_data740w[1..1] & sel_node[0..0]) & (! (((w_data740w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data740w[2..2]))))) # ((((w_data740w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data740w[2..2]))) & (w_data740w[3..3] # (! sel_node[0..0])))), (((w_data715w[1..1] & sel_node[0..0]) & (! (((w_data715w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data715w[2..2]))))) # ((((w_data715w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data715w[2..2]))) & (w_data715w[3..3] # (! sel_node[0..0])))), (((w_data690w[1..1] & sel_node[0..0]) & (! (((w_data690w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data690w[2..2]))))) # ((((w_data690w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data690w[2..2]))) & (w_data690w[3..3] # (! sel_node[0..0])))), (((w_data665w[1..1] & sel_node[0..0]) & (! (((w_data665w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data665w[2..2]))))) # ((((w_data665w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data665w[2..2]))) & (w_data665w[3..3] # (! sel_node[0..0])))), (((w_data640w[1..1] & sel_node[0..0]) & (! (((w_data640w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data640w[2..2]))))) # ((((w_data640w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data640w[2..2]))) & (w_data640w[3..3] # (! sel_node[0..0])))), (((w_data615w[1..1] & sel_node[0..0]) & (! (((w_data615w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data615w[2..2]))))) # ((((w_data615w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data615w[2..2]))) & (w_data615w[3..3] # (! sel_node[0..0])))), (((w_data590w[1..1] & sel_node[0..0]) & (! (((w_data590w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data590w[2..2]))))) # ((((w_data590w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data590w[2..2]))) & (w_data590w[3..3] # (! sel_node[0..0])))), (((w_data565w[1..1] & sel_node[0..0]) & (! (((w_data565w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data565w[2..2]))))) # ((((w_data565w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data565w[2..2]))) & (w_data565w[3..3] # (! sel_node[0..0])))), (((w_data540w[1..1] & sel_node[0..0]) & (! (((w_data540w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data540w[2..2]))))) # ((((w_data540w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data540w[2..2]))) & (w_data540w[3..3] # (! sel_node[0..0])))), (((w_data515w[1..1] & sel_node[0..0]) & (! (((w_data515w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data515w[2..2]))))) # ((((w_data515w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data515w[2..2]))) & (w_data515w[3..3] # (! sel_node[0..0])))), (((w_data490w[1..1] & sel_node[0..0]) & (! (((w_data490w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data490w[2..2]))))) # ((((w_data490w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data490w[2..2]))) & (w_data490w[3..3] # (! sel_node[0..0])))), (((w_data465w[1..1] & sel_node[0..0]) & (! (((w_data465w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data465w[2..2]))))) # ((((w_data465w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data465w[2..2]))) & (w_data465w[3..3] # (! sel_node[0..0])))), (((w_data440w[1..1] & sel_node[0..0]) & (! (((w_data440w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data440w[2..2]))))) # ((((w_data440w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data440w[2..2]))) & (w_data440w[3..3] # (! sel_node[0..0])))), (((w_data415w[1..1] & sel_node[0..0]) & (! (((w_data415w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data415w[2..2]))))) # ((((w_data415w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data415w[2..2]))) & (w_data415w[3..3] # (! sel_node[0..0])))), (((w_data390w[1..1] & sel_node[0..0]) & (! (((w_data390w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data390w[2..2]))))) # ((((w_data390w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data390w[2..2]))) & (w_data390w[3..3] # (! sel_node[0..0])))), (((w_data365w[1..1] & sel_node[0..0]) & (! (((w_data365w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data365w[2..2]))))) # ((((w_data365w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data365w[2..2]))) & (w_data365w[3..3] # (! sel_node[0..0])))), (((w_data340w[1..1] & sel_node[0..0]) & (! (((w_data340w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data340w[2..2]))))) # ((((w_data340w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data340w[2..2]))) & (w_data340w[3..3] # (! sel_node[0..0])))), (((w_data315w[1..1] & sel_node[0..0]) & (! (((w_data315w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data315w[2..2]))))) # ((((w_data315w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data315w[2..2]))) & (w_data315w[3..3] # (! sel_node[0..0])))), (((w_data290w[1..1] & sel_node[0..0]) & (! (((w_data290w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data290w[2..2]))))) # ((((w_data290w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data290w[2..2]))) & (w_data290w[3..3] # (! sel_node[0..0])))), (((w_data265w[1..1] & sel_node[0..0]) & (! (((w_data265w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data265w[2..2]))))) # ((((w_data265w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data265w[2..2]))) & (w_data265w[3..3] # (! sel_node[0..0])))), (((w_data240w[1..1] & sel_node[0..0]) & (! (((w_data240w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data240w[2..2]))))) # ((((w_data240w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data240w[2..2]))) & (w_data240w[3..3] # (! sel_node[0..0])))), (((w_data215w[1..1] & sel_node[0..0]) & (! (((w_data215w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data215w[2..2]))))) # ((((w_data215w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data215w[2..2]))) & (w_data215w[3..3] # (! sel_node[0..0])))), (((w_data190w[1..1] & sel_node[0..0]) & (! (((w_data190w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data190w[2..2]))))) # ((((w_data190w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data190w[2..2]))) & (w_data190w[3..3] # (! sel_node[0..0])))), (((w_data165w[1..1] & sel_node[0..0]) & (! (((w_data165w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data165w[2..2]))))) # ((((w_data165w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data165w[2..2]))) & (w_data165w[3..3] # (! sel_node[0..0])))), (((w_data140w[1..1] & sel_node[0..0]) & (! (((w_data140w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data140w[2..2]))))) # ((((w_data140w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data140w[2..2]))) & (w_data140w[3..3] # (! sel_node[0..0])))), (((w_data115w[1..1] & sel_node[0..0]) & (! (((w_data115w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data115w[2..2]))))) # ((((w_data115w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data115w[2..2]))) & (w_data115w[3..3] # (! sel_node[0..0])))), (((w_data90w[1..1] & sel_node[0..0]) & (! (((w_data90w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data90w[2..2]))))) # ((((w_data90w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data90w[2..2]))) & (w_data90w[3..3] # (! sel_node[0..0])))), (((w_data60w[1..1] & sel_node[0..0]) & (! (((w_data60w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data60w[2..2]))))) # ((((w_data60w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data60w[2..2]))) & (w_data60w[3..3] # (! sel_node[0..0]))))); - sel_node[] = ( sel[1..0]); - w_data1015w[] = ( data[296..296], data[210..210], data[124..124], data[38..38]); - w_data1040w[] = ( data[297..297], data[211..211], data[125..125], data[39..39]); - w_data1065w[] = ( data[298..298], data[212..212], data[126..126], data[40..40]); - w_data1090w[] = ( data[299..299], data[213..213], data[127..127], data[41..41]); - w_data1115w[] = ( data[300..300], data[214..214], data[128..128], data[42..42]); - w_data1140w[] = ( data[301..301], data[215..215], data[129..129], data[43..43]); - w_data115w[] = ( data[260..260], data[174..174], data[88..88], data[2..2]); - w_data1165w[] = ( data[302..302], data[216..216], data[130..130], data[44..44]); - w_data1190w[] = ( data[303..303], data[217..217], data[131..131], data[45..45]); - w_data1215w[] = ( data[304..304], data[218..218], data[132..132], data[46..46]); - w_data1240w[] = ( data[305..305], data[219..219], data[133..133], data[47..47]); - w_data1265w[] = ( data[306..306], data[220..220], data[134..134], data[48..48]); - w_data1290w[] = ( data[307..307], data[221..221], data[135..135], data[49..49]); - w_data1315w[] = ( data[308..308], data[222..222], data[136..136], data[50..50]); - w_data1340w[] = ( data[309..309], data[223..223], data[137..137], data[51..51]); - w_data1365w[] = ( data[310..310], data[224..224], data[138..138], data[52..52]); - w_data1390w[] = ( data[311..311], data[225..225], data[139..139], data[53..53]); - w_data140w[] = ( data[261..261], data[175..175], data[89..89], data[3..3]); - w_data1415w[] = ( data[312..312], data[226..226], data[140..140], data[54..54]); - w_data1440w[] = ( data[313..313], data[227..227], data[141..141], data[55..55]); - w_data1465w[] = ( data[314..314], data[228..228], data[142..142], data[56..56]); - w_data1490w[] = ( data[315..315], data[229..229], data[143..143], data[57..57]); - w_data1515w[] = ( data[316..316], data[230..230], data[144..144], data[58..58]); - w_data1540w[] = ( data[317..317], data[231..231], data[145..145], data[59..59]); - w_data1565w[] = ( data[318..318], data[232..232], data[146..146], data[60..60]); - w_data1590w[] = ( data[319..319], data[233..233], data[147..147], data[61..61]); - w_data1615w[] = ( data[320..320], data[234..234], data[148..148], data[62..62]); - w_data1640w[] = ( data[321..321], data[235..235], data[149..149], data[63..63]); - w_data165w[] = ( data[262..262], data[176..176], data[90..90], data[4..4]); - w_data1665w[] = ( data[322..322], data[236..236], data[150..150], data[64..64]); - w_data1690w[] = ( data[323..323], data[237..237], data[151..151], data[65..65]); - w_data1715w[] = ( data[324..324], data[238..238], data[152..152], data[66..66]); - w_data1740w[] = ( data[325..325], data[239..239], data[153..153], data[67..67]); - w_data1765w[] = ( data[326..326], data[240..240], data[154..154], data[68..68]); - w_data1790w[] = ( data[327..327], data[241..241], data[155..155], data[69..69]); - w_data1815w[] = ( data[328..328], data[242..242], data[156..156], data[70..70]); - w_data1840w[] = ( data[329..329], data[243..243], data[157..157], data[71..71]); - w_data1865w[] = ( data[330..330], data[244..244], data[158..158], data[72..72]); - w_data1890w[] = ( data[331..331], data[245..245], data[159..159], data[73..73]); - w_data190w[] = ( data[263..263], data[177..177], data[91..91], data[5..5]); - w_data1915w[] = ( data[332..332], data[246..246], data[160..160], data[74..74]); - w_data1940w[] = ( data[333..333], data[247..247], data[161..161], data[75..75]); - w_data1965w[] = ( data[334..334], data[248..248], data[162..162], data[76..76]); - w_data1990w[] = ( data[335..335], data[249..249], data[163..163], data[77..77]); - w_data2015w[] = ( data[336..336], data[250..250], data[164..164], data[78..78]); - w_data2040w[] = ( data[337..337], data[251..251], data[165..165], data[79..79]); - w_data2065w[] = ( data[338..338], data[252..252], data[166..166], data[80..80]); - w_data2090w[] = ( data[339..339], data[253..253], data[167..167], data[81..81]); - w_data2115w[] = ( data[340..340], data[254..254], data[168..168], data[82..82]); - w_data2140w[] = ( data[341..341], data[255..255], data[169..169], data[83..83]); - w_data215w[] = ( data[264..264], data[178..178], data[92..92], data[6..6]); - w_data2165w[] = ( data[342..342], data[256..256], data[170..170], data[84..84]); - w_data2190w[] = ( data[343..343], data[257..257], data[171..171], data[85..85]); - w_data240w[] = ( data[265..265], data[179..179], data[93..93], data[7..7]); - w_data265w[] = ( data[266..266], data[180..180], data[94..94], data[8..8]); - w_data290w[] = ( data[267..267], data[181..181], data[95..95], data[9..9]); - w_data315w[] = ( data[268..268], data[182..182], data[96..96], data[10..10]); - w_data340w[] = ( data[269..269], data[183..183], data[97..97], data[11..11]); - w_data365w[] = ( data[270..270], data[184..184], data[98..98], data[12..12]); - w_data390w[] = ( data[271..271], data[185..185], data[99..99], data[13..13]); - w_data415w[] = ( data[272..272], data[186..186], data[100..100], data[14..14]); - w_data440w[] = ( data[273..273], data[187..187], data[101..101], data[15..15]); - w_data465w[] = ( data[274..274], data[188..188], data[102..102], data[16..16]); - w_data490w[] = ( data[275..275], data[189..189], data[103..103], data[17..17]); - w_data515w[] = ( data[276..276], data[190..190], data[104..104], data[18..18]); - w_data540w[] = ( data[277..277], data[191..191], data[105..105], data[19..19]); - w_data565w[] = ( data[278..278], data[192..192], data[106..106], data[20..20]); - w_data590w[] = ( data[279..279], data[193..193], data[107..107], data[21..21]); - w_data60w[] = ( data[258..258], data[172..172], data[86..86], data[0..0]); - w_data615w[] = ( data[280..280], data[194..194], data[108..108], data[22..22]); - w_data640w[] = ( data[281..281], data[195..195], data[109..109], data[23..23]); - w_data665w[] = ( data[282..282], data[196..196], data[110..110], data[24..24]); - w_data690w[] = ( data[283..283], data[197..197], data[111..111], data[25..25]); - w_data715w[] = ( data[284..284], data[198..198], data[112..112], data[26..26]); - w_data740w[] = ( data[285..285], data[199..199], data[113..113], data[27..27]); - w_data765w[] = ( data[286..286], data[200..200], data[114..114], data[28..28]); - w_data790w[] = ( data[287..287], data[201..201], data[115..115], data[29..29]); - w_data815w[] = ( data[288..288], data[202..202], data[116..116], data[30..30]); - w_data840w[] = ( data[289..289], data[203..203], data[117..117], data[31..31]); - w_data865w[] = ( data[290..290], data[204..204], data[118..118], data[32..32]); - w_data890w[] = ( data[291..291], data[205..205], data[119..119], data[33..33]); - w_data90w[] = ( data[259..259], data[173..173], data[87..87], data[1..1]); - w_data915w[] = ( data[292..292], data[206..206], data[120..120], data[34..34]); - w_data940w[] = ( data[293..293], data[207..207], data[121..121], data[35..35]); - w_data965w[] = ( data[294..294], data[208..208], data[122..122], data[36..36]); - w_data990w[] = ( data[295..295], data[209..209], data[123..123], data[37..37]); -END; ---VALID FILE diff --git a/FPGA_61.440/db/prev_cmp_WOLF-LITE.qmsg b/FPGA_61.440/db/prev_cmp_WOLF-LITE.qmsg deleted file mode 100644 index e7a1cc6..0000000 --- a/FPGA_61.440/db/prev_cmp_WOLF-LITE.qmsg +++ /dev/null @@ -1,914 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1616603490203 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1616603490238 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 24 19:31:29 2021 " "Processing started: Wed Mar 24 19:31:29 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1616603490238 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603490238 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off WOLF-LITE -c WOLF-LITE " "Command: quartus_map --read_settings_files=on --write_settings_files=off WOLF-LITE -c WOLF-LITE" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603490238 ""} -{ "Info" "IQCU_OPT_MODE_DESCRIPTION" "Aggressive Performance timing performance increased logic area and compilation time " "Aggressive Performance optimization mode selected -- timing performance will be prioritized at the potential cost of increased logic area and compilation time" { } { } 0 16303 "%1!s! optimization mode selected -- %2!s! will be prioritized at the potential cost of %3!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603491598 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1616603491706 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "clock_buffer.qsys " "Elaborating Platform Designer system entity \"clock_buffer.qsys\"" { } { } 0 12248 "Elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603503519 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:31:48 Progress: Loading FPGA/clock_buffer.qsys " "2021.03.24.20:31:48 Progress: Loading FPGA/clock_buffer.qsys" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603508348 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:31:49 Progress: Reading input file " "2021.03.24.20:31:49 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603509071 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:31:49 Progress: Adding altclkctrl_0 \[altclkctrl 18.1\] " "2021.03.24.20:31:49 Progress: Adding altclkctrl_0 \[altclkctrl 18.1\]" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603509154 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:31:50 Progress: Parameterizing module altclkctrl_0 " "2021.03.24.20:31:50 Progress: Parameterizing module altclkctrl_0" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603510359 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:31:50 Progress: Building connections " "2021.03.24.20:31:50 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603510362 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:31:50 Progress: Parameterizing connections " "2021.03.24.20:31:50 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603510362 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:31:50 Progress: Validating " "2021.03.24.20:31:50 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603510401 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:31:51 Progress: Done reading input file " "2021.03.24.20:31:51 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603511325 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:31:51 : clock_buffer.altclkctrl_0: Targeting device family: Cyclone IV E. " "2021.03.24.20:31:51 : clock_buffer.altclkctrl_0: Targeting device family: Cyclone IV E." { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603511733 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:31:51 : clock_buffer.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs. " "2021.03.24.20:31:51 : clock_buffer.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs." { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603511733 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Clock_buffer: Generating clock_buffer \"clock_buffer\" for QUARTUS_SYNTH " "Clock_buffer: Generating clock_buffer \"clock_buffer\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603512488 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Altclkctrl_0: Generating top-level entity clock_buffer_altclkctrl_0. " "Altclkctrl_0: Generating top-level entity clock_buffer_altclkctrl_0." { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603513243 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Altclkctrl_0: \"clock_buffer\" instantiated altclkctrl \"altclkctrl_0\" " "Altclkctrl_0: \"clock_buffer\" instantiated altclkctrl \"altclkctrl_0\"" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603513563 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Clock_buffer: Done \"clock_buffer\" with 2 modules, 2 files " "Clock_buffer: Done \"clock_buffer\" with 2 modules, 2 files" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603513564 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "clock_buffer.qsys " "Finished elaborating Platform Designer system entity \"clock_buffer.qsys\"" { } { } 0 12249 "Finished elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603514389 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "rx_cic.qsys " "Elaborating Platform Designer system entity \"rx_cic.qsys\"" { } { } 0 12248 "Elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603514435 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:31:59 Progress: Loading FPGA/rx_cic.qsys " "2021.03.24.20:31:59 Progress: Loading FPGA/rx_cic.qsys" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603519241 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:31:59 Progress: Reading input file " "2021.03.24.20:31:59 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603519891 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:31:59 Progress: Adding cic_ii_0 \[altera_cic_ii 18.1\] " "2021.03.24.20:31:59 Progress: Adding cic_ii_0 \[altera_cic_ii 18.1\]" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603519980 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:00 Progress: Parameterizing module cic_ii_0 " "2021.03.24.20:32:00 Progress: Parameterizing module cic_ii_0" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603520269 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:00 Progress: Building connections " "2021.03.24.20:32:00 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603520297 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:00 Progress: Parameterizing connections " "2021.03.24.20:32:00 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603520297 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:00 Progress: Validating " "2021.03.24.20:32:00 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603520328 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:01 Progress: Done reading input file " "2021.03.24.20:32:01 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603521336 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Rx_cic.cic_ii_0: Clock Enable Port is deprecated and may be removed in a future release " "Rx_cic.cic_ii_0: Clock Enable Port is deprecated and may be removed in a future release" { } { } 0 12251 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603521761 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rx_cic: Generating rx_cic \"rx_cic\" for QUARTUS_SYNTH " "Rx_cic: Generating rx_cic \"rx_cic\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603522444 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cic_ii_0: \"rx_cic\" instantiated altera_cic_ii \"cic_ii_0\" " "Cic_ii_0: \"rx_cic\" instantiated altera_cic_ii \"cic_ii_0\"" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603523544 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rx_cic: Done \"rx_cic\" with 2 modules, 30 files " "Rx_cic: Done \"rx_cic\" with 2 modules, 30 files" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603523562 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "rx_cic.qsys " "Finished elaborating Platform Designer system entity \"rx_cic.qsys\"" { } { } 0 12249 "Finished elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603524354 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "tx_cic.qsys " "Elaborating Platform Designer system entity \"tx_cic.qsys\"" { } { } 0 12248 "Elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603524393 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:09 Progress: Loading FPGA/tx_cic.qsys " "2021.03.24.20:32:09 Progress: Loading FPGA/tx_cic.qsys" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603529467 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:10 Progress: Reading input file " "2021.03.24.20:32:10 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603530144 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:10 Progress: Adding cic_ii_0 \[altera_cic_ii 18.1\] " "2021.03.24.20:32:10 Progress: Adding cic_ii_0 \[altera_cic_ii 18.1\]" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603530226 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:10 Progress: Parameterizing module cic_ii_0 " "2021.03.24.20:32:10 Progress: Parameterizing module cic_ii_0" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603530452 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:10 Progress: Building connections " "2021.03.24.20:32:10 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603530462 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:10 Progress: Parameterizing connections " "2021.03.24.20:32:10 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603530462 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:10 Progress: Validating " "2021.03.24.20:32:10 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603530493 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:11 Progress: Done reading input file " "2021.03.24.20:32:11 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603531463 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Tx_cic: Generating tx_cic \"tx_cic\" for QUARTUS_SYNTH " "Tx_cic: Generating tx_cic \"tx_cic\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603532609 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cic_ii_0: \"tx_cic\" instantiated altera_cic_ii \"cic_ii_0\" " "Cic_ii_0: \"tx_cic\" instantiated altera_cic_ii \"cic_ii_0\"" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603533511 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Tx_cic: Done \"tx_cic\" with 2 modules, 30 files " "Tx_cic: Done \"tx_cic\" with 2 modules, 30 files" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603533528 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "tx_cic.qsys " "Finished elaborating Platform Designer system entity \"tx_cic.qsys\"" { } { } 0 12249 "Finished elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603534313 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "tx_nco.qsys " "Elaborating Platform Designer system entity \"tx_nco.qsys\"" { } { } 0 12248 "Elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603534354 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:19 Progress: Loading FPGA/tx_nco.qsys " "2021.03.24.20:32:19 Progress: Loading FPGA/tx_nco.qsys" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603539400 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:20 Progress: Reading input file " "2021.03.24.20:32:20 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603540107 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:20 Progress: Adding nco_ii_0 \[altera_nco_ii 18.1\] " "2021.03.24.20:32:20 Progress: Adding nco_ii_0 \[altera_nco_ii 18.1\]" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603540199 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:20 Progress: Parameterizing module nco_ii_0 " "2021.03.24.20:32:20 Progress: Parameterizing module nco_ii_0" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603540461 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:20 Progress: Building connections " "2021.03.24.20:32:20 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603540485 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:20 Progress: Parameterizing connections " "2021.03.24.20:32:20 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603540486 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:20 Progress: Validating " "2021.03.24.20:32:20 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603540518 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:21 Progress: Done reading input file " "2021.03.24.20:32:21 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603541484 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Tx_nco: Generating tx_nco \"tx_nco\" for QUARTUS_SYNTH " "Tx_nco: Generating tx_nco \"tx_nco\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603542619 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nco_ii_0: \"tx_nco\" instantiated altera_nco_ii \"nco_ii_0\" " "Nco_ii_0: \"tx_nco\" instantiated altera_nco_ii \"nco_ii_0\"" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603543683 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Tx_nco: Done \"tx_nco\" with 2 modules, 18 files " "Tx_nco: Done \"tx_nco\" with 2 modules, 18 files" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603543696 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "tx_nco.qsys " "Finished elaborating Platform Designer system entity \"tx_nco.qsys\"" { } { } 0 12249 "Finished elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603547349 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "nco.qsys " "Elaborating Platform Designer system entity \"nco.qsys\"" { } { } 0 12248 "Elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603547381 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:32 Progress: Loading FPGA/nco.qsys " "2021.03.24.20:32:32 Progress: Loading FPGA/nco.qsys" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603552197 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:32 Progress: Reading input file " "2021.03.24.20:32:32 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603552863 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:32 Progress: Adding nco_ii_0 \[altera_nco_ii 18.1\] " "2021.03.24.20:32:32 Progress: Adding nco_ii_0 \[altera_nco_ii 18.1\]" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603552943 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:33 Progress: Parameterizing module nco_ii_0 " "2021.03.24.20:32:33 Progress: Parameterizing module nco_ii_0" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603553173 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:33 Progress: Building connections " "2021.03.24.20:32:33 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603553185 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:33 Progress: Parameterizing connections " "2021.03.24.20:32:33 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603553185 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:33 Progress: Validating " "2021.03.24.20:32:33 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603553221 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:34 Progress: Done reading input file " "2021.03.24.20:32:34 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603554169 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nco: Generating nco \"nco\" for QUARTUS_SYNTH " "Nco: Generating nco \"nco\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603555329 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nco_ii_0: \"nco\" instantiated altera_nco_ii \"nco_ii_0\" " "Nco_ii_0: \"nco\" instantiated altera_nco_ii \"nco_ii_0\"" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603556293 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nco: Done \"nco\" with 2 modules, 18 files " "Nco: Done \"nco\" with 2 modules, 18 files" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603556306 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "nco.qsys " "Finished elaborating Platform Designer system entity \"nco.qsys\"" { } { } 0 12249 "Finished elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603557083 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "DEBUG.qsys " "Elaborating Platform Designer system entity \"DEBUG.qsys\"" { } { } 0 12248 "Elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603557137 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:42 Progress: Loading FPGA/DEBUG.qsys " "2021.03.24.20:32:42 Progress: Loading FPGA/DEBUG.qsys" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603562011 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:42 Progress: Reading input file " "2021.03.24.20:32:42 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603562723 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:42 Progress: Adding in_system_sources_probes_0 \[altera_in_system_sources_probes 18.1\] " "2021.03.24.20:32:42 Progress: Adding in_system_sources_probes_0 \[altera_in_system_sources_probes 18.1\]" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603562835 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:43 Progress: Parameterizing module in_system_sources_probes_0 " "2021.03.24.20:32:43 Progress: Parameterizing module in_system_sources_probes_0" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603563031 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:43 Progress: Building connections " "2021.03.24.20:32:43 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603563035 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:43 Progress: Parameterizing connections " "2021.03.24.20:32:43 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603563035 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:43 Progress: Validating " "2021.03.24.20:32:43 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603563064 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:44 Progress: Done reading input file " "2021.03.24.20:32:44 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603564032 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "DEBUG: Generating DEBUG \"DEBUG\" for QUARTUS_SYNTH " "DEBUG: Generating DEBUG \"DEBUG\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603565088 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "In_system_sources_probes_0: \"DEBUG\" instantiated altera_in_system_sources_probes \"in_system_sources_probes_0\" " "In_system_sources_probes_0: \"DEBUG\" instantiated altera_in_system_sources_probes \"in_system_sources_probes_0\"" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603565817 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "DEBUG: Done \"DEBUG\" with 2 modules, 2 files " "DEBUG: Done \"DEBUG\" with 2 modules, 2 files" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603565817 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "DEBUG.qsys " "Finished elaborating Platform Designer system entity \"DEBUG.qsys\"" { } { } 0 12249 "Finished elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603566630 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "DEBUG2.qsys " "Elaborating Platform Designer system entity \"DEBUG2.qsys\"" { } { } 0 12248 "Elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603566672 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:51 Progress: Loading FPGA/DEBUG2.qsys " "2021.03.24.20:32:51 Progress: Loading FPGA/DEBUG2.qsys" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603571671 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:52 Progress: Reading input file " "2021.03.24.20:32:52 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603572472 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:52 Progress: Adding in_system_sources_probes_0 \[altera_in_system_sources_probes 18.1\] " "2021.03.24.20:32:52 Progress: Adding in_system_sources_probes_0 \[altera_in_system_sources_probes 18.1\]" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603572560 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:52 Progress: Parameterizing module in_system_sources_probes_0 " "2021.03.24.20:32:52 Progress: Parameterizing module in_system_sources_probes_0" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603572772 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:52 Progress: Building connections " "2021.03.24.20:32:52 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603572775 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:52 Progress: Parameterizing connections " "2021.03.24.20:32:52 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603572775 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:52 Progress: Validating " "2021.03.24.20:32:52 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603572809 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2021.03.24.20:32:53 Progress: Done reading input file " "2021.03.24.20:32:53 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603573911 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "DEBUG2: Generating DEBUG2 \"DEBUG2\" for QUARTUS_SYNTH " "DEBUG2: Generating DEBUG2 \"DEBUG2\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603575075 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "In_system_sources_probes_0: \"DEBUG2\" instantiated altera_in_system_sources_probes \"in_system_sources_probes_0\" " "In_system_sources_probes_0: \"DEBUG2\" instantiated altera_in_system_sources_probes \"in_system_sources_probes_0\"" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603575838 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "DEBUG2: Done \"DEBUG2\" with 2 modules, 2 files " "DEBUG2: Done \"DEBUG2\" with 2 modules, 2 files" { } { } 0 12250 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603575839 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "DEBUG2.qsys " "Finished elaborating Platform Designer system entity \"DEBUG2.qsys\"" { } { } 0 12249 "Finished elaborating Platform Designer system entity \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603576619 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "wolf-lite.bdf 1 1 " "Found 1 design units, including 1 entities, in source file wolf-lite.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 WOLF-LITE " "Found entity 1: WOLF-LITE" { } { { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578070 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578070 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dac_corrector.v 1 1 " "Found 1 design units, including 1 entities, in source file dac_corrector.v" { { "Info" "ISGN_ENTITY_NAME" "1 DAC_corrector " "Found entity 1: DAC_corrector" { } { { "DAC_corrector.v" "" { Text "C:/FPGA/DAC_corrector.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578121 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578121 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file spi_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi_interface " "Found entity 1: spi_interface" { } { { "spi_interface.v" "" { Text "C:/FPGA/spi_interface.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578154 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578154 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "stm32_interface.v(93) " "Verilog HDL warning at stm32_interface.v(93): extended using \"x\" or \"z\"" { } { { "stm32_interface.v" "" { Text "C:/FPGA/stm32_interface.v" 93 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1616603578176 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "stm32_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file stm32_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 stm32_interface " "Found entity 1: stm32_interface" { } { { "stm32_interface.v" "" { Text "C:/FPGA/stm32_interface.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578187 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578187 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_shifter.v 1 1 " "Found 1 design units, including 1 entities, in source file data_shifter.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_shifter " "Found entity 1: data_shifter" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578214 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578214 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vcxo_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file vcxo_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 vcxo_controller " "Found entity 1: vcxo_controller" { } { { "vcxo_controller.v" "" { Text "C:/FPGA/vcxo_controller.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578243 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578243 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mixer.v 1 1 " "Found 1 design units, including 1 entities, in source file mixer.v" { { "Info" "ISGN_ENTITY_NAME" "1 mixer " "Found entity 1: mixer" { } { { "mixer.v" "" { Text "C:/FPGA/mixer.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578260 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578260 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux16.v 1 1 " "Found 1 design units, including 1 entities, in source file mux16.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux16 " "Found entity 1: mux16" { } { { "mux16.v" "" { Text "C:/FPGA/mux16.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578279 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578279 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "main_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file main_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 MAIN_PLL " "Found entity 1: MAIN_PLL" { } { { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578299 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578299 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux14.v 1 1 " "Found 1 design units, including 1 entities, in source file mux14.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux14 " "Found entity 1: mux14" { } { { "mux14.v" "" { Text "C:/FPGA/mux14.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578318 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578318 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux1.v 1 1 " "Found 1 design units, including 1 entities, in source file mux1.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux1 " "Found entity 1: mux1" { } { { "mux1.v" "" { Text "C:/FPGA/mux1.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578337 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578337 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_mixer.v 1 1 " "Found 1 design units, including 1 entities, in source file tx_mixer.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_mixer " "Found entity 1: tx_mixer" { } { { "tx_mixer.v" "" { Text "C:/FPGA/tx_mixer.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578357 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578357 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_summator.v 1 1 " "Found 1 design units, including 1 entities, in source file tx_summator.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_summator " "Found entity 1: tx_summator" { } { { "tx_summator.v" "" { Text "C:/FPGA/tx_summator.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578377 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578377 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adc_latch.v 1 1 " "Found 1 design units, including 1 entities, in source file adc_latch.v" { { "Info" "ISGN_ENTITY_NAME" "1 ADC_Latch " "Found entity 1: ADC_Latch" { } { { "ADC_Latch.v" "" { Text "C:/FPGA/ADC_Latch.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578399 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578399 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dac_null.v 1 1 " "Found 1 design units, including 1 entities, in source file dac_null.v" { { "Info" "ISGN_ENTITY_NAME" "1 dac_null " "Found entity 1: dac_null" { } { { "dac_null.v" "" { Text "C:/FPGA/dac_null.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578417 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578417 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp.v 1 1 " "Found 1 design units, including 1 entities, in source file rx_ciccomp.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_ciccomp " "Found entity 1: rx_ciccomp" { } { { "rx_ciccomp.v" "" { Text "C:/FPGA/rx_ciccomp.v" 8 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603578426 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603578426 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/dspba_library_package.vhd 1 0 " "Found 1 design units, including 0 entities, in source file rx_ciccomp/dspba_library_package.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dspba_library_package (rx_ciccomp) " "Found design unit 1: dspba_library_package (rx_ciccomp)" { } { { "rx_ciccomp/dspba_library_package.vhd" "" { Text "C:/FPGA/rx_ciccomp/dspba_library_package.vhd" 17 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579862 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603579862 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/dspba_library.vhd 6 3 " "Found 6 design units, including 3 entities, in source file rx_ciccomp/dspba_library.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dspba_delay-delay " "Found design unit 1: dspba_delay-delay" { } { { "rx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/rx_ciccomp/dspba_library.vhd" 34 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579878 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 dspba_sync_reg-sync_reg " "Found design unit 2: dspba_sync_reg-sync_reg" { } { { "rx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/rx_ciccomp/dspba_library.vhd" 117 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579878 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 dspba_pipe-rtl " "Found design unit 3: dspba_pipe-rtl" { } { { "rx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/rx_ciccomp/dspba_library.vhd" 356 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579878 ""} { "Info" "ISGN_ENTITY_NAME" "1 dspba_delay " "Found entity 1: dspba_delay" { } { { "rx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/rx_ciccomp/dspba_library.vhd" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579878 ""} { "Info" "ISGN_ENTITY_NAME" "2 dspba_sync_reg " "Found entity 2: dspba_sync_reg" { } { { "rx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/rx_ciccomp/dspba_library.vhd" 93 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579878 ""} { "Info" "ISGN_ENTITY_NAME" "3 dspba_pipe " "Found entity 3: dspba_pipe" { } { { "rx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/rx_ciccomp/dspba_library.vhd" 343 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579878 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603579878 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd 2 0 " "Found 2 design units, including 0 entities, in source file rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_math_pkg_hpfir (rx_ciccomp) " "Found design unit 1: auk_dspip_math_pkg_hpfir (rx_ciccomp)" { } { { "rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" 54 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579896 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_dspip_math_pkg_hpfir-body " "Found design unit 2: auk_dspip_math_pkg_hpfir-body" { } { { "rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" 131 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579896 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603579896 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd 1 0 " "Found 1 design units, including 0 entities, in source file rx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_lib_pkg_hpfir (rx_ciccomp) " "Found design unit 1: auk_dspip_lib_pkg_hpfir (rx_ciccomp)" { } { { "rx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd" 22 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579914 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603579914 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_controller_hpfir-struct " "Found design unit 1: auk_dspip_avalon_streaming_controller_hpfir-struct" { } { { "rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579931 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_controller_hpfir " "Found entity 1: auk_dspip_avalon_streaming_controller_hpfir" { } { { "rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579931 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603579931 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_sink_hpfir-rtl " "Found design unit 1: auk_dspip_avalon_streaming_sink_hpfir-rtl" { } { { "rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" 106 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579949 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_sink_hpfir " "Found entity 1: auk_dspip_avalon_streaming_sink_hpfir" { } { { "rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" 56 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579949 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603579949 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_source_hpfir-rtl " "Found design unit 1: auk_dspip_avalon_streaming_source_hpfir-rtl" { } { { "rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" 109 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579967 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_source_hpfir " "Found entity 1: auk_dspip_avalon_streaming_source_hpfir" { } { { "rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" 70 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579967 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603579967 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/auk_dspip_roundsat_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rx_ciccomp/auk_dspip_roundsat_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_roundsat_hpfir-beh " "Found design unit 1: auk_dspip_roundsat_hpfir-beh" { } { { "rx_ciccomp/auk_dspip_roundsat_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_roundsat_hpfir.vhd" 57 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579982 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_roundsat_hpfir " "Found entity 1: auk_dspip_roundsat_hpfir" { } { { "rx_ciccomp/auk_dspip_roundsat_hpfir.vhd" "" { Text "C:/FPGA/rx_ciccomp/auk_dspip_roundsat_hpfir.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603579982 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603579982 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file rx_ciccomp/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "rx_ciccomp/altera_avalon_sc_fifo.v" "" { Text "C:/FPGA/rx_ciccomp/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580012 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580012 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx_ciccomp_0002_rtl_core-normal " "Found design unit 1: rx_ciccomp_0002_rtl_core-normal" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 47 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580029 ""} { "Info" "ISGN_ENTITY_NAME" "1 rx_ciccomp_0002_rtl_core " "Found entity 1: rx_ciccomp_0002_rtl_core" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580029 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580029 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/rx_ciccomp_0002_ast.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rx_ciccomp/rx_ciccomp_0002_ast.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx_ciccomp_0002_ast-struct " "Found design unit 1: rx_ciccomp_0002_ast-struct" { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 55 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580046 ""} { "Info" "ISGN_ENTITY_NAME" "1 rx_ciccomp_0002_ast " "Found entity 1: rx_ciccomp_0002_ast" { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580046 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580046 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rx_ciccomp/rx_ciccomp_0002.vhd 2 1 " "Found 2 design units, including 1 entities, in source file rx_ciccomp/rx_ciccomp_0002.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx_ciccomp_0002-syn " "Found design unit 1: rx_ciccomp_0002-syn" { } { { "rx_ciccomp/rx_ciccomp_0002.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd" 33 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580062 ""} { "Info" "ISGN_ENTITY_NAME" "1 rx_ciccomp_0002 " "Found entity 1: rx_ciccomp_0002" { } { { "rx_ciccomp/rx_ciccomp_0002.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580062 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580062 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp.v 1 1 " "Found 1 design units, including 1 entities, in source file tx_ciccomp.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_ciccomp " "Found entity 1: tx_ciccomp" { } { { "tx_ciccomp.v" "" { Text "C:/FPGA/tx_ciccomp.v" 8 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580072 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580072 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/dspba_library_package.vhd 1 0 " "Found 1 design units, including 0 entities, in source file tx_ciccomp/dspba_library_package.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dspba_library_package (tx_ciccomp) " "Found design unit 1: dspba_library_package (tx_ciccomp)" { } { { "tx_ciccomp/dspba_library_package.vhd" "" { Text "C:/FPGA/tx_ciccomp/dspba_library_package.vhd" 17 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580083 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580083 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/dspba_library.vhd 6 3 " "Found 6 design units, including 3 entities, in source file tx_ciccomp/dspba_library.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dspba_delay-delay " "Found design unit 1: dspba_delay-delay" { } { { "tx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/tx_ciccomp/dspba_library.vhd" 34 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580100 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 dspba_sync_reg-sync_reg " "Found design unit 2: dspba_sync_reg-sync_reg" { } { { "tx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/tx_ciccomp/dspba_library.vhd" 117 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580100 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 dspba_pipe-rtl " "Found design unit 3: dspba_pipe-rtl" { } { { "tx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/tx_ciccomp/dspba_library.vhd" 356 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580100 ""} { "Info" "ISGN_ENTITY_NAME" "1 dspba_delay " "Found entity 1: dspba_delay" { } { { "tx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/tx_ciccomp/dspba_library.vhd" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580100 ""} { "Info" "ISGN_ENTITY_NAME" "2 dspba_sync_reg " "Found entity 2: dspba_sync_reg" { } { { "tx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/tx_ciccomp/dspba_library.vhd" 93 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580100 ""} { "Info" "ISGN_ENTITY_NAME" "3 dspba_pipe " "Found entity 3: dspba_pipe" { } { { "tx_ciccomp/dspba_library.vhd" "" { Text "C:/FPGA/tx_ciccomp/dspba_library.vhd" 343 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580100 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580100 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd 2 0 " "Found 2 design units, including 0 entities, in source file tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_math_pkg_hpfir (tx_ciccomp) " "Found design unit 1: auk_dspip_math_pkg_hpfir (tx_ciccomp)" { } { { "tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" 54 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580118 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_dspip_math_pkg_hpfir-body " "Found design unit 2: auk_dspip_math_pkg_hpfir-body" { } { { "tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_math_pkg_hpfir.vhd" 131 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580118 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580118 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd 1 0 " "Found 1 design units, including 0 entities, in source file tx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_lib_pkg_hpfir (tx_ciccomp) " "Found design unit 1: auk_dspip_lib_pkg_hpfir (tx_ciccomp)" { } { { "tx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_lib_pkg_hpfir.vhd" 22 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580137 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580137 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_controller_hpfir-struct " "Found design unit 1: auk_dspip_avalon_streaming_controller_hpfir-struct" { } { { "tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580146 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_controller_hpfir " "Found entity 1: auk_dspip_avalon_streaming_controller_hpfir" { } { { "tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_controller_hpfir.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580146 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580146 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_sink_hpfir-rtl " "Found design unit 1: auk_dspip_avalon_streaming_sink_hpfir-rtl" { } { { "tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" 106 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580162 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_sink_hpfir " "Found entity 1: auk_dspip_avalon_streaming_sink_hpfir" { } { { "tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_sink_hpfir.vhd" 56 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580162 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580162 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_source_hpfir-rtl " "Found design unit 1: auk_dspip_avalon_streaming_source_hpfir-rtl" { } { { "tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" 109 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580179 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_source_hpfir " "Found entity 1: auk_dspip_avalon_streaming_source_hpfir" { } { { "tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd" 70 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580179 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580179 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/auk_dspip_roundsat_hpfir.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tx_ciccomp/auk_dspip_roundsat_hpfir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_roundsat_hpfir-beh " "Found design unit 1: auk_dspip_roundsat_hpfir-beh" { } { { "tx_ciccomp/auk_dspip_roundsat_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_roundsat_hpfir.vhd" 57 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580188 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_roundsat_hpfir " "Found entity 1: auk_dspip_roundsat_hpfir" { } { { "tx_ciccomp/auk_dspip_roundsat_hpfir.vhd" "" { Text "C:/FPGA/tx_ciccomp/auk_dspip_roundsat_hpfir.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580188 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580188 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file tx_ciccomp/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "tx_ciccomp/altera_avalon_sc_fifo.v" "" { Text "C:/FPGA/tx_ciccomp/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580218 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580218 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tx_ciccomp_0002_rtl_core-normal " "Found design unit 1: tx_ciccomp_0002_rtl_core-normal" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 47 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580236 ""} { "Info" "ISGN_ENTITY_NAME" "1 tx_ciccomp_0002_rtl_core " "Found entity 1: tx_ciccomp_0002_rtl_core" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580236 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580236 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/tx_ciccomp_0002_ast.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tx_ciccomp/tx_ciccomp_0002_ast.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tx_ciccomp_0002_ast-struct " "Found design unit 1: tx_ciccomp_0002_ast-struct" { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 55 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580252 ""} { "Info" "ISGN_ENTITY_NAME" "1 tx_ciccomp_0002_ast " "Found entity 1: tx_ciccomp_0002_ast" { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580252 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580252 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_ciccomp/tx_ciccomp_0002.vhd 2 1 " "Found 2 design units, including 1 entities, in source file tx_ciccomp/tx_ciccomp_0002.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tx_ciccomp_0002-syn " "Found design unit 1: tx_ciccomp_0002-syn" { } { { "tx_ciccomp/tx_ciccomp_0002.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002.vhd" 33 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580268 ""} { "Info" "ISGN_ENTITY_NAME" "1 tx_ciccomp_0002 " "Found entity 1: tx_ciccomp_0002" { } { { "tx_ciccomp/tx_ciccomp_0002.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002.vhd" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580268 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580268 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "diffclock_buff.v 2 2 " "Found 2 design units, including 2 entities, in source file diffclock_buff.v" { { "Info" "ISGN_ENTITY_NAME" "1 diffclock_buff_iobuf_in_k0j " "Found entity 1: diffclock_buff_iobuf_in_k0j" { } { { "diffclock_buff.v" "" { Text "C:/FPGA/diffclock_buff.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580386 ""} { "Info" "ISGN_ENTITY_NAME" "2 diffclock_buff " "Found entity 2: diffclock_buff" { } { { "diffclock_buff.v" "" { Text "C:/FPGA/diffclock_buff.v" 82 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580386 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580386 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dcdc_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file dcdc_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 dcdc_pll " "Found entity 1: dcdc_pll" { } { { "dcdc_pll.v" "" { Text "C:/FPGA/dcdc_pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580409 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580409 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tx_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file tx_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_pll " "Found entity 1: tx_pll" { } { { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580430 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580430 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/clock_buffer/clock_buffer.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/clock_buffer/clock_buffer.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_buffer " "Found entity 1: clock_buffer" { } { { "db/ip/clock_buffer/clock_buffer.v" "" { Text "C:/FPGA/db/ip/clock_buffer/clock_buffer.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580450 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580450 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_buffer_altclkctrl_0_sub " "Found entity 1: clock_buffer_altclkctrl_0_sub" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580541 ""} { "Info" "ISGN_ENTITY_NAME" "2 clock_buffer_altclkctrl_0 " "Found entity 2: clock_buffer_altclkctrl_0" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 89 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580541 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580541 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/rx_cic.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/rx_cic.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_cic " "Found entity 1: rx_cic" { } { { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603580562 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603580562 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/alt_cic_core.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_core.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_core " "Found entity 1: alt_cic_core" { } { { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603581437 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603581437 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/alt_cic_dec_miso.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_dec_miso.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_dec_miso " "Found entity 1: alt_cic_dec_miso" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_miso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_miso.sv" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603581599 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603581599 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_dec_siso " "Found entity 1: alt_cic_dec_siso" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603581757 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603581757 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/alt_cic_int_simo.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_int_simo.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_int_simo " "Found entity 1: alt_cic_int_simo" { } { { "db/ip/rx_cic/submodules/alt_cic_int_simo.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_int_simo.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603581918 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603581918 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/alt_cic_int_siso.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/alt_cic_int_siso.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_int_siso " "Found entity 1: alt_cic_int_siso" { } { { "db/ip/rx_cic/submodules/alt_cic_int_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_int_siso.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582060 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603582060 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/alt_dsp_cic_common_pkg.sv 1 0 " "Found 1 design units, including 0 entities, in source file db/ip/rx_cic/submodules/alt_dsp_cic_common_pkg.sv" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alt_dsp_cic_common_pkg (SystemVerilog) (rx_cic) " "Found design unit 1: alt_dsp_cic_common_pkg (SystemVerilog) (rx_cic)" { } { { "db/ip/rx_cic/submodules/alt_dsp_cic_common_pkg.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_dsp_cic_common_pkg.sv" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582178 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603582178 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_controller-struct " "Found design unit 1: auk_dspip_avalon_streaming_controller-struct" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" 53 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582327 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_controller " "Found entity 1: auk_dspip_avalon_streaming_controller" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582327 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603582327 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_sink-rtl " "Found design unit 1: auk_dspip_avalon_streaming_sink-rtl" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582450 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_sink " "Found entity 1: auk_dspip_avalon_streaming_sink" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582450 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603582450 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_small_fifo-arch " "Found design unit 1: auk_dspip_avalon_streaming_small_fifo-arch" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" 50 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582576 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_small_fifo " "Found entity 1: auk_dspip_avalon_streaming_small_fifo" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582576 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603582576 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_source-rtl " "Found design unit 1: auk_dspip_avalon_streaming_source-rtl" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 57 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582701 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_source " "Found entity 1: auk_dspip_avalon_streaming_source" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582701 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603582701 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_channel_buffer-SYN " "Found design unit 1: auk_dspip_channel_buffer-SYN" { } { { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 47 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582827 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_channel_buffer " "Found entity 1: auk_dspip_channel_buffer" { } { { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582827 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603582827 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_cic_lib_pkg.vhd 1 0 " "Found 1 design units, including 0 entities, in source file db/ip/rx_cic/submodules/auk_dspip_cic_lib_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_cic_lib_pkg (rx_cic) " "Found design unit 1: auk_dspip_cic_lib_pkg (rx_cic)" { } { { "db/ip/rx_cic/submodules/auk_dspip_cic_lib_pkg.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_cic_lib_pkg.vhd" 23 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582941 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603582941 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_delay.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_delay.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_delay-rtl " "Found design unit 1: auk_dspip_delay-rtl" { } { { "db/ip/rx_cic/submodules/auk_dspip_delay.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_delay.vhd" 79 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582955 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_delay " "Found entity 1: auk_dspip_delay" { } { { "db/ip/rx_cic/submodules/auk_dspip_delay.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_delay.vhd" 52 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603582955 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603582955 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_differentiator-SYN " "Found design unit 1: auk_dspip_differentiator-SYN" { } { { "db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583092 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_differentiator " "Found entity 1: auk_dspip_differentiator" { } { { "db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_differentiator.vhd" 57 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583092 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583092 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_downsample.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_downsample.sv" { { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_downsample " "Found entity 1: auk_dspip_downsample" { } { { "db/ip/rx_cic/submodules/auk_dspip_downsample.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583216 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583216 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_fastadd-beh " "Found design unit 1: auk_dspip_fastadd-beh" { } { { "db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd" 36 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583223 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_fastadd " "Found entity 1: auk_dspip_fastadd" { } { { "db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_fastadd.vhd" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583223 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583223 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_fastaddsub-beh " "Found design unit 1: auk_dspip_fastaddsub-beh" { } { { "db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd" 87 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583229 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_fastaddsub " "Found entity 1: auk_dspip_fastaddsub" { } { { "db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_fastaddsub.vhd" 69 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583229 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583229 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_integrator.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_integrator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_integrator-SYN " "Found design unit 1: auk_dspip_integrator-SYN" { } { { "db/ip/rx_cic/submodules/auk_dspip_integrator.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_integrator.vhd" 74 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583354 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_integrator " "Found entity 1: auk_dspip_integrator" { } { { "db/ip/rx_cic/submodules/auk_dspip_integrator.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_integrator.vhd" 53 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583354 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583354 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd 1 0 " "Found 1 design units, including 0 entities, in source file db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_lib_pkg (rx_cic) " "Found design unit 1: auk_dspip_lib_pkg (rx_cic)" { } { { "db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_lib_pkg.vhd" 28 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583368 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583368 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd 2 0 " "Found 2 design units, including 0 entities, in source file db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_math_pkg (rx_cic) " "Found design unit 1: auk_dspip_math_pkg (rx_cic)" { } { { "db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd" 51 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583385 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_dspip_math_pkg-body " "Found design unit 2: auk_dspip_math_pkg-body" { } { { "db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_math_pkg.vhd" 128 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583385 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583385 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_pipelined_adder-rtl " "Found design unit 1: auk_dspip_pipelined_adder-rtl" { } { { "db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd" 80 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583401 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_pipelined_adder " "Found entity 1: auk_dspip_pipelined_adder" { } { { "db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_pipelined_adder.vhd" 57 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583401 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583401 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_roundsat-beh " "Found design unit 1: auk_dspip_roundsat-beh" { } { { "db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd" 61 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583415 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_roundsat " "Found entity 1: auk_dspip_roundsat" { } { { "db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_roundsat.vhd" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583415 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583415 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd 2 0 " "Found 2 design units, including 0 entities, in source file db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_text_pkg (rx_cic) " "Found design unit 1: auk_dspip_text_pkg (rx_cic)" { } { { "db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd" 60 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583421 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_dspip_text_pkg-body " "Found design unit 2: auk_dspip_text_pkg-body" { } { { "db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_text_pkg.vhd" 76 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583421 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583421 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_upsample.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_upsample.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_upsample-SYN " "Found design unit 1: auk_dspip_upsample-SYN" { } { { "db/ip/rx_cic/submodules/auk_dspip_upsample.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_upsample.vhd" 59 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583527 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_upsample " "Found entity 1: auk_dspip_upsample" { } { { "db/ip/rx_cic/submodules/auk_dspip_upsample.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_upsample.vhd" 44 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583527 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583527 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/auk_dspip_variable_downsample.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/auk_dspip_variable_downsample.sv" { { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_variable_downsample " "Found entity 1: auk_dspip_variable_downsample" { } { { "db/ip/rx_cic/submodules/auk_dspip_variable_downsample.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_variable_downsample.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583650 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583650 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/counter_module.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/counter_module.sv" { { "Info" "ISGN_ENTITY_NAME" "1 counter_module " "Found entity 1: counter_module" { } { { "db/ip/rx_cic/submodules/counter_module.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/counter_module.sv" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583788 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/hyper_pipeline_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/hyper_pipeline_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 hyper_pipeline_interface " "Found entity 1: hyper_pipeline_interface" { } { { "db/ip/rx_cic/submodules/hyper_pipeline_interface.v" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/hyper_pipeline_interface.v" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583911 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583911 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rx_cic_cic_ii_0 " "Found entity 1: rx_cic_cic_ii_0" { } { { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603583935 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603583935 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/alt_cic_core.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_core.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_core " "Found entity 1: alt_cic_core" { } { { "db/ip/tx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603584105 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603584105 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/alt_cic_dec_miso.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_dec_miso.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_dec_miso " "Found entity 1: alt_cic_dec_miso" { } { { "db/ip/tx_cic/submodules/alt_cic_dec_miso.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_dec_miso.sv" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603584281 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603584281 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/alt_cic_dec_siso.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_dec_siso.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_dec_siso " "Found entity 1: alt_cic_dec_siso" { } { { "db/ip/tx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_dec_siso.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603584450 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603584450 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/alt_cic_int_simo.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_int_simo.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_int_simo " "Found entity 1: alt_cic_int_simo" { } { { "db/ip/tx_cic/submodules/alt_cic_int_simo.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_simo.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603584622 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603584622 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/alt_cic_int_siso.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/alt_cic_int_siso.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_cic_int_siso " "Found entity 1: alt_cic_int_siso" { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603584778 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603584778 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/alt_dsp_cic_common_pkg.sv 1 0 " "Found 1 design units, including 0 entities, in source file db/ip/tx_cic/submodules/alt_dsp_cic_common_pkg.sv" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alt_dsp_cic_common_pkg (SystemVerilog) (tx_cic) " "Found design unit 1: alt_dsp_cic_common_pkg (SystemVerilog) (tx_cic)" { } { { "db/ip/tx_cic/submodules/alt_dsp_cic_common_pkg.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_dsp_cic_common_pkg.sv" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603584900 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603584900 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_controller-struct " "Found design unit 1: auk_dspip_avalon_streaming_controller-struct" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" 53 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585038 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_controller " "Found entity 1: auk_dspip_avalon_streaming_controller" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585038 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603585038 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_sink-rtl " "Found design unit 1: auk_dspip_avalon_streaming_sink-rtl" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 64 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585165 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_sink " "Found entity 1: auk_dspip_avalon_streaming_sink" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585165 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603585165 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_small_fifo-arch " "Found design unit 1: auk_dspip_avalon_streaming_small_fifo-arch" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" 50 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585287 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_small_fifo " "Found entity 1: auk_dspip_avalon_streaming_small_fifo" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_small_fifo.vhd" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585287 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603585287 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_avalon_streaming_source-rtl " "Found design unit 1: auk_dspip_avalon_streaming_source-rtl" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 57 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585423 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_avalon_streaming_source " "Found entity 1: auk_dspip_avalon_streaming_source" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585423 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603585423 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_channel_buffer-SYN " "Found design unit 1: auk_dspip_channel_buffer-SYN" { } { { "db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd" 47 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585540 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_channel_buffer " "Found entity 1: auk_dspip_channel_buffer" { } { { "db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_channel_buffer.vhd" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585540 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603585540 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_cic_lib_pkg.vhd 1 0 " "Found 1 design units, including 0 entities, in source file db/ip/tx_cic/submodules/auk_dspip_cic_lib_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_cic_lib_pkg (tx_cic) " "Found design unit 1: auk_dspip_cic_lib_pkg (tx_cic)" { } { { "db/ip/tx_cic/submodules/auk_dspip_cic_lib_pkg.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_cic_lib_pkg.vhd" 23 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585660 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603585660 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_delay.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_delay.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_delay-rtl " "Found design unit 1: auk_dspip_delay-rtl" { } { { "db/ip/tx_cic/submodules/auk_dspip_delay.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_delay.vhd" 79 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585674 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_delay " "Found entity 1: auk_dspip_delay" { } { { "db/ip/tx_cic/submodules/auk_dspip_delay.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_delay.vhd" 52 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585674 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603585674 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_differentiator-SYN " "Found design unit 1: auk_dspip_differentiator-SYN" { } { { "db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585802 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_differentiator " "Found entity 1: auk_dspip_differentiator" { } { { "db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd" 57 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585802 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603585802 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_downsample.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_downsample.sv" { { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_downsample " "Found entity 1: auk_dspip_downsample" { } { { "db/ip/tx_cic/submodules/auk_dspip_downsample.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_downsample.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585930 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603585930 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_fastadd-beh " "Found design unit 1: auk_dspip_fastadd-beh" { } { { "db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd" 36 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585936 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_fastadd " "Found entity 1: auk_dspip_fastadd" { } { { "db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_fastadd.vhd" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585936 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603585936 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_fastaddsub-beh " "Found design unit 1: auk_dspip_fastaddsub-beh" { } { { "db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd" 87 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585942 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_fastaddsub " "Found entity 1: auk_dspip_fastaddsub" { } { { "db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_fastaddsub.vhd" 69 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603585942 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603585942 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_integrator.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_integrator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_integrator-SYN " "Found design unit 1: auk_dspip_integrator-SYN" { } { { "db/ip/tx_cic/submodules/auk_dspip_integrator.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_integrator.vhd" 74 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586075 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_integrator " "Found entity 1: auk_dspip_integrator" { } { { "db/ip/tx_cic/submodules/auk_dspip_integrator.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_integrator.vhd" 53 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586075 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603586075 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd 1 0 " "Found 1 design units, including 0 entities, in source file db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_lib_pkg (tx_cic) " "Found design unit 1: auk_dspip_lib_pkg (tx_cic)" { } { { "db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_lib_pkg.vhd" 28 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586089 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603586089 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd 2 0 " "Found 2 design units, including 0 entities, in source file db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_math_pkg (tx_cic) " "Found design unit 1: auk_dspip_math_pkg (tx_cic)" { } { { "db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd" 51 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586103 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_dspip_math_pkg-body " "Found design unit 2: auk_dspip_math_pkg-body" { } { { "db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_math_pkg.vhd" 128 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586103 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603586103 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_pipelined_adder-rtl " "Found design unit 1: auk_dspip_pipelined_adder-rtl" { } { { "db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd" 80 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586129 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_pipelined_adder " "Found entity 1: auk_dspip_pipelined_adder" { } { { "db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_pipelined_adder.vhd" 57 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586129 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603586129 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_roundsat-beh " "Found design unit 1: auk_dspip_roundsat-beh" { } { { "db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd" 61 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586146 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_roundsat " "Found entity 1: auk_dspip_roundsat" { } { { "db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_roundsat.vhd" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586146 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603586146 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd 2 0 " "Found 2 design units, including 0 entities, in source file db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_text_pkg (tx_cic) " "Found design unit 1: auk_dspip_text_pkg (tx_cic)" { } { { "db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd" 60 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586152 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 auk_dspip_text_pkg-body " "Found design unit 2: auk_dspip_text_pkg-body" { } { { "db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_text_pkg.vhd" 76 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586152 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603586152 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_upsample.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_upsample.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 auk_dspip_upsample-SYN " "Found design unit 1: auk_dspip_upsample-SYN" { } { { "db/ip/tx_cic/submodules/auk_dspip_upsample.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_upsample.vhd" 59 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586268 ""} { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_upsample " "Found entity 1: auk_dspip_upsample" { } { { "db/ip/tx_cic/submodules/auk_dspip_upsample.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_upsample.vhd" 44 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586268 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603586268 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/auk_dspip_variable_downsample.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/auk_dspip_variable_downsample.sv" { { "Info" "ISGN_ENTITY_NAME" "1 auk_dspip_variable_downsample " "Found entity 1: auk_dspip_variable_downsample" { } { { "db/ip/tx_cic/submodules/auk_dspip_variable_downsample.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_variable_downsample.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586399 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603586399 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/counter_module.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/counter_module.sv" { { "Info" "ISGN_ENTITY_NAME" "1 counter_module " "Found entity 1: counter_module" { } { { "db/ip/tx_cic/submodules/counter_module.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/counter_module.sv" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586534 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603586534 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/hyper_pipeline_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/hyper_pipeline_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 hyper_pipeline_interface " "Found entity 1: hyper_pipeline_interface" { } { { "db/ip/tx_cic/submodules/hyper_pipeline_interface.v" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/hyper_pipeline_interface.v" 20 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586659 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603586659 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 tx_cic_cic_ii_0 " "Found entity 1: tx_cic_cic_ii_0" { } { { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603586685 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_cic/tx_cic.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_cic/tx_cic.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_cic " "Found entity 1: tx_cic" { } { { "db/ip/tx_cic/tx_cic.v" "" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603586709 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603586709 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_altqmcpipe.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_altqmcpipe.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_altqmcpipe " "Found entity 1: asj_altqmcpipe" { } { { "db/ip/tx_nco/submodules/asj_altqmcpipe.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_altqmcpipe.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603587963 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603587963 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_gam_dp.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_gam_dp.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_gam_dp " "Found entity 1: asj_gam_dp" { } { { "db/ip/tx_nco/submodules/asj_gam_dp.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_gam_dp.v" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603588114 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603588114 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_as_m_cen " "Found entity 1: asj_nco_as_m_cen" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603588245 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603588245 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_as_m_dp_cen " "Found entity 1: asj_nco_as_m_dp_cen" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" 63 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603588396 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603588396 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_nco_derot.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_derot.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_derot " "Found entity 1: asj_nco_derot" { } { { "db/ip/tx_nco/submodules/asj_nco_derot.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_derot.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603588543 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603588543 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_nco_isdr.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_isdr.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_isdr " "Found entity 1: asj_nco_isdr" { } { { "db/ip/tx_nco/submodules/asj_nco_isdr.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_isdr.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603588727 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603588727 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_nco_madx_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_madx_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_madx_cen " "Found entity 1: asj_nco_madx_cen" { } { { "db/ip/tx_nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603588855 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603588855 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_nco_mady_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_mady_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_mady_cen " "Found entity 1: asj_nco_mady_cen" { } { { "db/ip/tx_nco/submodules/asj_nco_mady_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mady_cen.v" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603589001 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603589001 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/asj_nco_mob_w.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/asj_nco_mob_w.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_mob_w " "Found entity 1: asj_nco_mob_w" { } { { "db/ip/tx_nco/submodules/asj_nco_mob_w.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mob_w.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603589147 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603589147 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_nco_nco_ii_0 " "Found entity 1: tx_nco_nco_ii_0" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603589172 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603589172 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/tx_nco/tx_nco.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/tx_nco/tx_nco.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_nco " "Found entity 1: tx_nco" { } { { "db/ip/tx_nco/tx_nco.v" "" { Text "C:/FPGA/db/ip/tx_nco/tx_nco.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603589194 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603589194 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/nco.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/nco.v" { { "Info" "ISGN_ENTITY_NAME" "1 nco " "Found entity 1: nco" { } { { "db/ip/nco/nco.v" "" { Text "C:/FPGA/db/ip/nco/nco.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603589218 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603589218 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_altqmcpipe.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_altqmcpipe.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_altqmcpipe " "Found entity 1: asj_altqmcpipe" { } { { "db/ip/nco/submodules/asj_altqmcpipe.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_altqmcpipe.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603589364 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603589364 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_gam_dp.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_gam_dp.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_gam_dp " "Found entity 1: asj_gam_dp" { } { { "db/ip/nco/submodules/asj_gam_dp.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_gam_dp.v" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603589495 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603589495 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_nco_as_m_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_as_m_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_as_m_cen " "Found entity 1: asj_nco_as_m_cen" { } { { "db/ip/nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603589627 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603589627 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_nco_as_m_dp_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_as_m_dp_cen " "Found entity 1: asj_nco_as_m_dp_cen" { } { { "db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" 63 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603589783 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603589783 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_nco_derot.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_derot.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_derot " "Found entity 1: asj_nco_derot" { } { { "db/ip/nco/submodules/asj_nco_derot.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_derot.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603589916 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603589916 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_nco_isdr.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_isdr.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_isdr " "Found entity 1: asj_nco_isdr" { } { { "db/ip/nco/submodules/asj_nco_isdr.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_isdr.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603590048 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603590048 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_nco_madx_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_madx_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_madx_cen " "Found entity 1: asj_nco_madx_cen" { } { { "db/ip/nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603590189 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603590189 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_nco_mady_cen.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_mady_cen.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_mady_cen " "Found entity 1: asj_nco_mady_cen" { } { { "db/ip/nco/submodules/asj_nco_mady_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mady_cen.v" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603590322 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603590322 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/asj_nco_mob_w.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/asj_nco_mob_w.v" { { "Info" "ISGN_ENTITY_NAME" "1 asj_nco_mob_w " "Found entity 1: asj_nco_mob_w" { } { { "db/ip/nco/submodules/asj_nco_mob_w.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mob_w.v" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603590464 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603590464 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nco/submodules/nco_nco_ii_0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nco/submodules/nco_nco_ii_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 nco_nco_ii_0 " "Found entity 1: nco_nco_ii_0" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603590489 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603590489 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/debug/debug.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/debug/debug.v" { { "Info" "ISGN_ENTITY_NAME" "1 DEBUG " "Found entity 1: DEBUG" { } { { "db/ip/debug/debug.v" "" { Text "C:/FPGA/db/ip/debug/debug.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603590514 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603590514 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/debug/submodules/altsource_probe_top.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/debug/submodules/altsource_probe_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 altsource_probe_top " "Found entity 1: altsource_probe_top" { } { { "db/ip/debug/submodules/altsource_probe_top.v" "" { Text "C:/FPGA/db/ip/debug/submodules/altsource_probe_top.v" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603590532 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603590532 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/debug2/debug2.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/debug2/debug2.v" { { "Info" "ISGN_ENTITY_NAME" "1 DEBUG2 " "Found entity 1: DEBUG2" { } { { "db/ip/debug2/debug2.v" "" { Text "C:/FPGA/db/ip/debug2/debug2.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603590556 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603590556 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/debug2/submodules/altsource_probe_top.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/debug2/submodules/altsource_probe_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 altsource_probe_top " "Found entity 1: altsource_probe_top" { } { { "db/ip/debug2/submodules/altsource_probe_top.v" "" { Text "C:/FPGA/db/ip/debug2/submodules/altsource_probe_top.v" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603590576 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603590576 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "WOLF-LITE " "Elaborating entity \"WOLF-LITE\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1616603594175 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "stm32_interface stm32_interface:STM32_INTERFACE " "Elaborating entity \"stm32_interface\" for hierarchy \"stm32_interface:STM32_INTERFACE\"" { } { { "WOLF-LITE.bdf" "STM32_INTERFACE" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 144 3088 3376 704 "STM32_INTERFACE" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603594279 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_summator tx_summator:TX_SUMMATOR " "Elaborating entity \"tx_summator\" for hierarchy \"tx_summator:TX_SUMMATOR\"" { } { { "WOLF-LITE.bdf" "TX_SUMMATOR" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 5544 5704 280 "TX_SUMMATOR" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603594649 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component " "Elaborating entity \"lpm_add_sub\" for hierarchy \"tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component\"" { } { { "tx_summator.v" "LPM_ADD_SUB_component" { Text "C:/FPGA/tx_summator.v" 73 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603595025 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component " "Elaborated megafunction instantiation \"tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component\"" { } { { "tx_summator.v" "" { Text "C:/FPGA/tx_summator.v" 73 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603595074 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component " "Instantiated megafunction \"tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Parameter \"lpm_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595075 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO " "Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595075 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595075 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Parameter \"lpm_representation\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595075 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595075 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 32 " "Parameter \"lpm_width\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595075 ""} } { { "tx_summator.v" "" { Text "C:/FPGA/tx_summator.v" 73 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603595075 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_1vk.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_1vk.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_1vk " "Found entity 1: add_sub_1vk" { } { { "db/add_sub_1vk.tdf" "" { Text "C:/FPGA/db/add_sub_1vk.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603595234 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603595234 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_1vk tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component\|add_sub_1vk:auto_generated " "Elaborating entity \"add_sub_1vk\" for hierarchy \"tx_summator:TX_SUMMATOR\|lpm_add_sub:LPM_ADD_SUB_component\|add_sub_1vk:auto_generated\"" { } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603595247 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_pll tx_pll:TX_PLL " "Elaborating entity \"tx_pll\" for hierarchy \"tx_pll:TX_PLL\"" { } { { "WOLF-LITE.bdf" "TX_PLL" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 720 3080 3320 872 "TX_PLL" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603595361 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll tx_pll:TX_PLL\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"tx_pll:TX_PLL\|altpll:altpll_component\"" { } { { "tx_pll.v" "altpll_component" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603595728 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_pll:TX_PLL\|altpll:altpll_component " "Elaborated megafunction instantiation \"tx_pll:TX_PLL\|altpll:altpll_component\"" { } { { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603595765 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_pll:TX_PLL\|altpll:altpll_component " "Instantiated megafunction \"tx_pll:TX_PLL\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2 " "Parameter \"clk0_divide_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 5 " "Parameter \"clk0_multiply_by\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 15547 " "Parameter \"inclk0_input_frequency\" = \"15547\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=tx_pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=tx_pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_UNUSED " "Parameter \"port_clk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603595766 ""} } { { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603595766 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/tx_pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/tx_pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_pll_altpll " "Found entity 1: tx_pll_altpll" { } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603595944 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603595944 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_pll_altpll tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated " "Elaborating entity \"tx_pll_altpll\" for hierarchy \"tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603595963 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_buffer clock_buffer:SYSCLK_BUFFER " "Elaborating entity \"clock_buffer\" for hierarchy \"clock_buffer:SYSCLK_BUFFER\"" { } { { "WOLF-LITE.bdf" "SYSCLK_BUFFER" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 624 2416 2688 728 "SYSCLK_BUFFER" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603596081 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_buffer_altclkctrl_0 clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0 " "Elaborating entity \"clock_buffer_altclkctrl_0\" for hierarchy \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\"" { } { { "db/ip/clock_buffer/clock_buffer.v" "altclkctrl_0" { Text "C:/FPGA/db/ip/clock_buffer/clock_buffer.v" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603596121 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_buffer_altclkctrl_0_sub clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component " "Elaborating entity \"clock_buffer_altclkctrl_0_sub\" for hierarchy \"clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\"" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "clock_buffer_altclkctrl_0_sub_component" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 112 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603596157 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_mixer tx_mixer:TX_MIXER_I " "Elaborating entity \"tx_mixer\" for hierarchy \"tx_mixer:TX_MIXER_I\"" { } { { "WOLF-LITE.bdf" "TX_MIXER_I" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 56 5272 5440 184 "TX_MIXER_I" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603596211 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component " "Elaborating entity \"lpm_mult\" for hierarchy \"tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\"" { } { { "tx_mixer.v" "lpm_mult_component" { Text "C:/FPGA/tx_mixer.v" 63 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603596582 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\"" { } { { "tx_mixer.v" "" { Text "C:/FPGA/tx_mixer.v" 63 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603596613 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component " "Instantiated megafunction \"tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9 " "Parameter \"lpm_hint\" = \"DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603596613 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603596613 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Parameter \"lpm_representation\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603596613 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MULT " "Parameter \"lpm_type\" = \"LPM_MULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603596613 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widtha 16 " "Parameter \"lpm_widtha\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603596613 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthb 16 " "Parameter \"lpm_widthb\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603596613 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthp 32 " "Parameter \"lpm_widthp\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603596613 ""} } { { "tx_mixer.v" "" { Text "C:/FPGA/tx_mixer.v" 63 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603596613 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_abt.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_abt.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_abt " "Found entity 1: mult_abt" { } { { "db/mult_abt.tdf" "" { Text "C:/FPGA/db/mult_abt.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603596769 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603596769 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_abt tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_abt:auto_generated " "Elaborating entity \"mult_abt\" for hierarchy \"tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_abt:auto_generated\"" { } { { "lpm_mult.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 376 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603596786 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_cic tx_cic:TX_CIC_I " "Elaborating entity \"tx_cic\" for hierarchy \"tx_cic:TX_CIC_I\"" { } { { "WOLF-LITE.bdf" "TX_CIC_I" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -40 4928 5184 192 "TX_CIC_I" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603596891 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_cic_cic_ii_0 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0 " "Elaborating entity \"tx_cic_cic_ii_0\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\"" { } { { "db/ip/tx_cic/tx_cic.v" "cic_ii_0" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 31 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603596945 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_cic_core tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core " "Elaborating entity \"alt_cic_core\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\"" { } { { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "core" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603597053 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_sink tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink " "Elaborating entity \"auk_dspip_avalon_streaming_sink\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\"" { } { { "db/ip/tx_cic/submodules/alt_cic_core.sv" "input_sink" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603597222 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\"" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "sink_FIFO" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603598137 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO " "Elaborated megafunction instantiation \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\"" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603598160 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO " "Instantiated megafunction \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Parameter \"add_ram_output_register\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603598160 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "allow_rwcycle_when_full OFF " "Parameter \"allow_rwcycle_when_full\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603598160 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_empty_value 4 " "Parameter \"almost_empty_value\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603598160 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_full_value 0 " "Parameter \"almost_full_value\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603598160 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 8 " "Parameter \"lpm_numwords\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603598160 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603598160 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 18 " "Parameter \"lpm_width\" = \"18\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603598160 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 3 " "Parameter \"lpm_widthu\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603598160 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603598160 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603598160 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603598160 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603598160 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603598160 ""} } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603598160 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_gf71.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_gf71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_gf71 " "Found entity 1: scfifo_gf71" { } { { "db/scfifo_gf71.tdf" "" { Text "C:/FPGA/db/scfifo_gf71.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603598326 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603598326 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_gf71 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated " "Elaborating entity \"scfifo_gf71\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603598346 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_1lv.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_1lv.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_1lv " "Found entity 1: a_dpfifo_1lv" { } { { "db/a_dpfifo_1lv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603598433 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603598433 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_1lv tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo " "Elaborating entity \"a_dpfifo_1lv\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\"" { } { { "db/scfifo_gf71.tdf" "dpfifo" { Text "C:/FPGA/db/scfifo_gf71.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603598461 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_l7h1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_l7h1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_l7h1 " "Found entity 1: altsyncram_l7h1" { } { { "db/altsyncram_l7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_l7h1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603598606 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603598606 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_l7h1 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram " "Elaborating entity \"altsyncram_l7h1\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\"" { } { { "db/a_dpfifo_1lv.tdf" "FIFOram" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603598646 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_gs8.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_gs8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_gs8 " "Found entity 1: cmpr_gs8" { } { { "db/cmpr_gs8.tdf" "" { Text "C:/FPGA/db/cmpr_gs8.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603598797 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603598797 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_gs8 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cmpr_gs8:almost_full_comparer " "Elaborating entity \"cmpr_gs8\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cmpr_gs8:almost_full_comparer\"" { } { { "db/a_dpfifo_1lv.tdf" "almost_full_comparer" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 52 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603598840 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_gs8 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cmpr_gs8:two_comparison " "Elaborating entity \"cmpr_gs8\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cmpr_gs8:two_comparison\"" { } { { "db/a_dpfifo_1lv.tdf" "two_comparison" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 53 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603598910 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_r9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_r9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_r9b " "Found entity 1: cntr_r9b" { } { { "db/cntr_r9b.tdf" "" { Text "C:/FPGA/db/cntr_r9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603599040 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603599040 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_r9b tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cntr_r9b:rd_ptr_msb " "Elaborating entity \"cntr_r9b\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cntr_r9b:rd_ptr_msb\"" { } { { "db/a_dpfifo_1lv.tdf" "rd_ptr_msb" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 54 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603599079 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_8a7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_8a7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_8a7 " "Found entity 1: cntr_8a7" { } { { "db/cntr_8a7.tdf" "" { Text "C:/FPGA/db/cntr_8a7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603599211 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603599211 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_8a7 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cntr_8a7:usedw_counter " "Elaborating entity \"cntr_8a7\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cntr_8a7:usedw_counter\"" { } { { "db/a_dpfifo_1lv.tdf" "usedw_counter" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 55 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603599250 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_s9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_s9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_s9b " "Found entity 1: cntr_s9b" { } { { "db/cntr_s9b.tdf" "" { Text "C:/FPGA/db/cntr_s9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603599376 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603599376 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_s9b tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cntr_s9b:wr_ptr " "Elaborating entity \"cntr_s9b\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|cntr_s9b:wr_ptr\"" { } { { "db/a_dpfifo_1lv.tdf" "wr_ptr" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 56 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603599415 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_source tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0 " "Elaborating entity \"auk_dspip_avalon_streaming_source\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\"" { } { { "db/ip/tx_cic/submodules/alt_cic_core.sv" "output_source_0" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 358 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603599584 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\"" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "source_FIFO" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603600116 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO " "Elaborated megafunction instantiation \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\"" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603600139 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO " "Instantiated megafunction \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Parameter \"add_ram_output_register\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603600139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "allow_rwcycle_when_full OFF " "Parameter \"allow_rwcycle_when_full\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603600139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_empty_value 0 " "Parameter \"almost_empty_value\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603600139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_full_value 13 " "Parameter \"almost_full_value\" = \"13\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603600139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 21 " "Parameter \"lpm_numwords\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603600139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603600139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 17 " "Parameter \"lpm_width\" = \"17\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603600139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 5 " "Parameter \"lpm_widthu\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603600139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603600139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603600139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603600139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603600139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603600139 ""} } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603600139 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_ci71.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_ci71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_ci71 " "Found entity 1: scfifo_ci71" { } { { "db/scfifo_ci71.tdf" "" { Text "C:/FPGA/db/scfifo_ci71.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603600298 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603600298 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_ci71 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated " "Elaborating entity \"scfifo_ci71\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603600318 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_9qv.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_9qv.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_9qv " "Found entity 1: a_dpfifo_9qv" { } { { "db/a_dpfifo_9qv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603600404 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603600404 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_9qv tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo " "Elaborating entity \"a_dpfifo_9qv\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\"" { } { { "db/scfifo_ci71.tdf" "dpfifo" { Text "C:/FPGA/db/scfifo_ci71.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603600436 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_hah1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_hah1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_hah1 " "Found entity 1: altsyncram_hah1" { } { { "db/altsyncram_hah1.tdf" "" { Text "C:/FPGA/db/altsyncram_hah1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603600567 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603600567 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_hah1 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|altsyncram_hah1:FIFOram " "Elaborating entity \"altsyncram_hah1\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|altsyncram_hah1:FIFOram\"" { } { { "db/a_dpfifo_9qv.tdf" "FIFOram" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603600607 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_is8.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_is8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_is8 " "Found entity 1: cmpr_is8" { } { { "db/cmpr_is8.tdf" "" { Text "C:/FPGA/db/cmpr_is8.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603600741 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603600741 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_is8 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cmpr_is8:almost_full_comparer " "Elaborating entity \"cmpr_is8\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cmpr_is8:almost_full_comparer\"" { } { { "db/a_dpfifo_9qv.tdf" "almost_full_comparer" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 52 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603600781 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_is8 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cmpr_is8:two_comparison " "Elaborating entity \"cmpr_is8\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cmpr_is8:two_comparison\"" { } { { "db/a_dpfifo_9qv.tdf" "two_comparison" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 53 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603600852 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_t9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_t9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_t9b " "Found entity 1: cntr_t9b" { } { { "db/cntr_t9b.tdf" "" { Text "C:/FPGA/db/cntr_t9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603600981 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603600981 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_t9b tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cntr_t9b:rd_ptr_msb " "Elaborating entity \"cntr_t9b\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cntr_t9b:rd_ptr_msb\"" { } { { "db/a_dpfifo_9qv.tdf" "rd_ptr_msb" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 54 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603601021 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_aa7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_aa7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_aa7 " "Found entity 1: cntr_aa7" { } { { "db/cntr_aa7.tdf" "" { Text "C:/FPGA/db/cntr_aa7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603601152 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603601152 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_aa7 tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cntr_aa7:usedw_counter " "Elaborating entity \"cntr_aa7\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cntr_aa7:usedw_counter\"" { } { { "db/a_dpfifo_9qv.tdf" "usedw_counter" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 55 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603601192 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_u9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_u9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_u9b " "Found entity 1: cntr_u9b" { } { { "db/cntr_u9b.tdf" "" { Text "C:/FPGA/db/cntr_u9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603601325 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603601325 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_u9b tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cntr_u9b:wr_ptr " "Elaborating entity \"cntr_u9b\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|cntr_u9b:wr_ptr\"" { } { { "db/a_dpfifo_9qv.tdf" "wr_ptr" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 56 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603601366 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_controller tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller " "Elaborating entity \"auk_dspip_avalon_streaming_controller\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller\"" { } { { "db/ip/tx_cic/submodules/alt_cic_core.sv" "avalon_controller" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 408 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603601532 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_small_fifo tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller\|auk_dspip_avalon_streaming_small_fifo:ready_FIFO " "Elaborating entity \"auk_dspip_avalon_streaming_small_fifo\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller\|auk_dspip_avalon_streaming_small_fifo:ready_FIFO\"" { } { { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" "ready_FIFO" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" 196 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603601696 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_cic_int_siso tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one " "Elaborating entity \"alt_cic_int_siso\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\"" { } { { "db/ip/tx_cic/submodules/alt_cic_core.sv" "int_one" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 540 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603601900 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_module tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|counter_module:latency_cnt_inst " "Elaborating entity \"counter_module\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|counter_module:latency_cnt_inst\"" { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "latency_cnt_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 270 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603602132 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_module tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|counter_module:counter_fs_inst " "Elaborating entity \"counter_module\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|counter_module:counter_fs_inst\"" { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "counter_fs_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 298 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603602318 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_module tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|counter_module:counter_ch_inst " "Elaborating entity \"counter_module\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|counter_module:counter_ch_inst\"" { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "counter_ch_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 313 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603602434 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_differentiator tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_differentiator:COMB_LOOP\[0\].auk_dsp_diff " "Elaborating entity \"auk_dspip_differentiator\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_differentiator:COMB_LOOP\[0\].auk_dsp_diff\"" { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "COMB_LOOP\[0\].auk_dsp_diff" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 361 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603602552 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_delay tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_differentiator:COMB_LOOP\[0\].auk_dsp_diff\|auk_dspip_delay:\\glogic:u0 " "Elaborating entity \"auk_dspip_delay\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_differentiator:COMB_LOOP\[0\].auk_dsp_diff\|auk_dspip_delay:\\glogic:u0\"" { } { { "db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd" "\\glogic:u0" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_differentiator.vhd" 135 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603602676 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_upsample tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_upsample:first_upsample " "Elaborating entity \"auk_dspip_upsample\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_upsample:first_upsample\"" { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "first_upsample" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 379 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603603383 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_integrator tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_integrator:integrator_loop\[0\].auK_integrator " "Elaborating entity \"auk_dspip_integrator\" for hierarchy \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_int_siso:int_one\|auk_dspip_integrator:integrator_loop\[0\].auK_integrator\"" { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "integrator_loop\[0\].auK_integrator" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 408 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603603537 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_shifter data_shifter:TX_CICCOMP_GAINER " "Elaborating entity \"data_shifter\" for hierarchy \"data_shifter:TX_CICCOMP_GAINER\"" { } { { "WOLF-LITE.bdf" "TX_CICCOMP_GAINER" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 224 4464 4768 368 "TX_CICCOMP_GAINER" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603604318 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 data_shifter.v(18) " "Verilog HDL assignment warning at data_shifter.v(18): truncated value with size 32 to match size of target (1)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1616603604318 "|WOLF-LITE|data_shifter:TX_CICCOMP_GAINER"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 data_shifter.v(19) " "Verilog HDL assignment warning at data_shifter.v(19): truncated value with size 32 to match size of target (1)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 19 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1616603604318 "|WOLF-LITE|data_shifter:TX_CICCOMP_GAINER"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 data_shifter.v(20) " "Verilog HDL assignment warning at data_shifter.v(20): truncated value with size 32 to match size of target (16)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1616603604319 "|WOLF-LITE|data_shifter:TX_CICCOMP_GAINER"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 data_shifter.v(21) " "Verilog HDL assignment warning at data_shifter.v(21): truncated value with size 32 to match size of target (16)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 21 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1616603604319 "|WOLF-LITE|data_shifter:TX_CICCOMP_GAINER"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_ciccomp tx_ciccomp:TX_CICCOMP_I " "Elaborating entity \"tx_ciccomp\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\"" { } { { "WOLF-LITE.bdf" "TX_CICCOMP_I" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 24 3968 4352 240 "TX_CICCOMP_I" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603604349 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_ciccomp_0002 tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst " "Elaborating entity \"tx_ciccomp_0002\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\"" { } { { "tx_ciccomp.v" "tx_ciccomp_inst" { Text "C:/FPGA/tx_ciccomp.v" 28 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603604381 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "coeff_in_read_sig tx_ciccomp_0002.vhd(54) " "Verilog HDL or VHDL warning at tx_ciccomp_0002.vhd(54): object \"coeff_in_read_sig\" assigned a value but never read" { } { { "tx_ciccomp/tx_ciccomp_0002.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002.vhd" 54 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "Analysis & Synthesis" 0 -1 1616603604382 "|WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_ciccomp_0002_ast tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst " "Elaborating entity \"tx_ciccomp_0002_ast\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\"" { } { { "tx_ciccomp/tx_ciccomp_0002.vhd" "tx_ciccomp_0002_ast_inst" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002.vhd" 62 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603604419 ""} -{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "core_channel_out_core tx_ciccomp_0002_ast.vhd(208) " "VHDL Signal Declaration warning at tx_ciccomp_0002_ast.vhd(208): used implicit default value for signal \"core_channel_out_core\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 208 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 1 0 "Analysis & Synthesis" 0 -1 1616603604422 "|WOLF-LITE|tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_sink_hpfir tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_sink_hpfir:sink " "Elaborating entity \"auk_dspip_avalon_streaming_sink_hpfir\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_sink_hpfir:sink\"" { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "sink" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 89 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603604471 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_source_hpfir tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source " "Elaborating entity \"auk_dspip_avalon_streaming_source_hpfir\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\"" { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "source" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 109 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603604530 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_controller_hpfir tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_controller_hpfir:intf_ctrl " "Elaborating entity \"auk_dspip_avalon_streaming_controller_hpfir\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_controller_hpfir:intf_ctrl\"" { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "intf_ctrl" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 137 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603604581 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_ciccomp_0002_rtl_core tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core " "Elaborating entity \"tx_ciccomp_0002_rtl_core\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\"" { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "\\real_passthrough:hpfircore_core" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603604609 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_memread " "Elaborating entity \"dspba_delay\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_memread\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_memread" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 175 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603604682 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_compute " "Elaborating entity \"dspba_delay\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_compute\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_compute" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 180 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603604721 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_xIn_0_13 " "Elaborating entity \"dspba_delay\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_xIn_0_13\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "d_xIn_0_13" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 286 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603604790 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13 " "Elaborating entity \"dspba_delay\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "d_in0_m0_wi0_wo0_assign_id1_q_13" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 291 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603604843 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem " "Elaborating entity \"altsyncram\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_wi0_r0_memr0_dmem" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 313 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603605393 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem " "Elaborated megafunction instantiation \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 313 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603605424 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem " "Instantiated megafunction \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a UNUSED " "Parameter \"address_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_aclr_a UNUSED " "Parameter \"byteena_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_aclr_b NONE " "Parameter \"byteena_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_reg_b CLOCK0 " "Parameter \"byteena_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_core_a USE_INPUT_CLKEN " "Parameter \"clock_enable_core_a\" = \"USE_INPUT_CLKEN\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_core_b USE_INPUT_CLKEN " "Parameter \"clock_enable_core_b\" = \"USE_INPUT_CLKEN\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a NORMAL " "Parameter \"clock_enable_input_a\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b NORMAL " "Parameter \"clock_enable_input_b\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a NORMAL " "Parameter \"clock_enable_output_a\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b NORMAL " "Parameter \"clock_enable_output_b\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ecc_pipeline_stage_enabled FALSE " "Parameter \"ecc_pipeline_stage_enabled\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "enable_ecc FALSE " "Parameter \"enable_ecc\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "implement_in_les OFF " "Parameter \"implement_in_les\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a UNUSED " "Parameter \"indata_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Parameter \"init_file\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file_layout PORT_A " "Parameter \"init_file_layout\" = \"PORT_A\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 64 " "Parameter \"numwords_a\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 64 " "Parameter \"numwords_b\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type M9K " "Parameter \"ram_block_type\" = \"M9K\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_aclr_b NONE " "Parameter \"rdcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "stratixiv_m144k_allow_dual_clocks ON " "Parameter \"stratixiv_m144k_allow_dual_clocks\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_eccstatus 3 " "Parameter \"width_eccstatus\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 6 " "Parameter \"widthad_a\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 6 " "Parameter \"widthad_b\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a UNUSED " "Parameter \"wrcontrol_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605425 ""} } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 313 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603605425 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0mn3.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0mn3.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0mn3 " "Found entity 1: altsyncram_0mn3" { } { { "db/altsyncram_0mn3.tdf" "" { Text "C:/FPGA/db/altsyncram_0mn3.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603605618 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603605618 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0mn3 tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\|altsyncram_0mn3:auto_generated " "Elaborating entity \"altsyncram_0mn3\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\|altsyncram_0mn3:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603605635 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component " "Elaborating entity \"lpm_mult\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_mtree_mult1_0_component" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 446 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603605828 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component " "Elaborated megafunction instantiation \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 446 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603605854 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component " "Instantiated megafunction \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 8 " "Parameter \"LPM_WIDTHA\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 16 " "Parameter \"LPM_WIDTHB\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 24 " "Parameter \"LPM_WIDTHP\" = \"24\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_PIPELINE 2 " "Parameter \"LPM_PIPELINE\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_MULT " "Parameter \"LPM_TYPE\" = \"LPM_MULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605854 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5 " "Parameter \"LPM_HINT\" = \"DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603605854 ""} } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 446 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603605854 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_ncu.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_ncu.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_ncu " "Found entity 1: mult_ncu" { } { { "db/mult_ncu.tdf" "" { Text "C:/FPGA/db/mult_ncu.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603606001 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603606001 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_ncu tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component\|mult_ncu:auto_generated " "Elaborating entity \"mult_ncu\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_component\|mult_ncu:auto_generated\"" { } { { "lpm_mult.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 376 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603606017 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16 " "Elaborating entity \"dspba_delay\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "d_u0_m0_wo0_mtree_mult1_0_q_16" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 502 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603606149 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17 " "Elaborating entity \"dspba_delay\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|tx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17\"" { } { { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "d_u0_m0_wo0_accum_p1_of_2_q_17" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 537 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603606190 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_roundsat_hpfir tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_roundsat_hpfir:\\real_passthrough:gen_outp_blk:0:outp_blk " "Elaborating entity \"auk_dspip_roundsat_hpfir\" for hierarchy \"tx_ciccomp:TX_CICCOMP_I\|tx_ciccomp_0002:tx_ciccomp_inst\|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst\|auk_dspip_roundsat_hpfir:\\real_passthrough:gen_outp_blk:0:outp_blk\"" { } { { "tx_ciccomp/tx_ciccomp_0002_ast.vhd" "\\real_passthrough:gen_outp_blk:0:outp_blk" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd" 244 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603606236 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_nco tx_nco:TX_NCO " "Elaborating entity \"tx_nco\" for hierarchy \"tx_nco:TX_NCO\"" { } { { "WOLF-LITE.bdf" "TX_NCO" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 632 3792 4048 832 "TX_NCO" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603606856 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_nco_nco_ii_0 tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0 " "Elaborating entity \"tx_nco_nco_ii_0\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\"" { } { { "db/ip/tx_nco/tx_nco.v" "nco_ii_0" { Text "C:/FPGA/db/ip/tx_nco/tx_nco.v" 24 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603606924 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_altqmcpipe tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000 " "Elaborating entity \"asj_altqmcpipe\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "ux000" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 304 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603607049 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc " "Elaborating entity \"lpm_add_sub\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\"" { } { { "db/ip/tx_nco/submodules/asj_altqmcpipe.v" "acc" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_altqmcpipe.v" 63 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603607229 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\"" { } { { "db/ip/tx_nco/submodules/asj_altqmcpipe.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_altqmcpipe.v" 63 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603607255 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Parameter \"lpm_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603607255 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 22 " "Parameter \"lpm_width\" = \"22\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603607255 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603607255 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation UNSIGNED " "Parameter \"lpm_representation\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603607255 ""} } { { "db/ip/tx_nco/submodules/asj_altqmcpipe.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_altqmcpipe.v" 63 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603607255 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_u4i.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_u4i.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_u4i " "Found entity 1: add_sub_u4i" { } { { "db/add_sub_u4i.tdf" "" { Text "C:/FPGA/db/add_sub_u4i.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603607407 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603607407 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_u4i tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_u4i:auto_generated " "Elaborating entity \"add_sub_u4i\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\|add_sub_u4i:auto_generated\"" { } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603607429 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_gam_dp tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_gam_dp:ux008 " "Elaborating entity \"asj_gam_dp\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_gam_dp:ux008\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "ux008" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603607612 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_dp_cen tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220 " "Elaborating entity \"asj_nco_as_m_dp_cen\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "ux0220" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 338 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603607809 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\"" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" "altsyncram_component" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" 109 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603607993 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\"" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" 109 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603608026 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 11 " "Parameter \"widthad_b\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 2048 " "Parameter \"numwords_b\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file tx_nco_nco_ii_0_sin_c.hex " "Parameter \"init_file\" = \"tx_nco_nco_ii_0_sin_c.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603608026 ""} } { { "db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_dp_cen.v" 109 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603608026 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4k82.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4k82.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4k82 " "Found entity 1: altsyncram_4k82" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603608213 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603608213 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4k82 tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated " "Elaborating entity \"altsyncram_4k82\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603608234 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_cen tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122 " "Elaborating entity \"asj_nco_as_m_cen\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "ux0122" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 350 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603608940 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Elaborating entity \"altsyncram\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\"" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" "altsyncram_component0" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603609113 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\"" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603609151 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603609151 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603609151 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603609151 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603609151 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603609151 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603609151 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603609151 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603609151 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603609151 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603609151 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file tx_nco_nco_ii_0_sin_f.hex " "Parameter \"init_file\" = \"tx_nco_nco_ii_0_sin_f.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603609151 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603609151 ""} } { { "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603609151 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_u8a1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_u8a1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_u8a1 " "Found entity 1: altsyncram_u8a1" { } { { "db/altsyncram_u8a1.tdf" "" { Text "C:/FPGA/db/altsyncram_u8a1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603609335 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603609335 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_u8a1 tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_u8a1:auto_generated " "Elaborating entity \"altsyncram_u8a1\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_u8a1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603609356 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_cen tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123 " "Elaborating entity \"asj_nco_as_m_cen\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "ux0123" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 362 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603610075 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Elaborating entity \"altsyncram\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\"" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" "altsyncram_component0" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603610187 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\"" { } { { "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603610217 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603610217 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603610217 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603610217 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603610217 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603610217 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603610217 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603610217 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603610217 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603610217 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603610217 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file tx_nco_nco_ii_0_cos_f.hex " "Parameter \"init_file\" = \"tx_nco_nco_ii_0_cos_f.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603610217 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603610217 ""} } { { "db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603610217 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_p8a1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_p8a1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_p8a1 " "Found entity 1: altsyncram_p8a1" { } { { "db/altsyncram_p8a1.tdf" "" { Text "C:/FPGA/db/altsyncram_p8a1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603610419 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603610419 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_p8a1 tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\|altsyncram_p8a1:auto_generated " "Elaborating entity \"altsyncram_p8a1\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\|altsyncram_p8a1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603610444 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_madx_cen tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1 " "Elaborating entity \"asj_nco_madx_cen\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "m1" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 377 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603611243 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_mady_cen tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0 " "Elaborating entity \"asj_nco_mady_cen\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "m0" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 389 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603611452 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_derot tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_derot:ux0136 " "Elaborating entity \"asj_nco_derot\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_derot:ux0136\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "ux0136" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 402 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603611668 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_mob_w tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0 " "Elaborating entity \"asj_nco_mob_w\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "blk0" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 410 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603611867 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Elaborating entity \"lpm_add_sub\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\"" { } { { "db/ip/tx_nco/submodules/asj_nco_mob_w.v" "lpm_add_sub_component" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mob_w.v" 75 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603612029 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\"" { } { { "db/ip/tx_nco/submodules/asj_nco_mob_w.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mob_w.v" 75 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603612056 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 16 " "Parameter \"lpm_width\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603612056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Parameter \"lpm_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603612056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603612056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO " "Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603612056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603612056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Parameter \"lpm_representation\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603612056 ""} } { { "db/ip/tx_nco/submodules/asj_nco_mob_w.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mob_w.v" 75 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603612056 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_jpk.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_jpk.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_jpk " "Found entity 1: add_sub_jpk" { } { { "db/add_sub_jpk.tdf" "" { Text "C:/FPGA/db/add_sub_jpk.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603612218 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603612218 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_jpk tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\|add_sub_jpk:auto_generated " "Elaborating entity \"add_sub_jpk\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\|add_sub_jpk:auto_generated\"" { } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603612241 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_isdr tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr " "Elaborating entity \"asj_nco_isdr\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\"" { } { { "db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" "ux710isdr" { Text "C:/FPGA/db/ip/tx_nco/submodules/tx_nco_nco_ii_0.v" 428 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603612657 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Elaborating entity \"lpm_counter\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\"" { } { { "db/ip/tx_nco/submodules/asj_nco_isdr.v" "lpm_counter_component" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_isdr.v" 59 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603613263 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\"" { } { { "db/ip/tx_nco/submodules/asj_nco_isdr.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_isdr.v" 59 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603613292 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 4 " "Parameter \"lpm_width\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603613292 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_COUNTER " "Parameter \"lpm_type\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603613292 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction UP " "Parameter \"lpm_direction\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603613292 ""} } { { "db/ip/tx_nco/submodules/asj_nco_isdr.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_isdr.v" 59 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603613292 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_asi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_asi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_asi " "Found entity 1: cntr_asi" { } { { "db/cntr_asi.tdf" "" { Text "C:/FPGA/db/cntr_asi.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603613492 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603613492 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_asi tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_asi:auto_generated " "Elaborating entity \"cntr_asi\" for hierarchy \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\|cntr_asi:auto_generated\"" { } { { "lpm_counter.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_counter.tdf" 258 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603613517 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_interface spi_interface:FLASH " "Elaborating entity \"spi_interface\" for hierarchy \"spi_interface:FLASH\"" { } { { "WOLF-LITE.bdf" "FLASH" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 912 3936 4152 1056 "FLASH" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603617805 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_shifter data_shifter:RX_CICFIR_GAINER " "Elaborating entity \"data_shifter\" for hierarchy \"data_shifter:RX_CICFIR_GAINER\"" { } { { "WOLF-LITE.bdf" "RX_CICFIR_GAINER" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 160 2248 2552 304 "RX_CICFIR_GAINER" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603617840 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 data_shifter.v(18) " "Verilog HDL assignment warning at data_shifter.v(18): truncated value with size 32 to match size of target (1)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1616603617840 "|WOLF-LITE|data_shifter:RX_CICFIR_GAINER"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 data_shifter.v(19) " "Verilog HDL assignment warning at data_shifter.v(19): truncated value with size 32 to match size of target (1)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 19 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1616603617841 "|WOLF-LITE|data_shifter:RX_CICFIR_GAINER"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 data_shifter.v(20) " "Verilog HDL assignment warning at data_shifter.v(20): truncated value with size 32 to match size of target (16)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1616603617841 "|WOLF-LITE|data_shifter:RX_CICFIR_GAINER"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 data_shifter.v(21) " "Verilog HDL assignment warning at data_shifter.v(21): truncated value with size 32 to match size of target (16)" { } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 21 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1616603617842 "|WOLF-LITE|data_shifter:RX_CICFIR_GAINER"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_ciccomp rx_ciccomp:RX_CICCOMP_I " "Elaborating entity \"rx_ciccomp\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\"" { } { { "WOLF-LITE.bdf" "RX_CICCOMP_I" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 8 1768 2152 224 "RX_CICCOMP_I" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603617880 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_ciccomp_0002 rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst " "Elaborating entity \"rx_ciccomp_0002\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\"" { } { { "rx_ciccomp.v" "rx_ciccomp_inst" { Text "C:/FPGA/rx_ciccomp.v" 28 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603617912 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "coeff_in_read_sig rx_ciccomp_0002.vhd(54) " "Verilog HDL or VHDL warning at rx_ciccomp_0002.vhd(54): object \"coeff_in_read_sig\" assigned a value but never read" { } { { "rx_ciccomp/rx_ciccomp_0002.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd" 54 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "Analysis & Synthesis" 0 -1 1616603617913 "|WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_ciccomp_0002_ast rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst " "Elaborating entity \"rx_ciccomp_0002_ast\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\"" { } { { "rx_ciccomp/rx_ciccomp_0002.vhd" "rx_ciccomp_0002_ast_inst" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd" 62 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603617953 ""} -{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "core_channel_out_core rx_ciccomp_0002_ast.vhd(208) " "VHDL Signal Declaration warning at rx_ciccomp_0002_ast.vhd(208): used implicit default value for signal \"core_channel_out_core\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 208 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 1 0 "Analysis & Synthesis" 0 -1 1616603617958 "|WOLF-LITE|rx_ciccomp:RX_CICCOMP_I|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_sink_hpfir rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_sink_hpfir:sink " "Elaborating entity \"auk_dspip_avalon_streaming_sink_hpfir\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_sink_hpfir:sink\"" { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "sink" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 89 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603618004 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_source_hpfir rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source " "Elaborating entity \"auk_dspip_avalon_streaming_source_hpfir\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\"" { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "source" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 109 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603618053 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_controller_hpfir rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_controller_hpfir:intf_ctrl " "Elaborating entity \"auk_dspip_avalon_streaming_controller_hpfir\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_controller_hpfir:intf_ctrl\"" { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "intf_ctrl" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 137 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603618100 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_ciccomp_0002_rtl_core rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core " "Elaborating entity \"rx_ciccomp_0002_rtl_core\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\"" { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "\\real_passthrough:hpfircore_core" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603618130 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_memread " "Elaborating entity \"dspba_delay\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_memread\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_memread" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 173 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603618249 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_compute " "Elaborating entity \"dspba_delay\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:u0_m0_wo0_compute\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_compute" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 178 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603618282 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_u0_m0_wo0_compute_q_15 " "Elaborating entity \"dspba_delay\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_u0_m0_wo0_compute_q_15\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "d_u0_m0_wo0_compute_q_15" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 183 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603618314 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dspba_delay rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_xIn_0_13 " "Elaborating entity \"dspba_delay\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|dspba_delay:d_xIn_0_13\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "d_xIn_0_13" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 375 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603618355 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem " "Elaborating entity \"altsyncram\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_wi0_r0_memr0_dmem" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 402 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603618484 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem " "Elaborated megafunction instantiation \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 402 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603618518 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem " "Instantiated megafunction \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a UNUSED " "Parameter \"address_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_aclr_a UNUSED " "Parameter \"byteena_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_aclr_b NONE " "Parameter \"byteena_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "byteena_reg_b CLOCK0 " "Parameter \"byteena_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_core_a USE_INPUT_CLKEN " "Parameter \"clock_enable_core_a\" = \"USE_INPUT_CLKEN\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_core_b USE_INPUT_CLKEN " "Parameter \"clock_enable_core_b\" = \"USE_INPUT_CLKEN\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a NORMAL " "Parameter \"clock_enable_input_a\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b NORMAL " "Parameter \"clock_enable_input_b\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a NORMAL " "Parameter \"clock_enable_output_a\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b NORMAL " "Parameter \"clock_enable_output_b\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ecc_pipeline_stage_enabled FALSE " "Parameter \"ecc_pipeline_stage_enabled\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "enable_ecc FALSE " "Parameter \"enable_ecc\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "implement_in_les OFF " "Parameter \"implement_in_les\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a UNUSED " "Parameter \"indata_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Parameter \"init_file\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file_layout PORT_A " "Parameter \"init_file_layout\" = \"PORT_A\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 64 " "Parameter \"numwords_a\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 64 " "Parameter \"numwords_b\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type M9K " "Parameter \"ram_block_type\" = \"M9K\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_aclr_b NONE " "Parameter \"rdcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_b NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "stratixiv_m144k_allow_dual_clocks ON " "Parameter \"stratixiv_m144k_allow_dual_clocks\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_eccstatus 3 " "Parameter \"width_eccstatus\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 6 " "Parameter \"widthad_a\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 6 " "Parameter \"widthad_b\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a UNUSED " "Parameter \"wrcontrol_aclr_a\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618518 ""} } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 402 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603618518 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sln3.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sln3.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sln3 " "Found entity 1: altsyncram_sln3" { } { { "db/altsyncram_sln3.tdf" "" { Text "C:/FPGA/db/altsyncram_sln3.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603618716 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603618716 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sln3 rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\|altsyncram_sln3:auto_generated " "Elaborating entity \"altsyncram_sln3\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem\|altsyncram_sln3:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603618734 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component " "Elaborating entity \"lpm_mult\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_mtree_mult1_0_im4_component" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 448 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603618921 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component " "Elaborated megafunction instantiation \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 448 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603618949 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component " "Instantiated megafunction \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 15 " "Parameter \"LPM_WIDTHA\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618949 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 8 " "Parameter \"LPM_WIDTHB\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618949 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618949 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 23 " "Parameter \"LPM_WIDTHP\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618949 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618949 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_PIPELINE 2 " "Parameter \"LPM_PIPELINE\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618949 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_MULT " "Parameter \"LPM_TYPE\" = \"LPM_MULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618949 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5 " "Parameter \"LPM_HINT\" = \"DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603618949 ""} } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 448 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603618949 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_lcu.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_lcu.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_lcu " "Found entity 1: mult_lcu" { } { { "db/mult_lcu.tdf" "" { Text "C:/FPGA/db/mult_lcu.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603619105 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603619105 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_lcu rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component\|mult_lcu:auto_generated " "Elaborating entity \"mult_lcu\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component\|mult_lcu:auto_generated\"" { } { { "lpm_mult.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 376 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603619126 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component " "Elaborating entity \"lpm_mult\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "u0_m0_wo0_mtree_mult1_0_im0_component" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 480 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603619250 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component " "Elaborated megafunction instantiation \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component\"" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 480 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603619276 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component " "Instantiated megafunction \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 18 " "Parameter \"LPM_WIDTHA\" = \"18\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603619276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 8 " "Parameter \"LPM_WIDTHB\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603619276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603619276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 26 " "Parameter \"LPM_WIDTHP\" = \"26\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603619276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603619276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_PIPELINE 2 " "Parameter \"LPM_PIPELINE\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603619276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_MULT " "Parameter \"LPM_TYPE\" = \"LPM_MULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603619276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5 " "Parameter \"LPM_HINT\" = \"DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603619276 ""} } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 480 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603619276 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_rcu.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_rcu.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_rcu " "Found entity 1: mult_rcu" { } { { "db/mult_rcu.tdf" "" { Text "C:/FPGA/db/mult_rcu.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603619429 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603619429 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_rcu rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component\|mult_rcu:auto_generated " "Elaborating entity \"mult_rcu\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|rx_ciccomp_0002_rtl_core:\\real_passthrough:hpfircore_core\|lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component\|mult_rcu:auto_generated\"" { } { { "lpm_mult.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 376 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603619447 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_roundsat_hpfir rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_roundsat_hpfir:\\real_passthrough:gen_outp_blk:0:outp_blk " "Elaborating entity \"auk_dspip_roundsat_hpfir\" for hierarchy \"rx_ciccomp:RX_CICCOMP_I\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_roundsat_hpfir:\\real_passthrough:gen_outp_blk:0:outp_blk\"" { } { { "rx_ciccomp/rx_ciccomp_0002_ast.vhd" "\\real_passthrough:gen_outp_blk:0:outp_blk" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd" 244 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603619553 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_cic rx_cic:RX_CIC_I " "Elaborating entity \"rx_cic\" for hierarchy \"rx_cic:RX_CIC_I\"" { } { { "WOLF-LITE.bdf" "RX_CIC_I" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603619600 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_cic_cic_ii_0 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0 " "Elaborating entity \"rx_cic_cic_ii_0\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\"" { } { { "db/ip/rx_cic/rx_cic.v" "cic_ii_0" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603619648 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_cic_core rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core " "Elaborating entity \"alt_cic_core\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\"" { } { { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "core" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603619745 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_sink rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink " "Elaborating entity \"auk_dspip_avalon_streaming_sink\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\"" { } { { "db/ip/rx_cic/submodules/alt_cic_core.sv" "input_sink" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603619919 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "sink_FIFO" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603620406 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO " "Elaborated megafunction instantiation \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603620431 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO " "Instantiated megafunction \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Parameter \"add_ram_output_register\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603620431 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "allow_rwcycle_when_full OFF " "Parameter \"allow_rwcycle_when_full\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603620431 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_empty_value 4 " "Parameter \"almost_empty_value\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603620431 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_full_value 0 " "Parameter \"almost_full_value\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603620431 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 8 " "Parameter \"lpm_numwords\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603620431 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603620431 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 25 " "Parameter \"lpm_width\" = \"25\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603620431 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 3 " "Parameter \"lpm_widthu\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603620431 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603620431 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603620431 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603620431 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603620431 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603620431 ""} } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603620431 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_ef71.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_ef71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_ef71 " "Found entity 1: scfifo_ef71" { } { { "db/scfifo_ef71.tdf" "" { Text "C:/FPGA/db/scfifo_ef71.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603620599 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603620599 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_ef71 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated " "Elaborating entity \"scfifo_ef71\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603620619 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_vkv.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_vkv.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_vkv " "Found entity 1: a_dpfifo_vkv" { } { { "db/a_dpfifo_vkv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_vkv.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603620713 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603620713 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_vkv rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo " "Elaborating entity \"a_dpfifo_vkv\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\"" { } { { "db/scfifo_ef71.tdf" "dpfifo" { Text "C:/FPGA/db/scfifo_ef71.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603620741 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_h7h1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_h7h1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_h7h1 " "Found entity 1: altsyncram_h7h1" { } { { "db/altsyncram_h7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_h7h1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603620889 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603620889 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_h7h1 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram " "Elaborating entity \"altsyncram_h7h1\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\"" { } { { "db/a_dpfifo_vkv.tdf" "FIFOram" { Text "C:/FPGA/db/a_dpfifo_vkv.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603620933 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_source rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0 " "Elaborating entity \"auk_dspip_avalon_streaming_source\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\"" { } { { "db/ip/rx_cic/submodules/alt_cic_core.sv" "output_source_0" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 358 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603621379 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "source_FIFO" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603621886 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO " "Elaborated megafunction instantiation \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603621911 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO " "Instantiated megafunction \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Parameter \"add_ram_output_register\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603621911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "allow_rwcycle_when_full OFF " "Parameter \"allow_rwcycle_when_full\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603621911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_empty_value 0 " "Parameter \"almost_empty_value\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603621911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_full_value 13 " "Parameter \"almost_full_value\" = \"13\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603621911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 21 " "Parameter \"lpm_numwords\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603621911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603621911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 33 " "Parameter \"lpm_width\" = \"33\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603621911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 5 " "Parameter \"lpm_widthu\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603621911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603621911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603621911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603621911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603621911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603621911 ""} } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603621911 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_ai71.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_ai71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_ai71 " "Found entity 1: scfifo_ai71" { } { { "db/scfifo_ai71.tdf" "" { Text "C:/FPGA/db/scfifo_ai71.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603622079 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603622079 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_ai71 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated " "Elaborating entity \"scfifo_ai71\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603622099 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_7qv.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_7qv.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_7qv " "Found entity 1: a_dpfifo_7qv" { } { { "db/a_dpfifo_7qv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_7qv.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603622196 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603622196 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_7qv rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo " "Elaborating entity \"a_dpfifo_7qv\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\"" { } { { "db/scfifo_ai71.tdf" "dpfifo" { Text "C:/FPGA/db/scfifo_ai71.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603622224 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_dah1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_dah1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_dah1 " "Found entity 1: altsyncram_dah1" { } { { "db/altsyncram_dah1.tdf" "" { Text "C:/FPGA/db/altsyncram_dah1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603622375 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603622375 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_dah1 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|altsyncram_dah1:FIFOram " "Elaborating entity \"altsyncram_dah1\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|altsyncram_dah1:FIFOram\"" { } { { "db/a_dpfifo_7qv.tdf" "FIFOram" { Text "C:/FPGA/db/a_dpfifo_7qv.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603622417 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_controller rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller " "Elaborating entity \"auk_dspip_avalon_streaming_controller\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller\"" { } { { "db/ip/rx_cic/submodules/alt_cic_core.sv" "avalon_controller" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 408 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603622879 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_avalon_streaming_small_fifo rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller\|auk_dspip_avalon_streaming_small_fifo:ready_FIFO " "Elaborating entity \"auk_dspip_avalon_streaming_small_fifo\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_controller:avalon_controller\|auk_dspip_avalon_streaming_small_fifo:ready_FIFO\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" "ready_FIFO" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_controller.vhd" 196 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603623043 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_cic_dec_siso rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one " "Elaborating entity \"alt_cic_dec_siso\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\"" { } { { "db/ip/rx_cic/submodules/alt_cic_core.sv" "dec_one" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603623241 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_integrator rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_integrator:integrator\[0\].integration " "Elaborating entity \"auk_dspip_integrator\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_integrator:integrator\[0\].integration\"" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "integrator\[0\].integration" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 275 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603623480 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_delay rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_integrator:integrator\[0\].integration\|auk_dspip_delay:\\glogic:integrator_pipeline_0_generate:u1 " "Elaborating entity \"auk_dspip_delay\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_integrator:integrator\[0\].integration\|auk_dspip_delay:\\glogic:integrator_pipeline_0_generate:u1\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_integrator.vhd" "\\glogic:integrator_pipeline_0_generate:u1" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_integrator.vhd" 97 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603623583 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_downsample rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_downsample:vrc_en_0.first_dsample " "Elaborating entity \"auk_dspip_downsample\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_downsample:vrc_en_0.first_dsample\"" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "vrc_en_0.first_dsample" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 330 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603624239 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_module rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_downsample:vrc_en_0.first_dsample\|counter_module:counter_fs_inst " "Elaborating entity \"counter_module\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_downsample:vrc_en_0.first_dsample\|counter_module:counter_fs_inst\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_downsample.sv" "counter_fs_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv" 50 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603624407 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_module rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_downsample:vrc_en_0.first_dsample\|counter_module:counter_ch_inst " "Elaborating entity \"counter_module\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_downsample:vrc_en_0.first_dsample\|counter_module:counter_ch_inst\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_downsample.sv" "counter_ch_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv" 79 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603624586 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_channel_buffer rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator " "Elaborating entity \"auk_dspip_channel_buffer\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\"" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "fifo_regulator" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603624711 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "buffer_FIFO" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603625297 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO " "Elaborated megafunction instantiation \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\"" { } { { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603625323 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO " "Instantiated megafunction \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Parameter \"add_ram_output_register\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603625323 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "allow_rwcycle_when_full OFF " "Parameter \"allow_rwcycle_when_full\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603625323 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_empty_value 0 " "Parameter \"almost_empty_value\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603625323 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "almost_full_value 0 " "Parameter \"almost_full_value\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603625323 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 3 " "Parameter \"lpm_numwords\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603625323 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603625323 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 86 " "Parameter \"lpm_width\" = \"86\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603625323 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 2 " "Parameter \"lpm_widthu\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603625323 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603625323 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603625323 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603625323 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603625323 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603625323 ""} } { { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603625323 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_qm51.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_qm51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_qm51 " "Found entity 1: scfifo_qm51" { } { { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603625485 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603625485 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_qm51 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated " "Elaborating entity \"scfifo_qm51\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603625506 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_5ku.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_5ku.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_5ku " "Found entity 1: a_dpfifo_5ku" { } { { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603625607 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603625607 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_5ku rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo " "Elaborating entity \"a_dpfifo_5ku\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\"" { } { { "db/scfifo_qm51.tdf" "dpfifo" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603625637 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_m7h1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_m7h1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_m7h1 " "Found entity 1: altsyncram_m7h1" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603625802 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603625802 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_m7h1 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram " "Elaborating entity \"altsyncram_m7h1\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\"" { } { { "db/a_dpfifo_5ku.tdf" "FIFOram" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603625844 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_fs8.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_fs8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_fs8 " "Found entity 1: cmpr_fs8" { } { { "db/cmpr_fs8.tdf" "" { Text "C:/FPGA/db/cmpr_fs8.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603626028 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603626028 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_fs8 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cmpr_fs8:almost_full_comparer " "Elaborating entity \"cmpr_fs8\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cmpr_fs8:almost_full_comparer\"" { } { { "db/a_dpfifo_5ku.tdf" "almost_full_comparer" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603626070 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_fs8 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cmpr_fs8:two_comparison " "Elaborating entity \"cmpr_fs8\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cmpr_fs8:two_comparison\"" { } { { "db/a_dpfifo_5ku.tdf" "two_comparison" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 51 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603626154 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_q9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_q9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_q9b " "Found entity 1: cntr_q9b" { } { { "db/cntr_q9b.tdf" "" { Text "C:/FPGA/db/cntr_q9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603626284 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603626284 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_q9b rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_q9b:rd_ptr_msb " "Elaborating entity \"cntr_q9b\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_q9b:rd_ptr_msb\"" { } { { "db/a_dpfifo_5ku.tdf" "rd_ptr_msb" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 52 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603626324 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_7a7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_7a7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_7a7 " "Found entity 1: cntr_7a7" { } { { "db/cntr_7a7.tdf" "" { Text "C:/FPGA/db/cntr_7a7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603626459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603626459 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_7a7 rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_7a7:usedw_counter " "Elaborating entity \"cntr_7a7\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_7a7:usedw_counter\"" { } { { "db/a_dpfifo_5ku.tdf" "usedw_counter" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 53 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603626502 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_module rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|counter_module:latency_cnt_inst " "Elaborating entity \"counter_module\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|counter_module:latency_cnt_inst\"" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "latency_cnt_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 419 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603626727 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_module rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|counter_module:channel_out_int_inst " "Elaborating entity \"counter_module\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|counter_module:channel_out_int_inst\"" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "channel_out_int_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 432 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603626839 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "auk_dspip_differentiator rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_differentiator:differentiate_stages\[0\].auk_dsp_diff " "Elaborating entity \"auk_dspip_differentiator\" for hierarchy \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_differentiator:differentiate_stages\[0\].auk_dsp_diff\"" { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "differentiate_stages\[0\].auk_dsp_diff" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 658 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603627034 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nco nco:RX_NCO " "Elaborating entity \"nco\" for hierarchy \"nco:RX_NCO\"" { } { { "WOLF-LITE.bdf" "RX_NCO" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 152 480 736 352 "RX_NCO" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603627748 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nco_nco_ii_0 nco:RX_NCO\|nco_nco_ii_0:nco_ii_0 " "Elaborating entity \"nco_nco_ii_0\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\"" { } { { "db/ip/nco/nco.v" "nco_ii_0" { Text "C:/FPGA/db/ip/nco/nco.v" 24 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603627826 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_altqmcpipe nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000 " "Elaborating entity \"asj_altqmcpipe\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "ux000" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 304 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603627982 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc " "Elaborating entity \"lpm_add_sub\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\"" { } { { "db/ip/nco/submodules/asj_altqmcpipe.v" "acc" { Text "C:/FPGA/db/ip/nco/submodules/asj_altqmcpipe.v" 63 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603628147 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\"" { } { { "db/ip/nco/submodules/asj_altqmcpipe.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_altqmcpipe.v" 63 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603628169 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_altqmcpipe:ux000\|lpm_add_sub:acc\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Parameter \"lpm_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 22 " "Parameter \"lpm_width\" = \"22\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation UNSIGNED " "Parameter \"lpm_representation\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628169 ""} } { { "db/ip/nco/submodules/asj_altqmcpipe.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_altqmcpipe.v" 63 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603628169 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_gam_dp nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_gam_dp:ux008 " "Elaborating entity \"asj_gam_dp\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_gam_dp:ux008\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "ux008" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 326 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603628424 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_dp_cen nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220 " "Elaborating entity \"asj_nco_as_m_dp_cen\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "ux0220" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 338 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603628653 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\"" { } { { "db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" "altsyncram_component" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" 109 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603628838 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\"" { } { { "db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" 109 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603628870 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 12 " "Parameter \"width_a\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 12 " "Parameter \"width_b\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 11 " "Parameter \"widthad_b\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 2048 " "Parameter \"numwords_b\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 1 " "Parameter \"width_byteena_b\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_reg_b CLOCK0 " "Parameter \"indata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_wraddress_reg_b CLOCK0 " "Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nco_nco_ii_0_sin_c.hex " "Parameter \"init_file\" = \"nco_nco_ii_0_sin_c.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603628870 ""} } { { "db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_dp_cen.v" 109 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603628870 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_h982.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_h982.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_h982 " "Found entity 1: altsyncram_h982" { } { { "db/altsyncram_h982.tdf" "" { Text "C:/FPGA/db/altsyncram_h982.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603629070 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603629070 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_h982 nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_h982:auto_generated " "Elaborating entity \"altsyncram_h982\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_h982:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603629098 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_cen nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122 " "Elaborating entity \"asj_nco_as_m_cen\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "ux0122" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 350 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603629758 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Elaborating entity \"altsyncram\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\"" { } { { "db/ip/nco/submodules/asj_nco_as_m_cen.v" "altsyncram_component0" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603629952 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\"" { } { { "db/ip/nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603629984 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0 " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603629984 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 12 " "Parameter \"width_a\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603629984 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603629984 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603629984 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603629984 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603629984 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603629984 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603629984 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603629984 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603629984 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nco_nco_ii_0_sin_f.hex " "Parameter \"init_file\" = \"nco_nco_ii_0_sin_f.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603629984 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603629984 ""} } { { "db/ip/nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603629984 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fu91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_fu91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fu91 " "Found entity 1: altsyncram_fu91" { } { { "db/altsyncram_fu91.tdf" "" { Text "C:/FPGA/db/altsyncram_fu91.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603630178 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603630178 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fu91 nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_fu91:auto_generated " "Elaborating entity \"altsyncram_fu91\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0122\|altsyncram:altsyncram_component0\|altsyncram_fu91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603630204 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_as_m_cen nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123 " "Elaborating entity \"asj_nco_as_m_cen\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "ux0123" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 362 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603630852 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Elaborating entity \"altsyncram\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\"" { } { { "db/ip/nco/submodules/asj_nco_as_m_cen.v" "altsyncram_component0" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603630979 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\"" { } { { "db/ip/nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603631009 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0 " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603631009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 12 " "Parameter \"width_a\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603631009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603631009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603631009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603631009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603631009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603631009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603631009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603631009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603631009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nco_nco_ii_0_cos_f.hex " "Parameter \"init_file\" = \"nco_nco_ii_0_cos_f.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603631009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603631009 ""} } { { "db/ip/nco/submodules/asj_nco_as_m_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_as_m_cen.v" 65 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603631009 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_au91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_au91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_au91 " "Found entity 1: altsyncram_au91" { } { { "db/altsyncram_au91.tdf" "" { Text "C:/FPGA/db/altsyncram_au91.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603631216 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603631216 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_au91 nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\|altsyncram_au91:auto_generated " "Elaborating entity \"altsyncram_au91\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_cen:ux0123\|altsyncram:altsyncram_component0\|altsyncram_au91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603631244 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_madx_cen nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1 " "Elaborating entity \"asj_nco_madx_cen\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "m1" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 377 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603631886 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_mady_cen nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0 " "Elaborating entity \"asj_nco_mady_cen\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "m0" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 389 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603632130 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_derot nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_derot:ux0136 " "Elaborating entity \"asj_nco_derot\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_derot:ux0136\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "ux0136" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 402 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603632358 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_mob_w nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0 " "Elaborating entity \"asj_nco_mob_w\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "blk0" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 410 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603632585 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Elaborating entity \"lpm_add_sub\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\"" { } { { "db/ip/nco/submodules/asj_nco_mob_w.v" "lpm_add_sub_component" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mob_w.v" 75 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603632756 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\"" { } { { "db/ip/nco/submodules/asj_nco_mob_w.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mob_w.v" 75 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603632781 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 12 " "Parameter \"lpm_width\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603632781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Parameter \"lpm_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603632781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603632781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO " "Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603632781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603632781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Parameter \"lpm_representation\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603632781 ""} } { { "db/ip/nco/submodules/asj_nco_mob_w.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mob_w.v" 75 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603632781 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_fpk.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_fpk.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_fpk " "Found entity 1: add_sub_fpk" { } { { "db/add_sub_fpk.tdf" "" { Text "C:/FPGA/db/add_sub_fpk.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603632951 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603632951 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_fpk nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\|add_sub_fpk:auto_generated " "Elaborating entity \"add_sub_fpk\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mob_w:blk0\|lpm_add_sub:lpm_add_sub_component\|add_sub_fpk:auto_generated\"" { } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603632978 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asj_nco_isdr nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr " "Elaborating entity \"asj_nco_isdr\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\"" { } { { "db/ip/nco/submodules/nco_nco_ii_0.v" "ux710isdr" { Text "C:/FPGA/db/ip/nco/submodules/nco_nco_ii_0.v" 428 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603633419 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Elaborating entity \"lpm_counter\" for hierarchy \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\"" { } { { "db/ip/nco/submodules/asj_nco_isdr.v" "lpm_counter_component" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_isdr.v" 59 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603633593 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\"" { } { { "db/ip/nco/submodules/asj_nco_isdr.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_isdr.v" 59 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603633616 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_isdr:ux710isdr\|lpm_counter:lpm_counter_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 4 " "Parameter \"lpm_width\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603633616 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_COUNTER " "Parameter \"lpm_type\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603633616 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction UP " "Parameter \"lpm_direction\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603633616 ""} } { { "db/ip/nco/submodules/asj_nco_isdr.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_isdr.v" 59 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603633616 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mixer mixer:RX_MIXER_I " "Elaborating entity \"mixer\" for hierarchy \"mixer:RX_MIXER_I\"" { } { { "WOLF-LITE.bdf" "RX_MIXER_I" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -24 528 696 104 "RX_MIXER_I" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603633961 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component " "Elaborating entity \"lpm_mult\" for hierarchy \"mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\"" { } { { "mixer.v" "lpm_mult_component" { Text "C:/FPGA/mixer.v" 63 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603634022 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\"" { } { { "mixer.v" "" { Text "C:/FPGA/mixer.v" 63 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603634050 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component " "Instantiated megafunction \"mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint MAXIMIZE_SPEED=5 " "Parameter \"lpm_hint\" = \"MAXIMIZE_SPEED=5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603634051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603634051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Parameter \"lpm_representation\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603634051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MULT " "Parameter \"lpm_type\" = \"LPM_MULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603634051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widtha 12 " "Parameter \"lpm_widtha\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603634051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthb 12 " "Parameter \"lpm_widthb\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603634051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthp 24 " "Parameter \"lpm_widthp\" = \"24\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603634051 ""} } { { "mixer.v" "" { Text "C:/FPGA/mixer.v" 63 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603634051 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_jnp.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_jnp.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_jnp " "Found entity 1: mult_jnp" { } { { "db/mult_jnp.tdf" "" { Text "C:/FPGA/db/mult_jnp.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603634207 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603634207 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_jnp mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated " "Elaborating entity \"mult_jnp\" for hierarchy \"mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated\"" { } { { "lpm_mult.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 376 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603634223 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADC_Latch ADC_Latch:ADC_Latch " "Elaborating entity \"ADC_Latch\" for hierarchy \"ADC_Latch:ADC_Latch\"" { } { { "WOLF-LITE.bdf" "ADC_Latch" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -88 160 320 24 "ADC_Latch" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603634326 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component " "Elaborating entity \"lpm_add_sub\" for hierarchy \"ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component\"" { } { { "ADC_Latch.v" "LPM_ADD_SUB_component" { Text "C:/FPGA/ADC_Latch.v" 69 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603634388 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component " "Elaborated megafunction instantiation \"ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component\"" { } { { "ADC_Latch.v" "" { Text "C:/FPGA/ADC_Latch.v" 69 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603634415 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component " "Instantiated megafunction \"ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Parameter \"lpm_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603634415 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO " "Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603634415 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Parameter \"lpm_pipeline\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603634415 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation SIGNED " "Parameter \"lpm_representation\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603634415 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603634415 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 12 " "Parameter \"lpm_width\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603634415 ""} } { { "ADC_Latch.v" "" { Text "C:/FPGA/ADC_Latch.v" 69 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603634415 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_b2k.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_b2k.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_b2k " "Found entity 1: add_sub_b2k" { } { { "db/add_sub_b2k.tdf" "" { Text "C:/FPGA/db/add_sub_b2k.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603634581 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603634581 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_b2k ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component\|add_sub_b2k:auto_generated " "Elaborating entity \"add_sub_b2k\" for hierarchy \"ADC_Latch:ADC_Latch\|lpm_add_sub:LPM_ADD_SUB_component\|add_sub_b2k:auto_generated\"" { } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 118 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603634598 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MAIN_PLL MAIN_PLL:MAIN_PLL " "Elaborating entity \"MAIN_PLL\" for hierarchy \"MAIN_PLL:MAIN_PLL\"" { } { { "WOLF-LITE.bdf" "MAIN_PLL" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603639819 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll MAIN_PLL:MAIN_PLL\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\"" { } { { "MAIN_PLL.v" "altpll_component" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603639918 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component " "Elaborated megafunction instantiation \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\"" { } { { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603639953 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component " "Instantiated megafunction \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 335 " "Parameter \"clk0_divide_by\" = \"335\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 64 " "Parameter \"clk0_multiply_by\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1340 " "Parameter \"clk1_divide_by\" = \"1340\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 1 " "Parameter \"clk1_multiply_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 15547 " "Parameter \"inclk0_input_frequency\" = \"15547\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=MAIN_PLL " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=MAIN_PLL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603639953 ""} } { { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603639953 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/main_pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/main_pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 MAIN_PLL_altpll " "Found entity 1: MAIN_PLL_altpll" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603640141 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603640141 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MAIN_PLL_altpll MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated " "Elaborating entity \"MAIN_PLL_altpll\" for hierarchy \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603640158 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux14 mux14:DAC_MUX " "Elaborating entity \"mux14\" for hierarchy \"mux14:DAC_MUX\"" { } { { "WOLF-LITE.bdf" "DAC_MUX" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 6040 6184 248 "DAC_MUX" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603640255 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux mux14:DAC_MUX\|lpm_mux:LPM_MUX_component " "Elaborating entity \"lpm_mux\" for hierarchy \"mux14:DAC_MUX\|lpm_mux:LPM_MUX_component\"" { } { { "mux14.v" "LPM_MUX_component" { Text "C:/FPGA/mux14.v" 68 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603640547 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "mux14:DAC_MUX\|lpm_mux:LPM_MUX_component " "Elaborated megafunction instantiation \"mux14:DAC_MUX\|lpm_mux:LPM_MUX_component\"" { } { { "mux14.v" "" { Text "C:/FPGA/mux14.v" 68 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603640582 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mux14:DAC_MUX\|lpm_mux:LPM_MUX_component " "Instantiated megafunction \"mux14:DAC_MUX\|lpm_mux:LPM_MUX_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_size 2 " "Parameter \"lpm_size\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603640582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MUX " "Parameter \"lpm_type\" = \"LPM_MUX\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603640582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 14 " "Parameter \"lpm_width\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603640582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widths 1 " "Parameter \"lpm_widths\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603640582 ""} } { { "mux14.v" "" { Text "C:/FPGA/mux14.v" 68 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603640582 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_rsc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_rsc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_rsc " "Found entity 1: mux_rsc" { } { { "db/mux_rsc.tdf" "" { Text "C:/FPGA/db/mux_rsc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603640741 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603640741 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_rsc mux14:DAC_MUX\|lpm_mux:LPM_MUX_component\|mux_rsc:auto_generated " "Elaborating entity \"mux_rsc\" for hierarchy \"mux14:DAC_MUX\|lpm_mux:LPM_MUX_component\|mux_rsc:auto_generated\"" { } { { "lpm_mux.tdf" "auto_generated" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mux.tdf" 86 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603640760 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dac_null dac_null:DAC_IDLE " "Elaborating entity \"dac_null\" for hierarchy \"dac_null:DAC_IDLE\"" { } { { "WOLF-LITE.bdf" "DAC_IDLE" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 296 5896 6008 344 "DAC_IDLE" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603640868 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_constant dac_null:DAC_IDLE\|lpm_constant:LPM_CONSTANT_component " "Elaborating entity \"lpm_constant\" for hierarchy \"dac_null:DAC_IDLE\|lpm_constant:LPM_CONSTANT_component\"" { } { { "dac_null.v" "LPM_CONSTANT_component" { Text "C:/FPGA/dac_null.v" 48 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603641020 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "dac_null:DAC_IDLE\|lpm_constant:LPM_CONSTANT_component " "Elaborated megafunction instantiation \"dac_null:DAC_IDLE\|lpm_constant:LPM_CONSTANT_component\"" { } { { "dac_null.v" "" { Text "C:/FPGA/dac_null.v" 48 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603641040 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dac_null:DAC_IDLE\|lpm_constant:LPM_CONSTANT_component " "Instantiated megafunction \"dac_null:DAC_IDLE\|lpm_constant:LPM_CONSTANT_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_cvalue 8192 " "Parameter \"lpm_cvalue\" = \"8192\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641040 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641040 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_CONSTANT " "Parameter \"lpm_type\" = \"LPM_CONSTANT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641040 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 14 " "Parameter \"lpm_width\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641040 ""} } { { "dac_null.v" "" { Text "C:/FPGA/dac_null.v" 48 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603641040 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DAC_corrector DAC_corrector:DAC_CORRECTOR " "Elaborating entity \"DAC_corrector\" for hierarchy \"DAC_corrector:DAC_CORRECTOR\"" { } { { "WOLF-LITE.bdf" "DAC_CORRECTOR" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 176 5760 6008 288 "DAC_CORRECTOR" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603641068 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DEBUG DEBUG:DBG_ADC " "Elaborating entity \"DEBUG\" for hierarchy \"DEBUG:DBG_ADC\"" { } { { "WOLF-LITE.bdf" "DBG_ADC" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -176 520 696 -72 "DBG_ADC" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603641105 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsource_probe_top DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0 " "Elaborating entity \"altsource_probe_top\" for hierarchy \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\"" { } { { "db/ip/debug/debug.v" "in_system_sources_probes_0" { Text "C:/FPGA/db/ip/debug/debug.v" 19 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603641189 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsource_probe DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl " "Elaborating entity \"altsource_probe\" for hierarchy \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\"" { } { { "db/ip/debug/submodules/altsource_probe_top.v" "issp_impl" { Text "C:/FPGA/db/ip/debug/submodules/altsource_probe_top.v" 55 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603641397 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl " "Elaborated megafunction instantiation \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\"" { } { { "db/ip/debug/submodules/altsource_probe_top.v" "" { Text "C:/FPGA/db/ip/debug/submodules/altsource_probe_top.v" 55 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603641421 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl " "Instantiated megafunction \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsource_probe " "Parameter \"lpm_type\" = \"altsource_probe\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641421 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641421 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641421 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641421 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_NODE_INFO 4746752 " "Parameter \"SLD_NODE_INFO\" = \"4746752\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641421 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 4 " "Parameter \"sld_ir_width\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641421 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "instance_id ADC " "Parameter \"instance_id\" = \"ADC\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641421 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "probe_width 12 " "Parameter \"probe_width\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641421 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "source_width 0 " "Parameter \"source_width\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641421 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "source_initial_value 0 " "Parameter \"source_initial_value\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641421 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "enable_metastability NO " "Parameter \"enable_metastability\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1616603641421 ""} } { { "db/ip/debug/submodules/altsource_probe_top.v" "" { Text "C:/FPGA/db/ip/debug/submodules/altsource_probe_top.v" 55 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1616603641421 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_jtag_endpoint_adapter DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|sld_jtag_endpoint_adapter:jtag_signal_adapter " "Elaborating entity \"sld_jtag_endpoint_adapter\" for hierarchy \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|sld_jtag_endpoint_adapter:jtag_signal_adapter\"" { } { { "altsource_probe.v" "jtag_signal_adapter" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe.v" 168 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603641668 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_jtag_endpoint_adapter_impl DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|sld_jtag_endpoint_adapter:jtag_signal_adapter\|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst " "Elaborating entity \"sld_jtag_endpoint_adapter_impl\" for hierarchy \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|sld_jtag_endpoint_adapter:jtag_signal_adapter\|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst\"" { } { { "sld_jtag_endpoint_adapter.vhd" "sld_jtag_endpoint_adapter_impl_inst" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd" 232 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603642033 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsource_probe_body DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|altsource_probe_body:altsource_probe_body_inst " "Elaborating entity \"altsource_probe_body\" for hierarchy \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|altsource_probe_body:altsource_probe_body_inst\"" { } { { "altsource_probe.v" "altsource_probe_body_inst" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe.v" 280 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603642266 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsource_probe_impl DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|altsource_probe_body:altsource_probe_body_inst\|altsource_probe_impl:\\wider_probe_gen:wider_probe_inst " "Elaborating entity \"altsource_probe_impl\" for hierarchy \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|altsource_probe_body:altsource_probe_body_inst\|altsource_probe_impl:\\wider_probe_gen:wider_probe_inst\"" { } { { "altsource_probe_body.vhd" "\\wider_probe_gen:wider_probe_inst" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe_body.vhd" 507 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603642341 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_rom_sr DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|altsource_probe_body:altsource_probe_body_inst\|altsource_probe_impl:\\wider_probe_gen:wider_probe_inst\|sld_rom_sr:\\instance_id_gen:rom_info_inst " "Elaborating entity \"sld_rom_sr\" for hierarchy \"DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|altsource_probe_body:altsource_probe_body_inst\|altsource_probe_impl:\\wider_probe_gen:wider_probe_inst\|sld_rom_sr:\\instance_id_gen:rom_info_inst\"" { } { { "altsource_probe_body.vhd" "\\instance_id_gen:rom_info_inst" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe_body.vhd" 755 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1616603642641 ""} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max rate_cnt_inst 32 11 " "Port \"counter_max\" on the entity instantiation of \"rate_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 11. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "rate_cnt_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 486 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643713 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max channel_out_int_inst 32 2 " "Port \"counter_max\" on the entity instantiation of \"channel_out_int_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 2. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "channel_out_int_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 432 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643713 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:channel_out_int_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max latency_cnt_inst 32 4 " "Port \"counter_max\" on the entity instantiation of \"latency_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 4. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "latency_cnt_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 419 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643714 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:latency_cnt_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_ch_inst 32 1 " "Port \"counter_max\" on the entity instantiation of \"counter_ch_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 1. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/auk_dspip_downsample.sv" "counter_ch_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv" 79 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643718 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_ch_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_fs_inst 32 11 " "Port \"counter_max\" on the entity instantiation of \"counter_fs_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 11. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/auk_dspip_downsample.sv" "counter_fs_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv" 50 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643718 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max rate_cnt_inst 32 11 " "Port \"counter_max\" on the entity instantiation of \"rate_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 11. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "rate_cnt_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 486 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643761 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:rate_cnt_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max channel_out_int_inst 32 2 " "Port \"counter_max\" on the entity instantiation of \"channel_out_int_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 2. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "channel_out_int_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 432 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643761 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:channel_out_int_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max latency_cnt_inst 32 4 " "Port \"counter_max\" on the entity instantiation of \"latency_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 4. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "latency_cnt_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 419 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643762 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|counter_module:latency_cnt_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_ch_inst 32 1 " "Port \"counter_max\" on the entity instantiation of \"counter_ch_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 1. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/auk_dspip_downsample.sv" "counter_ch_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv" 79 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643766 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_ch_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_fs_inst 32 11 " "Port \"counter_max\" on the entity instantiation of \"counter_fs_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 11. The extra bits will be ignored." { } { { "db/ip/rx_cic/submodules/auk_dspip_downsample.sv" "counter_fs_inst" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv" 50 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643766 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_dec_siso:dec_one|auk_dspip_downsample:vrc_en_0.first_dsample|counter_module:counter_fs_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_ch_inst 32 1 " "Port \"counter_max\" on the entity instantiation of \"counter_ch_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 1. The extra bits will be ignored." { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "counter_ch_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 313 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643809 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_ch_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_fs_inst 32 12 " "Port \"counter_max\" on the entity instantiation of \"counter_fs_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 12. The extra bits will be ignored." { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "counter_fs_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 298 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643809 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_fs_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max latency_cnt_inst 32 4 " "Port \"counter_max\" on the entity instantiation of \"latency_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 4. The extra bits will be ignored." { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "latency_cnt_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 270 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643809 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_ch_inst 32 1 " "Port \"counter_max\" on the entity instantiation of \"counter_ch_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 1. The extra bits will be ignored." { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "counter_ch_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 313 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643854 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_ch_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max counter_fs_inst 32 12 " "Port \"counter_max\" on the entity instantiation of \"counter_fs_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 12. The extra bits will be ignored." { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "counter_fs_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 298 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643854 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:counter_fs_inst"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "counter_max latency_cnt_inst 32 4 " "Port \"counter_max\" on the entity instantiation of \"latency_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 4. The extra bits will be ignored." { } { { "db/ip/tx_cic/submodules/alt_cic_int_siso.sv" "latency_cnt_inst" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv" 270 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 1 0 "Analysis & Synthesis" 0 -1 1616603643854 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|alt_cic_int_siso:int_one|counter_module:latency_cnt_inst"} -{ "Info" "ISCI_START_SUPER_FABRIC_GEN" "alt_sld_fab " "Starting IP generation for the debug fabric: alt_sld_fab." { } { } 0 11170 "Starting IP generation for the debug fabric: %1!s!." 0 0 "Analysis & Synthesis" 0 -1 1616603644480 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "2021.03.24.20:34:09 Progress: Loading sld0b974a4e/alt_sld_fab_wrapper_hw.tcl " "2021.03.24.20:34:09 Progress: Loading sld0b974a4e/alt_sld_fab_wrapper_hw.tcl" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603649979 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG " "Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603658381 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: Generating alt_sld_fab \"alt_sld_fab\" for QUARTUS_SYNTH " "Alt_sld_fab: Generating alt_sld_fab \"alt_sld_fab\" for QUARTUS_SYNTH" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603658567 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: \"alt_sld_fab\" instantiated alt_sld_fab \"alt_sld_fab\" " "Alt_sld_fab: \"alt_sld_fab\" instantiated alt_sld_fab \"alt_sld_fab\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603663645 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Presplit: \"alt_sld_fab\" instantiated altera_super_splitter \"presplit\" " "Presplit: \"alt_sld_fab\" instantiated altera_super_splitter \"presplit\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603664406 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Splitter: \"alt_sld_fab\" instantiated altera_sld_splitter \"splitter\" " "Splitter: \"alt_sld_fab\" instantiated altera_sld_splitter \"splitter\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603665210 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Sldfabric: \"alt_sld_fab\" instantiated altera_sld_jtag_hub \"sldfabric\" " "Sldfabric: \"alt_sld_fab\" instantiated altera_sld_jtag_hub \"sldfabric\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603666054 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Ident: \"alt_sld_fab\" instantiated altera_connection_identification_hub \"ident\" " "Ident: \"alt_sld_fab\" instantiated altera_connection_identification_hub \"ident\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603666071 ""} -{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: Done \"alt_sld_fab\" with 6 modules, 6 files " "Alt_sld_fab: Done \"alt_sld_fab\" with 6 modules, 6 files" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603666072 ""} -{ "Info" "ISCI_END_SUPER_FABRIC_GEN" "alt_sld_fab " "Finished IP generation for the debug fabric: alt_sld_fab." { } { } 0 11171 "Finished IP generation for the debug fabric: %1!s!." 0 0 "Analysis & Synthesis" 0 -1 1616603666827 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld0b974a4e/alt_sld_fab.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/alt_sld_fab.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab " "Found entity 1: alt_sld_fab" { } { { "db/ip/sld0b974a4e/alt_sld_fab.v" "" { Text "C:/FPGA/db/ip/sld0b974a4e/alt_sld_fab.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603667371 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603667371 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab " "Found entity 1: alt_sld_fab_alt_sld_fab" { } { { "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v" "" { Text "C:/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603667566 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603667566 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_ident " "Found entity 1: alt_sld_fab_alt_sld_fab_ident" { } { { "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv" "" { Text "C:/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_ident.sv" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603667639 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603667639 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_presplit " "Found entity 1: alt_sld_fab_alt_sld_fab_presplit" { } { { "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" "" { Text "C:/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603667804 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603667804 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alt_sld_fab_alt_sld_fab_sldfabric-rtl " "Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl" { } { { "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" "" { Text "C:/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" 102 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603668043 ""} { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_sldfabric " "Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric" { } { { "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" "" { Text "C:/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" 11 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603668043 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603668043 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_splitter.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_splitter " "Found entity 1: alt_sld_fab_alt_sld_fab_splitter" { } { { "db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" "" { Text "C:/FPGA/db/ip/sld0b974a4e/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1616603668210 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603668210 ""} -{ "Info" "ISGN_QIC_SYNTHESIS_TOP_SEVERAL" "2 " "2 design partitions require synthesis" { { "Info" "ISGN_QIC_SYNTHESIS_REASON_MISSING_NETLIST" "Top " "Partition \"Top\" requires synthesis because the project database does not contain a post-synthesis netlist for this partition" { } { } 0 12213 "Partition \"%1!s!\" requires synthesis because the project database does not contain a post-synthesis netlist for this partition" 0 0 "Design Software" 0 -1 1616603670618 ""} { "Info" "ISGN_QIC_SYNTHESIS_REASON_MISSING_NETLIST" "sld_hub:auto_hub " "Partition \"sld_hub:auto_hub\" requires synthesis because the project database does not contain a post-synthesis netlist for this partition" { } { } 0 12213 "Partition \"%1!s!\" requires synthesis because the project database does not contain a post-synthesis netlist for this partition" 0 0 "Design Software" 0 -1 1616603670618 ""} } { } 0 12206 "%1!d! design partitions require synthesis" 0 0 "Analysis & Synthesis" 0 -1 1616603670618 ""} -{ "Info" "ISGN_QIC_NO_SYNTHESIS_TOP_ZERO" "" "No design partitions will skip synthesis in the current incremental compilation" { } { } 0 12209 "No design partitions will skip synthesis in the current incremental compilation" 0 0 "Analysis & Synthesis" 0 -1 1616603670618 ""} -{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|altsyncram_dah1:FIFOram\|q_b\[32\] " "Synthesized away node \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|altsyncram_dah1:FIFOram\|q_b\[32\]\"" { } { { "db/altsyncram_dah1.tdf" "" { Text "C:/FPGA/db/altsyncram_dah1.tdf" 1063 2 0 } } { "db/a_dpfifo_7qv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_7qv.tdf" 44 2 0 } } { "db/scfifo_ai71.tdf" "" { Text "C:/FPGA/db/scfifo_ai71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 358 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603671366 "|WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ai71:auto_generated|a_dpfifo_7qv:dpfifo|altsyncram_dah1:FIFOram|ram_block1a32"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[23\] " "Synthesized away node \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[23\]\"" { } { { "db/altsyncram_h7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_h7h1.tdf" 775 2 0 } } { "db/a_dpfifo_vkv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_vkv.tdf" 44 2 0 } } { "db/scfifo_ef71.tdf" "" { Text "C:/FPGA/db/scfifo_ef71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603671366 "|WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|altsyncram_h7h1:FIFOram|ram_block1a23"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[24\] " "Synthesized away node \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[24\]\"" { } { { "db/altsyncram_h7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_h7h1.tdf" 807 2 0 } } { "db/a_dpfifo_vkv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_vkv.tdf" 44 2 0 } } { "db/scfifo_ef71.tdf" "" { Text "C:/FPGA/db/scfifo_ef71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603671366 "|WOLF-LITE|rx_cic:RX_CIC_Q|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|altsyncram_h7h1:FIFOram|ram_block1a24"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|altsyncram_dah1:FIFOram\|q_b\[32\] " "Synthesized away node \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|altsyncram_dah1:FIFOram\|q_b\[32\]\"" { } { { "db/altsyncram_dah1.tdf" "" { Text "C:/FPGA/db/altsyncram_dah1.tdf" 1063 2 0 } } { "db/a_dpfifo_7qv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_7qv.tdf" 44 2 0 } } { "db/scfifo_ai71.tdf" "" { Text "C:/FPGA/db/scfifo_ai71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 358 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603671366 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ai71:auto_generated|a_dpfifo_7qv:dpfifo|altsyncram_dah1:FIFOram|ram_block1a32"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[23\] " "Synthesized away node \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[23\]\"" { } { { "db/altsyncram_h7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_h7h1.tdf" 775 2 0 } } { "db/a_dpfifo_vkv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_vkv.tdf" 44 2 0 } } { "db/scfifo_ef71.tdf" "" { Text "C:/FPGA/db/scfifo_ef71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603671366 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|altsyncram_h7h1:FIFOram|ram_block1a23"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[24\] " "Synthesized away node \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_ef71:auto_generated\|a_dpfifo_vkv:dpfifo\|altsyncram_h7h1:FIFOram\|q_b\[24\]\"" { } { { "db/altsyncram_h7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_h7h1.tdf" 807 2 0 } } { "db/a_dpfifo_vkv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_vkv.tdf" 44 2 0 } } { "db/scfifo_ef71.tdf" "" { Text "C:/FPGA/db/scfifo_ef71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603671366 "|WOLF-LITE|rx_cic:RX_CIC_I|rx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_ef71:auto_generated|a_dpfifo_vkv:dpfifo|altsyncram_h7h1:FIFOram|ram_block1a24"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "tx_cic:TX_CIC_Q\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|altsyncram_hah1:FIFOram\|q_b\[16\] " "Synthesized away node \"tx_cic:TX_CIC_Q\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|altsyncram_hah1:FIFOram\|q_b\[16\]\"" { } { { "db/altsyncram_hah1.tdf" "" { Text "C:/FPGA/db/altsyncram_hah1.tdf" 551 2 0 } } { "db/a_dpfifo_9qv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 44 2 0 } } { "db/scfifo_ci71.tdf" "" { Text "C:/FPGA/db/scfifo_ci71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } { "db/ip/tx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 358 0 0 } } { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/tx_cic/tx_cic.v" "" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 31 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 248 4928 5184 480 "TX_CIC_Q" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603671366 "|WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|altsyncram_hah1:FIFOram|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "tx_cic:TX_CIC_Q\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[16\] " "Synthesized away node \"tx_cic:TX_CIC_Q\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[16\]\"" { } { { "db/altsyncram_l7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_l7h1.tdf" 551 2 0 } } { "db/a_dpfifo_1lv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 44 2 0 } } { "db/scfifo_gf71.tdf" "" { Text "C:/FPGA/db/scfifo_gf71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/tx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/tx_cic/tx_cic.v" "" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 31 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 248 4928 5184 480 "TX_CIC_Q" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603671366 "|WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|altsyncram_l7h1:FIFOram|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "tx_cic:TX_CIC_Q\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[17\] " "Synthesized away node \"tx_cic:TX_CIC_Q\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[17\]\"" { } { { "db/altsyncram_l7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_l7h1.tdf" 583 2 0 } } { "db/a_dpfifo_1lv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 44 2 0 } } { "db/scfifo_gf71.tdf" "" { Text "C:/FPGA/db/scfifo_gf71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/tx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/tx_cic/tx_cic.v" "" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 31 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 248 4928 5184 480 "TX_CIC_Q" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603671366 "|WOLF-LITE|tx_cic:TX_CIC_Q|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|altsyncram_l7h1:FIFOram|ram_block1a17"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|altsyncram_hah1:FIFOram\|q_b\[16\] " "Synthesized away node \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ci71:auto_generated\|a_dpfifo_9qv:dpfifo\|altsyncram_hah1:FIFOram\|q_b\[16\]\"" { } { { "db/altsyncram_hah1.tdf" "" { Text "C:/FPGA/db/altsyncram_hah1.tdf" 551 2 0 } } { "db/a_dpfifo_9qv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_9qv.tdf" 44 2 0 } } { "db/scfifo_ci71.tdf" "" { Text "C:/FPGA/db/scfifo_ci71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_source.vhd" 116 0 0 } } { "db/ip/tx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 358 0 0 } } { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/tx_cic/tx_cic.v" "" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 31 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -40 4928 5184 192 "TX_CIC_I" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603671366 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_source:output_source_0|scfifo:source_FIFO|scfifo_ci71:auto_generated|a_dpfifo_9qv:dpfifo|altsyncram_hah1:FIFOram|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[16\] " "Synthesized away node \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[16\]\"" { } { { "db/altsyncram_l7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_l7h1.tdf" 551 2 0 } } { "db/a_dpfifo_1lv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 44 2 0 } } { "db/scfifo_gf71.tdf" "" { Text "C:/FPGA/db/scfifo_gf71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/tx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/tx_cic/tx_cic.v" "" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 31 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -40 4928 5184 192 "TX_CIC_I" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603671366 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|altsyncram_l7h1:FIFOram|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[17\] " "Synthesized away node \"tx_cic:TX_CIC_I\|tx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_sink:input_sink\|scfifo:sink_FIFO\|scfifo_gf71:auto_generated\|a_dpfifo_1lv:dpfifo\|altsyncram_l7h1:FIFOram\|q_b\[17\]\"" { } { { "db/altsyncram_l7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_l7h1.tdf" 583 2 0 } } { "db/a_dpfifo_1lv.tdf" "" { Text "C:/FPGA/db/a_dpfifo_1lv.tdf" 44 2 0 } } { "db/scfifo_gf71.tdf" "" { Text "C:/FPGA/db/scfifo_gf71.tdf" 36 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/auk_dspip_avalon_streaming_sink.vhd" 123 0 0 } } { "db/ip/tx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/alt_cic_core.sv" 326 0 0 } } { "db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/tx_cic/submodules/tx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/tx_cic/tx_cic.v" "" { Text "C:/FPGA/db/ip/tx_cic/tx_cic.v" 31 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -40 4928 5184 192 "TX_CIC_I" "" } } } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603671366 "|WOLF-LITE|tx_cic:TX_CIC_I|tx_cic_cic_ii_0:cic_ii_0|alt_cic_core:core|auk_dspip_avalon_streaming_sink:input_sink|scfifo:sink_FIFO|scfifo_gf71:auto_generated|a_dpfifo_1lv:dpfifo|altsyncram_l7h1:FIFOram|ram_block1a17"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1616603671366 ""} } { } 0 14284 "Synthesized away the following node(s):" 1 0 "Analysis & Synthesis" 0 -1 1616603671366 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1616603672552 ""} -{ "Info" "IQSYN_PARALLEL_SYNTHESIS" "8 2 " "Using 8 processors to synthesize 2 partitions in parallel" { } { } 0 281037 "Using %1!d! processors to synthesize %2!d! partitions in parallel" 0 0 "Analysis & Synthesis" 0 -1 1616603672827 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 1 1616603674284 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 0 1616603674292 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 1 1616603674295 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 24 19:34:33 2021 " "Processing started: Wed Mar 24 19:34:33 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 1 1616603674295 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 1 1616603674295 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --parallel=1 --helper=1 --helper_type=user_partition --partition=sld_hub:auto_hub WOLF-LITE -c WOLF-LITE " "Command: quartus_map --parallel=1 --helper=1 --helper_type=user_partition --partition=sld_hub:auto_hub WOLF-LITE -c WOLF-LITE" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 1 1616603674295 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 0 1616603674303 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 24 19:34:33 2021 " "Processing started: Wed Mar 24 19:34:33 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 0 1616603674303 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 0 1616603674303 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --parallel=1 --helper=0 --helper_type=user_partition --partition=Top WOLF-LITE -c WOLF-LITE " "Command: quartus_map --parallel=1 --helper=0 --helper_type=user_partition --partition=Top WOLF-LITE -c WOLF-LITE" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 0 1616603674303 ""} -{ "Info" "IQSYN_SYNTHESIZE_PARTITION" "sld_hub:auto_hub " "Starting Logic Optimization and Technology Mapping for Partition sld_hub:auto_hub" { } { } 0 281019 "Starting Logic Optimization and Technology Mapping for Partition %1!s!" 0 0 "Analysis & Synthesis" 0 1 1616603676993 ""} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 speed 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"speed\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 1 1616603677004 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "sld_jtag_hub.vhd" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 386 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 1 1616603677018 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 1 1616603677018 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_hub:auto_hub " "Timing-Driven Synthesis is running on partition \"sld_hub:auto_hub\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 1 1616603677218 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" { } { } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Analysis & Synthesis" 0 1 1616603678137 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Analysis & Synthesis" 0 1 1616603678458 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1616603678458 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1616603678458 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 15.547 clk_sys " " 15.547 clk_sys" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1616603678458 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 clock_stm32 " " 40.000 clock_stm32" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1616603678458 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 81.378 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 81.378 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1616603678458 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "20832.980 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\] " "20832.980 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1616603678458 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 6.218 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 6.218 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 1 1616603678458 ""} } { } 0 332111 "%1!s!" 0 0 "Analysis & Synthesis" 0 1 1616603678458 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" { } { } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Analysis & Synthesis" 0 1 1616603678477 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" { } { } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Analysis & Synthesis" 0 1 1616603678586 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:00 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:00" { } { } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Analysis & Synthesis" 0 1 1616603678587 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "238 " "Implemented 238 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "39 " "Implemented 39 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 1 1616603678661 ""} { "Info" "ICUT_CUT_TM_OPINS" "56 " "Implemented 56 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 1 1616603678661 ""} { "Info" "ICUT_CUT_TM_LCELLS" "143 " "Implemented 143 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 1 1616603678661 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 1 1616603678661 ""} -{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DEBUG2 16 " "Ignored 16 assignments for entity \"DEBUG2\" -- entity does not exist in design" { } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 1 1616603678688 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4804 " "Peak virtual memory: 4804 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 1 1616603678772 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 24 19:34:38 2021 " "Processing ended: Wed Mar 24 19:34:38 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 1 1616603678772 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 1 1616603678772 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 1 1616603678772 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 1 1616603678772 ""} -{ "Info" "ILPMS_INFERENCING_SUMMARY" "8 " "Inferred 8 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult1\"" { } { { "db/ip/tx_nco/submodules/asj_nco_madx_cen.v" "Mult1" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1616603688405 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult0\"" { } { { "db/ip/tx_nco/submodules/asj_nco_madx_cen.v" "Mult0" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v" 50 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1616603688405 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult1\"" { } { { "db/ip/tx_nco/submodules/asj_nco_mady_cen.v" "Mult1" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mady_cen.v" 52 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1616603688405 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult0\"" { } { { "db/ip/tx_nco/submodules/asj_nco_mady_cen.v" "Mult0" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_mady_cen.v" 51 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1616603688405 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult1\"" { } { { "db/ip/nco/submodules/asj_nco_madx_cen.v" "Mult1" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1616603688405 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|Mult0\"" { } { { "db/ip/nco/submodules/asj_nco_madx_cen.v" "Mult0" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v" 50 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1616603688405 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult1\"" { } { { "db/ip/nco/submodules/asj_nco_mady_cen.v" "Mult1" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mady_cen.v" 52 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1616603688405 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_mady_cen:m0\|Mult0\"" { } { { "db/ip/nco/submodules/asj_nco_mady_cen.v" "Mult0" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_mady_cen.v" 51 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 0 1616603688405 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 0 1616603688405 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1\"" { } { { "db/ip/tx_nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 0 1616603688735 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1 " "Instantiated megafunction \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 16 " "Parameter \"LPM_WIDTHA\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603688735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 16 " "Parameter \"LPM_WIDTHB\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603688735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 32 " "Parameter \"LPM_WIDTHP\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603688735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 32 " "Parameter \"LPM_WIDTHR\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603688735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603688735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603688735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603688735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603688735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603688735 ""} } { { "db/ip/tx_nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/tx_nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 0 1616603688735 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_36t.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_36t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_36t " "Found entity 1: mult_36t" { } { { "db/mult_36t.tdf" "" { Text "C:/FPGA/db/mult_36t.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1616603688885 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1616603688885 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1\"" { } { { "db/ip/nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 0 1616603689362 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1 " "Instantiated megafunction \"nco:RX_NCO\|nco_nco_ii_0:nco_ii_0\|asj_nco_madx_cen:m1\|lpm_mult:Mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 12 " "Parameter \"LPM_WIDTHA\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603689362 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 12 " "Parameter \"LPM_WIDTHB\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603689362 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 24 " "Parameter \"LPM_WIDTHP\" = \"24\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603689362 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 24 " "Parameter \"LPM_WIDTHR\" = \"24\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603689362 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603689362 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603689362 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603689362 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603689362 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603689362 ""} } { { "db/ip/nco/submodules/asj_nco_madx_cen.v" "" { Text "C:/FPGA/db/ip/nco/submodules/asj_nco_madx_cen.v" 51 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 0 1616603689362 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_t5t.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_t5t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_t5t " "Found entity 1: mult_t5t" { } { { "db/mult_t5t.tdf" "" { Text "C:/FPGA/db/mult_t5t.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1616603689511 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1616603689511 ""} -{ "Info" "IBAL_BAL_CONVERTED_RAM_SLICES_TO_LCELLS_TOP_MSG" "2 " "Converted the following 2 logical RAM block slices to logic cells" { { "Info" "IBAL_BAL_CONVERTED_LOGICAL_RAM_GROUP_TO_LCELLS" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ALTSYNCRAM " "Converted the following logical RAM block \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ALTSYNCRAM\" slices to logic cells" { { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a54 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a54\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1767 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a55 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a55\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1799 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a56 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a56\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1831 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a57 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a57\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1863 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a58 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a58\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1895 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a59 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a59\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1927 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a60 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a60\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1959 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a61 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a61\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1991 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a62 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a62\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2023 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a63 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a63\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2055 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a64 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a64\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2087 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a65 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a65\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2119 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a66 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a66\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2151 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a67 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a67\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2183 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a68 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a68\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2215 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a69 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a69\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2247 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a70 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a70\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2279 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a71 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a71\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2311 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a72 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a72\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2343 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a73 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a73\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2375 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a74 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a74\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2407 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a75 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a75\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2439 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a76 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a76\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2471 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a77 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a77\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2503 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a78 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a78\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2535 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a79 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a79\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2567 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a80 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a80\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2599 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a81 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a81\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2631 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a82 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a82\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2663 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a83 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a83\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2695 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a84 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a84\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2727 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a85 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a85\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2759 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a53 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a53\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1735 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a52 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a52\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1703 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a51 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a51\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1671 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a50 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a50\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1639 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a49 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a49\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1607 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a48 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a48\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1575 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a47 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a47\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1543 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a46 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a46\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1511 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a45 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a45\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1479 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a44 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a44\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1447 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a43 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a43\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1415 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a42 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a42\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1383 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a41 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a41\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1351 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a40 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a40\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1319 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a39 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a39\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1287 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a38 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a38\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1255 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a37 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a37\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1223 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a36 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a36\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1191 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a35 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a35\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1159 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a34 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a34\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1127 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a33 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a33\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1095 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a32 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a32\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1063 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a31 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a31\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1031 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a30 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a30\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 999 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a29 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a29\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 967 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a28 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a28\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 935 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a27 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a27\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 903 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a26 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a26\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 871 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a25 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a25\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 839 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a24 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a24\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 807 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a23 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a23\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 775 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a22 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a22\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 743 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a21 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a21\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 711 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a20 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a20\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 679 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a19 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a19\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 647 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a18 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a18\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 615 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a17 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a17\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 583 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a16 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a16\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 551 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a15 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a15\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 519 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a14 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a14\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 487 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a13 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a13\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 455 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a12 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a12\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 423 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a11 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a11\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 391 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a10 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a10\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 359 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a9 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a9\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 327 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a8 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a8\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 295 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a7 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a7\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 263 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a6 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a6\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 231 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a5 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a5\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 199 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a4 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a4\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 167 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a3 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a3\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 135 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a2 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a2\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 103 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a1 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a1\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 71 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a0 " "RAM block slice \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a0\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 39 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 272 896 1152 544 "RX_CIC_Q" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} } { } 0 270022 "Converted the following logical RAM block \"%1!s!\" slices to logic cells" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_CONVERTED_LOGICAL_RAM_GROUP_TO_LCELLS" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ALTSYNCRAM " "Converted the following logical RAM block \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ALTSYNCRAM\" slices to logic cells" { { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a54 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a54\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1767 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a55 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a55\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1799 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a56 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a56\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1831 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a57 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a57\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1863 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a58 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a58\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1895 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a59 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a59\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1927 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a60 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a60\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1959 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a61 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a61\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1991 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a62 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a62\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2023 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a63 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a63\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2055 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a64 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a64\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2087 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a65 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a65\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2119 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a66 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a66\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2151 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a67 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a67\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2183 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a68 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a68\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2215 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a69 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a69\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2247 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a70 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a70\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2279 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a71 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a71\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2311 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a72 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a72\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2343 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a73 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a73\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2375 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a74 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a74\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2407 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a75 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a75\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2439 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a76 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a76\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2471 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a77 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a77\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2503 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a78 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a78\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2535 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a79 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a79\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2567 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a80 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a80\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2599 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a81 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a81\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2631 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a82 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a82\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2663 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a83 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a83\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2695 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a84 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a84\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2727 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a85 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a85\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 2759 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a53 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a53\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1735 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a52 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a52\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1703 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a51 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a51\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1671 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a50 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a50\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1639 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a49 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a49\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1607 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a48 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a48\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1575 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a47 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a47\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1543 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a46 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a46\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1511 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a45 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a45\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1479 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a44 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a44\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1447 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a43 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a43\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1415 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a42 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a42\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1383 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a41 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a41\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1351 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a40 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a40\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1319 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a39 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a39\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1287 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a38 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a38\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1255 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a37 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a37\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1223 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a36 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a36\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1191 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a35 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a35\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1159 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a34 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a34\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1127 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a33 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a33\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1095 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a32 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a32\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1063 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a31 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a31\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 1031 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a30 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a30\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 999 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a29 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a29\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 967 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a28 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a28\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 935 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a27 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a27\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 903 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a26 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a26\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 871 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a25 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a25\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 839 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a24 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a24\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 807 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a23 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a23\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 775 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a22 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a22\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 743 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a21 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a21\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 711 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a20 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a20\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 679 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a19 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a19\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 647 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a18 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a18\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 615 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a17 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a17\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 583 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a16 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a16\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 551 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a15 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a15\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 519 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a14 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a14\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 487 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a13 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a13\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 455 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a12 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a12\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 423 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a11 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a11\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 391 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a10 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a10\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 359 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a9 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a9\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 327 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a8 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a8\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 295 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a7 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a7\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 263 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a6 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a6\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 231 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a5 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a5\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 199 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a4 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a4\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 167 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a3 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a3\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 135 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a2 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a2\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 103 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a1 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a1\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 71 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} { "Info" "IBAL_BAL_RAM_SLICE" "rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a0 " "RAM block slice \"rx_cic:RX_CIC_I\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|ram_block1a0\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 39 2 0 } } { "db/a_dpfifo_5ku.tdf" "" { Text "C:/FPGA/db/a_dpfifo_5ku.tdf" 42 2 0 } } { "db/scfifo_qm51.tdf" "" { Text "C:/FPGA/db/scfifo_qm51.tdf" 34 2 0 } } { "scfifo.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } } { "db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/auk_dspip_channel_buffer.vhd" 89 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv" 367 0 0 } } { "db/ip/rx_cic/submodules/alt_cic_core.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/alt_cic_core.sv" 475 0 0 } } { "db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" "" { Text "C:/FPGA/db/ip/rx_cic/submodules/rx_cic_cic_ii_0.sv" 213 0 0 } } { "db/ip/rx_cic/rx_cic.v" "" { Text "C:/FPGA/db/ip/rx_cic/rx_cic.v" 32 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -8 896 1152 264 "RX_CIC_I" "" } } } } } 0 270019 "RAM block slice \"%1!s!\"" 0 0 "Design Software" 0 0 1616603690215 ""} } { } 0 270022 "Converted the following logical RAM block \"%1!s!\" slices to logic cells" 0 0 "Design Software" 0 0 1616603690215 ""} } { } 0 270023 "Converted the following %1!d! logical RAM block slices to logic cells" 0 0 "Analysis & Synthesis" 0 0 1616603690215 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|altsyncram:ram_block1a0 " "Elaborated megafunction instantiation \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|altsyncram:ram_block1a0\"" { } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 39 2 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 0 1616603690762 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|altsyncram:ram_block1a0 " "Instantiated megafunction \"rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|altsyncram_m7h1:FIFOram\|altsyncram:ram_block1a0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE altsyncram " "Parameter \"LPM_TYPE\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 86 " "Parameter \"WIDTH_A\" = \"86\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 2 " "Parameter \"WIDTHAD_A\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 4 " "Parameter \"NUMWORDS_A\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_A UNREGISTERED " "Parameter \"OUTDATA_REG_A\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_A NONE " "Parameter \"OUTDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "BYTEENA_ACLR_A NONE " "Parameter \"BYTEENA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_INPUT_A BYPASS " "Parameter \"CLOCK_ENABLE_INPUT_A\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_OUTPUT_A BYPASS " "Parameter \"CLOCK_ENABLE_OUTPUT_A\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 86 " "Parameter \"WIDTH_B\" = \"86\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 2 " "Parameter \"WIDTHAD_B\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 4 " "Parameter \"NUMWORDS_B\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_REG_B UNUSED " "Parameter \"INDATA_REG_B\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_WRADDRESS_REG_B CLOCK1 " "Parameter \"WRCONTROL_WRADDRESS_REG_B\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RDCONTROL_REG_B CLOCK1 " "Parameter \"RDCONTROL_REG_B\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK1 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "BYTEENA_REG_B UNUSED " "Parameter \"BYTEENA_REG_B\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B CLOCK1 " "Parameter \"OUTDATA_REG_B\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_B NONE " "Parameter \"INDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_B NONE " "Parameter \"WRCONTROL_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RDCONTROL_ACLR_B NONE " "Parameter \"RDCONTROL_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "BYTEENA_ACLR_B NONE " "Parameter \"BYTEENA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_INPUT_B BYPASS " "Parameter \"CLOCK_ENABLE_INPUT_B\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_OUTPUT_B NORMAL " "Parameter \"CLOCK_ENABLE_OUTPUT_B\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_BYTEENA_A 1 " "Parameter \"WIDTH_BYTEENA_A\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_BYTEENA_B 1 " "Parameter \"WIDTH_BYTEENA_B\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RAM_BLOCK_TYPE AUTO " "Parameter \"RAM_BLOCK_TYPE\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "BYTE_SIZE 8 " "Parameter \"BYTE_SIZE\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS DONT_CARE " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE " "Parameter \"INIT_FILE\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE_LAYOUT PORT_B " "Parameter \"INIT_FILE_LAYOUT\" = \"PORT_B\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMUM_DEPTH 4 " "Parameter \"MAXIMUM_DEPTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ENABLE_RUNTIME_MOD NO " "Parameter \"ENABLE_RUNTIME_MOD\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_NAME UNUSED " "Parameter \"INSTANCE_NAME\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ENABLE_ECC FALSE " "Parameter \"ENABLE_ECC\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ECCSTATUS_REG UNREGISTERED " "Parameter \"ECCSTATUS_REG\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_CORE_A BYPASS " "Parameter \"CLOCK_ENABLE_CORE_A\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_CORE_B BYPASS " "Parameter \"CLOCK_ENABLE_CORE_B\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_PORT_A NEW_DATA_WITH_NBE_READ " "Parameter \"READ_DURING_WRITE_MODE_PORT_A\" = \"NEW_DATA_WITH_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_PORT_B NEW_DATA_WITH_NBE_READ " "Parameter \"READ_DURING_WRITE_MODE_PORT_B\" = \"NEW_DATA_WITH_NBE_READ\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CLOCK_ENABLE_ECC_STATUS NORMAL " "Parameter \"CLOCK_ENABLE_ECC_STATUS\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IMPLEMENT_IN_LES ON " "Parameter \"IMPLEMENT_IN_LES\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 0 1616603690762 ""} } { { "db/altsyncram_m7h1.tdf" "" { Text "C:/FPGA/db/altsyncram_m7h1.tdf" 39 2 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 0 1616603690762 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_nci3.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_nci3.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_nci3 " "Found entity 1: altsyncram_nci3" { } { { "db/altsyncram_nci3.tdf" "" { Text "C:/FPGA/db/altsyncram_nci3.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1616603690946 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1616603690946 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_msa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_msa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_msa " "Found entity 1: decode_msa" { } { { "db/decode_msa.tdf" "" { Text "C:/FPGA/db/decode_msa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1616603691151 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1616603691151 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_sob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_sob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_sob " "Found entity 1: mux_sob" { } { { "db/mux_sob.tdf" "" { Text "C:/FPGA/db/mux_sob.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 0 1616603691350 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 0 1616603691350 ""} -{ "Info" "IQSYN_SYNTHESIZE_TOP_PARTITION" "" "Starting Logic Optimization and Technology Mapping for Top Partition" { } { } 0 281020 "Starting Logic Optimization and Technology Mapping for Top Partition" 0 0 "Analysis & Synthesis" 0 0 1616603693048 ""} -{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 speed 102 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"speed\" technology mapper which leaves 102 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 0 1616603693129 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd" 388 -1 0 } } { "tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" "" { Text "C:/FPGA/tx_ciccomp/tx_ciccomp_0002_rtl_core.vhd" 299 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 0 1616603693417 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 0 1616603693417 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 0 1616603698616 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "37 " "37 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 0 1616603706978 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" { } { } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Analysis & Synthesis" 0 0 1616603707469 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Analysis & Synthesis" 0 0 1616603708836 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1616603708837 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1616603708837 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 15.547 clk_sys " " 15.547 clk_sys" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1616603708837 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 clock_stm32 " " 40.000 clock_stm32" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1616603708837 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 81.378 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 81.378 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1616603708837 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "20832.980 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\] " "20832.980 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1616603708837 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 6.218 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 6.218 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 0 1616603708837 ""} } { } 0 332111 "%1!s!" 0 0 "Analysis & Synthesis" 0 0 1616603708837 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" { } { } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Analysis & Synthesis" 0 0 1616603709653 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" { } { } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Analysis & Synthesis" 0 0 1616603709892 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:02 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:02" { } { } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Analysis & Synthesis" 0 0 1616603709909 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "10749 " "Implemented 10749 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "33 " "Implemented 33 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 0 1616603710010 ""} { "Info" "ICUT_CUT_TM_OPINS" "41 " "Implemented 41 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 0 1616603710010 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 0 1616603710010 ""} { "Info" "ICUT_CUT_TM_LCELLS" "10274 " "Implemented 10274 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 0 1616603710010 ""} { "Info" "ICUT_CUT_TM_RAMS" "354 " "Implemented 354 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 0 1616603710010 ""} { "Info" "ICUT_CUT_TM_PLLS" "2 " "Implemented 2 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 0 1616603710010 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "36 " "Implemented 36 DSP elements" { } { } 0 21062 "Implemented %1!d! DSP elements" 0 0 "Design Software" 0 0 1616603710010 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 0 1616603710010 ""} -{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DEBUG2 16 " "Ignored 16 assignments for entity \"DEBUG2\" -- entity does not exist in design" { } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 0 1616603710583 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4902 " "Peak virtual memory: 4902 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 0 1616603710824 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 24 19:35:10 2021 " "Processing ended: Wed Mar 24 19:35:10 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 0 1616603710824 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:37 " "Elapsed time: 00:00:37" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 0 1616603710824 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 0 1616603710824 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 0 1616603710824 ""} -{ "Info" "IQSYN_PARALLEL_SYNTHESIS_SUCCESS" "" "Finished parallel synthesis of all partitions" { } { } 0 281038 "Finished parallel synthesis of all partitions" 0 0 "Analysis & Synthesis" 0 -1 1616603711639 ""} -{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DEBUG2 16 " "Ignored 16 assignments for entity \"DEBUG2\" -- entity does not exist in design" { } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 -1 1616603711729 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/FPGA/output_files/WOLF-LITE.map.smsg " "Generated suppressed messages file C:/FPGA/output_files/WOLF-LITE.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603714530 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4928 " "Peak virtual memory: 4928 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1616603719733 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 24 19:35:19 2021 " "Processing ended: Wed Mar 24 19:35:19 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1616603719733 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:03:50 " "Elapsed time: 00:03:50" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1616603719733 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:06:03 " "Total CPU time (on all processors): 00:06:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1616603719733 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1616603719733 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1616603722776 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Partition Merge Quartus Prime " "Running Quartus Prime Partition Merge" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1616603722794 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 24 19:35:21 2021 " "Processing started: Wed Mar 24 19:35:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1616603722794 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1616603722794 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb --read_settings_files=off --write_settings_files=off WOLF-LITE -c WOLF-LITE --merge=on " "Command: quartus_cdb --read_settings_files=off --write_settings_files=off WOLF-LITE -c WOLF-LITE --merge=on" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1616603722795 ""} -{ "Warning" "WAMERGE_PARTITION_SOURCE_POST_FIT_MISSING" "Top " "Previously generated Fitter netlist for partition \"Top\" does not exist -- using previously generated Synthesis netlist instead" { } { } 0 35009 "Previously generated Fitter netlist for partition \"%1!s!\" does not exist -- using previously generated Synthesis netlist instead" 0 0 "Design Software" 0 -1 1616603723127 ""} -{ "Info" "IAMERGE_PARTITION_SOURCE_SOURCE" "Top " "Using synthesis netlist for partition \"Top\"" { } { } 0 35007 "Using synthesis netlist for partition \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603723127 ""} -{ "Info" "IAMERGE_PARTITION_SOURCE_SOURCE" "sld_hub:auto_hub " "Using synthesis netlist for partition \"sld_hub:auto_hub\"" { } { } 0 35007 "Using synthesis netlist for partition \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603725511 ""} -{ "Info" "IAMERGE_ATOM_BLACKBOX_RESOLVED" "2 " "Resolved and merged 2 partition(s)" { } { } 0 35002 "Resolved and merged %1!d! partition(s)" 0 0 "Design Software" 0 -1 1616603727545 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "2 0 2 0 0 " "Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1616603727765 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Design Software" 0 -1 1616603727765 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "10872 " "Implemented 10872 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "20 " "Implemented 20 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1616603729277 ""} { "Info" "ICUT_CUT_TM_OPINS" "37 " "Implemented 37 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1616603729277 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1616603729277 ""} { "Info" "ICUT_CUT_TM_LCELLS" "10413 " "Implemented 10413 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1616603729277 ""} { "Info" "ICUT_CUT_TM_RAMS" "354 " "Implemented 354 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1616603729277 ""} { "Info" "ICUT_CUT_TM_PLLS" "2 " "Implemented 2 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1616603729277 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "36 " "Implemented 36 DSP elements" { } { } 0 21062 "Implemented %1!d! DSP elements" 0 0 "Design Software" 0 -1 1616603729277 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Design Software" 0 -1 1616603729277 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Partition Merge 0 s 1 Quartus Prime " "Quartus Prime Partition Merge was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4734 " "Peak virtual memory: 4734 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1616603730106 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 24 19:35:30 2021 " "Processing ended: Wed Mar 24 19:35:30 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1616603730106 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1616603730106 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1616603730106 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1616603730106 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1616603733117 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1616603733141 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 24 19:35:31 2021 " "Processing started: Wed Mar 24 19:35:31 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1616603733141 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1616603733141 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off WOLF-LITE -c WOLF-LITE --plan " "Command: quartus_fit --read_settings_files=off --write_settings_files=off WOLF-LITE -c WOLF-LITE --plan" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1616603733141 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1616603734240 ""} -{ "Info" "0" "" "Project = WOLF-LITE" { } { } 0 0 "Project = WOLF-LITE" 0 0 "Fitter" 0 0 1616603734241 ""} -{ "Info" "0" "" "Revision = WOLF-LITE" { } { } 0 0 "Revision = WOLF-LITE" 0 0 "Fitter" 0 0 1616603734242 ""} -{ "Info" "IQCU_OPT_MODE_DESCRIPTION" "Aggressive Performance timing performance increased logic area and compilation time " "Aggressive Performance optimization mode selected -- timing performance will be prioritized at the potential cost of increased logic area and compilation time" { } { } 0 16303 "%1!s! optimization mode selected -- %2!s! will be prioritized at the potential cost of %3!s!" 0 0 "Fitter" 0 -1 1616603734615 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1616603734629 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "WOLF-LITE EP4CE10E22C8 " "Selected device EP4CE10E22C8 for design \"WOLF-LITE\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1616603734766 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616603734842 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616603734843 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] 64 335 0 0 " "Implementing clock multiplication of 64, clock division of 335, and phase shift of 0 degrees (0 ps) for MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1616603735018 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] 1 1340 0 0 " "Implementing clock multiplication of 1, clock division of 1340, and phase shift of 0 degrees (0 ps) for MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 600 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1616603735018 ""} } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1616603735018 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|wire_pll1_clk\[0\] 5 2 0 0 " "Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3172 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1616603735022 ""} } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3172 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1616603735022 ""} -{ "Warning" "WMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a0 " "Atom \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a0\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Design Software" 0 -1 1616603735027 "|WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4k82:auto_generated|ram_block1a0"} } { } 0 18550 "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." 1 0 "Fitter" 0 -1 1616603735027 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6E22C8 " "Device EP4CE6E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1616603736377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C8 " "Device EP4CE15E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1616603736377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C8 " "Device EP4CE22E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1616603736377 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1616603736377 ""} -{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1616603736434 ""} -{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1616603736434 ""} -{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1616603736434 ""} -{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1616603736434 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 1 0 "Fitter" 0 -1 1616603736443 ""} -{ "Info" "IFIOMGR_CONFIGURATION_VOLTAGE_IS_AUTOMATICALLY_ENFORCED" "Cyclone IV E Active Serial " "Configuration voltage level is automatically enforced for the device family 'Cyclone IV E' with the configuration scheme 'Active Serial'" { } { } 0 169197 "Configuration voltage level is automatically enforced for the device family '%1!s!' with the configuration scheme '%2!s!'" 0 0 "Fitter" 0 -1 1616603736841 ""} -{ "Info" "IFIOMGR_IO_BANK_VCCIO_SET_FOR_CONFIGURATION" "2.5V 1 " "Configuration voltage level of 2.5V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 2.5V." { } { } 0 169213 "Configuration voltage level of %1!s! is enforced on the I/O bank %2!s!. The VCCIO of the I/O bank %2!s! is set to %1!s!." 0 0 "Fitter" 0 -1 1616603736841 ""} -{ "Info" "IFIOMGR_IO_BANK_VCCIO_SET_FOR_CONFIGURATION" "2.5V 1 " "Configuration voltage level of 2.5V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 2.5V." { } { } 0 169213 "Configuration voltage level of %1!s! is enforced on the I/O bank %2!s!. The VCCIO of the I/O bank %2!s! is set to %1!s!." 0 0 "Fitter" 0 -1 1616603736841 ""} -{ "Warning" "WFSAC_FSAC_PLL_MERGING_PARAMETERS_MISMATCH_WARNING" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 " "The parameters of the PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 and the PLL MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 do not have the same values - hence these PLLs cannot be merged" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "M MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"M\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 64 " "The value of the parameter \"M\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 64" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 10 " "The value of the parameter \"M\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 10" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "N MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"N\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 5 " "The value of the parameter \"N\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 5" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 1 " "The value of the parameter \"N\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "LOOP FILTER R MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"LOOP FILTER R\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 6000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 6000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 4000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 4000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "VCO POST SCALE MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"VCO POST SCALE\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 1 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 2 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 2" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min VCO Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min VCO Period\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Min VCO Period\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Min VCO Period\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max VCO Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max VCO Period\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 1666 " "The value of the parameter \"Max VCO Period\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 1666" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 3333 " "The value of the parameter \"Max VCO Period\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 3333" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Center VCO Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Center VCO Period\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Center VCO Period\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Center VCO Period\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min Lock Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min Lock Period\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 9843 " "The value of the parameter \"Min Lock Period\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 9843" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 15380 " "The value of the parameter \"Min Lock Period\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 15380" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max Lock Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max Lock Period\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 20408 " "The value of the parameter \"Max Lock Period\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 20408" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 33330 " "The value of the parameter \"Max Lock Period\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 33330" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603737287 ""} } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3172 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 77 -1 0 } } } 0 176127 "The parameters of the PLL %1!s! and the PLL %2!s! do not have the same values - hence these PLLs cannot be merged" 0 0 "Fitter" 0 -1 1616603737287 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "clk_sys~input (placed in PIN 89 (CLK6, DIFFCLK_3p)) " "Promoted node clk_sys~input (placed in PIN 89 (CLK6, DIFFCLK_3p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1 Global Clock CLKCTRL_G9 " "Automatically promoted clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1 to use location or clock signal Global Clock CLKCTRL_G9" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3170 14177 15141 0 0 "" 0 "" "" } } } } } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} } { { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 688 2216 2392 704 "clk_sys" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 28473 14177 15141 0 0 "" 0 "" "" } } } } } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603737915 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_2) " "Automatically promoted node MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G8 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603737915 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_2) " "Automatically promoted node MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G7 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603737915 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1) " "Automatically promoted node tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3172 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603737915 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "data_shifter:RX_CICFIR_GAINER\|data_valid_out_Q " "Automatically promoted node data_shifter:RX_CICFIR_GAINER\|data_valid_out_Q " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 13 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 1986 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603737915 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} } { { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 28064 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603737915 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "stm32_interface:STM32_INTERFACE\|reset_n " "Automatically promoted node stm32_interface:STM32_INTERFACE\|reset_n " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated\|mac_out2 " "Destination node mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated\|mac_out2" { } { { "db/mult_jnp.tdf" "" { Text "C:/FPGA/db/mult_jnp.tdf" 46 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 633 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mixer:RX_MIXER_Q\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated\|mac_out2 " "Destination node mixer:RX_MIXER_Q\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated\|mac_out2" { } { { "db/mult_jnp.tdf" "" { Text "C:/FPGA/db/mult_jnp.tdf" 46 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3868 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_r9b:wr_ptr\|counter_reg_bit\[1\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_r9b:wr_ptr\|counter_reg_bit\[1\]" { } { { "db/cntr_r9b.tdf" "" { Text "C:/FPGA/db/cntr_r9b.tdf" 43 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4890 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_r9b:wr_ptr\|counter_reg_bit\[0\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_r9b:wr_ptr\|counter_reg_bit\[0\]" { } { { "db/cntr_r9b.tdf" "" { Text "C:/FPGA/db/cntr_r9b.tdf" 43 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4891 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_7a7:usedw_counter\|counter_reg_bit\[1\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_7a7:usedw_counter\|counter_reg_bit\[1\]" { } { { "db/cntr_7a7.tdf" "" { Text "C:/FPGA/db/cntr_7a7.tdf" 44 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4898 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_7a7:usedw_counter\|counter_reg_bit\[0\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_7a7:usedw_counter\|counter_reg_bit\[0\]" { } { { "db/cntr_7a7.tdf" "" { Text "C:/FPGA/db/cntr_7a7.tdf" 44 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4899 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_q9b:rd_ptr_msb\|counter_reg_bit\[0\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_q9b:rd_ptr_msb\|counter_reg_bit\[0\]" { } { { "db/cntr_q9b.tdf" "" { Text "C:/FPGA/db/cntr_q9b.tdf" 38 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4906 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[4\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[4\]" { } { { "db/cntr_u9b.tdf" "" { Text "C:/FPGA/db/cntr_u9b.tdf" 58 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 5501 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[3\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[3\]" { } { { "db/cntr_u9b.tdf" "" { Text "C:/FPGA/db/cntr_u9b.tdf" 58 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 5502 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[2\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[2\]" { } { { "db/cntr_u9b.tdf" "" { Text "C:/FPGA/db/cntr_u9b.tdf" 58 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 5503 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737915 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Design Software" 0 -1 1616603737915 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1616603737915 ""} } { { "stm32_interface.v" "" { Text "C:/FPGA/stm32_interface.v" 64 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3841 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603737915 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "stm32_interface:STM32_INTERFACE\|tx " "Automatically promoted node stm32_interface:STM32_INTERFACE\|tx " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603737917 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_abt:auto_generated\|mac_out2 " "Destination node tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_abt:auto_generated\|mac_out2" { } { { "db/mult_abt.tdf" "" { Text "C:/FPGA/db/mult_abt.tdf" 46 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3104 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737917 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a0 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a0" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 39 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2202 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737917 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a1 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a1" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 76 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2203 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737917 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a2 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a2" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 113 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2204 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737917 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a3 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a3" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 150 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2205 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737917 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a4 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a4" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 187 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2206 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737917 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a5 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a5" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 224 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2207 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737917 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a6 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a6" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 261 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2208 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737917 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a7 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a7" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 298 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2209 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737917 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a8 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a8" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 335 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2210 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737917 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Design Software" 0 -1 1616603737917 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1616603737917 ""} } { { "stm32_interface.v" "" { Text "C:/FPGA/stm32_interface.v" 63 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3831 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603737917 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|alt_sld_fab_with_jtag_input:\\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric\|alt_sld_fab:instrumentation_fabric\|alt_sld_fab_alt_sld_fab:alt_sld_fab\|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric\|sld_jtag_hub:\\jtag_hub_gen:real_sld_jtag_hub\|clr_reg " "Automatically promoted node sld_hub:auto_hub\|alt_sld_fab_with_jtag_input:\\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric\|alt_sld_fab:instrumentation_fabric\|alt_sld_fab_alt_sld_fab:alt_sld_fab\|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric\|sld_jtag_hub:\\jtag_hub_gen:real_sld_jtag_hub\|clr_reg " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603737918 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|alt_sld_fab_with_jtag_input:\\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric\|alt_sld_fab:instrumentation_fabric\|alt_sld_fab_alt_sld_fab:alt_sld_fab\|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric\|sld_jtag_hub:\\jtag_hub_gen:real_sld_jtag_hub\|clr_reg~_wirecell " "Destination node sld_hub:auto_hub\|alt_sld_fab_with_jtag_input:\\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric\|alt_sld_fab:instrumentation_fabric\|alt_sld_fab_alt_sld_fab:alt_sld_fab\|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric\|sld_jtag_hub:\\jtag_hub_gen:real_sld_jtag_hub\|clr_reg~_wirecell" { } { { "sld_jtag_hub.vhd" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 255 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 28425 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737918 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1616603737918 ""} } { { "sld_jtag_hub.vhd" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 255 -1 0 } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sld_hub:auto_hub\|alt_sld_fab_with_jtag_input:\\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric\|alt_sld_fab:instrumentation_fabric\|alt_sld_fab_alt_sld_fab:alt_sld_fab\|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric\|sld_jtag_hub:\\jtag_hub_gen:real_sld_jtag_hub\|clr_reg" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 28174 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603737918 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|alt_sld_fab_with_jtag_input:\\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric\|alt_sld_fab:instrumentation_fabric\|alt_sld_fab_alt_sld_fab:alt_sld_fab\|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric\|sld_jtag_hub:\\jtag_hub_gen:real_sld_jtag_hub\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell " "Automatically promoted node sld_hub:auto_hub\|alt_sld_fab_with_jtag_input:\\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric\|alt_sld_fab:instrumentation_fabric\|alt_sld_fab_alt_sld_fab:alt_sld_fab\|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric\|sld_jtag_hub:\\jtag_hub_gen:real_sld_jtag_hub\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603737918 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|altsource_probe_body:altsource_probe_body_inst\|altsource_probe_impl:\\wider_probe_gen:wider_probe_inst\|hold_reg\[0\]~0 " "Destination node DEBUG:DBG_ADC\|altsource_probe_top:in_system_sources_probes_0\|altsource_probe:issp_impl\|altsource_probe_body:altsource_probe_body_inst\|altsource_probe_impl:\\wider_probe_gen:wider_probe_inst\|hold_reg\[0\]~0" { } { { "altsource_probe_body.vhd" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altsource_probe_body.vhd" 803 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 12264 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603737918 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1616603737918 ""} } { { "sld_hub.vhd" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/sld_hub.vhd" 1584 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 28426 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603737918 ""} -{ "Warning" "WCUT_PLL_INCLK_NOT_FROM_DEDICATED_INPUT" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 0 " "PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input" { { "Info" "ICUT_CUT_INPUT_PORT_SIGNAL_SOURCE" "INCLK\[0\] MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 driven by clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1 " "Input port INCLK\[0\] of node \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" is driven by clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 45 -1 0 } } { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 112 0 0 } } { "db/ip/clock_buffer/clock_buffer.v" "" { Text "C:/FPGA/db/ip/clock_buffer/clock_buffer.v" 14 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 624 2416 2688 728 "SYSCLK_BUFFER" "" } } } } } 0 15024 "Input port %1!s! of node \"%2!s!\" is %3!s!" 0 0 "Design Software" 0 -1 1616603738169 ""} } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } } 0 15055 "PLL \"%1!s!\" input clock inclk\[%2!d!\] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input" 0 0 "Fitter" 0 -1 1616603738169 ""} -{ "Warning" "WCUT_PLL_NON_ZDB_COMP_CLK_FEEDING_IO" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 compensate_clock 0 " "PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" is in normal or source synchronous mode with output clock \"compensate_clock\" set to clk\[0\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } } 0 15058 "PLL \"%1!s!\" is in normal or source synchronous mode with output clock \"%2!s!\" set to clk\[%3!d!\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" 0 0 "Fitter" 0 -1 1616603738173 ""} -{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 clk\[0\] AUDIO_I2S_CLOCK~output " "PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" output port clk\[0\] feeds output pin \"AUDIO_I2S_CLOCK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 1000 3408 3584 1016 "AUDIO_I2S_CLOCK" "" } } } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "Fitter" 0 -1 1616603738174 ""} -{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 clk\[1\] AUDIO_48K_CLOCK~output " "PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"AUDIO_48K_CLOCK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 1016 3408 3584 1032 "AUDIO_48K_CLOCK" "" } } } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "Fitter" 0 -1 1616603738174 ""} -{ "Warning" "WCUT_PLL_INCLK_NOT_FROM_DEDICATED_INPUT" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 0 " "PLL \"tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input" { { "Info" "ICUT_CUT_INPUT_PORT_SIGNAL_SOURCE" "INCLK\[0\] tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 driven by clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1 " "Input port INCLK\[0\] of node \"tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1\" is driven by clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1" { } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 720 3080 3320 872 "TX_PLL" "" } } } } { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 45 -1 0 } } { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 112 0 0 } } { "db/ip/clock_buffer/clock_buffer.v" "" { Text "C:/FPGA/db/ip/clock_buffer/clock_buffer.v" 14 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 624 2416 2688 728 "SYSCLK_BUFFER" "" } } } } } 0 15024 "Input port %1!s! of node \"%2!s!\" is %3!s!" 0 0 "Design Software" 0 -1 1616603738180 ""} } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 720 3080 3320 872 "TX_PLL" "" } } } } } 0 15055 "PLL \"%1!s!\" input clock inclk\[%2!d!\] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input" 0 0 "Fitter" 0 -1 1616603738180 ""} -{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 clk\[0\] DAC_CLK~output " "PLL \"tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1\" output port clk\[0\] feeds output pin \"DAC_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 720 3080 3320 872 "TX_PLL" "" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 80 6288 6464 96 "DAC_CLK" "" } } } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "Fitter" 0 -1 1616603738181 ""} -{ "Info" "IFIOMGR_CONFIGURATION_VOLTAGE_IS_AUTOMATICALLY_ENFORCED" "Cyclone IV E Active Serial " "Configuration voltage level is automatically enforced for the device family 'Cyclone IV E' with the configuration scheme 'Active Serial'" { } { } 0 169197 "Configuration voltage level is automatically enforced for the device family '%1!s!' with the configuration scheme '%2!s!'" 0 0 "Fitter" 0 -1 1616603738601 ""} -{ "Info" "IFIOMGR_IO_BANK_VCCIO_SET_FOR_CONFIGURATION" "2.5V 1 " "Configuration voltage level of 2.5V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 2.5V." { } { } 0 169213 "Configuration voltage level of %1!s! is enforced on the I/O bank %2!s!. The VCCIO of the I/O bank %2!s! is set to %1!s!." 0 0 "Fitter" 0 -1 1616603738601 ""} -{ "Info" "IFIOMGR_IO_BANK_VCCIO_SET_FOR_CONFIGURATION" "2.5V 1 " "Configuration voltage level of 2.5V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 2.5V." { } { } 0 169213 "Configuration voltage level of %1!s! is enforced on the I/O bank %2!s!. The VCCIO of the I/O bank %2!s! is set to %1!s!." 0 0 "Fitter" 0 -1 1616603738601 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616603738628 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 1 0 "Fitter" 0 -1 1616603748615 ""} -{ "Warning" "WFIOMGR_FIOMGR_MUST_USE_EXTERNAL_CLAMPING_DIODE_TOP_LEVEL" "1 " "Following 1 pins must use external clamping diodes." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "FLASH_MISO 2.5 V 13 " "Pin FLASH_MISO uses I/O standard 2.5 V at 13" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { FLASH_MISO } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FLASH_MISO" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 1000 3744 3920 1016 "FLASH_MISO" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 468 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748656 ""} } { } 0 169180 "Following %1!d! pins must use external clamping diodes." 1 0 "Fitter" 0 -1 1616603748656 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "24 Cyclone IV E " "24 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[7\] 3.3-V LVTTL 46 " "Pin STM32_DATA_BUS\[7\] uses I/O standard 3.3-V LVTTL at 46" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[7] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[7\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 441 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[6\] 3.3-V LVTTL 43 " "Pin STM32_DATA_BUS\[6\] uses I/O standard 3.3-V LVTTL at 43" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[6] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[6\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 442 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[5\] 3.3-V LVTTL 42 " "Pin STM32_DATA_BUS\[5\] uses I/O standard 3.3-V LVTTL at 42" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[5] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[5\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 443 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[4\] 3.3-V LVTTL 39 " "Pin STM32_DATA_BUS\[4\] uses I/O standard 3.3-V LVTTL at 39" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[4] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[4\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 444 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[3\] 3.3-V LVTTL 38 " "Pin STM32_DATA_BUS\[3\] uses I/O standard 3.3-V LVTTL at 38" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[3] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[3\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 445 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[2\] 3.3-V LVTTL 51 " "Pin STM32_DATA_BUS\[2\] uses I/O standard 3.3-V LVTTL at 51" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[2] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[2\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 446 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[1\] 3.3-V LVTTL 50 " "Pin STM32_DATA_BUS\[1\] uses I/O standard 3.3-V LVTTL at 50" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[1] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[1\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 447 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[0\] 3.3-V LVTTL 49 " "Pin STM32_DATA_BUS\[0\] uses I/O standard 3.3-V LVTTL at 49" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[0] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[0\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 448 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_CLK 3.3-V LVTTL 33 " "Pin STM32_CLK uses I/O standard 3.3-V LVTTL at 33" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_CLK } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_CLK" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 2840 3016 184 "STM32_CLK" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 464 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_SYNC 3.3-V LVTTL 32 " "Pin STM32_SYNC uses I/O standard 3.3-V LVTTL at 32" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_SYNC } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_SYNC" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 216 2840 3016 232 "STM32_SYNC" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 465 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "clk_sys 3.3-V LVTTL 89 " "Pin clk_sys uses I/O standard 3.3-V LVTTL at 89" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { clk_sys } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk_sys" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 688 2216 2392 704 "clk_sys" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 467 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[0\] 3.3-V LVTTL 68 " "Pin ADC_INPUT\[0\] uses I/O standard 3.3-V LVTTL at 68" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[0] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[0\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 440 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[1\] 3.3-V LVTTL 67 " "Pin ADC_INPUT\[1\] uses I/O standard 3.3-V LVTTL at 67" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[1] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[1\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 439 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_OTR 3.3-V LVTTL 44 " "Pin ADC_OTR uses I/O standard 3.3-V LVTTL at 44" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_OTR } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_OTR" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 232 2840 3016 248 "ADC_OTR" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 466 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[2\] 3.3-V LVTTL 66 " "Pin ADC_INPUT\[2\] uses I/O standard 3.3-V LVTTL at 66" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[2] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[2\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 438 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[3\] 3.3-V LVTTL 65 " "Pin ADC_INPUT\[3\] uses I/O standard 3.3-V LVTTL at 65" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[3] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[3\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 437 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[7\] 3.3-V LVTTL 58 " "Pin ADC_INPUT\[7\] uses I/O standard 3.3-V LVTTL at 58" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[7] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[7\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 433 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[6\] 3.3-V LVTTL 59 " "Pin ADC_INPUT\[6\] uses I/O standard 3.3-V LVTTL at 59" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[6] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[6\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 434 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[5\] 3.3-V LVTTL 60 " "Pin ADC_INPUT\[5\] uses I/O standard 3.3-V LVTTL at 60" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[5] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[5\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 435 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[4\] 3.3-V LVTTL 64 " "Pin ADC_INPUT\[4\] uses I/O standard 3.3-V LVTTL at 64" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[4] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[4\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 436 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[11\] 3.3-V LVTTL 52 " "Pin ADC_INPUT\[11\] uses I/O standard 3.3-V LVTTL at 52" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[11] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[11\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 429 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[10\] 3.3-V LVTTL 53 " "Pin ADC_INPUT\[10\] uses I/O standard 3.3-V LVTTL at 53" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[10] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[10\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 430 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[9\] 3.3-V LVTTL 54 " "Pin ADC_INPUT\[9\] uses I/O standard 3.3-V LVTTL at 54" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[9] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[9\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 431 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[8\] 3.3-V LVTTL 55 " "Pin ADC_INPUT\[8\] uses I/O standard 3.3-V LVTTL at 55" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[8] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[8\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 432 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603748657 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 1 0 "Fitter" 0 -1 1616603748657 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/FPGA/output_files/WOLF-LITE.fit.smsg " "Generated suppressed messages file C:/FPGA/output_files/WOLF-LITE.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1616603749044 ""} -{ "Info" "IQFIT_LEGACY_FLOW_QID_AND_CHECK_IO_COMPILE" "" "Results from the I/O assignment analysis compilation cannot be preserved because I/O assignment analysis was run with Incremental Compilation enabled" { } { } 0 11763 "Results from the I/O assignment analysis compilation cannot be preserved because I/O assignment analysis was run with Incremental Compilation enabled" 0 0 "Fitter" 0 -1 1616603749321 ""} -{ "Info" "IQEXE_ERROR_COUNT" "I/O Assignment Analysis 0 s 7 s Quartus Prime " "Quartus Prime I/O Assignment Analysis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4987 " "Peak virtual memory: 4987 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1616603749354 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 24 19:35:49 2021 " "Processing ended: Wed Mar 24 19:35:49 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1616603749354 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1616603749354 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1616603749354 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1616603749354 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1616603751996 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1616603752013 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 24 19:35:50 2021 " "Processing started: Wed Mar 24 19:35:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1616603752013 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1616603752013 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off WOLF-LITE -c WOLF-LITE " "Command: quartus_fit --read_settings_files=off --write_settings_files=off WOLF-LITE -c WOLF-LITE" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1616603752013 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1616603752277 ""} -{ "Info" "0" "" "Project = WOLF-LITE" { } { } 0 0 "Project = WOLF-LITE" 0 0 "Fitter" 0 0 1616603752278 ""} -{ "Info" "0" "" "Revision = WOLF-LITE" { } { } 0 0 "Revision = WOLF-LITE" 0 0 "Fitter" 0 0 1616603752278 ""} -{ "Info" "IQCU_OPT_MODE_DESCRIPTION" "Aggressive Performance timing performance increased logic area and compilation time " "Aggressive Performance optimization mode selected -- timing performance will be prioritized at the potential cost of increased logic area and compilation time" { } { } 0 16303 "%1!s! optimization mode selected -- %2!s! will be prioritized at the potential cost of %3!s!" 0 0 "Fitter" 0 -1 1616603752706 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1616603752719 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "WOLF-LITE EP4CE10E22C8 " "Selected device EP4CE10E22C8 for design \"WOLF-LITE\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1616603752853 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616603752931 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1616603752931 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] 64 335 0 0 " "Implementing clock multiplication of 64, clock division of 335, and phase shift of 0 degrees (0 ps) for MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1616603752993 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] 1 1340 0 0 " "Implementing clock multiplication of 1, clock division of 1340, and phase shift of 0 degrees (0 ps) for MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 600 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1616603752993 ""} } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1616603752993 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|wire_pll1_clk\[0\] 5 2 0 0 " "Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3172 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1616603753000 ""} } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3172 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1616603753000 ""} -{ "Warning" "WMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a0 " "Atom \"tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a0\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Design Software" 0 -1 1616603753004 "|WOLF-LITE|tx_nco:TX_NCO|tx_nco_nco_ii_0:nco_ii_0|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_4k82:auto_generated|ram_block1a0"} } { } 0 18550 "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." 1 0 "Fitter" 0 -1 1616603753004 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1616603753310 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6E22C8 " "Device EP4CE6E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1616603754145 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C8 " "Device EP4CE15E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1616603754145 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C8 " "Device EP4CE22E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1616603754145 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1616603754145 ""} -{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1616603754179 ""} -{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1616603754179 ""} -{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1616603754179 ""} -{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1616603754179 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 1 0 "Fitter" 0 -1 1616603754184 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1616603754458 ""} -{ "Info" "IFIOMGR_CONFIGURATION_VOLTAGE_IS_AUTOMATICALLY_ENFORCED" "Cyclone IV E Active Serial " "Configuration voltage level is automatically enforced for the device family 'Cyclone IV E' with the configuration scheme 'Active Serial'" { } { } 0 169197 "Configuration voltage level is automatically enforced for the device family '%1!s!' with the configuration scheme '%2!s!'" 0 0 "Fitter" 0 -1 1616603754852 ""} -{ "Info" "IFIOMGR_IO_BANK_VCCIO_SET_FOR_CONFIGURATION" "2.5V 1 " "Configuration voltage level of 2.5V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 2.5V." { } { } 0 169213 "Configuration voltage level of %1!s! is enforced on the I/O bank %2!s!. The VCCIO of the I/O bank %2!s! is set to %1!s!." 0 0 "Fitter" 0 -1 1616603754852 ""} -{ "Info" "IFIOMGR_IO_BANK_VCCIO_SET_FOR_CONFIGURATION" "2.5V 1 " "Configuration voltage level of 2.5V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 2.5V." { } { } 0 169213 "Configuration voltage level of %1!s! is enforced on the I/O bank %2!s!. The VCCIO of the I/O bank %2!s! is set to %1!s!." 0 0 "Fitter" 0 -1 1616603754852 ""} -{ "Warning" "WFSAC_FSAC_PLL_MERGING_PARAMETERS_MISMATCH_WARNING" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 " "The parameters of the PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 and the PLL MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 do not have the same values - hence these PLLs cannot be merged" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "M MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"M\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 64 " "The value of the parameter \"M\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 64" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "M tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 10 " "The value of the parameter \"M\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 10" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "N MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"N\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 5 " "The value of the parameter \"N\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 5" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "N tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 1 " "The value of the parameter \"N\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "LOOP FILTER R MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"LOOP FILTER R\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 6000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 6000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "LOOP FILTER R tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 4000 " "The value of the parameter \"LOOP FILTER R\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 4000" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "VCO POST SCALE MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"VCO POST SCALE\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 1 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 1" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "VCO POST SCALE tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 2 " "The value of the parameter \"VCO POST SCALE\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 2" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min VCO Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min VCO Period\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Min VCO Period\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min VCO Period tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Min VCO Period\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max VCO Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max VCO Period\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 1666 " "The value of the parameter \"Max VCO Period\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 1666" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max VCO Period tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 3333 " "The value of the parameter \"Max VCO Period\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 3333" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Center VCO Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Center VCO Period\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 769 " "The value of the parameter \"Center VCO Period\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 769" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Center VCO Period tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 1538 " "The value of the parameter \"Center VCO Period\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 1538" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Min Lock Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Min Lock Period\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 9843 " "The value of the parameter \"Min Lock Period\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 9843" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Min Lock Period tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 15380 " "The value of the parameter \"Min Lock Period\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 15380" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUES_MISMATCH" "Max Lock Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 " "The values of the parameter \"Max Lock Period\" do not match for the PLL atoms MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 and PLL tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1" { { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 20408 " "The value of the parameter \"Max Lock Period\" for the PLL atom MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 is 20408" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} { "Info" "IFSAC_FSAC_PLL_MERGING_PARAMETER_VALUE" "Max Lock Period tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 33330 " "The value of the parameter \"Max Lock Period\" for the PLL atom tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 is 33330" { } { } 0 176121 "The value of the parameter \"%1!s!\" for the PLL atom %2!s! is %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} } { } 0 176120 "The values of the parameter \"%1!s!\" do not match for the PLL atoms %2!s! and PLL %3!s!" 0 0 "Design Software" 0 -1 1616603755297 ""} } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3172 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 77 -1 0 } } } 0 176127 "The parameters of the PLL %1!s! and the PLL %2!s! do not have the same values - hence these PLLs cannot be merged" 0 0 "Fitter" 0 -1 1616603755297 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1616603756915 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1616603756915 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1616603756915 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1616603756915 ""} -{ "Info" "ISTA_SDC_FOUND" "SDC.sdc " "Reading SDC File: 'SDC.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1616603757047 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 5 rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid port or pin or register or keeper or net or combinational node or node " "Ignored filter at SDC.sdc(5): rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid could not be matched with a port or pin or register or keeper or net or combinational node or node" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1616603757049 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock SDC.sdc 5 Argument is not an object ID " "Ignored create_clock at SDC.sdc(5): Argument is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name \"iq_valid\" -period 48KHz \{rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid\} " "create_clock -name \"iq_valid\" -period 48KHz \{rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid\}" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603757050 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1616603757050 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 7 clock_sys clock " "Ignored filter at SDC.sdc(7): clock_sys could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 7 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1616603757050 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 7 iq_valid clock " "Ignored filter at SDC.sdc(7): iq_valid could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 7 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1616603757050 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1616603757051 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 335 -multiply_by 64 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 335 -multiply_by 64 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1616603757058 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 1340 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 1340 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1616603757058 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{TX_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{TX_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1616603757058 ""} } { } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1616603757058 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 13 clock_crystal clock " "Ignored filter at SDC.sdc(13): clock_crystal could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1616603757058 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_output_delay SDC.sdc 13 Argument -clock is not an object ID " "Ignored set_output_delay at SDC.sdc(13): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_output_delay -clock clock_crystal -max 36ps \[get_ports \{DAC_OUTPUT\[*\]\}\] " "set_output_delay -clock clock_crystal -max 36ps \[get_ports \{DAC_OUTPUT\[*\]\}\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603757058 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1616603757058 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_output_delay SDC.sdc 14 Argument -clock is not an object ID " "Ignored set_output_delay at SDC.sdc(14): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_output_delay -clock clock_crystal -min 0ps \[get_ports \{DAC_OUTPUT\[*\]\}\] " "set_output_delay -clock clock_crystal -min 0ps \[get_ports \{DAC_OUTPUT\[*\]\}\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 14 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603757059 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 14 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1616603757059 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 18 clock_adc clock " "Ignored filter at SDC.sdc(18): clock_adc could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1616603757059 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 18 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(18): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_INPUT\[*\]\] " "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_INPUT\[*\]\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603757060 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1616603757060 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 19 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(19): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_INPUT\[*\]\] " "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_INPUT\[*\]\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 19 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603757060 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 19 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1616603757060 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 20 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(20): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_OTR\] " "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_OTR\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 20 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603757060 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 20 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1616603757060 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 21 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(21): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_OTR\] " "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_OTR\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603757061 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1616603757061 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 27 iq_valid clock " "Ignored filter at SDC.sdc(27): iq_valid could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1616603757062 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 27 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(27): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603757063 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1616603757063 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 28 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(28): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 28 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603757063 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 28 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1616603757063 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 29 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(29): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 29 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603757063 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 29 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1616603757063 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 30 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(30): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 30 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603757064 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 30 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1616603757064 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 31 clock_sys clock " "Ignored filter at SDC.sdc(31): clock_sys could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1616603757064 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 31 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(31): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603757064 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1616603757064 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 32 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(32): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 32 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603757065 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 32 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1616603757065 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Node: rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_head\[14\] rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_head\[14\] is being clocked by rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1616603757123 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 1 0 "Fitter" 0 -1 1616603757123 "|WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1616603757272 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1616603757278 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1616603757279 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1616603757279 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1616603757279 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 15.547 clk_sys " " 15.547 clk_sys" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1616603757279 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 clock_stm32 " " 40.000 clock_stm32" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1616603757279 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 81.378 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 81.378 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1616603757279 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "20832.980 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\] " "20832.980 MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1616603757279 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 6.218 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 6.218 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1616603757279 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1616603757279 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "clk_sys~input (placed in PIN 89 (CLK6, DIFFCLK_3p)) " "Promoted node clk_sys~input (placed in PIN 89 (CLK6, DIFFCLK_3p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1 Global Clock CLKCTRL_G9 " "Automatically promoted clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1 to use location or clock signal Global Clock CLKCTRL_G9" { } { { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 61 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3170 14177 15141 0 0 "" 0 "" "" } } } } } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603758816 ""} } { { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 688 2216 2392 704 "clk_sys" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 28473 14177 15141 0 0 "" 0 "" "" } } } } } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603758816 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_2) " "Automatically promoted node MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G8 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603758816 ""} } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603758816 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_2) " "Automatically promoted node MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G7 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603758816 ""} } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603758816 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1) " "Automatically promoted node tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603758816 ""} } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3172 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603758816 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "data_shifter:RX_CICFIR_GAINER\|data_valid_out_Q " "Automatically promoted node data_shifter:RX_CICFIR_GAINER\|data_valid_out_Q " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603758816 ""} } { { "data_shifter.v" "" { Text "C:/FPGA/data_shifter.v" 13 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 1986 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603758816 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603758817 ""} } { { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 28064 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603758817 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "stm32_interface:STM32_INTERFACE\|reset_n " "Automatically promoted node stm32_interface:STM32_INTERFACE\|reset_n " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603758817 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated\|mac_out2 " "Destination node mixer:RX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated\|mac_out2" { } { { "db/mult_jnp.tdf" "" { Text "C:/FPGA/db/mult_jnp.tdf" 46 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 633 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758817 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mixer:RX_MIXER_Q\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated\|mac_out2 " "Destination node mixer:RX_MIXER_Q\|lpm_mult:lpm_mult_component\|mult_jnp:auto_generated\|mac_out2" { } { { "db/mult_jnp.tdf" "" { Text "C:/FPGA/db/mult_jnp.tdf" 46 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3868 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758817 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_r9b:wr_ptr\|counter_reg_bit\[1\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_r9b:wr_ptr\|counter_reg_bit\[1\]" { } { { "db/cntr_r9b.tdf" "" { Text "C:/FPGA/db/cntr_r9b.tdf" 43 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4890 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758817 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_r9b:wr_ptr\|counter_reg_bit\[0\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_r9b:wr_ptr\|counter_reg_bit\[0\]" { } { { "db/cntr_r9b.tdf" "" { Text "C:/FPGA/db/cntr_r9b.tdf" 43 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4891 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758817 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_7a7:usedw_counter\|counter_reg_bit\[1\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_7a7:usedw_counter\|counter_reg_bit\[1\]" { } { { "db/cntr_7a7.tdf" "" { Text "C:/FPGA/db/cntr_7a7.tdf" 44 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4898 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758817 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_7a7:usedw_counter\|counter_reg_bit\[0\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_7a7:usedw_counter\|counter_reg_bit\[0\]" { } { { "db/cntr_7a7.tdf" "" { Text "C:/FPGA/db/cntr_7a7.tdf" 44 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4899 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758817 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_q9b:rd_ptr_msb\|counter_reg_bit\[0\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|alt_cic_dec_siso:dec_one\|auk_dspip_channel_buffer:fifo_regulator\|scfifo:buffer_FIFO\|scfifo_qm51:auto_generated\|a_dpfifo_5ku:dpfifo\|cntr_q9b:rd_ptr_msb\|counter_reg_bit\[0\]" { } { { "db/cntr_q9b.tdf" "" { Text "C:/FPGA/db/cntr_q9b.tdf" 38 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 4906 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758817 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[4\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[4\]" { } { { "db/cntr_u9b.tdf" "" { Text "C:/FPGA/db/cntr_u9b.tdf" 58 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 5501 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758817 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[3\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[3\]" { } { { "db/cntr_u9b.tdf" "" { Text "C:/FPGA/db/cntr_u9b.tdf" 58 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 5502 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758817 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[2\] " "Destination node rx_cic:RX_CIC_Q\|rx_cic_cic_ii_0:cic_ii_0\|alt_cic_core:core\|auk_dspip_avalon_streaming_source:output_source_0\|scfifo:source_FIFO\|scfifo_ai71:auto_generated\|a_dpfifo_7qv:dpfifo\|cntr_u9b:wr_ptr\|counter_reg_bit\[2\]" { } { { "db/cntr_u9b.tdf" "" { Text "C:/FPGA/db/cntr_u9b.tdf" 58 17 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 5503 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758817 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Design Software" 0 -1 1616603758817 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1616603758817 ""} } { { "stm32_interface.v" "" { Text "C:/FPGA/stm32_interface.v" 64 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3841 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603758817 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "stm32_interface:STM32_INTERFACE\|tx " "Automatically promoted node stm32_interface:STM32_INTERFACE\|tx " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1616603758818 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_abt:auto_generated\|mac_out2 " "Destination node tx_mixer:TX_MIXER_I\|lpm_mult:lpm_mult_component\|mult_abt:auto_generated\|mac_out2" { } { { "db/mult_abt.tdf" "" { Text "C:/FPGA/db/mult_abt.tdf" 46 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3104 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758818 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a0 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a0" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 39 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2202 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758818 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a1 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a1" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 76 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2203 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758818 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a2 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a2" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 113 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2204 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758818 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a3 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a3" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 150 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2205 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758818 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a4 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a4" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 187 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2206 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758818 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a5 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a5" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 224 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2207 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758818 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a6 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a6" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 261 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2208 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758818 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a7 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a7" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 298 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2209 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758818 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a8 " "Destination node tx_nco:TX_NCO\|tx_nco_nco_ii_0:nco_ii_0\|asj_nco_as_m_dp_cen:ux0220\|altsyncram:altsyncram_component\|altsyncram_4k82:auto_generated\|ram_block1a8" { } { { "db/altsyncram_4k82.tdf" "" { Text "C:/FPGA/db/altsyncram_4k82.tdf" 335 2 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 2210 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1616603758818 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Design Software" 0 -1 1616603758818 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1616603758818 ""} } { { "stm32_interface.v" "" { Text "C:/FPGA/stm32_interface.v" 63 -1 0 } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 3831 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1616603758818 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1616603760801 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616603760843 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1616603760846 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1616603760892 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1616603760961 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1616603761029 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1616603762034 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "32 Embedded multiplier block " "Packed 32 registers into blocks of type Embedded multiplier block" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Design Software" 0 -1 1616603762070 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1616603762070 ""} -{ "Warning" "WCUT_PLL_INCLK_NOT_FROM_DEDICATED_INPUT" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 0 " "PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input" { { "Info" "ICUT_CUT_INPUT_PORT_SIGNAL_SOURCE" "INCLK\[0\] MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 driven by clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1 " "Input port INCLK\[0\] of node \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" is driven by clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 45 -1 0 } } { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 112 0 0 } } { "db/ip/clock_buffer/clock_buffer.v" "" { Text "C:/FPGA/db/ip/clock_buffer/clock_buffer.v" 14 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 624 2416 2688 728 "SYSCLK_BUFFER" "" } } } } } 0 15024 "Input port %1!s! of node \"%2!s!\" is %3!s!" 0 0 "Design Software" 0 -1 1616603762337 ""} } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } } 0 15055 "PLL \"%1!s!\" input clock inclk\[%2!d!\] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input" 0 0 "Fitter" 0 -1 1616603762337 ""} -{ "Warning" "WCUT_PLL_NON_ZDB_COMP_CLK_FEEDING_IO" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 compensate_clock 0 " "PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" is in normal or source synchronous mode with output clock \"compensate_clock\" set to clk\[0\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } } 0 15058 "PLL \"%1!s!\" is in normal or source synchronous mode with output clock \"%2!s!\" set to clk\[%3!d!\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" 0 0 "Fitter" 0 -1 1616603762341 ""} -{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 clk\[0\] AUDIO_I2S_CLOCK~output " "PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" output port clk\[0\] feeds output pin \"AUDIO_I2S_CLOCK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 1000 3408 3584 1016 "AUDIO_I2S_CLOCK" "" } } } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "Fitter" 0 -1 1616603762341 ""} -{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1 clk\[1\] AUDIO_48K_CLOCK~output " "PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"AUDIO_48K_CLOCK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/main_pll_altpll.v" "" { Text "C:/FPGA/db/main_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "MAIN_PLL.v" "" { Text "C:/FPGA/MAIN_PLL.v" 94 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 944 3080 3320 1112 "MAIN_PLL" "" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 1016 3408 3584 1032 "AUDIO_48K_CLOCK" "" } } } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "Fitter" 0 -1 1616603762341 ""} -{ "Warning" "WCUT_PLL_INCLK_NOT_FROM_DEDICATED_INPUT" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 0 " "PLL \"tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input" { { "Info" "ICUT_CUT_INPUT_PORT_SIGNAL_SOURCE" "INCLK\[0\] tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 driven by clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1 " "Input port INCLK\[0\] of node \"tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1\" is driven by clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node clock_buffer:SYSCLK_BUFFER\|clock_buffer_altclkctrl_0:altclkctrl_0\|clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component\|clkctrl1" { } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 720 3080 3320 872 "TX_PLL" "" } } } } { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 45 -1 0 } } { "db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" "" { Text "C:/FPGA/db/ip/clock_buffer/submodules/clock_buffer_altclkctrl_0.v" 112 0 0 } } { "db/ip/clock_buffer/clock_buffer.v" "" { Text "C:/FPGA/db/ip/clock_buffer/clock_buffer.v" 14 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 624 2416 2688 728 "SYSCLK_BUFFER" "" } } } } } 0 15024 "Input port %1!s! of node \"%2!s!\" is %3!s!" 0 0 "Design Software" 0 -1 1616603762348 ""} } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 720 3080 3320 872 "TX_PLL" "" } } } } } 0 15055 "PLL \"%1!s!\" input clock inclk\[%2!d!\] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input" 0 0 "Fitter" 0 -1 1616603762348 ""} -{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1 clk\[0\] DAC_CLK~output " "PLL \"tx_pll:TX_PLL\|altpll:altpll_component\|tx_pll_altpll:auto_generated\|pll1\" output port clk\[0\] feeds output pin \"DAC_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/tx_pll_altpll.v" "" { Text "C:/FPGA/db/tx_pll_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "c:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "tx_pll.v" "" { Text "C:/FPGA/tx_pll.v" 90 0 0 } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 720 3080 3320 872 "TX_PLL" "" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 80 6288 6464 96 "DAC_CLK" "" } } } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "Fitter" 0 -1 1616603762349 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" { } { } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Fitter" 0 -1 1616603762710 ""} -{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:04 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:04" { } { } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Fitter" 0 -1 1616603766283 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:13 " "Fitter preparation operations ending: elapsed time is 00:00:13" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616603766505 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1616603766551 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1616603768561 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:04 " "Fitter placement preparation operations ending: elapsed time is 00:00:04" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616603772293 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1616603772433 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1616603826007 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:54 " "Fitter placement operations ending: elapsed time is 00:00:54" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616603826007 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1616603828809 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "26 X11_Y0 X22_Y11 " "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11" { } { { "loc" "" { Generic "C:/FPGA/" { { 1 { 0 "Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11"} { { 12 { 0 ""} 11 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1616603838231 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1616603838231 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:21 " "Fitter routing operations ending: elapsed time is 00:00:21" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616603850692 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 18.10 " "Total time spent on timing analysis during the Fitter is 18.10 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1616603851207 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1616603851352 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1616603852650 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1616603852658 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1616603854526 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:07 " "Fitter post-fit operations ending: elapsed time is 00:00:07" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1616603858247 ""} -{ "Info" "IFIOMGR_CONFIGURATION_VOLTAGE_IS_AUTOMATICALLY_ENFORCED" "Cyclone IV E Active Serial " "Configuration voltage level is automatically enforced for the device family 'Cyclone IV E' with the configuration scheme 'Active Serial'" { } { } 0 169197 "Configuration voltage level is automatically enforced for the device family '%1!s!' with the configuration scheme '%2!s!'" 0 0 "Fitter" 0 -1 1616603858957 ""} -{ "Info" "IFIOMGR_IO_BANK_VCCIO_SET_FOR_CONFIGURATION" "2.5V 1 " "Configuration voltage level of 2.5V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 2.5V." { } { } 0 169213 "Configuration voltage level of %1!s! is enforced on the I/O bank %2!s!. The VCCIO of the I/O bank %2!s! is set to %1!s!." 0 0 "Fitter" 0 -1 1616603858957 ""} -{ "Info" "IFIOMGR_IO_BANK_VCCIO_SET_FOR_CONFIGURATION" "2.5V 1 " "Configuration voltage level of 2.5V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 2.5V." { } { } 0 169213 "Configuration voltage level of %1!s! is enforced on the I/O bank %2!s!. The VCCIO of the I/O bank %2!s! is set to %1!s!." 0 0 "Fitter" 0 -1 1616603858957 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 1 0 "Fitter" 0 -1 1616603859129 ""} -{ "Warning" "WFIOMGR_FIOMGR_MUST_USE_EXTERNAL_CLAMPING_DIODE_TOP_LEVEL" "1 " "Following 1 pins must use external clamping diodes." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "FLASH_MISO 2.5 V 13 " "Pin FLASH_MISO uses I/O standard 2.5 V at 13" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { FLASH_MISO } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FLASH_MISO" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 1000 3744 3920 1016 "FLASH_MISO" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 468 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} } { } 0 169180 "Following %1!d! pins must use external clamping diodes." 1 0 "Fitter" 0 -1 1616603859221 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "24 Cyclone IV E " "24 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[7\] 3.3-V LVTTL 46 " "Pin STM32_DATA_BUS\[7\] uses I/O standard 3.3-V LVTTL at 46" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[7] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[7\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 441 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[6\] 3.3-V LVTTL 43 " "Pin STM32_DATA_BUS\[6\] uses I/O standard 3.3-V LVTTL at 43" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[6] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[6\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 442 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[5\] 3.3-V LVTTL 42 " "Pin STM32_DATA_BUS\[5\] uses I/O standard 3.3-V LVTTL at 42" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[5] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[5\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 443 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[4\] 3.3-V LVTTL 39 " "Pin STM32_DATA_BUS\[4\] uses I/O standard 3.3-V LVTTL at 39" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[4] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[4\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 444 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[3\] 3.3-V LVTTL 38 " "Pin STM32_DATA_BUS\[3\] uses I/O standard 3.3-V LVTTL at 38" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[3] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[3\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 445 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[2\] 3.3-V LVTTL 51 " "Pin STM32_DATA_BUS\[2\] uses I/O standard 3.3-V LVTTL at 51" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[2] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[2\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 446 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[1\] 3.3-V LVTTL 50 " "Pin STM32_DATA_BUS\[1\] uses I/O standard 3.3-V LVTTL at 50" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[1] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[1\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 447 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_DATA_BUS\[0\] 3.3-V LVTTL 49 " "Pin STM32_DATA_BUS\[0\] uses I/O standard 3.3-V LVTTL at 49" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_DATA_BUS[0] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_DATA_BUS\[0\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 3456 3632 184 "STM32_DATA_BUS" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 448 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_CLK 3.3-V LVTTL 33 " "Pin STM32_CLK uses I/O standard 3.3-V LVTTL at 33" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_CLK } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_CLK" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 168 2840 3016 184 "STM32_CLK" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 464 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "STM32_SYNC 3.3-V LVTTL 32 " "Pin STM32_SYNC uses I/O standard 3.3-V LVTTL at 32" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { STM32_SYNC } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "STM32_SYNC" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 216 2840 3016 232 "STM32_SYNC" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 465 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "clk_sys 3.3-V LVTTL 89 " "Pin clk_sys uses I/O standard 3.3-V LVTTL at 89" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { clk_sys } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk_sys" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 688 2216 2392 704 "clk_sys" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 467 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[0\] 3.3-V LVTTL 68 " "Pin ADC_INPUT\[0\] uses I/O standard 3.3-V LVTTL at 68" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[0] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[0\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 440 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[1\] 3.3-V LVTTL 67 " "Pin ADC_INPUT\[1\] uses I/O standard 3.3-V LVTTL at 67" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[1] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[1\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 439 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_OTR 3.3-V LVTTL 44 " "Pin ADC_OTR uses I/O standard 3.3-V LVTTL at 44" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_OTR } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_OTR" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { 232 2840 3016 248 "ADC_OTR" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 466 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[2\] 3.3-V LVTTL 66 " "Pin ADC_INPUT\[2\] uses I/O standard 3.3-V LVTTL at 66" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[2] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[2\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 438 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[3\] 3.3-V LVTTL 65 " "Pin ADC_INPUT\[3\] uses I/O standard 3.3-V LVTTL at 65" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[3] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[3\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 437 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[7\] 3.3-V LVTTL 58 " "Pin ADC_INPUT\[7\] uses I/O standard 3.3-V LVTTL at 58" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[7] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[7\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 433 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[6\] 3.3-V LVTTL 59 " "Pin ADC_INPUT\[6\] uses I/O standard 3.3-V LVTTL at 59" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[6] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[6\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 434 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[5\] 3.3-V LVTTL 60 " "Pin ADC_INPUT\[5\] uses I/O standard 3.3-V LVTTL at 60" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[5] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[5\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 435 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[4\] 3.3-V LVTTL 64 " "Pin ADC_INPUT\[4\] uses I/O standard 3.3-V LVTTL at 64" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[4] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[4\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 436 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[11\] 3.3-V LVTTL 52 " "Pin ADC_INPUT\[11\] uses I/O standard 3.3-V LVTTL at 52" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[11] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[11\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 429 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[10\] 3.3-V LVTTL 53 " "Pin ADC_INPUT\[10\] uses I/O standard 3.3-V LVTTL at 53" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[10] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[10\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 430 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[9\] 3.3-V LVTTL 54 " "Pin ADC_INPUT\[9\] uses I/O standard 3.3-V LVTTL at 54" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[9] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[9\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 431 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ADC_INPUT\[8\] 3.3-V LVTTL 55 " "Pin ADC_INPUT\[8\] uses I/O standard 3.3-V LVTTL at 55" { } { { "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ADC_INPUT[8] } } } { "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_INPUT\[8\]" } } } } { "WOLF-LITE.bdf" "" { Schematic "C:/FPGA/WOLF-LITE.bdf" { { -56 -56 120 -40 "ADC_INPUT" "" } } } } { "temporary_test_loc" "" { Generic "C:/FPGA/" { { 0 { 0 ""} 0 432 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1616603859221 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 1 0 "Fitter" 0 -1 1616603859221 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/FPGA/output_files/WOLF-LITE.fit.smsg " "Generated suppressed messages file C:/FPGA/output_files/WOLF-LITE.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1616603860299 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 27 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 27 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "6156 " "Peak virtual memory: 6156 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1616603865252 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 24 19:37:45 2021 " "Processing ended: Wed Mar 24 19:37:45 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1616603865252 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:55 " "Elapsed time: 00:01:55" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1616603865252 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:05:22 " "Total CPU time (on all processors): 00:05:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1616603865252 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1616603865252 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1616603867802 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1616603867823 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 24 19:37:46 2021 " "Processing started: Wed Mar 24 19:37:46 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1616603867823 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616603867823 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off WOLF-LITE -c WOLF-LITE " "Command: quartus_asm --read_settings_files=off --write_settings_files=off WOLF-LITE -c WOLF-LITE" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616603867824 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616603873645 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616603873690 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4721 " "Peak virtual memory: 4721 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1616603874605 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 24 19:37:54 2021 " "Processing ended: Wed Mar 24 19:37:54 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1616603874605 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1616603874605 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1616603874605 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616603874605 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1616603876749 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Power Analyzer Quartus Prime " "Running Quartus Prime Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1616603876774 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 24 19:37:55 2021 " "Processing started: Wed Mar 24 19:37:55 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1616603876774 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Power Analyzer" 0 -1 1616603876774 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=off --write_settings_files=off WOLF-LITE -c WOLF-LITE " "Command: quartus_pow --read_settings_files=off --write_settings_files=off WOLF-LITE -c WOLF-LITE" { } { } 0 0 "Command: %1!s!" 0 0 "Power Analyzer" 0 -1 1616603876774 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1616603877655 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1616603877655 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1616603879111 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1616603879111 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1616603879111 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Power Analyzer" 0 -1 1616603879111 ""} -{ "Info" "ISTA_SDC_FOUND" "SDC.sdc " "Reading SDC File: 'SDC.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Power Analyzer" 0 -1 1616603879238 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 5 rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid port or pin or register or keeper or net or combinational node or node " "Ignored filter at SDC.sdc(5): rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid could not be matched with a port or pin or register or keeper or net or combinational node or node" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879241 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock SDC.sdc 5 Argument is not an object ID " "Ignored create_clock at SDC.sdc(5): Argument is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name \"iq_valid\" -period 48KHz \{rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid\} " "create_clock -name \"iq_valid\" -period 48KHz \{rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid\}" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603879243 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879243 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 7 clock_sys clock " "Ignored filter at SDC.sdc(7): clock_sys could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 7 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879243 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 7 iq_valid clock " "Ignored filter at SDC.sdc(7): iq_valid could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 7 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879243 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Power Analyzer" 0 -1 1616603879244 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 335 -multiply_by 64 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 335 -multiply_by 64 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1616603879247 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 1340 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 1340 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1616603879247 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{TX_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{TX_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1616603879247 ""} } { } 0 332110 "%1!s!" 0 0 "Power Analyzer" 0 -1 1616603879247 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 13 clock_crystal clock " "Ignored filter at SDC.sdc(13): clock_crystal could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879247 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_output_delay SDC.sdc 13 Argument -clock is not an object ID " "Ignored set_output_delay at SDC.sdc(13): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_output_delay -clock clock_crystal -max 36ps \[get_ports \{DAC_OUTPUT\[*\]\}\] " "set_output_delay -clock clock_crystal -max 36ps \[get_ports \{DAC_OUTPUT\[*\]\}\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603879247 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879247 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_output_delay SDC.sdc 14 Argument -clock is not an object ID " "Ignored set_output_delay at SDC.sdc(14): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_output_delay -clock clock_crystal -min 0ps \[get_ports \{DAC_OUTPUT\[*\]\}\] " "set_output_delay -clock clock_crystal -min 0ps \[get_ports \{DAC_OUTPUT\[*\]\}\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 14 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603879248 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 14 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879248 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 18 clock_adc clock " "Ignored filter at SDC.sdc(18): clock_adc could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879248 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 18 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(18): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_INPUT\[*\]\] " "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_INPUT\[*\]\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603879249 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879249 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 19 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(19): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_INPUT\[*\]\] " "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_INPUT\[*\]\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 19 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603879249 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 19 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879249 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 20 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(20): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_OTR\] " "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_OTR\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 20 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603879249 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 20 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879249 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 21 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(21): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_OTR\] " "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_OTR\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603879250 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879250 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 27 iq_valid clock " "Ignored filter at SDC.sdc(27): iq_valid could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879250 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 27 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(27): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603879251 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879251 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 28 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(28): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 28 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603879251 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 28 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879251 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 29 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(29): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 29 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603879251 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 29 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879251 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 30 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(30): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 30 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603879252 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 30 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879252 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 31 clock_sys clock " "Ignored filter at SDC.sdc(31): clock_sys could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879252 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 31 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(31): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603879252 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879252 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 32 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(32): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 32 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603879253 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 32 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Power Analyzer" 0 -1 1616603879253 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Node: rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_head\[2\] rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_head\[2\] is being clocked by rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1616603879306 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 1 0 "Power Analyzer" 0 -1 1616603879306 "|WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Power Analyzer" 0 -1 1616603879435 ""} -{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1616603879731 ""} -{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1616603880187 ""} -{ "Info" "IPUTIL_EXTERNAL_PUTIL_SAF_WRITTEN" "output_files/signal_activity.saf " "Created Signal Activity File output_files/signal_activity.saf" { } { } 0 221012 "Created Signal Activity File %1!s!" 0 0 "Power Analyzer" 0 -1 1616603880535 ""} -{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" { } { } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "Power Analyzer" 0 -1 1616603880721 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Power Analyzer" 0 -1 1616603880930 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Power Analyzer" 0 -1 1616603882807 ""} -{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "9.826 millions of transitions / sec " "Average toggle rate for this design is 9.826 millions of transitions / sec" { } { } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "Power Analyzer" 0 -1 1616603888898 ""} -{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "301.03 mW " "Total thermal power estimate for the design is 301.03 mW" { } { { "c:/intelfpga/18.1/quartus/bin64/Report_Window_01.qrpt" "" { Report "c:/intelfpga/18.1/quartus/bin64/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } } } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "Power Analyzer" 0 -1 1616603889942 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/FPGA/output_files/WOLF-LITE.pow.smsg " "Generated suppressed messages file C:/FPGA/output_files/WOLF-LITE.pow.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Power Analyzer" 0 -1 1616603890082 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Power Analyzer 0 s 20 s Quartus Prime " "Quartus Prime Power Analyzer was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4929 " "Peak virtual memory: 4929 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1616603890935 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 24 19:38:10 2021 " "Processing ended: Wed Mar 24 19:38:10 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1616603890935 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1616603890935 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1616603890935 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Power Analyzer" 0 -1 1616603890935 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Power Analyzer" 0 -1 1616603894387 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1616603894407 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 24 19:38:12 2021 " "Processing started: Wed Mar 24 19:38:12 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1616603894407 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1616603894407 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta WOLF-LITE -c WOLF-LITE " "Command: quartus_sta WOLF-LITE -c WOLF-LITE" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1616603894407 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1616603894696 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1616603897243 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603897312 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603897313 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1616603898363 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1616603898363 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1616603898363 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Timing Analyzer" 0 -1 1616603898363 ""} -{ "Info" "ISTA_SDC_FOUND" "SDC.sdc " "Reading SDC File: 'SDC.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1616603898482 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 5 rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid port or pin or register or keeper or net or combinational node or node " "Ignored filter at SDC.sdc(5): rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid could not be matched with a port or pin or register or keeper or net or combinational node or node" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898485 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock SDC.sdc 5 Argument is not an object ID " "Ignored create_clock at SDC.sdc(5): Argument is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name \"iq_valid\" -period 48KHz \{rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid\} " "create_clock -name \"iq_valid\" -period 48KHz \{rx_ciccomp:RX1_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid\}" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603898486 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 5 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898486 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 7 clock_sys clock " "Ignored filter at SDC.sdc(7): clock_sys could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 7 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898487 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 7 iq_valid clock " "Ignored filter at SDC.sdc(7): iq_valid could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 7 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898487 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Timing Analyzer" 0 -1 1616603898487 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 335 -multiply_by 64 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 335 -multiply_by 64 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1616603898490 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 1340 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 1340 -duty_cycle 50.00 -name \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{MAIN_PLL\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1616603898490 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{TX_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{TX_PLL\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1616603898490 ""} } { } 0 332110 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1616603898490 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 13 clock_crystal clock " "Ignored filter at SDC.sdc(13): clock_crystal could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898491 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_output_delay SDC.sdc 13 Argument -clock is not an object ID " "Ignored set_output_delay at SDC.sdc(13): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_output_delay -clock clock_crystal -max 36ps \[get_ports \{DAC_OUTPUT\[*\]\}\] " "set_output_delay -clock clock_crystal -max 36ps \[get_ports \{DAC_OUTPUT\[*\]\}\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603898491 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 13 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898491 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_output_delay SDC.sdc 14 Argument -clock is not an object ID " "Ignored set_output_delay at SDC.sdc(14): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_output_delay -clock clock_crystal -min 0ps \[get_ports \{DAC_OUTPUT\[*\]\}\] " "set_output_delay -clock clock_crystal -min 0ps \[get_ports \{DAC_OUTPUT\[*\]\}\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 14 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603898492 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 14 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898492 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 18 clock_adc clock " "Ignored filter at SDC.sdc(18): clock_adc could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898492 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 18 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(18): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_INPUT\[*\]\] " "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_INPUT\[*\]\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603898492 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 18 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898492 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 19 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(19): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_INPUT\[*\]\] " "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_INPUT\[*\]\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 19 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603898493 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 19 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898493 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 20 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(20): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_OTR\] " "set_input_delay -clock clock_adc -max 36ps \[get_ports ADC_OTR\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 20 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603898493 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 20 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898493 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_input_delay SDC.sdc 21 Argument -clock is not an object ID " "Ignored set_input_delay at SDC.sdc(21): Argument -clock is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_OTR\] " "set_input_delay -clock clock_adc -min 0ps \[get_ports ADC_OTR\]" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 21 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603898493 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 21 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898493 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 27 iq_valid clock " "Ignored filter at SDC.sdc(27): iq_valid could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898494 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 27 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(27): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603898494 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 27 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898494 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 28 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(28): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{iq_valid\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 28 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603898495 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 28 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898495 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 29 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(29): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 29 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603898495 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 29 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898495 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 30 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(30): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{iq_valid\}\] -to \[get_clocks \{clock_stm32\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 30 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603898495 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 30 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898495 ""} -{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "SDC.sdc 31 clock_sys clock " "Ignored filter at SDC.sdc(31): clock_sys could not be matched with a clock" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898496 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 31 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(31): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -setup -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -setup -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603898496 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 31 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898496 ""} -{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_multicycle_path SDC.sdc 32 Argument is an empty collection " "Ignored set_multicycle_path at SDC.sdc(32): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -hold -end 2 " "set_multicycle_path -from \[get_clocks \{clock_stm32\}\] -to \[get_clocks \{clock_sys\}\] -hold -end 2" { } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 32 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1616603898497 ""} } { { "C:/FPGA/SDC.sdc" "" { Text "C:/FPGA/SDC.sdc" 32 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1616603898497 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Node: rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_head\[2\] rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_head\[2\] is being clocked by rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1616603898561 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 1 0 "Timing Analyzer" 0 -1 1616603898561 "|WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1616603898652 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = OFF" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = OFF" 0 0 "Timing Analyzer" 0 0 1616603898658 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1616603898762 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1616603899272 ""} } { } 1 332148 "Timing requirements not met" 1 0 "Timing Analyzer" 0 -1 1616603899272 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.426 " "Worst-case setup slack is -4.426" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.426 -419.911 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -4.426 -419.911 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.734 0.000 clk_sys " " 1.734 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 30.279 0.000 clock_stm32 " " 30.279 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 44.707 0.000 altera_reserved_tck " " 44.707 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899285 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603899285 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.322 " "Worst-case hold slack is 0.322" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899369 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899369 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.322 0.000 clk_sys " " 0.322 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899369 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.406 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.406 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899369 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.452 0.000 altera_reserved_tck " " 0.452 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899369 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.485 0.000 clock_stm32 " " 0.485 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899369 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603899369 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 3.480 " "Worst-case recovery slack is 3.480" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.480 0.000 clk_sys " " 3.480 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 93.581 0.000 altera_reserved_tck " " 93.581 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899397 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603899397 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.135 " "Worst-case removal slack is 1.135" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899421 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899421 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.135 0.000 altera_reserved_tck " " 1.135 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899421 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 11.201 0.000 clk_sys " " 11.201 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899421 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603899421 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.218 " "Worst-case minimum pulse width slack is 1.218" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899437 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899437 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.218 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.218 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899437 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.227 0.000 clk_sys " " 7.227 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899437 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.693 0.000 clock_stm32 " " 19.693 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899437 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.521 0.000 altera_reserved_tck " " 49.521 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603899437 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603899437 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 33 synchronizer chains. " "Report Metastability: Found 33 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603899994 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 33 " "Number of Synchronizer Chains Found: 33" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603899994 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 3 Registers " "Shortest Synchronizer Chain: 3 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603899994 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603899994 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 13.386 ns " "Worst Case Available Settling Time: 13.386 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603899994 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603899994 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1616603899994 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1616603900008 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1616603900071 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1616603902164 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Node: rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_head\[2\] rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_head\[2\] is being clocked by rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1616603902821 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 1 0 "Timing Analyzer" 0 -1 1616603902821 "|WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1616603902859 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1616603903073 ""} } { } 1 332148 "Timing requirements not met" 1 0 "Timing Analyzer" 0 -1 1616603903073 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.444 " "Worst-case setup slack is -3.444" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903084 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903084 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.444 -182.304 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -3.444 -182.304 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903084 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.039 0.000 clk_sys " " 2.039 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903084 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 30.926 0.000 clock_stm32 " " 30.926 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903084 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 45.217 0.000 altera_reserved_tck " " 45.217 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903084 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603903084 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.312 " "Worst-case hold slack is 0.312" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903163 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903163 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.312 0.000 clk_sys " " 0.312 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903163 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.390 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.390 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903163 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.400 0.000 altera_reserved_tck " " 0.400 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903163 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.430 0.000 clock_stm32 " " 0.430 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903163 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603903163 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 3.798 " "Worst-case recovery slack is 3.798" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903185 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903185 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.798 0.000 clk_sys " " 3.798 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903185 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 93.981 0.000 altera_reserved_tck " " 93.981 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903185 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603903185 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.035 " "Worst-case removal slack is 1.035" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903206 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903206 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.035 0.000 altera_reserved_tck " " 1.035 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903206 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 10.850 0.000 clk_sys " " 10.850 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903206 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603903206 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.218 " "Worst-case minimum pulse width slack is 1.218" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.218 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.218 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.257 0.000 clk_sys " " 7.257 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.583 0.000 clock_stm32 " " 19.583 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.397 0.000 altera_reserved_tck " " 49.397 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603903225 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603903225 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 33 synchronizer chains. " "Report Metastability: Found 33 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603903782 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 33 " "Number of Synchronizer Chains Found: 33" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603903782 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 3 Registers " "Shortest Synchronizer Chain: 3 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603903782 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603903782 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 13.754 ns " "Worst Case Available Settling Time: 13.754 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603903782 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603903782 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1616603903782 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1616603903800 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Node: rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_head\[2\] rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid " "Register stm32_interface:STM32_INTERFACE\|BUFFER_RX_head\[2\] is being clocked by rx_ciccomp:RX_CICOMP_Q\|rx_ciccomp_0002:rx_ciccomp_inst\|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst\|auk_dspip_avalon_streaming_source_hpfir:source\|data_valid" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1616603904303 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 1 0 "Timing Analyzer" 0 -1 1616603904303 "|WOLF-LITE|rx_ciccomp:RX_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid"} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1616603904335 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.433 " "Worst-case setup slack is 1.433" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.433 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.433 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.415 0.000 clk_sys " " 4.415 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.976 0.000 clock_stm32 " " 34.976 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.929 0.000 altera_reserved_tck " " 47.929 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904425 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603904425 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.098 " "Worst-case hold slack is 0.098" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904511 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904511 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.098 0.000 clk_sys " " 0.098 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904511 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.140 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.140 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904511 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 altera_reserved_tck " " 0.186 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904511 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.201 0.000 clock_stm32 " " 0.201 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904511 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603904511 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 5.276 " "Worst-case recovery slack is 5.276" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904538 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904538 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.276 0.000 clk_sys " " 5.276 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904538 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.081 0.000 altera_reserved_tck " " 97.081 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904538 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603904538 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.495 " "Worst-case removal slack is 0.495" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904564 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904564 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.495 0.000 altera_reserved_tck " " 0.495 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904564 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.802 0.000 clk_sys " " 9.802 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904564 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603904564 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 2.841 " "Worst-case minimum pulse width slack is 2.841" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904586 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904586 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.841 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.841 0.000 TX_PLL\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904586 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.972 0.000 clk_sys " " 6.972 0.000 clk_sys " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904586 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.169 0.000 clock_stm32 " " 19.169 0.000 clock_stm32 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904586 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.468 0.000 altera_reserved_tck " " 49.468 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1616603904586 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1616603904586 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 33 synchronizer chains. " "Report Metastability: Found 33 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603905191 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 33 " "Number of Synchronizer Chains Found: 33" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603905191 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 3 Registers " "Shortest Synchronizer Chain: 3 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603905191 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603905191 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 16.346 ns " "Worst Case Available Settling Time: 16.346 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603905191 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1616603905191 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1616603905191 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1616603905765 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1616603905767 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/FPGA/output_files/WOLF-LITE.sta.smsg " "Generated suppressed messages file C:/FPGA/output_files/WOLF-LITE.sta.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Timing Analyzer" 0 -1 1616603905908 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 20 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4950 " "Peak virtual memory: 4950 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1616603906189 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 24 19:38:26 2021 " "Processing ended: Wed Mar 24 19:38:26 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1616603906189 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1616603906189 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1616603906189 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1616603906189 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1616603908269 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Shell Quartus Prime " "Running Quartus Prime Shell" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1616603908288 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 24 19:38:27 2021 " "Processing started: Wed Mar 24 19:38:27 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1616603908288 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Shell" 0 -1 1616603908288 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sh -t auto_convert.tcl compile WOLF-LITE WOLF-LITE " "Command: quartus_sh -t auto_convert.tcl compile WOLF-LITE WOLF-LITE" { } { } 0 0 "Command: %1!s!" 0 0 "Shell" 0 -1 1616603908288 ""} -{ "Info" "IQEXE_START_BANNER_TCL_ARGS" "compile WOLF-LITE WOLF-LITE " "Quartus(args): compile WOLF-LITE WOLF-LITE" { } { } 0 0 "Quartus(args): %1!s!" 0 0 "Shell" 0 -1 1616603908288 ""} -{ "Info" "IQEXE_TCL_SCRIPT_STATUS" "auto_convert.tcl " "Evaluation of Tcl script auto_convert.tcl was successful" { } { } 0 23030 "Evaluation of Tcl script %1!s! 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was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Shell" 0 -1 1616603911365 ""} diff --git a/FPGA_61.440/db/scfifo_ai71.tdf b/FPGA_61.440/db/scfifo_ai71.tdf deleted file mode 100644 index 0ceb37c..0000000 --- a/FPGA_61.440/db/scfifo_ai71.tdf +++ /dev/null @@ -1,75 +0,0 @@ ---scfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" ALMOST_EMPTY_VALUE=0 ALMOST_FULL_VALUE=13 DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=21 LPM_SHOWAHEAD="OFF" LPM_WIDTH=33 LPM_WIDTHU=5 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" almost_full clock data empty q rdreq sclr wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ---VERSION_BEGIN 18.1 cbx_altdpram 2018:09:12:13:04:24:SJ cbx_altera_counter 2018:09:12:13:04:24:SJ cbx_altera_syncram 2018:09:12:13:04:24:SJ cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_fifo_common 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_scfifo 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION a_dpfifo_7qv (clock, data[32..0], rreq, sclr, wreq) -RETURNS ( empty, q[32..0], usedw[4..0]); - ---synthesis_resources = M9K 1 reg 12 -SUBDESIGN scfifo_ai71 -( - almost_full : output; - clock : input; - data[32..0] : input; - empty : output; - q[32..0] : output; - rdreq : input; - sclr : input; - wrreq : input; -) -VARIABLE - dpfifo : a_dpfifo_7qv; - dffe_af : dffe; - comparison_af0 : WIRE; - comparison_af1 : WIRE; - comparison_af2 : WIRE; - comparison_af3 : WIRE; - comparison_af4 : WIRE; - comparison_pre_af0 : WIRE; - comparison_pre_af1 : WIRE; - comparison_pre_af2 : WIRE; - comparison_pre_af3 : WIRE; - comparison_pre_af4 : WIRE; - wire_af[4..0] : WIRE; - wire_pre_af[4..0] : WIRE; - -BEGIN - dpfifo.clock = clock; - dpfifo.data[] = data[]; - dpfifo.rreq = rdreq; - dpfifo.sclr = sclr; - dpfifo.wreq = wrreq; - dffe_af.clk = clock; - dffe_af.d = ((dffe_af.q & (dffe_af.q $ (sclr # ((comparison_af4 & (! wrreq)) & rdreq)))) # ((! dffe_af.q) & ((((! sclr) & comparison_pre_af4) & wrreq) & (! rdreq)))); - almost_full = dffe_af.q; - comparison_af0 = (dpfifo.usedw[0..0] $ wire_af[0..0]); - comparison_af1 = ((dpfifo.usedw[1..1] $ wire_af[1..1]) & comparison_af0); - comparison_af2 = ((dpfifo.usedw[2..2] $ wire_af[2..2]) & comparison_af1); - comparison_af3 = ((dpfifo.usedw[3..3] $ wire_af[3..3]) & comparison_af2); - comparison_af4 = ((dpfifo.usedw[4..4] $ wire_af[4..4]) & comparison_af3); - comparison_pre_af0 = (dpfifo.usedw[0..0] $ wire_pre_af[0..0]); - comparison_pre_af1 = ((dpfifo.usedw[1..1] $ wire_pre_af[1..1]) & comparison_pre_af0); - comparison_pre_af2 = ((dpfifo.usedw[2..2] $ wire_pre_af[2..2]) & comparison_pre_af1); - comparison_pre_af3 = ((dpfifo.usedw[3..3] $ wire_pre_af[3..3]) & comparison_pre_af2); - comparison_pre_af4 = ((dpfifo.usedw[4..4] $ wire_pre_af[4..4]) & comparison_pre_af3); - empty = dpfifo.empty; - q[] = dpfifo.q[]; - wire_af[] = ( B"1", B"0", B"0", B"1", B"0"); - wire_pre_af[] = ( B"1", B"0", B"0", B"1", B"1"); -END; ---VALID FILE diff --git a/FPGA_61.440/db/scfifo_ci71.tdf b/FPGA_61.440/db/scfifo_ci71.tdf deleted file mode 100644 index 389e14a..0000000 --- a/FPGA_61.440/db/scfifo_ci71.tdf +++ /dev/null @@ -1,75 +0,0 @@ ---scfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" ALMOST_EMPTY_VALUE=0 ALMOST_FULL_VALUE=13 DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=21 LPM_SHOWAHEAD="OFF" LPM_WIDTH=17 LPM_WIDTHU=5 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" almost_full clock data empty q rdreq sclr wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ---VERSION_BEGIN 18.1 cbx_altdpram 2018:09:12:13:04:24:SJ cbx_altera_counter 2018:09:12:13:04:24:SJ cbx_altera_syncram 2018:09:12:13:04:24:SJ cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_fifo_common 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_scfifo 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION a_dpfifo_9qv (clock, data[16..0], rreq, sclr, wreq) -RETURNS ( empty, q[16..0], usedw[4..0]); - ---synthesis_resources = lut 14 M9K 1 reg 26 -SUBDESIGN scfifo_ci71 -( - almost_full : output; - clock : input; - data[16..0] : input; - empty : output; - q[16..0] : output; - rdreq : input; - sclr : input; - wrreq : input; -) -VARIABLE - dpfifo : a_dpfifo_9qv; - dffe_af : dffe; - comparison_af0 : WIRE; - comparison_af1 : WIRE; - comparison_af2 : WIRE; - comparison_af3 : WIRE; - comparison_af4 : WIRE; - comparison_pre_af0 : WIRE; - comparison_pre_af1 : WIRE; - comparison_pre_af2 : WIRE; - comparison_pre_af3 : WIRE; - comparison_pre_af4 : WIRE; - wire_af[4..0] : WIRE; - wire_pre_af[4..0] : WIRE; - -BEGIN - dpfifo.clock = clock; - dpfifo.data[] = data[]; - dpfifo.rreq = rdreq; - dpfifo.sclr = sclr; - dpfifo.wreq = wrreq; - dffe_af.clk = clock; - dffe_af.d = ((dffe_af.q & (dffe_af.q $ (sclr # ((comparison_af4 & (! wrreq)) & rdreq)))) # ((! dffe_af.q) & ((((! sclr) & comparison_pre_af4) & wrreq) & (! rdreq)))); - almost_full = dffe_af.q; - comparison_af0 = (dpfifo.usedw[0..0] $ wire_af[0..0]); - comparison_af1 = ((dpfifo.usedw[1..1] $ wire_af[1..1]) & comparison_af0); - comparison_af2 = ((dpfifo.usedw[2..2] $ wire_af[2..2]) & comparison_af1); - comparison_af3 = ((dpfifo.usedw[3..3] $ wire_af[3..3]) & comparison_af2); - comparison_af4 = ((dpfifo.usedw[4..4] $ wire_af[4..4]) & comparison_af3); - comparison_pre_af0 = (dpfifo.usedw[0..0] $ wire_pre_af[0..0]); - comparison_pre_af1 = ((dpfifo.usedw[1..1] $ wire_pre_af[1..1]) & comparison_pre_af0); - comparison_pre_af2 = ((dpfifo.usedw[2..2] $ wire_pre_af[2..2]) & comparison_pre_af1); - comparison_pre_af3 = ((dpfifo.usedw[3..3] $ wire_pre_af[3..3]) & comparison_pre_af2); - comparison_pre_af4 = ((dpfifo.usedw[4..4] $ wire_pre_af[4..4]) & comparison_pre_af3); - empty = dpfifo.empty; - q[] = dpfifo.q[]; - wire_af[] = ( B"1", B"0", B"0", B"1", B"0"); - wire_pre_af[] = ( B"1", B"0", B"0", B"1", B"1"); -END; ---VALID FILE diff --git a/FPGA_61.440/db/scfifo_ef71.tdf b/FPGA_61.440/db/scfifo_ef71.tdf deleted file mode 100644 index 56db6c5..0000000 --- a/FPGA_61.440/db/scfifo_ef71.tdf +++ /dev/null @@ -1,67 +0,0 @@ ---scfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" ALMOST_EMPTY_VALUE=4 ALMOST_FULL_VALUE=0 DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=8 LPM_SHOWAHEAD="OFF" LPM_WIDTH=25 LPM_WIDTHU=3 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" almost_empty clock data full q rdreq sclr wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ---VERSION_BEGIN 18.1 cbx_altdpram 2018:09:12:13:04:24:SJ cbx_altera_counter 2018:09:12:13:04:24:SJ cbx_altera_syncram 2018:09:12:13:04:24:SJ cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_fifo_common 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_scfifo 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION a_dpfifo_vkv (clock, data[24..0], rreq, sclr, wreq) -RETURNS ( full, q[24..0], usedw[2..0]); - ---synthesis_resources = M9K 1 reg 10 -SUBDESIGN scfifo_ef71 -( - almost_empty : output; - clock : input; - data[24..0] : input; - full : output; - q[24..0] : output; - rdreq : input; - sclr : input; - wrreq : input; -) -VARIABLE - dpfifo : a_dpfifo_vkv; - dffe_nae : dffe; - comparison_ae0 : WIRE; - comparison_ae1 : WIRE; - comparison_ae2 : WIRE; - comparison_pre_ae0 : WIRE; - comparison_pre_ae1 : WIRE; - comparison_pre_ae2 : WIRE; - wire_ae[2..0] : WIRE; - wire_pre_ae[2..0] : WIRE; - -BEGIN - dpfifo.clock = clock; - dpfifo.data[] = data[]; - dpfifo.rreq = rdreq; - dpfifo.sclr = sclr; - dpfifo.wreq = wrreq; - dffe_nae.clk = clock; - dffe_nae.d = ((dffe_nae.q & (dffe_nae.q $ (sclr # ((comparison_ae2 & (! wrreq)) & rdreq)))) # ((! dffe_nae.q) & ((((! sclr) & comparison_pre_ae2) & wrreq) & (! rdreq)))); - almost_empty = (! dffe_nae.q); - comparison_ae0 = (dpfifo.usedw[0..0] $ wire_ae[0..0]); - comparison_ae1 = ((dpfifo.usedw[1..1] $ wire_ae[1..1]) & comparison_ae0); - comparison_ae2 = ((dpfifo.usedw[2..2] $ wire_ae[2..2]) & comparison_ae1); - comparison_pre_ae0 = (dpfifo.usedw[0..0] $ wire_pre_ae[0..0]); - comparison_pre_ae1 = ((dpfifo.usedw[1..1] $ wire_pre_ae[1..1]) & comparison_pre_ae0); - comparison_pre_ae2 = ((dpfifo.usedw[2..2] $ wire_pre_ae[2..2]) & comparison_pre_ae1); - full = dpfifo.full; - q[] = dpfifo.q[]; - wire_ae[] = ( B"0", B"1", B"1"); - wire_pre_ae[] = ( B"1", B"0", B"0"); -END; ---VALID FILE diff --git a/FPGA_61.440/db/scfifo_gf71.tdf b/FPGA_61.440/db/scfifo_gf71.tdf deleted file mode 100644 index 6a926c1..0000000 --- a/FPGA_61.440/db/scfifo_gf71.tdf +++ /dev/null @@ -1,67 +0,0 @@ ---scfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" ALMOST_EMPTY_VALUE=4 ALMOST_FULL_VALUE=0 DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=8 LPM_SHOWAHEAD="OFF" LPM_WIDTH=18 LPM_WIDTHU=3 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" almost_empty clock data full q rdreq sclr wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ---VERSION_BEGIN 18.1 cbx_altdpram 2018:09:12:13:04:24:SJ cbx_altera_counter 2018:09:12:13:04:24:SJ cbx_altera_syncram 2018:09:12:13:04:24:SJ cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_fifo_common 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_scfifo 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION a_dpfifo_1lv (clock, data[17..0], rreq, sclr, wreq) -RETURNS ( full, q[17..0], usedw[2..0]); - ---synthesis_resources = lut 8 M9K 1 reg 18 -SUBDESIGN scfifo_gf71 -( - almost_empty : output; - clock : input; - data[17..0] : input; - full : output; - q[17..0] : output; - rdreq : input; - sclr : input; - wrreq : input; -) -VARIABLE - dpfifo : a_dpfifo_1lv; - dffe_nae : dffe; - comparison_ae0 : WIRE; - comparison_ae1 : WIRE; - comparison_ae2 : WIRE; - comparison_pre_ae0 : WIRE; - comparison_pre_ae1 : WIRE; - comparison_pre_ae2 : WIRE; - wire_ae[2..0] : WIRE; - wire_pre_ae[2..0] : WIRE; - -BEGIN - dpfifo.clock = clock; - dpfifo.data[] = data[]; - dpfifo.rreq = rdreq; - dpfifo.sclr = sclr; - dpfifo.wreq = wrreq; - dffe_nae.clk = clock; - dffe_nae.d = ((dffe_nae.q & (dffe_nae.q $ (sclr # ((comparison_ae2 & (! wrreq)) & rdreq)))) # ((! dffe_nae.q) & ((((! sclr) & comparison_pre_ae2) & wrreq) & (! rdreq)))); - almost_empty = (! dffe_nae.q); - comparison_ae0 = (dpfifo.usedw[0..0] $ wire_ae[0..0]); - comparison_ae1 = ((dpfifo.usedw[1..1] $ wire_ae[1..1]) & comparison_ae0); - comparison_ae2 = ((dpfifo.usedw[2..2] $ wire_ae[2..2]) & comparison_ae1); - comparison_pre_ae0 = (dpfifo.usedw[0..0] $ wire_pre_ae[0..0]); - comparison_pre_ae1 = ((dpfifo.usedw[1..1] $ wire_pre_ae[1..1]) & comparison_pre_ae0); - comparison_pre_ae2 = ((dpfifo.usedw[2..2] $ wire_pre_ae[2..2]) & comparison_pre_ae1); - full = dpfifo.full; - q[] = dpfifo.q[]; - wire_ae[] = ( B"0", B"1", B"1"); - wire_pre_ae[] = ( B"1", B"0", B"0"); -END; ---VALID FILE diff --git a/FPGA_61.440/db/scfifo_pm51.tdf b/FPGA_61.440/db/scfifo_pm51.tdf deleted file mode 100644 index 77fcf38..0000000 --- a/FPGA_61.440/db/scfifo_pm51.tdf +++ /dev/null @@ -1,44 +0,0 @@ ---scfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" ALMOST_EMPTY_VALUE=0 ALMOST_FULL_VALUE=0 DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=3 LPM_SHOWAHEAD="OFF" LPM_WIDTH=85 LPM_WIDTHU=2 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" clock data q rdreq sclr wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ---VERSION_BEGIN 18.1 cbx_altdpram 2018:09:12:13:04:24:SJ cbx_altera_counter 2018:09:12:13:04:24:SJ cbx_altera_syncram 2018:09:12:13:04:24:SJ cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_fifo_common 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_scfifo 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION a_dpfifo_4ku (clock, data[84..0], rreq, sclr, wreq) -RETURNS ( q[84..0]); - ---synthesis_resources = M9K 3 reg 8 -SUBDESIGN scfifo_pm51 -( - clock : input; - data[84..0] : input; - q[84..0] : output; - rdreq : input; - sclr : input; - wrreq : input; -) -VARIABLE - dpfifo : a_dpfifo_4ku; - -BEGIN - dpfifo.clock = clock; - dpfifo.data[] = data[]; - dpfifo.rreq = rdreq; - dpfifo.sclr = sclr; - dpfifo.wreq = wrreq; - q[] = dpfifo.q[]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/scfifo_qm51.tdf b/FPGA_61.440/db/scfifo_qm51.tdf deleted file mode 100644 index fece717..0000000 --- a/FPGA_61.440/db/scfifo_qm51.tdf +++ /dev/null @@ -1,44 +0,0 @@ ---scfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" ALMOST_EMPTY_VALUE=0 ALMOST_FULL_VALUE=0 DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=3 LPM_SHOWAHEAD="OFF" LPM_WIDTH=86 LPM_WIDTHU=2 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" clock data q rdreq sclr wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ---VERSION_BEGIN 18.1 cbx_altdpram 2018:09:12:13:04:24:SJ cbx_altera_counter 2018:09:12:13:04:24:SJ cbx_altera_syncram 2018:09:12:13:04:24:SJ cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_fifo_common 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_scfifo 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END - - --- Copyright (C) 2018 Intel Corporation. All rights reserved. --- Your use of Intel Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Intel Program License --- Subscription Agreement, the Intel Quartus Prime License Agreement, --- the Intel FPGA IP License Agreement, or other applicable license --- agreement, including, without limitation, that your use is for --- the sole purpose of programming logic devices manufactured by --- Intel and sold by Intel or its authorized distributors. Please --- refer to the applicable agreement for further details. - - -FUNCTION a_dpfifo_5ku (clock, data[85..0], rreq, sclr, wreq) -RETURNS ( q[85..0]); - ---synthesis_resources = lut 3 M9K 3 reg 11 -SUBDESIGN scfifo_qm51 -( - clock : input; - data[85..0] : input; - q[85..0] : output; - rdreq : input; - sclr : input; - wrreq : input; -) -VARIABLE - dpfifo : a_dpfifo_5ku; - -BEGIN - dpfifo.clock = clock; - dpfifo.data[] = data[]; - dpfifo.rreq = rdreq; - dpfifo.sclr = sclr; - dpfifo.wreq = wrreq; - q[] = dpfifo.q[]; -END; ---VALID FILE diff --git a/FPGA_61.440/db/tx_pll_altpll.v b/FPGA_61.440/db/tx_pll_altpll.v deleted file mode 100644 index 007270e..0000000 --- a/FPGA_61.440/db/tx_pll_altpll.v +++ /dev/null @@ -1,92 +0,0 @@ -//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=2 clk0_duty_cycle=50 clk0_multiply_by=5 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=16276 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=tx_pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 -//VERSION_BEGIN 18.1 cbx_altclkbuf 2018:09:12:13:04:24:SJ cbx_altiobuf_bidir 2018:09:12:13:04:24:SJ cbx_altiobuf_in 2018:09:12:13:04:24:SJ cbx_altiobuf_out 2018:09:12:13:04:24:SJ cbx_altpll 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END -//CBXI_INSTANCE_NAME="WOLF_LITE_tx_pll_TX_PLL_altpll_altpll_component" -// synthesis VERILOG_INPUT_VERSION VERILOG_2001 -// altera message_off 10463 - - - -// Copyright (C) 2018 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License -// Subscription Agreement, the Intel Quartus Prime License Agreement, -// the Intel FPGA IP License Agreement, or other applicable license -// agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by -// Intel and sold by Intel or its authorized distributors. Please -// refer to the applicable agreement for further details. - - - -//synthesis_resources = cycloneive_pll 1 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module tx_pll_altpll - ( - clk, - inclk) /* synthesis synthesis_clearbox=1 */; - output [4:0] clk; - input [1:0] inclk; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri0 [1:0] inclk; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [4:0] wire_pll1_clk; - wire wire_pll1_fbout; - - cycloneive_pll pll1 - ( - .activeclock(), - .clk(wire_pll1_clk), - .clkbad(), - .fbin(wire_pll1_fbout), - .fbout(wire_pll1_fbout), - .inclk(inclk), - .locked(), - .phasedone(), - .scandataout(), - .scandone(), - .vcooverrange(), - .vcounderrange() - `ifndef FORMAL_VERIFICATION - // synopsys translate_off - `endif - , - .areset(1'b0), - .clkswitch(1'b0), - .configupdate(1'b0), - .pfdena(1'b1), - .phasecounterselect({3{1'b0}}), - .phasestep(1'b0), - .phaseupdown(1'b0), - .scanclk(1'b0), - .scanclkena(1'b1), - .scandata(1'b0) - `ifndef FORMAL_VERIFICATION - // synopsys translate_on - `endif - ); - defparam - pll1.bandwidth_type = "auto", - pll1.clk0_divide_by = 2, - pll1.clk0_duty_cycle = 50, - pll1.clk0_multiply_by = 5, - pll1.clk0_phase_shift = "0", - pll1.compensate_clock = "clk0", - pll1.inclk0_input_frequency = 16276, - pll1.operation_mode = "normal", - pll1.pll_type = "auto", - pll1.lpm_type = "cycloneive_pll"; - assign - clk = {wire_pll1_clk[4:0]}; -endmodule //tx_pll_altpll -//VALID FILE diff --git a/FPGA_61.440/greybox_tmp/cbx_args.txt b/FPGA_61.440/greybox_tmp/cbx_args.txt deleted file mode 100644 index cc77e1e..0000000 --- a/FPGA_61.440/greybox_tmp/cbx_args.txt +++ /dev/null @@ -1,63 +0,0 @@ -BANDWIDTH_TYPE=AUTO -CLK0_DIVIDE_BY=5 -CLK0_DUTY_CYCLE=50 -CLK0_MULTIPLY_BY=1 -CLK0_PHASE_SHIFT=0 -CLK1_DIVIDE_BY=1280 -CLK1_DUTY_CYCLE=50 -CLK1_MULTIPLY_BY=1 -CLK1_PHASE_SHIFT=0 -COMPENSATE_CLOCK=CLK0 -INCLK0_INPUT_FREQUENCY=16276 -INTENDED_DEVICE_FAMILY="Cyclone IV E" -LPM_TYPE=altpll -OPERATION_MODE=NORMAL -PLL_TYPE=AUTO -PORT_ACTIVECLOCK=PORT_UNUSED -PORT_ARESET=PORT_UNUSED -PORT_CLKBAD0=PORT_UNUSED -PORT_CLKBAD1=PORT_UNUSED -PORT_CLKLOSS=PORT_UNUSED -PORT_CLKSWITCH=PORT_UNUSED -PORT_CONFIGUPDATE=PORT_UNUSED -PORT_FBIN=PORT_UNUSED -PORT_INCLK0=PORT_USED -PORT_INCLK1=PORT_UNUSED -PORT_LOCKED=PORT_UNUSED -PORT_PFDENA=PORT_UNUSED -PORT_PHASECOUNTERSELECT=PORT_UNUSED -PORT_PHASEDONE=PORT_UNUSED -PORT_PHASESTEP=PORT_UNUSED -PORT_PHASEUPDOWN=PORT_UNUSED -PORT_PLLENA=PORT_UNUSED -PORT_SCANACLR=PORT_UNUSED -PORT_SCANCLK=PORT_UNUSED -PORT_SCANCLKENA=PORT_UNUSED -PORT_SCANDATA=PORT_UNUSED -PORT_SCANDATAOUT=PORT_UNUSED -PORT_SCANDONE=PORT_UNUSED -PORT_SCANREAD=PORT_UNUSED -PORT_SCANWRITE=PORT_UNUSED -PORT_clk0=PORT_USED -PORT_clk1=PORT_USED -PORT_clk2=PORT_UNUSED -PORT_clk3=PORT_UNUSED -PORT_clk4=PORT_UNUSED -PORT_clk5=PORT_UNUSED -PORT_clkena0=PORT_UNUSED -PORT_clkena1=PORT_UNUSED -PORT_clkena2=PORT_UNUSED -PORT_clkena3=PORT_UNUSED -PORT_clkena4=PORT_UNUSED -PORT_clkena5=PORT_UNUSED -PORT_extclk0=PORT_UNUSED -PORT_extclk1=PORT_UNUSED -PORT_extclk2=PORT_UNUSED -PORT_extclk3=PORT_UNUSED -WIDTH_CLOCK=5 -DEVICE_FAMILY="Cyclone IV E" -CBX_AUTO_BLACKBOX=ALL -inclk -inclk -clk -clk diff --git a/FPGA_61.440/incremental_db/README b/FPGA_61.440/incremental_db/README deleted file mode 100644 index 9f62dcd..0000000 --- a/FPGA_61.440/incremental_db/README +++ /dev/null @@ -1,11 +0,0 @@ -This folder contains data for incremental compilation. - -The compiled_partitions sub-folder contains previous compilation results for each partition. -As long as this folder is preserved, incremental compilation results from earlier compiles -can be re-used. To perform a clean compilation from source files for all partitions, both -the db and incremental_db folder should be removed. - -The imported_partitions sub-folder contains the last imported QXP for each imported partition. -As long as this folder is preserved, imported partitions will be automatically re-imported -when the db or incremental_db/compiled_partitions folders are removed. - diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.ammdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.ammdb deleted file mode 100644 index b8342da..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.ammdb and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.cdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.cdb deleted file mode 100644 index 7635784..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.cdb and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.dfp b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.dfp deleted file mode 100644 index b1c67d6..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.dfp and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.hdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.hdb deleted file mode 100644 index 67bd1e3..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.hdb and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.logdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.logdb deleted file mode 100644 index 626799f..0000000 --- a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.rcfdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.rcfdb deleted file mode 100644 index 0516708..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.cmp.rcfdb and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.cdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.cdb deleted file mode 100644 index e961c3b..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.cdb and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.dpi b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.dpi deleted file mode 100644 index c850805..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.dpi and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.hdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.hdb deleted file mode 100644 index 381262e..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.hdb and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.kpt b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.kpt deleted file mode 100644 index 139fca6..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.kpt and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.logdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.logdb deleted file mode 100644 index 626799f..0000000 --- a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.autoh_e40e1.map.logdb +++ /dev/null @@ -1 +0,0 @@ -v1 diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.db_info b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.db_info deleted file mode 100644 index 3c88977..0000000 --- a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition -Version_Index = 486699264 -Creation_Time = Wed Mar 24 19:34:30 2021 diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.ammdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.ammdb deleted file mode 100644 index 986545d..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.ammdb and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.cdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.cdb deleted file mode 100644 index 9bfcab0..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.cdb and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.dfp b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.dfp deleted file mode 100644 index b1c67d6..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.dfp and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.hdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.hdb deleted file mode 100644 index 2e1c45b..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.hdb and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.logdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.logdb deleted file mode 100644 index f672f38..0000000 --- a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.logdb +++ /dev/null @@ -1,3 +0,0 @@ -v1 -PORT_SWAPPING,PORT_SWAP_TYPE_DSPMULT,tx_ciccomp:TX_CICCOMP_Q|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1, -PORT_SWAPPING,PORT_SWAP_TYPE_DSPMULT,tx_ciccomp:TX_CICCOMP_I|tx_ciccomp_0002:tx_ciccomp_inst|tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst|tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core|lpm_mult:u0_m0_wo0_mtree_mult1_0_component|mult_ncu:auto_generated|mac_mult1, diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.rcfdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.rcfdb deleted file mode 100644 index 2301434..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.cmp.rcfdb and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.cdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.cdb deleted file mode 100644 index 92d5cf8..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.cdb and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.dpi b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.dpi deleted file mode 100644 index 467755e..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.dpi and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hbdb.cdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hbdb.cdb deleted file mode 100644 index 16784f9..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hbdb.cdb and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hbdb.hb_info b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hbdb.hb_info deleted file mode 100644 index f20007c..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hbdb.hb_info and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hbdb.hdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hbdb.hdb deleted file mode 100644 index 185a064..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hbdb.hdb and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hbdb.sig b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hbdb.sig deleted file mode 100644 index f5fb2e2..0000000 --- a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hbdb.sig +++ /dev/null @@ -1 +0,0 @@ -142a525f215c95aaad0edf8ba7ed1d0f \ No newline at end of file diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hdb deleted file mode 100644 index f6fa97c..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.hdb and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.kpt b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.kpt deleted file mode 100644 index 971f03c..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.root_partition.map.kpt and /dev/null differ diff --git a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.rrp.hdb b/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.rrp.hdb deleted file mode 100644 index f288408..0000000 Binary files a/FPGA_61.440/incremental_db/compiled_partitions/WOLF-LITE.rrp.hdb and /dev/null differ diff --git a/FPGA_61.440/nco.sopcinfo b/FPGA_61.440/nco.sopcinfo index 69f4300..aa3e059 100644 --- a/FPGA_61.440/nco.sopcinfo +++ b/FPGA_61.440/nco.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1617214577 + 1644138389 false true false diff --git a/FPGA_61.440/output_files/WOLF-LITE.done b/FPGA_61.440/output_files/WOLF-LITE.done deleted file mode 100644 index 54f3a7b..0000000 --- a/FPGA_61.440/output_files/WOLF-LITE.done +++ /dev/null @@ -1 +0,0 @@ -Sat Oct 16 15:12:32 2021 diff --git a/FPGA_61.440/output_files/WOLF-LITE.jdi b/FPGA_61.440/output_files/WOLF-LITE.jdi deleted file mode 100644 index 093872a..0000000 --- a/FPGA_61.440/output_files/WOLF-LITE.jdi +++ /dev/null @@ -1,123 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FPGA_61.440/output_files/WOLF-LITE.pin b/FPGA_61.440/output_files/WOLF-LITE.pin deleted file mode 100644 index 6f2c893..0000000 --- a/FPGA_61.440/output_files/WOLF-LITE.pin +++ /dev/null @@ -1,215 +0,0 @@ - -- Copyright (C) 2018 Intel Corporation. All rights reserved. - -- Your use of Intel Corporation's design tools, logic functions - -- and other software and tools, and its AMPP partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Intel Program License - -- Subscription Agreement, the Intel Quartus Prime License Agreement, - -- the Intel FPGA IP License Agreement, or other applicable license - -- agreement, including, without limitation, that your use is for - -- the sole purpose of programming logic devices manufactured by - -- Intel and sold by Intel or its authorized distributors. Please - -- refer to the applicable agreement for further details. - -- - -- This is a Quartus Prime output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus Prime input file. This file cannot be used - -- to make Quartus Prime pin assignments - for instructions on how to make pin - -- assignments, please see Quartus Prime help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- Bank 1: 2.5V - -- Bank 2: 3.3V - -- Bank 3: 3.3V - -- Bank 4: 3.3V - -- Bank 5: 3.3V - -- Bank 6: 3.3V - -- Bank 7: 3.3V - -- Bank 8: 3.3V - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND - -- or leave it unconnected. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition -CHIP "WOLF-LITE" ASSIGNED TO AN: EP4CE10E22C8 - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment -------------------------------------------------------------------------------------------------------------- -GND* : 1 : : : : 1 : -GND* : 2 : : : : 1 : -GND* : 3 : : : : 1 : -GND : 4 : gnd : : : : -VCCINT : 5 : power : : 1.2V : : -FLASH_MOSI : 6 : output : 2.5 V : : 1 : Y -GND* : 7 : : : : 1 : -FLASH_S : 8 : output : 2.5 V : : 1 : Y -nSTATUS : 9 : : : : 1 : -GND* : 10 : : : : 1 : -GND* : 11 : : : : 1 : -FLASH_C : 12 : output : 2.5 V : : 1 : Y -FLASH_MISO : 13 : input : 2.5 V : : 1 : Y -nCONFIG : 14 : : : : 1 : -altera_reserved_tdi : 15 : input : 2.5 V : : 1 : N -altera_reserved_tck : 16 : input : 2.5 V : : 1 : N -VCCIO1 : 17 : power : : 2.5V : 1 : -altera_reserved_tms : 18 : input : 2.5 V : : 1 : N -GND : 19 : gnd : : : : -altera_reserved_tdo : 20 : output : 2.5 V : : 1 : N -nCE : 21 : : : : 1 : -GND : 22 : gnd : : : : -GND+ : 23 : : : : 1 : -GND+ : 24 : : : : 2 : -GND+ : 25 : : : : 2 : -VCCIO2 : 26 : power : : 3.3V : 2 : -GND : 27 : gnd : : : : -GND* : 28 : : : : 2 : -VCCINT : 29 : power : : 1.2V : : -GND* : 30 : : : : 2 : -GND* : 31 : : : : 2 : -STM32_SYNC : 32 : input : 3.3-V LVTTL : : 2 : Y -STM32_CLK : 33 : input : 3.3-V LVTTL : : 2 : Y -GND* : 34 : : : : 2 : -VCCA1 : 35 : power : : 2.5V : : -GNDA1 : 36 : gnd : : : : -VCCD_PLL1 : 37 : power : : 1.2V : : -STM32_DATA_BUS[3] : 38 : bidir : 3.3-V LVTTL : : 3 : Y -STM32_DATA_BUS[4] : 39 : bidir : 3.3-V LVTTL : : 3 : Y -VCCIO3 : 40 : power : : 3.3V : 3 : -GND : 41 : gnd : : : : -STM32_DATA_BUS[5] : 42 : bidir : 3.3-V LVTTL : : 3 : Y -STM32_DATA_BUS[6] : 43 : bidir : 3.3-V LVTTL : : 3 : Y -ADC_OTR : 44 : input : 3.3-V LVTTL : : 3 : Y -VCCINT : 45 : power : : 1.2V : : -STM32_DATA_BUS[7] : 46 : bidir : 3.3-V LVTTL : : 3 : Y -VCCIO3 : 47 : power : : 3.3V : 3 : -GND : 48 : gnd : : : : -STM32_DATA_BUS[0] : 49 : bidir : 3.3-V LVTTL : : 3 : Y -STM32_DATA_BUS[1] : 50 : bidir : 3.3-V LVTTL : : 3 : Y -STM32_DATA_BUS[2] : 51 : bidir : 3.3-V LVTTL : : 3 : Y -ADC_INPUT[11] : 52 : input : 3.3-V LVTTL : : 3 : Y -ADC_INPUT[10] : 53 : input : 3.3-V LVTTL : : 3 : Y -ADC_INPUT[9] : 54 : input : 3.3-V LVTTL : : 4 : Y -ADC_INPUT[8] : 55 : input : 3.3-V LVTTL : : 4 : Y -VCCIO4 : 56 : power : : 3.3V : 4 : -GND : 57 : gnd : : : : -ADC_INPUT[7] : 58 : input : 3.3-V LVTTL : : 4 : Y -ADC_INPUT[6] : 59 : input : 3.3-V LVTTL : : 4 : Y -ADC_INPUT[5] : 60 : input : 3.3-V LVTTL : : 4 : Y -VCCINT : 61 : power : : 1.2V : : -VCCIO4 : 62 : power : : 3.3V : 4 : -GND : 63 : gnd : : : : -ADC_INPUT[4] : 64 : input : 3.3-V LVTTL : : 4 : Y -ADC_INPUT[3] : 65 : input : 3.3-V LVTTL : : 4 : Y -ADC_INPUT[2] : 66 : input : 3.3-V LVTTL : : 4 : Y -ADC_INPUT[1] : 67 : input : 3.3-V LVTTL : : 4 : Y -ADC_INPUT[0] : 68 : input : 3.3-V LVTTL : : 4 : Y -PREAMP : 69 : output : 3.3-V LVTTL : : 4 : Y -GND* : 70 : : : : 4 : -GND* : 71 : : : : 4 : -TXRX_OUT : 72 : output : 3.3-V LVTTL : : 4 : Y -GND* : 73 : : : : 5 : -LPF_3 : 74 : output : 3.3-V LVTTL : : 5 : Y -LPF_2 : 75 : output : 3.3-V LVTTL : : 5 : Y -LPF_1 : 76 : output : 3.3-V LVTTL : : 5 : Y -BPF_OE1 : 77 : output : 3.3-V LVTTL : : 5 : Y -VCCINT : 78 : power : : 1.2V : : -GND : 79 : gnd : : : : -BPF_A : 80 : output : 3.3-V LVTTL : : 5 : Y -VCCIO5 : 81 : power : : 3.3V : 5 : -GND : 82 : gnd : : : : -BPF_B : 83 : output : 3.3-V LVTTL : : 5 : Y -BPF_OE2 : 84 : output : 3.3-V LVTTL : : 5 : Y -ATT_16 : 85 : output : 3.3-V LVTTL : : 5 : Y -ATT_05 : 86 : output : 3.3-V LVTTL : : 5 : Y -ATT_1 : 87 : output : 3.3-V LVTTL : : 5 : Y -GND+ : 88 : : : : 5 : -clk_sys : 89 : input : 3.3-V LVTTL : : 5 : Y -GND+ : 90 : : : : 6 : -GND+ : 91 : : : : 6 : -CONF_DONE : 92 : : : : 6 : -VCCIO6 : 93 : power : : 3.3V : 6 : -MSEL0 : 94 : : : : 6 : -GND : 95 : gnd : : : : -MSEL1 : 96 : : : : 6 : -MSEL2 : 97 : : : : 6 : -ATT_2 : 98 : output : 3.3-V LVTTL : : 6 : Y -ATT_4 : 99 : output : 3.3-V LVTTL : : 6 : Y -ATT_8 : 100 : output : 3.3-V LVTTL : : 6 : Y -DAC_OUTPUT[0] : 101 : output : 3.3-V LVTTL : : 6 : Y -VCCINT : 102 : power : : 1.2V : : -DAC_OUTPUT[1] : 103 : output : 3.3-V LVTTL : : 6 : Y -DAC_OUTPUT[2] : 104 : output : 3.3-V LVTTL : : 6 : Y -DAC_OUTPUT[3] : 105 : output : 3.3-V LVTTL : : 6 : Y -DAC_OUTPUT[4] : 106 : output : 3.3-V LVTTL : : 6 : Y -VCCA2 : 107 : power : : 2.5V : : -GNDA2 : 108 : gnd : : : : -VCCD_PLL2 : 109 : power : : 1.2V : : -DAC_OUTPUT[5] : 110 : output : 3.3-V LVTTL : : 7 : Y -DAC_OUTPUT[6] : 111 : output : 3.3-V LVTTL : : 7 : Y -DAC_OUTPUT[7] : 112 : output : 3.3-V LVTTL : : 7 : Y -DAC_OUTPUT[8] : 113 : output : 3.3-V LVTTL : : 7 : Y -DAC_OUTPUT[9] : 114 : output : 3.3-V LVTTL : : 7 : Y -DAC_OUTPUT[10] : 115 : output : 3.3-V LVTTL : : 7 : Y -VCCINT : 116 : power : : 1.2V : : -VCCIO7 : 117 : power : : 3.3V : 7 : -GND : 118 : gnd : : : : -DAC_OUTPUT[11] : 119 : output : 3.3-V LVTTL : : 7 : Y -DAC_OUTPUT[12] : 120 : output : 3.3-V LVTTL : : 7 : Y -DAC_OUTPUT[13] : 121 : output : 3.3-V LVTTL : : 7 : Y -VCCIO7 : 122 : power : : 3.3V : 7 : -GND : 123 : gnd : : : : -DAC_PD : 124 : output : 3.3-V LVTTL : : 7 : Y -DAC_CLK : 125 : output : 3.3-V LVTTL : : 7 : Y -GND* : 126 : : : : 7 : -GND* : 127 : : : : 7 : -GND* : 128 : : : : 8 : -GND* : 129 : : : : 8 : -VCCIO8 : 130 : power : : 3.3V : 8 : -GND : 131 : gnd : : : : -GND* : 132 : : : : 8 : -GND* : 133 : : : : 8 : -VCCINT : 134 : power : : 1.2V : : -AUDIO_48K_CLOCK : 135 : output : 3.3-V LVTTL : : 8 : Y -AUDIO_I2S_CLOCK : 136 : output : 3.3-V LVTTL : : 8 : Y -GND* : 137 : : : : 8 : -GND* : 138 : : : : 8 : -VCCIO8 : 139 : power : : 3.3V : 8 : -GND : 140 : gnd : : : : -GND* : 141 : : : : 8 : -GND* : 142 : : : : 8 : -GND* : 143 : : : : 8 : -GND* : 144 : : : : 8 : -GND : EPAD : : : : : diff --git a/FPGA_61.440/output_files/WOLF-LITE.sld b/FPGA_61.440/output_files/WOLF-LITE.sld deleted file mode 100644 index 11c0032..0000000 --- a/FPGA_61.440/output_files/WOLF-LITE.sld +++ /dev/null @@ -1,49 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FPGA_61.440/output_files/signal_activity.saf b/FPGA_61.440/output_files/signal_activity.saf deleted file mode 100644 index 5cb1c1c..0000000 --- a/FPGA_61.440/output_files/signal_activity.saf +++ /dev/null @@ -1,22623 +0,0 @@ -# Copyright (C) 2018 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. - -# Signal Activity File Name: "output_files/signal_activity.saf" -# Created On: "05/11/2021 21:59:03" -# Created By: "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" -# This file was created by the Quartus Prime Power Analyzer. - -FORMAT_VERSION 1; - -DEFINE_FLAG TOGGLE_RATE_FROM_SIMULATION 0x1; -DEFINE_FLAG STATIC_PROBABILITY_FROM_SIMULATION 0x2; -DEFINE_FLAG TOGGLE_RATE_FROM_USER 0x4; -DEFINE_FLAG STATIC_PROBABILITY_FROM_USER 0x8; -DEFINE_FLAG TOGGLE_RATE_FROM_USER_DEFAULT 0x10; -DEFINE_FLAG STATIC_PROBABILITY_FROM_USER_DEFAULT 0x20; -DEFINE_FLAG TOGGLE_RATE_FROM_VECTORLESS_ESTIMATION 0x40; -DEFINE_FLAG STATIC_PROBABILITY_FROM_VECTORLESS_ESTIMATION 0x80; -DEFINE_FLAG TOGGLE_RATE_ASSUMED_ZERO 0x100; -DEFINE_FLAG TOGGLE_RATE_CLIPPED_TO_MAX 0x200; - -BEGIN_OUTPUT_SIGNAL_INFO; - -# Output Signal Information Line Format Description: - -# []<;> - - ADC_INPUT[0] 0x30 4.91521e+07 0.5; - ADC_INPUT[0]~input 0xc0 4.91521e+07 0.5; - ADC_INPUT[1] 0x30 4.91521e+07 0.5; - ADC_INPUT[1]~input 0xc0 4.91521e+07 0.5; - ADC_INPUT[2] 0x30 4.91521e+07 0.5; - ADC_INPUT[2]~input 0xc0 4.91521e+07 0.5; - ADC_INPUT[3] 0x30 4.91521e+07 0.5; - ADC_INPUT[3]~input 0xc0 4.91521e+07 0.5; - ADC_INPUT[4] 0x30 4.91521e+07 0.5; - ADC_INPUT[4]~input 0xc0 4.91521e+07 0.5; - ADC_INPUT[5] 0x30 4.91521e+07 0.5; - ADC_INPUT[5]~input 0xc0 4.91521e+07 0.5; - ADC_INPUT[6] 0x30 4.91521e+07 0.5; - ADC_INPUT[6]~input 0xc0 4.91521e+07 0.5; - ADC_INPUT[7] 0x30 4.91521e+07 0.5; - ADC_INPUT[7]~input 0xc0 4.91521e+07 0.5; - ADC_INPUT[8] 0x30 4.91521e+07 0.5; - ADC_INPUT[8]~input 0xc0 4.91521e+07 0.5; - ADC_INPUT[9] 0x30 4.91521e+07 0.5; - ADC_INPUT[9]~input 0xc0 4.91521e+07 0.5; - ADC_INPUT[10] 0x30 4.91521e+07 0.5; - ADC_INPUT[10]~input 0xc0 4.91521e+07 0.5; - ADC_INPUT[11] 0x30 4.91521e+07 0.5; - ADC_INPUT[11]~input 0xc0 4.91521e+07 0.5; - ADC_Latch:ADC_Latch; - lpm_add_sub:LPM_ADD_SUB_component; - add_sub_b2k:auto_generated; - pipeline_dffe[0] 0xc0 7.68002e+06 0.5; - pipeline_dffe[1] 0xc0 7.68002e+06 0.5; - pipeline_dffe[2] 0xc0 7.68002e+06 0.5; - pipeline_dffe[2]~feeder 0xc0 4.91521e+07 0.5; - pipeline_dffe[3] 0xc0 7.68002e+06 0.5; - pipeline_dffe[3]~feeder 0xc0 4.91521e+07 0.5; - pipeline_dffe[4] 0xc0 7.68002e+06 0.5; - pipeline_dffe[5] 0xc0 7.68002e+06 0.5; - pipeline_dffe[5]~feeder 0xc0 4.91521e+07 0.5; - pipeline_dffe[6] 0xc0 7.68002e+06 0.5; - pipeline_dffe[6]~feeder 0xc0 4.91521e+07 0.5; - pipeline_dffe[7] 0xc0 7.68002e+06 0.5; - pipeline_dffe[8] 0xc0 7.68002e+06 0.5; - pipeline_dffe[8]~feeder 0xc0 4.91521e+07 0.5; - pipeline_dffe[9] 0xc0 7.68002e+06 0.5; - pipeline_dffe[9]~feeder 0xc0 4.91521e+07 0.5; - pipeline_dffe[10] 0xc0 7.68002e+06 0.5; - pipeline_dffe[10]~feeder 0xc0 4.91521e+07 0.5; - pipeline_dffe[11] 0xc0 7.68002e+06 0.5; - ADC_OTR 0x30 2e+07 0.5; - ADC_OTR~input 0xc0 2e+07 0.5; - altera_internal_jtag~TCKUTAP 0xc0 2e+07 0.5; - altera_internal_jtag~TCKUTAPclkctrl 0xc0 2e+07 0.5; - altera_internal_jtag~TDIUTAP 0xc0 8e+06 0.5; - altera_internal_jtag~TDO 0xc0 5e+06 0.5; - altera_internal_jtag~TMSUTAP 0xc0 8e+06 0.5; - altera_reserved_tck 0xc 2e+07 0.5; - altera_reserved_tck~input 0xc0 2e+07 0.5; - altera_reserved_tdi 0x30 8e+06 0.5; - altera_reserved_tdi~input 0xc0 8e+06 0.5; - altera_reserved_tdo 0xc0 5e+06 0.5; - altera_reserved_tdo~output 0xc0 5e+06 0.5; - altera_reserved_tms 0x30 8e+06 0.5; - altera_reserved_tms~input 0xc0 8e+06 0.5; - ATT_1 0xc0 3.125e+06 0.5; - ATT_1~output 0xc0 3.125e+06 0.5; - ATT_2 0xc0 3.125e+06 0.5; - ATT_2~output 0xc0 3.125e+06 0.5; - ATT_4 0xc0 3.125e+06 0.5; - ATT_4~output 0xc0 3.125e+06 0.5; - ATT_05 0xc0 3.125e+06 0.5; - ATT_05~output 0xc0 3.125e+06 0.5; - ATT_8 0xc0 3.125e+06 0.5; - ATT_8~output 0xc0 3.125e+06 0.5; - ATT_16 0xc0 3.125e+06 0.5; - ATT_16~output 0xc0 3.125e+06 0.5; - AUDIO_48K_CLOCK 0xc0 96000.2 0.5; - AUDIO_48K_CLOCK~output 0xc0 96000.2 0.5; - AUDIO_I2S_CLOCK 0xc0 2.45761e+07 0.5; - AUDIO_I2S_CLOCK~output 0xc0 2.45761e+07 0.5; - hard_block:auto_generated_inst; - sld_hub:auto_hub; - alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric; - alt_sld_fab:instrumentation_fabric; - alt_sld_fab_alt_sld_fab:alt_sld_fab; - alt_sld_fab_alt_sld_fab_ident:ident; - Mux0~0 0xc0 567627 0.4375; - Mux0~1 0xc0 509033 0.09375; - Mux1~0 0xc0 478821 0.5625; - Mux1~1 0xc0 605469 0.3125; - Mux1~2 0xc0 424805 0.15625; - Mux1~3 0xc0 703125 0.25; - Mux2~0 0xc0 459595 0.375; - Mux2~1 0xc0 350647 0.1875; - Mux2~2 0xc0 153522 0.09375; - Mux3~0 0xc0 629883 0.5625; - Mux3~1 0xc0 703125 0.25; - Mux3~2 0xc0 344696 0.15625; - alt_sld_fab_alt_sld_fab_sldfabric:sldfabric; - sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub; - clr_reg 0xc0 1.25e+06 0.5; - clr_reg_proc~0 0xc0 703125 0.25; - design_hash_proc~0 0xc0 937500 0.75; - design_hash_reg[0] 0xc0 1.25e+06 0.5; - design_hash_reg[0]~0 0xc0 515692 0.296875; - design_hash_reg[1] 0xc0 1.25e+06 0.5; - design_hash_reg[1]~1 0xc0 1.16438e+06 0.359375; - design_hash_reg[2] 0xc0 1.25e+06 0.5; - design_hash_reg[2]~2 0xc0 533266 0.296875; - design_hash_reg[3] 0xc0 1.25e+06 0.5; - design_hash_reg[3]~3 0xc0 571203 0.328125; - design_hash_reg~4 0xc0 590820 0.5; - design_hash_reg~5 0xc0 590820 0.5; - design_hash_reg~6 0xc0 590820 0.5; - design_hash_reg~7 0xc0 1.01709e+06 0.5; - Equal0~0 0xc0 168457 0.0625; - Equal0~1 0xc0 168457 0.0625; - Equal0~2 0xc0 694.469 0.000976563; - Equal1~0 0xc0 694.469 0.000976563; - Equal7~0 0xc0 371094 0.125; - sld_rom_sr:hub_info_reg; - Add0~0 0xc0 1.25e+06 0.5; - Add0~1 0xc0 1.25e+06 0.5; - Add0~2 0xc0 1.25e+06 0.5; - Add0~3 0xc0 703125 0.75; - Add0~4 0xc0 1.13281e+06 0.5; - Add0~5 0xc0 957031 0.125; - Add0~6 0xc0 1.45508e+06 0.5; - Add0~7 0xc0 278320 0.9375; - Add0~8 0xc0 1.24268e+06 0.5; - clear_signal 0xc0 937500 0.25; - Equal0~0 0xc0 153809 0.0625; - Mux0~0 0xc0 568848 0.3125; - Mux1~0 0xc0 615234 0.625; - word_counter[0] 0xc0 1.25e+06 0.5; - word_counter[1] 0xc0 1.25e+06 0.5; - word_counter[2] 0xc0 1.25e+06 0.5; - word_counter[3] 0xc0 1.25e+06 0.5; - word_counter[4] 0xc0 1.25e+06 0.5; - word_counter~0 0xc0 1.17188e+06 0.375; - word_counter~1 0xc0 1.06201e+06 0.34375; - word_counter~2 0xc0 1.08398e+06 0.375; - word_counter~3 0xc0 1.06759e+06 0.375; - word_counter~4 0xc0 975952 0.375; - word_counter~5 0xc0 1.11957e+06 0.375; - WORD_SR[0] 0xc0 1.25e+06 0.5; - WORD_SR[1] 0xc0 1.25e+06 0.5; - WORD_SR[2] 0xc0 1.25e+06 0.5; - WORD_SR[3] 0xc0 1.25e+06 0.5; - WORD_SR~0 0xc0 541992 0.1875; - WORD_SR~1 0xc0 893555 0.53125; - WORD_SR~2 0xc0 607910 0.375; - WORD_SR~3 0xc0 587769 0.28125; - WORD_SR~4 0xc0 194149 0.0703125; - WORD_SR~5 0xc0 1.76795e+06 0.244629; - WORD_SR~6 0xc0 1.2637e+06 0.304688; - hub_info_reg_ena~0 0xc0 703125 0.75; - hub_minor_ver_reg[0] 0xc0 1.25e+06 0.5; - hub_minor_ver_reg[1] 0xc0 1.25e+06 0.5; - hub_minor_ver_reg[2] 0xc0 1.25e+06 0.5; - hub_minor_ver_reg[3] 0xc0 1.25e+06 0.5; - hub_minor_ver_reg~0 0xc0 937500 0.75; - hub_minor_ver_reg~1 0xc0 937500 0.25; - hub_minor_ver_reg~2 0xc0 937500 0.75; - hub_minor_ver_reg~3 0xc0 2.8125e+06 0.25; - hub_mode_reg[0] 0xc0 1.25e+06 0.5; - hub_mode_reg[1] 0xc0 1.25e+06 0.5; - hub_mode_reg[1]~0 0xc0 568848 0.3125; - hub_mode_reg[1]~1 0xc0 737409 0.5; - hub_mode_reg[2] 0xc0 1.25e+06 0.5; - hub_mode_reg[2]~2 0xc0 153809 0.0625; - hub_mode_reg[2]~3 0xc0 465622 0.265625; - hub_mode_reg~4 0xc0 112610 0.0625; - identity_contrib_shift_reg[0] 0xc0 1.25e+06 0.5; - identity_contrib_shift_reg[0]~0 0xc0 153809 0.0625; - identity_contrib_shift_reg[0]~1 0xc0 17767 0.015625; - identity_contrib_shift_reg[1] 0xc0 1.25e+06 0.5; - identity_contrib_shift_reg[2] 0xc0 1.25e+06 0.5; - identity_contrib_shift_reg[3] 0xc0 1.25e+06 0.5; - irf_reg[1][0] 0xc0 1.25e+06 0.5; - irf_reg[1][0]~0 0xc0 455933 0.09375; - irf_reg[1][0]~feeder 0xc0 1.25e+06 0.5; - irf_reg[1][1] 0xc0 1.25e+06 0.5; - irf_reg[1][1]~feeder 0xc0 1.25e+06 0.5; - irf_reg[1][2] 0xc0 1.25e+06 0.5; - irf_reg[1][2]~feeder 0xc0 1.25e+06 0.5; - irf_reg[1][3] 0xc0 1.25e+06 0.5; - irf_reg[1][3]~feeder 0xc0 1.25e+06 0.5; - irsr_reg[0] 0xc0 1.25e+06 0.5; - irsr_reg[1] 0xc0 1.25e+06 0.5; - irsr_reg[2] 0xc0 1.25e+06 0.5; - irsr_reg[2]~3 0xc0 611572 0.25; - irsr_reg[3] 0xc0 1.25e+06 0.5; - irsr_reg[3]~6 0xc0 1.25e+06 0.25; - irsr_reg[3]~7 0xc0 786133 0.46875; - irsr_reg[3]~8 0xc0 861034 0.408203; - irsr_reg[4] 0xc0 1.25e+06 0.5; - irsr_reg~0 0xc0 2.16406e+06 0.5; - irsr_reg~1 0xc0 1.25e+06 0.25; - irsr_reg~2 0xc0 1.13281e+06 0.5; - irsr_reg~4 0xc0 1.25e+06 0.25; - irsr_reg~5 0xc0 1.25e+06 0.25; - jtag_ir_reg[0] 0xc0 1.25e+06 0.5; - jtag_ir_reg[0]~1 0xc0 1.25e+06 0.5; - jtag_ir_reg[1] 0xc0 1.25e+06 0.5; - jtag_ir_reg[1]~feeder 0xc0 1.25e+06 0.5; - jtag_ir_reg[2] 0xc0 1.25e+06 0.5; - jtag_ir_reg[2]~0 0xc0 1.25e+06 0.5; - jtag_ir_reg[3] 0xc0 1.25e+06 0.5; - jtag_ir_reg[3]~feeder 0xc0 1.25e+06 0.5; - jtag_ir_reg[4] 0xc0 1.25e+06 0.5; - jtag_ir_reg[5] 0xc0 1.25e+06 0.5; - jtag_ir_reg[6] 0xc0 1.25e+06 0.5; - jtag_ir_reg[6]~feeder 0xc0 1.25e+06 0.5; - jtag_ir_reg[7] 0xc0 1.25e+06 0.5; - jtag_ir_reg[7]~feeder 0xc0 1.25e+06 0.5; - jtag_ir_reg[8] 0xc0 1.25e+06 0.5; - jtag_ir_reg[8]~feeder 0xc0 1.25e+06 0.5; - jtag_ir_reg[9] 0xc0 1.25e+06 0.5; - mixer_addr_reg_internal[0] 0xc0 1.25e+06 0.5; - mixer_addr_reg_internal[0]~5 0xc0 1.25e+06 0.5; - mixer_addr_reg_internal[0]~6 0xc0 1.25e+06 0.5; - mixer_addr_reg_internal[1] 0xc0 1.25e+06 0.5; - mixer_addr_reg_internal[1]~9 0xc0 1.25e+06 0.5; - mixer_addr_reg_internal[1]~10 0xc0 703125 0.25; - mixer_addr_reg_internal[2] 0xc0 1.25e+06 0.5; - mixer_addr_reg_internal[2]~11 0xc0 1.13281e+06 0.5; - mixer_addr_reg_internal[2]~12 0xc0 332031 0.875; - mixer_addr_reg_internal[3] 0xc0 1.25e+06 0.5; - mixer_addr_reg_internal[3]~13 0xc0 1.14258e+06 0.5; - mixer_addr_reg_internal[3]~14 0xc0 1.05957e+06 0.0625; - mixer_addr_reg_internal[4] 0xc0 1.25e+06 0.5; - mixer_addr_reg_internal[4]~15 0xc0 1.6333e+06 0.5; - mixer_addr_reg_internal~7 0xc0 1.32259e+06 0.273438; - mixer_addr_reg_internal~8 0xc0 820313 0.4375; - node_ena_proc~0 0xc0 2.8125e+06 0.25; - node_ena_proc~1 0xc0 4.3125e+06 0.25; - node_ena~0 0xc0 2.2168e+06 0.5; - node_ena~1 0xc0 2.79591e+06 0.1875; - node_ena~2 0xc0 2.14355e+06 0.40625; - node_ena~3 0xc0 1.5828e+06 0.298828; - reset_ena_reg 0xc0 1.25e+06 0.5; - reset_ena_reg_proc~0 0xc0 1.31836e+06 0.1875; - sld_shadow_jsm:shadow_jsm; - state[0] 0xc0 1.25e+06 0.5; - state[0]~_wirecell 0xc0 1.25e+06 0.5; - state[1] 0xc0 1.25e+06 0.5; - state[2] 0xc0 1.25e+06 0.5; - state[3] 0xc0 1.25e+06 0.5; - state[4] 0xc0 1.25e+06 0.5; - state[5] 0xc0 1.25e+06 0.5; - state[6] 0xc0 1.25e+06 0.5; - state[7] 0xc0 1.25e+06 0.5; - state[8] 0xc0 1.25e+06 0.5; - state[9] 0xc0 1.25e+06 0.5; - state[10] 0xc0 1.25e+06 0.5; - state[11] 0xc0 1.25e+06 0.5; - state[12] 0xc0 1.25e+06 0.5; - state[13] 0xc0 1.25e+06 0.5; - state[14] 0xc0 1.25e+06 0.5; - state[15] 0xc0 1.25e+06 0.5; - state[15]~feeder 0xc0 3.46875e+06 0.375; - state~0 0xc0 4.51172e+06 0.5625; - state~1 0xc0 112610 0.9375; - state~2 0xc0 2.49023e+06 0.4375; - state~3 0xc0 2.625e+06 0.25; - state~4 0xc0 546875 0.875; - state~5 0xc0 2.51953e+06 0.375; - state~6 0xc0 703125 0.75; - state~7 0xc0 4.3125e+06 0.25; - state~8 0xc0 3.46875e+06 0.375; - state~9 0xc0 4.3125e+06 0.25; - state~10 0xc0 356445 0.875; - state~11 0xc0 3.98438e+06 0.375; - state~12 0xc0 703125 0.75; - state~13 0xc0 4.3125e+06 0.25; - tms_cnt[0] 0xc0 1.25e+06 0.5; - tms_cnt[1] 0xc0 1.25e+06 0.5; - tms_cnt[2] 0xc0 1.25e+06 0.5; - tms_cnt~0 0xc0 751953 0.5; - tms_cnt~1 0xc0 4.3125e+06 0.25; - tms_cnt~2 0xc0 1.25e+06 0.5; - tdo 0xc0 1.25e+06 0.5; - tdo_bypass_reg 0xc0 1.25e+06 0.5; - tdo_bypass_reg~0 0xc0 2.16406e+06 0.5; - tdo_mux_out~0 0xc0 1.02539e+06 0.5625; - tdo_mux_out~1 0xc0 352892 0.375; - tdo_mux_out~2 0xc0 534973 0.3125; - tdo_mux_out~3 0xc0 413086 0.359375; - tdo_mux_out~4 0xc0 863980 0.68042; - tdo_mux_out~5 0xc0 297852 0.125; - tdo_mux_out~6 0xc0 311279 0.25; - tdo_mux_out~7 0xc0 746819 0.34375; - tdo_mux_out~8 0xc0 1.01563e+06 0.5; - tdo_mux_out~9 0xc0 366991 0.721616; - virtual_dr_scan_reg 0xc0 1.25e+06 0.5; - virtual_ir_dr_scan_proc~0 0xc0 3.46875e+06 0.375; - virtual_ir_scan_reg 0xc0 1.25e+06 0.5; - virtual_ir_tdo_sel_reg[0] 0xc0 1.25e+06 0.5; - sldfabric_ident_writedata[0] 0xc0 1.25e+06 0.5; - sldfabric_ident_writedata[0]~0 0xc0 5857.35 0.0078125; - sldfabric_ident_writedata[1] 0xc0 1.25e+06 0.5; - sldfabric_ident_writedata[2] 0xc0 1.25e+06 0.5; - sldfabric_ident_writedata[3] 0xc0 1.25e+06 0.5; - splitter_nodes_receive_0[3] 0xc0 1.25e+06 0.5; - sld_jtag_interface_mod:\jtag_interface_mod_gen:device_family_mod_inst; - BPF_A 0xc0 3.125e+06 0.5; - BPF_A~output 0xc0 3.125e+06 0.5; - BPF_B 0xc0 3.125e+06 0.5; - BPF_B~output 0xc0 3.125e+06 0.5; - BPF_OE1 0xc0 3.125e+06 0.5; - BPF_OE1~output 0xc0 3.125e+06 0.5; - BPF_OE2 0xc0 3.125e+06 0.5; - BPF_OE2~output 0xc0 3.125e+06 0.5; - clk_sys 0xc 1.2288e+08 0.5; - clk_sys~input 0xc0 1.2288e+08 0.5; - DAC_CLK 0xc0 3.0722e+08 0.5; - DAC_CLK~output 0xc0 3.0722e+08 0.5; - DAC_corrector:DAC_CORRECTOR; - DATA_OUT[0] 0xc0 1.92012e+07 0.5; - DATA_OUT[0]~13 0xc0 4.78141e+06 0.294922; - DATA_OUT[1] 0xc0 1.92012e+07 0.5; - DATA_OUT[1]~12 0xc0 4.63974e+06 0.30957; - DATA_OUT[2] 0xc0 1.92012e+07 0.5; - DATA_OUT[2]~11 0xc0 4.57117e+06 0.324219; - DATA_OUT[3] 0xc0 1.92012e+07 0.5; - DATA_OUT[3]~10 0xc0 4.2516e+06 0.34375; - DATA_OUT[4] 0xc0 1.92012e+07 0.5; - DATA_OUT[4]~9 0xc0 4.01638e+06 0.359375; - DATA_OUT[5] 0xc0 1.92012e+07 0.5; - DATA_OUT[5]~8 0xc0 3.81977e+06 0.375; - DATA_OUT[6] 0xc0 1.92012e+07 0.5; - DATA_OUT[6]~7 0xc0 3.66314e+06 0.390625; - DATA_OUT[7] 0xc0 1.92012e+07 0.5; - DATA_OUT[7]~6 0xc0 3.37183e+06 0.420898; - DATA_OUT[8] 0xc0 1.92012e+07 0.5; - DATA_OUT[8]~5 0xc0 3.22697e+06 0.439453; - DATA_OUT[9] 0xc0 1.92012e+07 0.5; - DATA_OUT[9]~4 0xc0 3.14897e+06 0.458008; - DATA_OUT[10] 0xc0 1.92012e+07 0.5; - DATA_OUT[10]~3 0xc0 3.14408e+06 0.476563; - DATA_OUT[11] 0xc0 1.92012e+07 0.5; - DATA_OUT[11]~2 0xc0 3.10888e+06 0.484375; - DATA_OUT[12] 0xc0 1.92012e+07 0.5; - DATA_OUT[12]~1 0xc0 3.08921e+06 0.490234; - DATA_OUT[13] 0xc0 1.92012e+07 0.5; - DATA_OUT[13]~0 0xc0 3.08372e+06 0.5; - LessThan0~0 0xc0 100183 0.96875; - LessThan0~1 0xc0 705148 0.871094; - Mux0~0 0xc0 6.65668e+06 0.5; - Mux0~1 0xc0 4.51283e+06 0.5; - Mux0~2 0xc0 6.65668e+06 0.5; - Mux0~3 0xc0 4.51283e+06 0.5; - Mux0~4 0xc0 6.65668e+06 0.5; - Mux0~5 0xc0 4.51283e+06 0.5; - Mux0~6 0xc0 3.99805e+06 0.5; - Mux0~7 0xc0 6.65668e+06 0.5; - Mux0~8 0xc0 4.51283e+06 0.5; - Mux0~9 0xc0 2.13405e+06 0.5; - Mux0~10 0xc0 6.65668e+06 0.5; - Mux0~11 0xc0 4.51283e+06 0.5; - Mux0~12 0xc0 6.65668e+06 0.5; - Mux0~13 0xc0 4.51283e+06 0.5; - Mux0~14 0xc0 6.65668e+06 0.5; - Mux0~15 0xc0 4.51283e+06 0.5; - Mux0~16 0xc0 3.99805e+06 0.5; - Mux0~17 0xc0 6.65668e+06 0.5; - Mux0~18 0xc0 4.51283e+06 0.5; - Mux0~19 0xc0 2.13405e+06 0.5; - Mux1~0 0xc0 6.65668e+06 0.5; - Mux1~1 0xc0 4.51283e+06 0.5; - Mux1~2 0xc0 6.65668e+06 0.5; - Mux1~3 0xc0 4.51283e+06 0.5; - Mux1~4 0xc0 4.78156e+06 0.25; - Mux1~5 0xc0 3.59505e+06 0.34375; - Mux1~6 0xc0 3.98145e+06 0.460938; - Mux1~7 0xc0 6.65668e+06 0.5; - Mux1~8 0xc0 4.51283e+06 0.5; - Mux1~9 0xc0 2.14205e+06 0.480469; - Mux1~10 0xc0 6.65668e+06 0.5; - Mux1~11 0xc0 4.51283e+06 0.5; - Mux1~12 0xc0 6.65668e+06 0.5; - Mux1~13 0xc0 4.51283e+06 0.5; - Mux1~14 0xc0 6.65668e+06 0.5; - Mux1~15 0xc0 4.51283e+06 0.5; - Mux1~16 0xc0 3.99805e+06 0.5; - Mux1~17 0xc0 6.65668e+06 0.5; - Mux1~18 0xc0 4.51283e+06 0.5; - Mux1~19 0xc0 2.13405e+06 0.5; - Mux2~0 0xc0 1.75781e+06 0.25; - Mux2~1 0xc0 6.65668e+06 0.5; - Mux2~2 0xc0 4.51283e+06 0.5; - Mux2~3 0xc0 6.65668e+06 0.5; - Mux2~4 0xc0 4.51283e+06 0.5; - Mux2~5 0xc0 5.48473e+06 0.25; - Mux2~6 0xc0 4.50852e+06 0.4375; - Mux2~7 0xc0 6.65668e+06 0.5; - Mux2~8 0xc0 4.51283e+06 0.5; - Mux2~9 0xc0 2.22233e+06 0.46875; - Mux2~10 0xc0 6.65668e+06 0.5; - Mux2~11 0xc0 4.51283e+06 0.5; - Mux2~12 0xc0 6.65668e+06 0.5; - Mux2~13 0xc0 4.51283e+06 0.5; - Mux2~14 0xc0 6.65668e+06 0.5; - Mux2~15 0xc0 4.51283e+06 0.5; - Mux2~16 0xc0 3.99805e+06 0.5; - Mux2~17 0xc0 6.65668e+06 0.5; - Mux2~18 0xc0 4.51283e+06 0.5; - Mux2~19 0xc0 2.13405e+06 0.5; - Mux3~0 0xc0 6.65668e+06 0.5; - Mux3~1 0xc0 4.51283e+06 0.5; - Mux3~2 0xc0 6.65668e+06 0.5; - Mux3~3 0xc0 4.51283e+06 0.5; - Mux3~4 0xc0 4.57529e+06 0.125; - Mux3~5 0xc0 5.33314e+06 0.40625; - Mux3~6 0xc0 6.65668e+06 0.5; - Mux3~7 0xc0 4.51283e+06 0.5; - Mux3~8 0xc0 2.35554e+06 0.453125; - Mux3~9 0xc0 6.65668e+06 0.5; - Mux3~10 0xc0 4.51283e+06 0.5; - Mux3~11 0xc0 6.65668e+06 0.5; - Mux3~12 0xc0 4.51283e+06 0.5; - Mux3~13 0xc0 6.65668e+06 0.5; - Mux3~14 0xc0 4.51283e+06 0.5; - Mux3~15 0xc0 3.99805e+06 0.5; - Mux3~16 0xc0 6.65668e+06 0.5; - Mux3~17 0xc0 4.51283e+06 0.5; - Mux3~18 0xc0 2.13405e+06 0.5; - Mux4~0 0xc0 9.75062e+06 0.5; - Mux4~1 0xc0 4.58687e+06 0.375; - Mux4~2 0xc0 4.57529e+06 0.125; - Mux4~3 0xc0 5.33314e+06 0.40625; - Mux4~4 0xc0 2.06169e+06 0.416016; - Mux4~5 0xc0 3.99805e+06 0.5; - Mux4~6 0xc0 2.13405e+06 0.5; - Mux5~0 0xc0 4.78156e+06 0.25; - Mux5~1 0xc0 4.57529e+06 0.125; - Mux5~2 0xc0 5.33314e+06 0.40625; - Mux5~3 0xc0 2.0299e+06 0.378906; - Mux5~4 0xc0 3.99805e+06 0.5; - Mux5~5 0xc0 2.13405e+06 0.5; - Mux6~0 0xc0 4.57529e+06 0.125; - Mux6~1 0xc0 4.57529e+06 0.125; - Mux6~2 0xc0 5.33314e+06 0.40625; - Mux6~3 0xc0 2.22206e+06 0.341797; - Mux6~4 0xc0 3.99805e+06 0.5; - Mux6~5 0xc0 2.13405e+06 0.5; - Mux7~0 0xc0 3.30444e+06 0.3125; - Mux7~1 0xc0 2.47655e+06 0.28125; - Mux7~2 0xc0 3.99805e+06 0.5; - Mux7~3 0xc0 2.13405e+06 0.5; - Mux8~0 0xc0 2.58463e+06 0.25; - Mux8~1 0xc0 2.45494e+06 0.25; - Mux8~2 0xc0 3.99805e+06 0.5; - Mux8~3 0xc0 2.13405e+06 0.5; - Mux9~0 0xc0 2.21435e+06 0.1875; - Mux9~1 0xc0 2.5469e+06 0.21875; - Mux9~2 0xc0 3.99805e+06 0.5; - Mux9~3 0xc0 2.13405e+06 0.5; - Mux10~0 0xc0 2.11888e+06 0.125; - Mux10~1 0xc0 2.74394e+06 0.1875; - Mux10~2 0xc0 3.99805e+06 0.5; - Mux10~3 0xc0 2.13405e+06 0.5; - Mux11~0 0xc0 1.7298e+06 0.0625; - Mux11~1 0xc0 2.963e+06 0.148438; - Mux11~2 0xc0 3.99805e+06 0.5; - Mux11~3 0xc0 2.13405e+06 0.5; - Mux12~0 0xc0 1.7298e+06 0.0625; - Mux12~1 0xc0 1.95082e+06 0.119141; - Mux12~2 0xc0 3.99805e+06 0.5; - Mux12~3 0xc0 2.13405e+06 0.5; - Mux13~0 0xc0 1.7298e+06 0.0625; - Mux13~1 0xc0 1.26984e+06 0.0898438; - Mux13~2 0xc0 3.99805e+06 0.5; - Mux13~3 0xc0 2.13405e+06 0.5; - dac_null:DAC_IDLE; - mux14:DAC_MUX; - lpm_mux:LPM_MUX_component; - mux_rsc:auto_generated; - result_node[0]~12 0xc0 1.08007e+07 0.25; - result_node[1]~11 0xc0 1.08007e+07 0.25; - result_node[2]~10 0xc0 1.08007e+07 0.25; - result_node[3]~9 0xc0 1.08007e+07 0.25; - result_node[4]~8 0xc0 1.08007e+07 0.25; - result_node[5]~7 0xc0 1.08007e+07 0.25; - result_node[6]~6 0xc0 1.08007e+07 0.25; - result_node[7]~5 0xc0 1.08007e+07 0.25; - result_node[8]~4 0xc0 1.08007e+07 0.25; - result_node[9]~3 0xc0 1.08007e+07 0.25; - result_node[10]~2 0xc0 1.08007e+07 0.25; - result_node[11]~1 0xc0 1.08007e+07 0.25; - result_node[12]~0 0xc0 1.08007e+07 0.25; - result_node[13] 0xc0 1.08007e+07 0.75; - DAC_OUTPUT[0] 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[0]~output 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[1] 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[1]~output 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[2] 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[2]~output 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[3] 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[3]~output 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[4] 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[4]~output 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[5] 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[5]~output 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[6] 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[6]~output 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[7] 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[7]~output 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[8] 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[8]~output 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[9] 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[9]~output 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[10] 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[10]~output 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[11] 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[11]~output 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[12] 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[12]~output 0xc0 1.08007e+07 0.25; - DAC_OUTPUT[13] 0xc0 1.08007e+07 0.75; - DAC_OUTPUT[13]~output 0xc0 1.08007e+07 0.75; - DAC_PD 0xc0 3.125e+06 0.5; - DAC_PD~output 0xc0 3.125e+06 0.5; - DEBUG:DBG_ADC; - altsource_probe_top:in_system_sources_probes_0; - altsource_probe:issp_impl; - altsource_probe_body:altsource_probe_body_inst; - altsource_probe_impl:\wider_probe_gen:wider_probe_inst; - sld_rom_sr:\instance_id_gen:rom_info_inst; - Add0~0 0xc0 703125 0.25; - Add0~1 0xc0 297852 0.125; - Equal0~0 0xc0 112610 0.0625; - Mux1~0 0xc0 348206 0.6875; - Mux2~0 0xc0 215454 0.125; - Mux3~0 0xc0 377197 0.75; - word_counter[0] 0xc0 1.25e+06 0.5; - word_counter[1] 0xc0 1.25e+06 0.5; - word_counter[2] 0xc0 1.25e+06 0.5; - word_counter[3] 0xc0 1.25e+06 0.5; - word_counter~0 0xc0 1.05303e+06 0.4375; - word_counter~1 0xc0 979666 0.410156; - word_counter~2 0xc0 252910 0.179688; - word_counter~3 0xc0 904103 0.410156; - word_counter~4 0xc0 918071 0.410156; - WORD_SR[0] 0xc0 1.25e+06 0.5; - WORD_SR[1] 0xc0 1.25e+06 0.5; - WORD_SR[2] 0xc0 1.25e+06 0.5; - WORD_SR[3] 0xc0 1.25e+06 0.5; - WORD_SR~0 0xc0 677816 0.246094; - WORD_SR~1 0xc0 370622 0.289063; - WORD_SR~2 0xc0 605133 0.150391; - WORD_SR~3 0xc0 898383 0.293945; - WORD_SR~4 0xc0 112610 0.0625; - WORD_SR~5 0xc0 4.58439e+06 0.102539; - bypass_reg 0xc0 1.25e+06 0.5; - hold_reg[0] 0xc0 1.25e+06 0.5; - hold_reg[0]~0 0xc0 234375 0.0625; - hold_reg[0]~1 0xc0 917435 0.5; - shift_reg[0] 0xc0 1.25e+06 0.5; - shift_reg[1] 0xc0 1.25e+06 0.5; - shift_reg[2] 0xc0 1.25e+06 0.5; - shift_reg[3] 0xc0 1.25e+06 0.5; - shift_reg[4] 0xc0 1.25e+06 0.5; - shift_reg[5] 0xc0 1.25e+06 0.5; - shift_reg[6] 0xc0 1.25e+06 0.5; - shift_reg[7] 0xc0 1.25e+06 0.5; - shift_reg[8] 0xc0 1.25e+06 0.5; - shift_reg[9] 0xc0 1.25e+06 0.5; - shift_reg[10] 0xc0 1.25e+06 0.5; - shift_reg[11] 0xc0 1.25e+06 0.5; - shift_reg~0 0xc0 937500 0.25; - shift_reg~1 0xc0 2.36251e+06 0.375; - shift_reg~2 0xc0 1.84041e+06 0.458984; - shift_reg~3 0xc0 619812 0.171875; - shift_reg~4 0xc0 315018 0.21875; - shift_reg~5 0xc0 918747 0.165039; - shift_reg~6 0xc0 429688 0.125; - shift_reg~7 0xc0 918747 0.165039; - shift_reg~8 0xc0 918747 0.165039; - shift_reg~9 0xc0 918747 0.165039; - shift_reg~10 0xc0 918747 0.165039; - shift_reg~11 0xc0 918747 0.165039; - shift_reg~12 0xc0 918747 0.165039; - shift_reg~13 0xc0 918747 0.165039; - shift_reg~14 0xc0 918747 0.165039; - shift_reg~15 0xc0 918747 0.165039; - shift_reg~16 0xc0 2.12005e+06 0.165039; - tdo~0 0xc0 781250 0.5; - tdo~1 0xc0 361195 0.5; - vjtag_sdr_i~0 0xc0 488281 0.125; - vjtag_sdr_i~1 0xc0 937500 0.25; - vjtag_uir_i~0 0xc0 546875 0.125; - sld_jtag_endpoint_adapter:jtag_signal_adapter; - spi_interface:FLASH; - Add0~0 0xc0 7.68002e+06 0.5; - Add0~1 0xc0 7.68002e+06 0.5; - Add0~2 0xc0 7.68002e+06 0.5; - Add0~3 0xc0 5.76001e+06 0.25; - Add0~4 0xc0 7.68002e+06 0.5; - Add0~5 0xc0 2.40001e+06 0.875; - Add0~6 0xc0 7.20002e+06 0.5; - Add0~7 0xc0 6.60002e+06 0.0625; - Add0~8 0xc0 1.008e+07 0.5; - Add0~9 0xc0 1.71e+06 0.96875; - Add0~10 0xc0 8.07002e+06 0.5; - Add0~11 0xc0 7.64252e+06 0.015625; - Add0~12 0xc0 1.1265e+07 0.5; - Add0~13 0xc0 1.91438e+06 0.992188; - Add0~14 0xc0 8.51815e+06 0.5; - CS_S 0xc0 7.68002e+06 0.5; - CS_S~0 0xc0 3.91023e+06 0.265625; - Decoder0~0 0xc0 246212 0.03125; - Decoder0~1 0xc0 293.055 0.000488281; - Decoder0~2 0xc0 4.32001e+06 0.25; - Decoder0~3 0xc0 4.32001e+06 0.25; - Decoder0~4 0xc0 293.055 0.000488281; - Decoder0~5 0xc0 4.32001e+06 0.25; - Equal0~0 0xc0 1.83e+06 0.125; - Equal0~1 0xc0 691877 0.0625; - Equal1~0 0xc0 691877 0.0625; - Equal1~1 0xc0 1.83e+06 0.125; - Equal5~0 0xc0 5.76001e+06 0.25; - Equal5~1 0xc0 781877 0.0625; - Equal5~2 0xc0 11603.3 0.00390625; - Equal5~3 0xc0 357657 0.03125; - Equal5~4 0xc0 4.32001e+06 0.25; - MOSI_DQ0 0xc0 7.68002e+06 0.5; - MOSI_DQ0~0 0xc0 2.4575e+06 0.5; - MOSI_DQ0~1 0xc0 2.10066e+06 0.25; - Mux0~0 0xc0 2.66251e+06 0.5; - Mux0~1 0xc0 1.80502e+06 0.5; - Mux0~2 0xc0 2.66251e+06 0.5; - Mux0~3 0xc0 1.80502e+06 0.5; - SCK_C 0xc0 7.68002e+06 0.5; - SCK_C~0 0xc0 1.83e+06 0.875; - SCK_C~1 0xc0 2.93168e+06 0.753906; - SCK_C~2 0xc0 4.32001e+06 0.25; - always0~0 0xc0 4.32001e+06 0.25; - busy 0xc0 7.68002e+06 0.5; - busy~0 0xc0 5.28435e+06 0.671509; - continue_read_prev 0xc0 7.68002e+06 0.5; - continue_read_prev~0 0xc0 4.32001e+06 0.25; - continue_read_prev~1 0xc0 2.45297e+06 0.257813; - data_out[0] 0xc0 7.68002e+06 0.5; - data_out[0]~11 0xc0 9.34802e+06 0.5; - data_out[1] 0xc0 7.68002e+06 0.5; - data_out[1]~10 0xc0 1.21023e+07 0.5; - data_out[2] 0xc0 7.68002e+06 0.5; - data_out[2]~8 0xc0 7.19402e+06 0.5; - data_out[2]~9 0xc0 4.39983e+06 0.5; - data_out[3] 0xc0 7.68002e+06 0.5; - data_out[3]~6 0xc0 7.99502e+06 0.5; - data_out[3]~7 0xc0 5.35203e+06 0.5; - data_out[4] 0xc0 7.68002e+06 0.5; - data_out[4]~5 0xc0 1.21023e+07 0.5; - data_out[5] 0xc0 7.68002e+06 0.5; - data_out[5]~3 0xc0 7.99502e+06 0.5; - data_out[5]~4 0xc0 4.48924e+06 0.5; - data_out[6] 0xc0 7.68002e+06 0.5; - data_out[6]~1 0xc0 8.32802e+06 0.5; - data_out[6]~2 0xc0 1.82717e+07 0.5; - data_out[7] 0xc0 7.68002e+06 0.5; - data_out[7]~0 0xc0 1.21023e+07 0.5; - enabled_prev 0xc0 7.68002e+06 0.5; - enabled_prev~feeder 0xc0 3.125e+06 0.5; - spi_bit_position[0] 0xc0 7.68002e+06 0.5; - spi_bit_position[1] 0xc0 7.68002e+06 0.5; - spi_bit_position[2] 0xc0 7.68002e+06 0.5; - spi_bit_position[3] 0xc0 7.68002e+06 0.5; - spi_bit_position[4] 0xc0 7.68002e+06 0.5; - spi_bit_position[5] 0xc0 7.68002e+06 0.5; - spi_bit_position[6] 0xc0 7.68002e+06 0.5; - spi_bit_position[7] 0xc0 7.68002e+06 0.5; - spi_bit_position~0 0xc0 2.54692e+06 0.175781; - spi_bit_position~1 0xc0 2.99011e+06 0.351563; - spi_bit_position~2 0xc0 6.91764e+06 0.670324; - spi_bit_position~3 0xc0 2.54692e+06 0.175781; - spi_bit_position~4 0xc0 2.54692e+06 0.175781; - spi_bit_position~5 0xc0 2.46762e+06 0.175781; - spi_bit_position~6 0xc0 2.94341e+06 0.175781; - spi_bit_position~7 0xc0 2.68538e+06 0.175781; - spi_bit_position~8 0xc0 2.61135e+06 0.175781; - spi_bit_position~9 0xc0 3.13917e+06 0.175781; - spi_stage[0] 0xc0 7.68002e+06 0.5; - spi_stage[1] 0xc0 7.68002e+06 0.5; - spi_stage[2] 0xc0 7.68002e+06 0.5; - spi_stage[5] 0xc0 7.68002e+06 0.5; - spi_stage~0 0xc0 2.88563e+06 0.4375; - spi_stage~1 0xc0 1.68181e+06 0.292969; - spi_stage~2 0xc0 2.33626e+06 0.5; - spi_stage~3 0xc0 849326 0.09375; - spi_stage~4 0xc0 1.53563e+06 0.1875; - spi_stage~5 0xc0 1.83e+06 0.125; - spi_stage~6 0xc0 771682 0.0937958; - spi_stage~7 0xc0 382.029 0.000488281; - spi_stage~8 0xc0 631699 0.0937958; - FLASH_C 0xc0 7.68002e+06 0.5; - FLASH_C~output 0xc0 7.68002e+06 0.5; - FLASH_MISO 0x30 4.91521e+07 0.5; - FLASH_MISO~input 0xc0 4.91521e+07 0.5; - FLASH_MOSI 0xc0 7.68002e+06 0.5; - FLASH_MOSI~output 0xc0 7.68002e+06 0.5; - FLASH_S 0xc0 7.68002e+06 0.5; - FLASH_S~output 0xc0 7.68002e+06 0.5; - LPF_1 0xc0 3.125e+06 0.5; - LPF_1~output 0xc0 3.125e+06 0.5; - LPF_2 0xc0 3.125e+06 0.5; - LPF_2~output 0xc0 3.125e+06 0.5; - LPF_3 0xc0 3.125e+06 0.5; - LPF_3~output 0xc0 3.125e+06 0.5; - MAIN_PLL:MAIN_PLL; - altpll:altpll_component; - MAIN_PLL_altpll:auto_generated; - wire_pll1_clk[0] 0xc 2.45761e+07 0.5; - wire_pll1_clk[0]~clkctrl 0xc0 2.45761e+07 0.5; - wire_pll1_clk[1] 0xc 96000.2 0.5; - wire_pll1_clk[1]~clkctrl 0xc0 96000.2 0.5; - wire_pll1_fbout 0xc0 0 0; - PREAMP 0xc0 3.125e+06 0.5; - PREAMP~output 0xc0 3.125e+06 0.5; - rx_cic:RX_CIC_I; - rx_cic_cic_ii_0:cic_ii_0; - alt_cic_core:core; - auk_dspip_avalon_streaming_controller:avalon_controller; - auk_dspip_avalon_streaming_small_fifo:ready_FIFO; - Decoder0~0 0xc0 381380 0.0512695; - Decoder0~1 0xc0 381380 0.0512695; - Decoder0~2 0xc0 381380 0.0512695; - Equal2~0 0xc0 2.28001e+06 0.125; - Equal3~0 0xc0 2.28001e+06 0.125; - fifo_array[0][0] 0xc0 7.68002e+06 0.5; - fifo_array[1][0] 0xc0 7.68002e+06 0.5; - fifo_array[2][0] 0xc0 7.68002e+06 0.5; - fifo_array[3][0] 0xc0 7.68002e+06 0.5; - fifo_array[4][0] 0xc0 7.68002e+06 0.5; - fifo_array[5][0] 0xc0 7.68002e+06 0.5; - fifo_array~0 0xc0 4.45098e+06 0.512817; - fifo_array~1 0xc0 4.45098e+06 0.512817; - fifo_array~2 0xc0 4.38394e+06 0.512817; - fifo_array~3 0xc0 4.52249e+06 0.512817; - fifo_array~4 0xc0 4.38394e+06 0.512817; - fifo_array~5 0xc0 4.52249e+06 0.512817; - fifo_usedw[0] 0xc0 7.68002e+06 0.5; - fifo_usedw[1] 0xc0 7.68002e+06 0.5; - fifo_usedw[2] 0xc0 7.68002e+06 0.5; - fifo_usedw~0 0xc0 5.74689e+06 0.28125; - fifo_usedw~1 0xc0 5.51361e+06 0.437378; - fifo_usedw~2 0xc0 3.65549e+06 0.5; - fifo_usedw~3 0xc0 1.57283e+06 0.123047; - fifo_usedw~4 0xc0 6.46394e+06 0.5; - Mux0~0 0xc0 2.66251e+06 0.5; - Mux0~1 0xc0 3.65603e+06 0.5; - rd_addr_ptr[0] 0xc0 7.68002e+06 0.5; - rd_addr_ptr[1] 0xc0 7.68002e+06 0.5; - rd_addr_ptr[2] 0xc0 7.68002e+06 0.5; - rd_addr_ptr~0 0xc0 2.62152e+06 0.472656; - rd_addr_ptr~1 0xc0 3.7789e+06 0.5; - rd_addr_ptr~2 0xc0 3.82782e+06 0.472656; - usedw_process~0 0xc0 1.47068e+06 0.109375; - usedw_process~1 0xc0 655312 0.794922; - wr_addr_ptr[0] 0xc0 7.68002e+06 0.5; - wr_addr_ptr[1] 0xc0 7.68002e+06 0.5; - wr_addr_ptr[2] 0xc0 7.68002e+06 0.5; - wr_addr_ptr~0 0xc0 6.23347e+06 0.5; - wr_addr_ptr~1 0xc0 2.1416e+06 0.474365; - wr_addr_ptr~2 0xc0 2.1416e+06 0.474365; - ready_fifo_rdreq~0 0xc0 1.1761e+06 0.78125; - ready_fifo_wrreq~0 0xc0 2.21546e+06 0.234375; - sink_ready_ctrl~0 0xc0 4.32001e+06 0.25; - sink_ready_ctrl~1 0xc0 3.90001e+06 0.5; - sink_ready_ctrl~2 0xc0 1.94926e+06 0.234375; - sink_ready_ctrl~3 0xc0 573034 0.106445; - stall_reg 0xc0 7.68002e+06 0.5; - stall_reg~0 0xc0 1.83e+06 0.875; - alt_cic_dec_siso:dec_one; - Equal2~0 0xc0 804377 0.0625; - Equal2~1 0xc0 4.32001e+06 0.25; - comb~0 0xc0 8.82612e+06 0.53125; - auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84]~feeder 0xc0 7.68002e+06 0.5; - dout[0] 0xc0 7.68002e+06 0.5; - dout[0]~85 0xc0 7.68002e+06 0.5; - dout[0]~86 0xc0 4.32001e+06 0.75; - dout[1] 0xc0 7.68002e+06 0.5; - dout[1]~87 0xc0 6.48002e+06 0.5; - dout[1]~88 0xc0 3.57751e+06 0.375; - dout[2] 0xc0 7.68002e+06 0.5; - dout[2]~89 0xc0 5.48439e+06 0.5; - dout[2]~90 0xc0 4.2122e+06 0.5625; - dout[3] 0xc0 7.68002e+06 0.5; - dout[3]~91 0xc0 5.44056e+06 0.5; - dout[3]~92 0xc0 5.69779e+06 0.46875; - dout[4] 0xc0 7.68002e+06 0.5; - dout[4]~93 0xc0 5.76133e+06 0.5; - dout[4]~94 0xc0 5.02005e+06 0.515625; - dout[5] 0xc0 7.68002e+06 0.5; - dout[5]~95 0xc0 5.57924e+06 0.5; - dout[5]~96 0xc0 5.32697e+06 0.492188; - dout[6] 0xc0 7.68002e+06 0.5; - dout[6]~97 0xc0 5.65281e+06 0.5; - dout[6]~98 0xc0 5.1595e+06 0.503906; - dout[7] 0xc0 7.68002e+06 0.5; - dout[7]~99 0xc0 5.61015e+06 0.5; - dout[7]~100 0xc0 5.23898e+06 0.498047; - dout[8] 0xc0 7.68002e+06 0.5; - dout[8]~101 0xc0 5.62982e+06 0.5; - dout[8]~102 0xc0 5.19808e+06 0.500977; - dout[9] 0xc0 7.68002e+06 0.5; - dout[9]~103 0xc0 5.61955e+06 0.5; - dout[9]~104 0xc0 5.21823e+06 0.499512; - dout[10] 0xc0 7.68002e+06 0.5; - dout[10]~105 0xc0 5.62457e+06 0.5; - dout[10]~106 0xc0 5.20808e+06 0.500244; - dout[11] 0xc0 7.68002e+06 0.5; - dout[11]~107 0xc0 5.62203e+06 0.5; - dout[11]~108 0xc0 5.21313e+06 0.499878; - dout[12] 0xc0 7.68002e+06 0.5; - dout[12]~109 0xc0 5.62329e+06 0.5; - dout[12]~110 0xc0 5.2106e+06 0.500061; - dout[13] 0xc0 7.68002e+06 0.5; - dout[13]~111 0xc0 5.62266e+06 0.5; - dout[13]~112 0xc0 5.21186e+06 0.499969; - dout[14] 0xc0 7.68002e+06 0.5; - dout[14]~113 0xc0 5.62298e+06 0.5; - dout[14]~114 0xc0 5.21123e+06 0.500015; - dout[15] 0xc0 7.68002e+06 0.5; - dout[15]~115 0xc0 5.62282e+06 0.5; - dout[15]~116 0xc0 5.21155e+06 0.499992; - dout[16] 0xc0 7.68002e+06 0.5; - dout[16]~117 0xc0 5.6229e+06 0.5; - dout[16]~118 0xc0 5.21139e+06 0.500004; - dout[17] 0xc0 7.68002e+06 0.5; - dout[17]~119 0xc0 5.62286e+06 0.5; - dout[17]~120 0xc0 5.21147e+06 0.499998; - dout[18] 0xc0 7.68002e+06 0.5; - dout[18]~121 0xc0 5.62288e+06 0.5; - dout[18]~122 0xc0 5.21143e+06 0.500001; - dout[19] 0xc0 7.68002e+06 0.5; - dout[19]~123 0xc0 5.62287e+06 0.5; - dout[19]~124 0xc0 5.21145e+06 0.5; - dout[20] 0xc0 7.68002e+06 0.5; - dout[20]~125 0xc0 5.62287e+06 0.5; - dout[20]~126 0xc0 5.21144e+06 0.5; - dout[21] 0xc0 7.68002e+06 0.5; - dout[21]~127 0xc0 5.62287e+06 0.5; - dout[21]~128 0xc0 5.21144e+06 0.5; - dout[22] 0xc0 7.68002e+06 0.5; - dout[22]~129 0xc0 5.62287e+06 0.5; - dout[22]~130 0xc0 5.21144e+06 0.5; - dout[23] 0xc0 7.68002e+06 0.5; - dout[23]~131 0xc0 5.62287e+06 0.5; - dout[23]~132 0xc0 5.21144e+06 0.5; - dout[24] 0xc0 7.68002e+06 0.5; - dout[24]~133 0xc0 5.62287e+06 0.5; - dout[24]~134 0xc0 5.21144e+06 0.5; - dout[25] 0xc0 7.68002e+06 0.5; - dout[25]~135 0xc0 5.62287e+06 0.5; - dout[25]~136 0xc0 5.21144e+06 0.5; - dout[26] 0xc0 7.68002e+06 0.5; - dout[26]~137 0xc0 5.62287e+06 0.5; - dout[26]~138 0xc0 5.21144e+06 0.5; - dout[27] 0xc0 7.68002e+06 0.5; - dout[27]~139 0xc0 5.62287e+06 0.5; - dout[27]~140 0xc0 5.21144e+06 0.5; - dout[28] 0xc0 7.68002e+06 0.5; - dout[28]~141 0xc0 5.62287e+06 0.5; - dout[28]~142 0xc0 5.21144e+06 0.5; - dout[29] 0xc0 7.68002e+06 0.5; - dout[29]~143 0xc0 5.62287e+06 0.5; - dout[29]~144 0xc0 5.21144e+06 0.5; - dout[30] 0xc0 7.68002e+06 0.5; - dout[30]~145 0xc0 5.62287e+06 0.5; - dout[30]~146 0xc0 5.21144e+06 0.5; - dout[31] 0xc0 7.68002e+06 0.5; - dout[31]~147 0xc0 5.62287e+06 0.5; - dout[31]~148 0xc0 5.21144e+06 0.5; - dout[32] 0xc0 7.68002e+06 0.5; - dout[32]~149 0xc0 5.62287e+06 0.5; - dout[32]~150 0xc0 5.21144e+06 0.5; - dout[33] 0xc0 7.68002e+06 0.5; - dout[33]~151 0xc0 5.62287e+06 0.5; - dout[33]~152 0xc0 5.21144e+06 0.5; - dout[34] 0xc0 7.68002e+06 0.5; - dout[34]~153 0xc0 5.62287e+06 0.5; - dout[34]~154 0xc0 5.21144e+06 0.5; - dout[35] 0xc0 7.68002e+06 0.5; - dout[35]~155 0xc0 5.62287e+06 0.5; - dout[35]~156 0xc0 5.21144e+06 0.5; - dout[36] 0xc0 7.68002e+06 0.5; - dout[36]~157 0xc0 5.62287e+06 0.5; - dout[36]~158 0xc0 5.21144e+06 0.5; - dout[37] 0xc0 7.68002e+06 0.5; - dout[37]~159 0xc0 5.62287e+06 0.5; - dout[37]~160 0xc0 5.21144e+06 0.5; - dout[38] 0xc0 7.68002e+06 0.5; - dout[38]~161 0xc0 5.62287e+06 0.5; - dout[38]~162 0xc0 5.21144e+06 0.5; - dout[39] 0xc0 7.68002e+06 0.5; - dout[39]~163 0xc0 5.62287e+06 0.5; - dout[39]~164 0xc0 5.21144e+06 0.5; - dout[40] 0xc0 7.68002e+06 0.5; - dout[40]~165 0xc0 5.62287e+06 0.5; - dout[40]~166 0xc0 5.21144e+06 0.5; - dout[41] 0xc0 7.68002e+06 0.5; - dout[41]~167 0xc0 5.62287e+06 0.5; - dout[41]~168 0xc0 5.21144e+06 0.5; - dout[42] 0xc0 7.68002e+06 0.5; - dout[42]~169 0xc0 5.62287e+06 0.5; - dout[42]~170 0xc0 5.21144e+06 0.5; - dout[43] 0xc0 7.68002e+06 0.5; - dout[43]~171 0xc0 5.62287e+06 0.5; - dout[43]~172 0xc0 5.21144e+06 0.5; - dout[44] 0xc0 7.68002e+06 0.5; - dout[44]~173 0xc0 5.62287e+06 0.5; - dout[44]~174 0xc0 5.21144e+06 0.5; - dout[45] 0xc0 7.68002e+06 0.5; - dout[45]~175 0xc0 5.62287e+06 0.5; - dout[45]~176 0xc0 5.21144e+06 0.5; - dout[46] 0xc0 7.68002e+06 0.5; - dout[46]~177 0xc0 5.62287e+06 0.5; - dout[46]~178 0xc0 5.21144e+06 0.5; - dout[47] 0xc0 7.68002e+06 0.5; - dout[47]~179 0xc0 5.62287e+06 0.5; - dout[47]~180 0xc0 5.21144e+06 0.5; - dout[48] 0xc0 7.68002e+06 0.5; - dout[48]~181 0xc0 5.62287e+06 0.5; - dout[48]~182 0xc0 5.21144e+06 0.5; - dout[49] 0xc0 7.68002e+06 0.5; - dout[49]~183 0xc0 5.62287e+06 0.5; - dout[49]~184 0xc0 5.21144e+06 0.5; - dout[50] 0xc0 7.68002e+06 0.5; - dout[50]~185 0xc0 5.62287e+06 0.5; - dout[50]~186 0xc0 5.21144e+06 0.5; - dout[51] 0xc0 7.68002e+06 0.5; - dout[51]~187 0xc0 5.62287e+06 0.5; - dout[51]~188 0xc0 5.21144e+06 0.5; - dout[52] 0xc0 7.68002e+06 0.5; - dout[52]~189 0xc0 5.62287e+06 0.5; - dout[52]~190 0xc0 5.21144e+06 0.5; - dout[53] 0xc0 7.68002e+06 0.5; - dout[53]~191 0xc0 5.62287e+06 0.5; - dout[53]~192 0xc0 5.21144e+06 0.5; - dout[54] 0xc0 7.68002e+06 0.5; - dout[54]~194 0xc0 5.62287e+06 0.5; - dout[54]~195 0xc0 5.21144e+06 0.5; - dout[55] 0xc0 7.68002e+06 0.5; - dout[55]~196 0xc0 5.62287e+06 0.5; - dout[55]~197 0xc0 5.21144e+06 0.5; - dout[56] 0xc0 7.68002e+06 0.5; - dout[56]~198 0xc0 5.62287e+06 0.5; - dout[56]~199 0xc0 5.21144e+06 0.5; - dout[57] 0xc0 7.68002e+06 0.5; - dout[57]~200 0xc0 5.62287e+06 0.5; - dout[57]~201 0xc0 5.21144e+06 0.5; - dout[58] 0xc0 7.68002e+06 0.5; - dout[58]~202 0xc0 5.62287e+06 0.5; - dout[58]~203 0xc0 5.21144e+06 0.5; - dout[59] 0xc0 7.68002e+06 0.5; - dout[59]~204 0xc0 5.62287e+06 0.5; - dout[59]~205 0xc0 5.21144e+06 0.5; - dout[60] 0xc0 7.68002e+06 0.5; - dout[60]~206 0xc0 5.62287e+06 0.5; - dout[60]~207 0xc0 5.21144e+06 0.5; - dout[61] 0xc0 7.68002e+06 0.5; - dout[61]~208 0xc0 5.62287e+06 0.5; - dout[61]~209 0xc0 5.21144e+06 0.5; - dout[62] 0xc0 7.68002e+06 0.5; - dout[62]~210 0xc0 5.62287e+06 0.5; - dout[62]~211 0xc0 5.21144e+06 0.5; - dout[63] 0xc0 7.68002e+06 0.5; - dout[63]~212 0xc0 5.62287e+06 0.5; - dout[63]~213 0xc0 5.21144e+06 0.5; - dout[64] 0xc0 7.68002e+06 0.5; - dout[64]~214 0xc0 5.62287e+06 0.5; - dout[64]~215 0xc0 5.21144e+06 0.5; - dout[65] 0xc0 7.68002e+06 0.5; - dout[65]~216 0xc0 5.62287e+06 0.5; - dout[65]~217 0xc0 5.21144e+06 0.5; - dout[66] 0xc0 7.68002e+06 0.5; - dout[66]~218 0xc0 5.62287e+06 0.5; - dout[66]~219 0xc0 5.21144e+06 0.5; - dout[67] 0xc0 7.68002e+06 0.5; - dout[67]~220 0xc0 5.62287e+06 0.5; - dout[67]~221 0xc0 5.21144e+06 0.5; - dout[68] 0xc0 7.68002e+06 0.5; - dout[68]~222 0xc0 5.62287e+06 0.5; - dout[68]~223 0xc0 5.21144e+06 0.5; - dout[69] 0xc0 7.68002e+06 0.5; - dout[69]~224 0xc0 5.62287e+06 0.5; - dout[69]~225 0xc0 5.21144e+06 0.5; - dout[70] 0xc0 7.68002e+06 0.5; - dout[70]~226 0xc0 5.62287e+06 0.5; - dout[70]~227 0xc0 5.21144e+06 0.5; - dout[71] 0xc0 7.68002e+06 0.5; - dout[71]~228 0xc0 5.62287e+06 0.5; - dout[71]~229 0xc0 5.21144e+06 0.5; - dout[72] 0xc0 7.68002e+06 0.5; - dout[72]~230 0xc0 5.62287e+06 0.5; - dout[72]~231 0xc0 5.21144e+06 0.5; - dout[73] 0xc0 7.68002e+06 0.5; - dout[73]~232 0xc0 5.62287e+06 0.5; - dout[73]~233 0xc0 5.21144e+06 0.5; - dout[74] 0xc0 7.68002e+06 0.5; - dout[74]~234 0xc0 5.62287e+06 0.5; - dout[74]~235 0xc0 5.21144e+06 0.5; - dout[75] 0xc0 7.68002e+06 0.5; - dout[75]~236 0xc0 5.62287e+06 0.5; - dout[75]~237 0xc0 5.21144e+06 0.5; - dout[76] 0xc0 7.68002e+06 0.5; - dout[76]~238 0xc0 5.62287e+06 0.5; - dout[76]~239 0xc0 5.21144e+06 0.5; - dout[77] 0xc0 7.68002e+06 0.5; - dout[77]~240 0xc0 5.62287e+06 0.5; - dout[77]~241 0xc0 5.21144e+06 0.5; - dout[78] 0xc0 7.68002e+06 0.5; - dout[78]~242 0xc0 5.62287e+06 0.5; - dout[78]~243 0xc0 5.21144e+06 0.5; - dout[79] 0xc0 7.68002e+06 0.5; - dout[79]~244 0xc0 5.62287e+06 0.5; - dout[79]~245 0xc0 5.21144e+06 0.5; - dout[80] 0xc0 7.68002e+06 0.5; - dout[80]~246 0xc0 5.62287e+06 0.5; - dout[80]~247 0xc0 5.21144e+06 0.5; - dout[81] 0xc0 7.68002e+06 0.5; - dout[81]~248 0xc0 5.62287e+06 0.5; - dout[81]~249 0xc0 5.21144e+06 0.5; - dout[82] 0xc0 7.68002e+06 0.5; - dout[82]~250 0xc0 5.62287e+06 0.5; - dout[82]~251 0xc0 5.21144e+06 0.5; - dout[83] 0xc0 7.68002e+06 0.5; - dout[83]~252 0xc0 5.62287e+06 0.5; - dout[83]~253 0xc0 5.21144e+06 0.5; - dout[84] 0xc0 7.68002e+06 0.5; - dout[84]~254 0xc0 7.06288e+06 0.5; - dout_valid 0xc0 7.68002e+06 0.5; - dout_valid~0 0xc0 4.32001e+06 0.75; - dout_valid~1 0xc0 4.32001e+06 0.25; - dout~193 0xc0 3.33001e+06 0.625; - dout~256 0xc0 5.76001e+06 0.25; - auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84]~feeder 0xc0 7.68002e+06 0.5; - dout[0] 0xc0 7.68002e+06 0.5; - dout[0]~85 0xc0 7.68002e+06 0.5; - dout[0]~86 0xc0 4.32001e+06 0.75; - dout[1] 0xc0 7.68002e+06 0.5; - dout[1]~87 0xc0 6.48002e+06 0.5; - dout[1]~88 0xc0 3.57751e+06 0.375; - dout[2] 0xc0 7.68002e+06 0.5; - dout[2]~89 0xc0 5.48439e+06 0.5; - dout[2]~90 0xc0 4.2122e+06 0.5625; - dout[3] 0xc0 7.68002e+06 0.5; - dout[3]~91 0xc0 5.44056e+06 0.5; - dout[3]~92 0xc0 5.69779e+06 0.46875; - dout[4] 0xc0 7.68002e+06 0.5; - dout[4]~93 0xc0 5.76133e+06 0.5; - dout[4]~94 0xc0 5.02005e+06 0.515625; - dout[5] 0xc0 7.68002e+06 0.5; - dout[5]~95 0xc0 5.57924e+06 0.5; - dout[5]~96 0xc0 5.32697e+06 0.492188; - dout[6] 0xc0 7.68002e+06 0.5; - dout[6]~97 0xc0 5.65281e+06 0.5; - dout[6]~98 0xc0 5.1595e+06 0.503906; - dout[7] 0xc0 7.68002e+06 0.5; - dout[7]~99 0xc0 5.61015e+06 0.5; - dout[7]~100 0xc0 5.23898e+06 0.498047; - dout[8] 0xc0 7.68002e+06 0.5; - dout[8]~101 0xc0 5.62982e+06 0.5; - dout[8]~102 0xc0 5.19808e+06 0.500977; - dout[9] 0xc0 7.68002e+06 0.5; - dout[9]~103 0xc0 5.61955e+06 0.5; - dout[9]~104 0xc0 5.21823e+06 0.499512; - dout[10] 0xc0 7.68002e+06 0.5; - dout[10]~105 0xc0 5.62457e+06 0.5; - dout[10]~106 0xc0 5.20808e+06 0.500244; - dout[11] 0xc0 7.68002e+06 0.5; - dout[11]~107 0xc0 5.62203e+06 0.5; - dout[11]~108 0xc0 5.21313e+06 0.499878; - dout[12] 0xc0 7.68002e+06 0.5; - dout[12]~109 0xc0 5.62329e+06 0.5; - dout[12]~110 0xc0 5.2106e+06 0.500061; - dout[13] 0xc0 7.68002e+06 0.5; - dout[13]~111 0xc0 5.62266e+06 0.5; - dout[13]~112 0xc0 5.21186e+06 0.499969; - dout[14] 0xc0 7.68002e+06 0.5; - dout[14]~113 0xc0 5.62298e+06 0.5; - dout[14]~114 0xc0 5.21123e+06 0.500015; - dout[15] 0xc0 7.68002e+06 0.5; - dout[15]~115 0xc0 5.62282e+06 0.5; - dout[15]~116 0xc0 5.21155e+06 0.499992; - dout[16] 0xc0 7.68002e+06 0.5; - dout[16]~117 0xc0 5.6229e+06 0.5; - dout[16]~118 0xc0 5.21139e+06 0.500004; - dout[17] 0xc0 7.68002e+06 0.5; - dout[17]~119 0xc0 5.62286e+06 0.5; - dout[17]~120 0xc0 5.21147e+06 0.499998; - dout[18] 0xc0 7.68002e+06 0.5; - dout[18]~121 0xc0 5.62288e+06 0.5; - dout[18]~122 0xc0 5.21143e+06 0.500001; - dout[19] 0xc0 7.68002e+06 0.5; - dout[19]~123 0xc0 5.62287e+06 0.5; - dout[19]~124 0xc0 5.21145e+06 0.5; - dout[20] 0xc0 7.68002e+06 0.5; - dout[20]~125 0xc0 5.62287e+06 0.5; - dout[20]~126 0xc0 5.21144e+06 0.5; - dout[21] 0xc0 7.68002e+06 0.5; - dout[21]~127 0xc0 5.62287e+06 0.5; - dout[21]~128 0xc0 5.21144e+06 0.5; - dout[22] 0xc0 7.68002e+06 0.5; - dout[22]~129 0xc0 5.62287e+06 0.5; - dout[22]~130 0xc0 5.21144e+06 0.5; - dout[23] 0xc0 7.68002e+06 0.5; - dout[23]~131 0xc0 5.62287e+06 0.5; - dout[23]~132 0xc0 5.21144e+06 0.5; - dout[24] 0xc0 7.68002e+06 0.5; - dout[24]~133 0xc0 5.62287e+06 0.5; - dout[24]~134 0xc0 5.21144e+06 0.5; - dout[25] 0xc0 7.68002e+06 0.5; - dout[25]~135 0xc0 5.62287e+06 0.5; - dout[25]~136 0xc0 5.21144e+06 0.5; - dout[26] 0xc0 7.68002e+06 0.5; - dout[26]~137 0xc0 5.62287e+06 0.5; - dout[26]~138 0xc0 5.21144e+06 0.5; - dout[27] 0xc0 7.68002e+06 0.5; - dout[27]~139 0xc0 5.62287e+06 0.5; - dout[27]~140 0xc0 5.21144e+06 0.5; - dout[28] 0xc0 7.68002e+06 0.5; - dout[28]~141 0xc0 5.62287e+06 0.5; - dout[28]~142 0xc0 5.21144e+06 0.5; - dout[29] 0xc0 7.68002e+06 0.5; - dout[29]~143 0xc0 5.62287e+06 0.5; - dout[29]~144 0xc0 5.21144e+06 0.5; - dout[30] 0xc0 7.68002e+06 0.5; - dout[30]~145 0xc0 5.62287e+06 0.5; - dout[30]~146 0xc0 5.21144e+06 0.5; - dout[31] 0xc0 7.68002e+06 0.5; - dout[31]~147 0xc0 5.62287e+06 0.5; - dout[31]~148 0xc0 5.21144e+06 0.5; - dout[32] 0xc0 7.68002e+06 0.5; - dout[32]~149 0xc0 5.62287e+06 0.5; - dout[32]~150 0xc0 5.21144e+06 0.5; - dout[33] 0xc0 7.68002e+06 0.5; - dout[33]~151 0xc0 5.62287e+06 0.5; - dout[33]~152 0xc0 5.21144e+06 0.5; - dout[34] 0xc0 7.68002e+06 0.5; - dout[34]~153 0xc0 5.62287e+06 0.5; - dout[34]~154 0xc0 5.21144e+06 0.5; - dout[35] 0xc0 7.68002e+06 0.5; - dout[35]~155 0xc0 5.62287e+06 0.5; - dout[35]~156 0xc0 5.21144e+06 0.5; - dout[36] 0xc0 7.68002e+06 0.5; - dout[36]~157 0xc0 5.62287e+06 0.5; - dout[36]~158 0xc0 5.21144e+06 0.5; - dout[37] 0xc0 7.68002e+06 0.5; - dout[37]~159 0xc0 5.62287e+06 0.5; - dout[37]~160 0xc0 5.21144e+06 0.5; - dout[38] 0xc0 7.68002e+06 0.5; - dout[38]~161 0xc0 5.62287e+06 0.5; - dout[38]~162 0xc0 5.21144e+06 0.5; - dout[39] 0xc0 7.68002e+06 0.5; - dout[39]~163 0xc0 5.62287e+06 0.5; - dout[39]~164 0xc0 5.21144e+06 0.5; - dout[40] 0xc0 7.68002e+06 0.5; - dout[40]~165 0xc0 5.62287e+06 0.5; - dout[40]~166 0xc0 5.21144e+06 0.5; - dout[41] 0xc0 7.68002e+06 0.5; - dout[41]~167 0xc0 5.62287e+06 0.5; - dout[41]~168 0xc0 5.21144e+06 0.5; - dout[42] 0xc0 7.68002e+06 0.5; - dout[42]~169 0xc0 5.62287e+06 0.5; - dout[42]~170 0xc0 5.21144e+06 0.5; - dout[43] 0xc0 7.68002e+06 0.5; - dout[43]~171 0xc0 5.62287e+06 0.5; - dout[43]~172 0xc0 5.21144e+06 0.5; - dout[44] 0xc0 7.68002e+06 0.5; - dout[44]~173 0xc0 5.62287e+06 0.5; - dout[44]~174 0xc0 5.21144e+06 0.5; - dout[45] 0xc0 7.68002e+06 0.5; - dout[45]~175 0xc0 5.62287e+06 0.5; - dout[45]~176 0xc0 5.21144e+06 0.5; - dout[46] 0xc0 7.68002e+06 0.5; - dout[46]~177 0xc0 5.62287e+06 0.5; - dout[46]~178 0xc0 5.21144e+06 0.5; - dout[47] 0xc0 7.68002e+06 0.5; - dout[47]~179 0xc0 5.62287e+06 0.5; - dout[47]~180 0xc0 5.21144e+06 0.5; - dout[48] 0xc0 7.68002e+06 0.5; - dout[48]~181 0xc0 5.62287e+06 0.5; - dout[48]~182 0xc0 5.21144e+06 0.5; - dout[49] 0xc0 7.68002e+06 0.5; - dout[49]~183 0xc0 5.62287e+06 0.5; - dout[49]~184 0xc0 5.21144e+06 0.5; - dout[50] 0xc0 7.68002e+06 0.5; - dout[50]~185 0xc0 5.62287e+06 0.5; - dout[50]~186 0xc0 5.21144e+06 0.5; - dout[51] 0xc0 7.68002e+06 0.5; - dout[51]~187 0xc0 5.62287e+06 0.5; - dout[51]~188 0xc0 5.21144e+06 0.5; - dout[52] 0xc0 7.68002e+06 0.5; - dout[52]~189 0xc0 5.62287e+06 0.5; - dout[52]~190 0xc0 5.21144e+06 0.5; - dout[53] 0xc0 7.68002e+06 0.5; - dout[53]~191 0xc0 5.62287e+06 0.5; - dout[53]~192 0xc0 5.21144e+06 0.5; - dout[54] 0xc0 7.68002e+06 0.5; - dout[54]~194 0xc0 5.62287e+06 0.5; - dout[54]~195 0xc0 5.21144e+06 0.5; - dout[55] 0xc0 7.68002e+06 0.5; - dout[55]~196 0xc0 5.62287e+06 0.5; - dout[55]~197 0xc0 5.21144e+06 0.5; - dout[56] 0xc0 7.68002e+06 0.5; - dout[56]~198 0xc0 5.62287e+06 0.5; - dout[56]~199 0xc0 5.21144e+06 0.5; - dout[57] 0xc0 7.68002e+06 0.5; - dout[57]~200 0xc0 5.62287e+06 0.5; - dout[57]~201 0xc0 5.21144e+06 0.5; - dout[58] 0xc0 7.68002e+06 0.5; - dout[58]~202 0xc0 5.62287e+06 0.5; - dout[58]~203 0xc0 5.21144e+06 0.5; - dout[59] 0xc0 7.68002e+06 0.5; - dout[59]~204 0xc0 5.62287e+06 0.5; - dout[59]~205 0xc0 5.21144e+06 0.5; - dout[60] 0xc0 7.68002e+06 0.5; - dout[60]~206 0xc0 5.62287e+06 0.5; - dout[60]~207 0xc0 5.21144e+06 0.5; - dout[61] 0xc0 7.68002e+06 0.5; - dout[61]~208 0xc0 5.62287e+06 0.5; - dout[61]~209 0xc0 5.21144e+06 0.5; - dout[62] 0xc0 7.68002e+06 0.5; - dout[62]~210 0xc0 5.62287e+06 0.5; - dout[62]~211 0xc0 5.21144e+06 0.5; - dout[63] 0xc0 7.68002e+06 0.5; - dout[63]~212 0xc0 5.62287e+06 0.5; - dout[63]~213 0xc0 5.21144e+06 0.5; - dout[64] 0xc0 7.68002e+06 0.5; - dout[64]~214 0xc0 5.62287e+06 0.5; - dout[64]~215 0xc0 5.21144e+06 0.5; - dout[65] 0xc0 7.68002e+06 0.5; - dout[65]~216 0xc0 5.62287e+06 0.5; - dout[65]~217 0xc0 5.21144e+06 0.5; - dout[66] 0xc0 7.68002e+06 0.5; - dout[66]~218 0xc0 5.62287e+06 0.5; - dout[66]~219 0xc0 5.21144e+06 0.5; - dout[67] 0xc0 7.68002e+06 0.5; - dout[67]~220 0xc0 5.62287e+06 0.5; - dout[67]~221 0xc0 5.21144e+06 0.5; - dout[68] 0xc0 7.68002e+06 0.5; - dout[68]~222 0xc0 5.62287e+06 0.5; - dout[68]~223 0xc0 5.21144e+06 0.5; - dout[69] 0xc0 7.68002e+06 0.5; - dout[69]~224 0xc0 5.62287e+06 0.5; - dout[69]~225 0xc0 5.21144e+06 0.5; - dout[70] 0xc0 7.68002e+06 0.5; - dout[70]~226 0xc0 5.62287e+06 0.5; - dout[70]~227 0xc0 5.21144e+06 0.5; - dout[71] 0xc0 7.68002e+06 0.5; - dout[71]~228 0xc0 5.62287e+06 0.5; - dout[71]~229 0xc0 5.21144e+06 0.5; - dout[72] 0xc0 7.68002e+06 0.5; - dout[72]~230 0xc0 5.62287e+06 0.5; - dout[72]~231 0xc0 5.21144e+06 0.5; - dout[73] 0xc0 7.68002e+06 0.5; - dout[73]~232 0xc0 5.62287e+06 0.5; - dout[73]~233 0xc0 5.21144e+06 0.5; - dout[74] 0xc0 7.68002e+06 0.5; - dout[74]~234 0xc0 5.62287e+06 0.5; - dout[74]~235 0xc0 5.21144e+06 0.5; - dout[75] 0xc0 7.68002e+06 0.5; - dout[75]~236 0xc0 5.62287e+06 0.5; - dout[75]~237 0xc0 5.21144e+06 0.5; - dout[76] 0xc0 7.68002e+06 0.5; - dout[76]~238 0xc0 5.62287e+06 0.5; - dout[76]~239 0xc0 5.21144e+06 0.5; - dout[77] 0xc0 7.68002e+06 0.5; - dout[77]~240 0xc0 5.62287e+06 0.5; - dout[77]~241 0xc0 5.21144e+06 0.5; - dout[78] 0xc0 7.68002e+06 0.5; - dout[78]~242 0xc0 5.62287e+06 0.5; - dout[78]~243 0xc0 5.21144e+06 0.5; - dout[79] 0xc0 7.68002e+06 0.5; - dout[79]~244 0xc0 5.62287e+06 0.5; - dout[79]~245 0xc0 5.21144e+06 0.5; - dout[80] 0xc0 7.68002e+06 0.5; - dout[80]~246 0xc0 5.62287e+06 0.5; - dout[80]~247 0xc0 5.21144e+06 0.5; - dout[81] 0xc0 7.68002e+06 0.5; - dout[81]~248 0xc0 5.62287e+06 0.5; - dout[81]~249 0xc0 5.21144e+06 0.5; - dout[82] 0xc0 7.68002e+06 0.5; - dout[82]~250 0xc0 5.62287e+06 0.5; - dout[82]~251 0xc0 5.21144e+06 0.5; - dout[83] 0xc0 7.68002e+06 0.5; - dout[83]~252 0xc0 5.62287e+06 0.5; - dout[83]~253 0xc0 5.21144e+06 0.5; - dout[84] 0xc0 7.68002e+06 0.5; - dout[84]~254 0xc0 5.62287e+06 0.5; - dout_valid 0xc0 7.68002e+06 0.5; - dout_valid~0 0xc0 4.32001e+06 0.25; - dout~193 0xc0 3.33001e+06 0.625; - dout~256 0xc0 5.76001e+06 0.25; - auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84]~feeder 0xc0 7.68002e+06 0.5; - dout[0] 0xc0 7.68002e+06 0.5; - dout[0]~85 0xc0 7.68002e+06 0.5; - dout[0]~86 0xc0 4.32001e+06 0.75; - dout[1] 0xc0 7.68002e+06 0.5; - dout[1]~87 0xc0 6.48002e+06 0.5; - dout[1]~88 0xc0 3.57751e+06 0.375; - dout[2] 0xc0 7.68002e+06 0.5; - dout[2]~89 0xc0 5.48439e+06 0.5; - dout[2]~90 0xc0 4.2122e+06 0.5625; - dout[3] 0xc0 7.68002e+06 0.5; - dout[3]~91 0xc0 5.44056e+06 0.5; - dout[3]~92 0xc0 5.69779e+06 0.46875; - dout[4] 0xc0 7.68002e+06 0.5; - dout[4]~93 0xc0 5.76133e+06 0.5; - dout[4]~94 0xc0 5.02005e+06 0.515625; - dout[5] 0xc0 7.68002e+06 0.5; - dout[5]~95 0xc0 5.57924e+06 0.5; - dout[5]~96 0xc0 5.32697e+06 0.492188; - dout[6] 0xc0 7.68002e+06 0.5; - dout[6]~97 0xc0 5.65281e+06 0.5; - dout[6]~98 0xc0 5.1595e+06 0.503906; - dout[7] 0xc0 7.68002e+06 0.5; - dout[7]~99 0xc0 5.61015e+06 0.5; - dout[7]~100 0xc0 5.23898e+06 0.498047; - dout[8] 0xc0 7.68002e+06 0.5; - dout[8]~101 0xc0 5.62982e+06 0.5; - dout[8]~102 0xc0 5.19808e+06 0.500977; - dout[9] 0xc0 7.68002e+06 0.5; - dout[9]~103 0xc0 5.61955e+06 0.5; - dout[9]~104 0xc0 5.21823e+06 0.499512; - dout[10] 0xc0 7.68002e+06 0.5; - dout[10]~105 0xc0 5.62457e+06 0.5; - dout[10]~106 0xc0 5.20808e+06 0.500244; - dout[11] 0xc0 7.68002e+06 0.5; - dout[11]~107 0xc0 5.62203e+06 0.5; - dout[11]~108 0xc0 5.21313e+06 0.499878; - dout[12] 0xc0 7.68002e+06 0.5; - dout[12]~109 0xc0 5.62329e+06 0.5; - dout[12]~110 0xc0 5.2106e+06 0.500061; - dout[13] 0xc0 7.68002e+06 0.5; - dout[13]~111 0xc0 5.62266e+06 0.5; - dout[13]~112 0xc0 5.21186e+06 0.499969; - dout[14] 0xc0 7.68002e+06 0.5; - dout[14]~113 0xc0 5.62298e+06 0.5; - dout[14]~114 0xc0 5.21123e+06 0.500015; - dout[15] 0xc0 7.68002e+06 0.5; - dout[15]~115 0xc0 5.62282e+06 0.5; - dout[15]~116 0xc0 5.21155e+06 0.499992; - dout[16] 0xc0 7.68002e+06 0.5; - dout[16]~117 0xc0 5.6229e+06 0.5; - dout[16]~118 0xc0 5.21139e+06 0.500004; - dout[17] 0xc0 7.68002e+06 0.5; - dout[17]~119 0xc0 5.62286e+06 0.5; - dout[17]~120 0xc0 5.21147e+06 0.499998; - dout[18] 0xc0 7.68002e+06 0.5; - dout[18]~121 0xc0 5.62288e+06 0.5; - dout[18]~122 0xc0 5.21143e+06 0.500001; - dout[19] 0xc0 7.68002e+06 0.5; - dout[19]~123 0xc0 5.62287e+06 0.5; - dout[19]~124 0xc0 5.21145e+06 0.5; - dout[20] 0xc0 7.68002e+06 0.5; - dout[20]~125 0xc0 5.62287e+06 0.5; - dout[20]~126 0xc0 5.21144e+06 0.5; - dout[21] 0xc0 7.68002e+06 0.5; - dout[21]~127 0xc0 5.62287e+06 0.5; - dout[21]~128 0xc0 5.21144e+06 0.5; - dout[22] 0xc0 7.68002e+06 0.5; - dout[22]~129 0xc0 5.62287e+06 0.5; - dout[22]~130 0xc0 5.21144e+06 0.5; - dout[23] 0xc0 7.68002e+06 0.5; - dout[23]~131 0xc0 5.62287e+06 0.5; - dout[23]~132 0xc0 5.21144e+06 0.5; - dout[24] 0xc0 7.68002e+06 0.5; - dout[24]~133 0xc0 5.62287e+06 0.5; - dout[24]~134 0xc0 5.21144e+06 0.5; - dout[25] 0xc0 7.68002e+06 0.5; - dout[25]~135 0xc0 5.62287e+06 0.5; - dout[25]~136 0xc0 5.21144e+06 0.5; - dout[26] 0xc0 7.68002e+06 0.5; - dout[26]~137 0xc0 5.62287e+06 0.5; - dout[26]~138 0xc0 5.21144e+06 0.5; - dout[27] 0xc0 7.68002e+06 0.5; - dout[27]~139 0xc0 5.62287e+06 0.5; - dout[27]~140 0xc0 5.21144e+06 0.5; - dout[28] 0xc0 7.68002e+06 0.5; - dout[28]~141 0xc0 5.62287e+06 0.5; - dout[28]~142 0xc0 5.21144e+06 0.5; - dout[29] 0xc0 7.68002e+06 0.5; - dout[29]~143 0xc0 5.62287e+06 0.5; - dout[29]~144 0xc0 5.21144e+06 0.5; - dout[30] 0xc0 7.68002e+06 0.5; - dout[30]~145 0xc0 5.62287e+06 0.5; - dout[30]~146 0xc0 5.21144e+06 0.5; - dout[31] 0xc0 7.68002e+06 0.5; - dout[31]~147 0xc0 5.62287e+06 0.5; - dout[31]~148 0xc0 5.21144e+06 0.5; - dout[32] 0xc0 7.68002e+06 0.5; - dout[32]~149 0xc0 5.62287e+06 0.5; - dout[32]~150 0xc0 5.21144e+06 0.5; - dout[33] 0xc0 7.68002e+06 0.5; - dout[33]~151 0xc0 5.62287e+06 0.5; - dout[33]~152 0xc0 5.21144e+06 0.5; - dout[34] 0xc0 7.68002e+06 0.5; - dout[34]~153 0xc0 5.62287e+06 0.5; - dout[34]~154 0xc0 5.21144e+06 0.5; - dout[35] 0xc0 7.68002e+06 0.5; - dout[35]~155 0xc0 5.62287e+06 0.5; - dout[35]~156 0xc0 5.21144e+06 0.5; - dout[36] 0xc0 7.68002e+06 0.5; - dout[36]~157 0xc0 5.62287e+06 0.5; - dout[36]~158 0xc0 5.21144e+06 0.5; - dout[37] 0xc0 7.68002e+06 0.5; - dout[37]~159 0xc0 5.62287e+06 0.5; - dout[37]~160 0xc0 5.21144e+06 0.5; - dout[38] 0xc0 7.68002e+06 0.5; - dout[38]~161 0xc0 5.62287e+06 0.5; - dout[38]~162 0xc0 5.21144e+06 0.5; - dout[39] 0xc0 7.68002e+06 0.5; - dout[39]~163 0xc0 5.62287e+06 0.5; - dout[39]~164 0xc0 5.21144e+06 0.5; - dout[40] 0xc0 7.68002e+06 0.5; - dout[40]~165 0xc0 5.62287e+06 0.5; - dout[40]~166 0xc0 5.21144e+06 0.5; - dout[41] 0xc0 7.68002e+06 0.5; - dout[41]~167 0xc0 5.62287e+06 0.5; - dout[41]~168 0xc0 5.21144e+06 0.5; - dout[42] 0xc0 7.68002e+06 0.5; - dout[42]~169 0xc0 5.62287e+06 0.5; - dout[42]~170 0xc0 5.21144e+06 0.5; - dout[43] 0xc0 7.68002e+06 0.5; - dout[43]~171 0xc0 5.62287e+06 0.5; - dout[43]~172 0xc0 5.21144e+06 0.5; - dout[44] 0xc0 7.68002e+06 0.5; - dout[44]~173 0xc0 5.62287e+06 0.5; - dout[44]~174 0xc0 5.21144e+06 0.5; - dout[45] 0xc0 7.68002e+06 0.5; - dout[45]~175 0xc0 5.62287e+06 0.5; - dout[45]~176 0xc0 5.21144e+06 0.5; - dout[46] 0xc0 7.68002e+06 0.5; - dout[46]~177 0xc0 5.62287e+06 0.5; - dout[46]~178 0xc0 5.21144e+06 0.5; - dout[47] 0xc0 7.68002e+06 0.5; - dout[47]~179 0xc0 5.62287e+06 0.5; - dout[47]~180 0xc0 5.21144e+06 0.5; - dout[48] 0xc0 7.68002e+06 0.5; - dout[48]~181 0xc0 5.62287e+06 0.5; - dout[48]~182 0xc0 5.21144e+06 0.5; - dout[49] 0xc0 7.68002e+06 0.5; - dout[49]~183 0xc0 5.62287e+06 0.5; - dout[49]~184 0xc0 5.21144e+06 0.5; - dout[50] 0xc0 7.68002e+06 0.5; - dout[50]~185 0xc0 5.62287e+06 0.5; - dout[50]~186 0xc0 5.21144e+06 0.5; - dout[51] 0xc0 7.68002e+06 0.5; - dout[51]~187 0xc0 5.62287e+06 0.5; - dout[51]~188 0xc0 5.21144e+06 0.5; - dout[52] 0xc0 7.68002e+06 0.5; - dout[52]~189 0xc0 5.62287e+06 0.5; - dout[52]~190 0xc0 5.21144e+06 0.5; - dout[53] 0xc0 7.68002e+06 0.5; - dout[53]~191 0xc0 5.62287e+06 0.5; - dout[53]~192 0xc0 5.21144e+06 0.5; - dout[54] 0xc0 7.68002e+06 0.5; - dout[54]~194 0xc0 5.62287e+06 0.5; - dout[54]~195 0xc0 5.21144e+06 0.5; - dout[55] 0xc0 7.68002e+06 0.5; - dout[55]~196 0xc0 5.62287e+06 0.5; - dout[55]~197 0xc0 5.21144e+06 0.5; - dout[56] 0xc0 7.68002e+06 0.5; - dout[56]~198 0xc0 5.62287e+06 0.5; - dout[56]~199 0xc0 5.21144e+06 0.5; - dout[57] 0xc0 7.68002e+06 0.5; - dout[57]~200 0xc0 5.62287e+06 0.5; - dout[57]~201 0xc0 5.21144e+06 0.5; - dout[58] 0xc0 7.68002e+06 0.5; - dout[58]~202 0xc0 5.62287e+06 0.5; - dout[58]~203 0xc0 5.21144e+06 0.5; - dout[59] 0xc0 7.68002e+06 0.5; - dout[59]~204 0xc0 5.62287e+06 0.5; - dout[59]~205 0xc0 5.21144e+06 0.5; - dout[60] 0xc0 7.68002e+06 0.5; - dout[60]~206 0xc0 5.62287e+06 0.5; - dout[60]~207 0xc0 5.21144e+06 0.5; - dout[61] 0xc0 7.68002e+06 0.5; - dout[61]~208 0xc0 5.62287e+06 0.5; - dout[61]~209 0xc0 5.21144e+06 0.5; - dout[62] 0xc0 7.68002e+06 0.5; - dout[62]~210 0xc0 5.62287e+06 0.5; - dout[62]~211 0xc0 5.21144e+06 0.5; - dout[63] 0xc0 7.68002e+06 0.5; - dout[63]~212 0xc0 5.62287e+06 0.5; - dout[63]~213 0xc0 5.21144e+06 0.5; - dout[64] 0xc0 7.68002e+06 0.5; - dout[64]~214 0xc0 5.62287e+06 0.5; - dout[64]~215 0xc0 5.21144e+06 0.5; - dout[65] 0xc0 7.68002e+06 0.5; - dout[65]~216 0xc0 5.62287e+06 0.5; - dout[65]~217 0xc0 5.21144e+06 0.5; - dout[66] 0xc0 7.68002e+06 0.5; - dout[66]~218 0xc0 5.62287e+06 0.5; - dout[66]~219 0xc0 5.21144e+06 0.5; - dout[67] 0xc0 7.68002e+06 0.5; - dout[67]~220 0xc0 5.62287e+06 0.5; - dout[67]~221 0xc0 5.21144e+06 0.5; - dout[68] 0xc0 7.68002e+06 0.5; - dout[68]~222 0xc0 5.62287e+06 0.5; - dout[68]~223 0xc0 5.21144e+06 0.5; - dout[69] 0xc0 7.68002e+06 0.5; - dout[69]~224 0xc0 5.62287e+06 0.5; - dout[69]~225 0xc0 5.21144e+06 0.5; - dout[70] 0xc0 7.68002e+06 0.5; - dout[70]~226 0xc0 5.62287e+06 0.5; - dout[70]~227 0xc0 5.21144e+06 0.5; - dout[71] 0xc0 7.68002e+06 0.5; - dout[71]~228 0xc0 5.62287e+06 0.5; - dout[71]~229 0xc0 5.21144e+06 0.5; - dout[72] 0xc0 7.68002e+06 0.5; - dout[72]~230 0xc0 5.62287e+06 0.5; - dout[72]~231 0xc0 5.21144e+06 0.5; - dout[73] 0xc0 7.68002e+06 0.5; - dout[73]~232 0xc0 5.62287e+06 0.5; - dout[73]~233 0xc0 5.21144e+06 0.5; - dout[74] 0xc0 7.68002e+06 0.5; - dout[74]~234 0xc0 5.62287e+06 0.5; - dout[74]~235 0xc0 5.21144e+06 0.5; - dout[75] 0xc0 7.68002e+06 0.5; - dout[75]~236 0xc0 5.62287e+06 0.5; - dout[75]~237 0xc0 5.21144e+06 0.5; - dout[76] 0xc0 7.68002e+06 0.5; - dout[76]~238 0xc0 5.62287e+06 0.5; - dout[76]~239 0xc0 5.21144e+06 0.5; - dout[77] 0xc0 7.68002e+06 0.5; - dout[77]~240 0xc0 5.62287e+06 0.5; - dout[77]~241 0xc0 5.21144e+06 0.5; - dout[78] 0xc0 7.68002e+06 0.5; - dout[78]~242 0xc0 5.62287e+06 0.5; - dout[78]~243 0xc0 5.21144e+06 0.5; - dout[79] 0xc0 7.68002e+06 0.5; - dout[79]~244 0xc0 5.62287e+06 0.5; - dout[79]~245 0xc0 5.21144e+06 0.5; - dout[80] 0xc0 7.68002e+06 0.5; - dout[80]~246 0xc0 5.62287e+06 0.5; - dout[80]~247 0xc0 5.21144e+06 0.5; - dout[81] 0xc0 7.68002e+06 0.5; - dout[81]~248 0xc0 5.62287e+06 0.5; - dout[81]~249 0xc0 5.21144e+06 0.5; - dout[82] 0xc0 7.68002e+06 0.5; - dout[82]~250 0xc0 5.62287e+06 0.5; - dout[82]~251 0xc0 5.21144e+06 0.5; - dout[83] 0xc0 7.68002e+06 0.5; - dout[83]~252 0xc0 5.62287e+06 0.5; - dout[83]~253 0xc0 5.21144e+06 0.5; - dout[84] 0xc0 7.68002e+06 0.5; - dout[84]~254 0xc0 5.62287e+06 0.5; - dout_valid 0xc0 7.68002e+06 0.5; - dout_valid~0 0xc0 4.32001e+06 0.25; - dout~193 0xc0 3.33001e+06 0.625; - dout~256 0xc0 5.76001e+06 0.25; - auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84] 0xc0 7.68002e+06 0.5; - dout[0] 0xc0 7.68002e+06 0.5; - dout[0]~85 0xc0 7.68002e+06 0.5; - dout[0]~86 0xc0 4.32001e+06 0.75; - dout[1] 0xc0 7.68002e+06 0.5; - dout[1]~87 0xc0 6.48002e+06 0.5; - dout[1]~88 0xc0 3.57751e+06 0.375; - dout[2] 0xc0 7.68002e+06 0.5; - dout[2]~89 0xc0 5.48439e+06 0.5; - dout[2]~90 0xc0 4.2122e+06 0.5625; - dout[3] 0xc0 7.68002e+06 0.5; - dout[3]~91 0xc0 5.44056e+06 0.5; - dout[3]~92 0xc0 5.69779e+06 0.46875; - dout[4] 0xc0 7.68002e+06 0.5; - dout[4]~93 0xc0 5.76133e+06 0.5; - dout[4]~94 0xc0 5.02005e+06 0.515625; - dout[5] 0xc0 7.68002e+06 0.5; - dout[5]~95 0xc0 5.57924e+06 0.5; - dout[5]~96 0xc0 5.32697e+06 0.492188; - dout[6] 0xc0 7.68002e+06 0.5; - dout[6]~97 0xc0 5.65281e+06 0.5; - dout[6]~98 0xc0 5.1595e+06 0.503906; - dout[7] 0xc0 7.68002e+06 0.5; - dout[7]~99 0xc0 5.61015e+06 0.5; - dout[7]~100 0xc0 5.23898e+06 0.498047; - dout[8] 0xc0 7.68002e+06 0.5; - dout[8]~101 0xc0 5.62982e+06 0.5; - dout[8]~102 0xc0 5.19808e+06 0.500977; - dout[9] 0xc0 7.68002e+06 0.5; - dout[9]~103 0xc0 5.61955e+06 0.5; - dout[9]~104 0xc0 5.21823e+06 0.499512; - dout[10] 0xc0 7.68002e+06 0.5; - dout[10]~105 0xc0 5.62457e+06 0.5; - dout[10]~106 0xc0 5.20808e+06 0.500244; - dout[11] 0xc0 7.68002e+06 0.5; - dout[11]~107 0xc0 5.62203e+06 0.5; - dout[11]~108 0xc0 5.21313e+06 0.499878; - dout[12] 0xc0 7.68002e+06 0.5; - dout[12]~109 0xc0 5.62329e+06 0.5; - dout[12]~110 0xc0 5.2106e+06 0.500061; - dout[13] 0xc0 7.68002e+06 0.5; - dout[13]~111 0xc0 5.62266e+06 0.5; - dout[13]~112 0xc0 5.21186e+06 0.499969; - dout[14] 0xc0 7.68002e+06 0.5; - dout[14]~113 0xc0 5.62298e+06 0.5; - dout[14]~114 0xc0 5.21123e+06 0.500015; - dout[15] 0xc0 7.68002e+06 0.5; - dout[15]~115 0xc0 5.62282e+06 0.5; - dout[15]~116 0xc0 5.21155e+06 0.499992; - dout[16] 0xc0 7.68002e+06 0.5; - dout[16]~117 0xc0 5.6229e+06 0.5; - dout[16]~118 0xc0 5.21139e+06 0.500004; - dout[17] 0xc0 7.68002e+06 0.5; - dout[17]~119 0xc0 5.62286e+06 0.5; - dout[17]~120 0xc0 5.21147e+06 0.499998; - dout[18] 0xc0 7.68002e+06 0.5; - dout[18]~121 0xc0 5.62288e+06 0.5; - dout[18]~122 0xc0 5.21143e+06 0.500001; - dout[19] 0xc0 7.68002e+06 0.5; - dout[19]~123 0xc0 5.62287e+06 0.5; - dout[19]~124 0xc0 5.21145e+06 0.5; - dout[20] 0xc0 7.68002e+06 0.5; - dout[20]~125 0xc0 5.62287e+06 0.5; - dout[20]~126 0xc0 5.21144e+06 0.5; - dout[21] 0xc0 7.68002e+06 0.5; - dout[21]~127 0xc0 5.62287e+06 0.5; - dout[21]~128 0xc0 5.21144e+06 0.5; - dout[22] 0xc0 7.68002e+06 0.5; - dout[22]~129 0xc0 5.62287e+06 0.5; - dout[22]~130 0xc0 5.21144e+06 0.5; - dout[23] 0xc0 7.68002e+06 0.5; - dout[23]~131 0xc0 5.62287e+06 0.5; - dout[23]~132 0xc0 5.21144e+06 0.5; - dout[24] 0xc0 7.68002e+06 0.5; - dout[24]~133 0xc0 5.62287e+06 0.5; - dout[24]~134 0xc0 5.21144e+06 0.5; - dout[25] 0xc0 7.68002e+06 0.5; - dout[25]~135 0xc0 5.62287e+06 0.5; - dout[25]~136 0xc0 5.21144e+06 0.5; - dout[26] 0xc0 7.68002e+06 0.5; - dout[26]~137 0xc0 5.62287e+06 0.5; - dout[26]~138 0xc0 5.21144e+06 0.5; - dout[27] 0xc0 7.68002e+06 0.5; - dout[27]~139 0xc0 5.62287e+06 0.5; - dout[27]~140 0xc0 5.21144e+06 0.5; - dout[28] 0xc0 7.68002e+06 0.5; - dout[28]~141 0xc0 5.62287e+06 0.5; - dout[28]~142 0xc0 5.21144e+06 0.5; - dout[29] 0xc0 7.68002e+06 0.5; - dout[29]~143 0xc0 5.62287e+06 0.5; - dout[29]~144 0xc0 5.21144e+06 0.5; - dout[30] 0xc0 7.68002e+06 0.5; - dout[30]~145 0xc0 5.62287e+06 0.5; - dout[30]~146 0xc0 5.21144e+06 0.5; - dout[31] 0xc0 7.68002e+06 0.5; - dout[31]~147 0xc0 5.62287e+06 0.5; - dout[31]~148 0xc0 5.21144e+06 0.5; - dout[32] 0xc0 7.68002e+06 0.5; - dout[32]~149 0xc0 5.62287e+06 0.5; - dout[32]~150 0xc0 5.21144e+06 0.5; - dout[33] 0xc0 7.68002e+06 0.5; - dout[33]~151 0xc0 5.62287e+06 0.5; - dout[33]~152 0xc0 5.21144e+06 0.5; - dout[34] 0xc0 7.68002e+06 0.5; - dout[34]~153 0xc0 5.62287e+06 0.5; - dout[34]~154 0xc0 5.21144e+06 0.5; - dout[35] 0xc0 7.68002e+06 0.5; - dout[35]~155 0xc0 5.62287e+06 0.5; - dout[35]~156 0xc0 5.21144e+06 0.5; - dout[36] 0xc0 7.68002e+06 0.5; - dout[36]~157 0xc0 5.62287e+06 0.5; - dout[36]~158 0xc0 5.21144e+06 0.5; - dout[37] 0xc0 7.68002e+06 0.5; - dout[37]~159 0xc0 5.62287e+06 0.5; - dout[37]~160 0xc0 5.21144e+06 0.5; - dout[38] 0xc0 7.68002e+06 0.5; - dout[38]~161 0xc0 5.62287e+06 0.5; - dout[38]~162 0xc0 5.21144e+06 0.5; - dout[39] 0xc0 7.68002e+06 0.5; - dout[39]~163 0xc0 5.62287e+06 0.5; - dout[39]~164 0xc0 5.21144e+06 0.5; - dout[40] 0xc0 7.68002e+06 0.5; - dout[40]~165 0xc0 5.62287e+06 0.5; - dout[40]~166 0xc0 5.21144e+06 0.5; - dout[41] 0xc0 7.68002e+06 0.5; - dout[41]~167 0xc0 5.62287e+06 0.5; - dout[41]~168 0xc0 5.21144e+06 0.5; - dout[42] 0xc0 7.68002e+06 0.5; - dout[42]~169 0xc0 5.62287e+06 0.5; - dout[42]~170 0xc0 5.21144e+06 0.5; - dout[43] 0xc0 7.68002e+06 0.5; - dout[43]~171 0xc0 5.62287e+06 0.5; - dout[43]~172 0xc0 5.21144e+06 0.5; - dout[44] 0xc0 7.68002e+06 0.5; - dout[44]~173 0xc0 5.62287e+06 0.5; - dout[44]~174 0xc0 5.21144e+06 0.5; - dout[45] 0xc0 7.68002e+06 0.5; - dout[45]~175 0xc0 5.62287e+06 0.5; - dout[45]~176 0xc0 5.21144e+06 0.5; - dout[46] 0xc0 7.68002e+06 0.5; - dout[46]~177 0xc0 5.62287e+06 0.5; - dout[46]~178 0xc0 5.21144e+06 0.5; - dout[47] 0xc0 7.68002e+06 0.5; - dout[47]~179 0xc0 5.62287e+06 0.5; - dout[47]~180 0xc0 5.21144e+06 0.5; - dout[48] 0xc0 7.68002e+06 0.5; - dout[48]~181 0xc0 5.62287e+06 0.5; - dout[48]~182 0xc0 5.21144e+06 0.5; - dout[49] 0xc0 7.68002e+06 0.5; - dout[49]~183 0xc0 5.62287e+06 0.5; - dout[49]~184 0xc0 5.21144e+06 0.5; - dout[50] 0xc0 7.68002e+06 0.5; - dout[50]~185 0xc0 5.62287e+06 0.5; - dout[50]~186 0xc0 5.21144e+06 0.5; - dout[51] 0xc0 7.68002e+06 0.5; - dout[51]~187 0xc0 5.62287e+06 0.5; - dout[51]~188 0xc0 5.21144e+06 0.5; - dout[52] 0xc0 7.68002e+06 0.5; - dout[52]~189 0xc0 5.62287e+06 0.5; - dout[52]~190 0xc0 5.21144e+06 0.5; - dout[53] 0xc0 7.68002e+06 0.5; - dout[53]~191 0xc0 5.62287e+06 0.5; - dout[53]~192 0xc0 5.21144e+06 0.5; - dout[54] 0xc0 7.68002e+06 0.5; - dout[54]~194 0xc0 5.62287e+06 0.5; - dout[54]~195 0xc0 5.21144e+06 0.5; - dout[55] 0xc0 7.68002e+06 0.5; - dout[55]~196 0xc0 5.62287e+06 0.5; - dout[55]~197 0xc0 5.21144e+06 0.5; - dout[56] 0xc0 7.68002e+06 0.5; - dout[56]~198 0xc0 5.62287e+06 0.5; - dout[56]~199 0xc0 5.21144e+06 0.5; - dout[57] 0xc0 7.68002e+06 0.5; - dout[57]~200 0xc0 5.62287e+06 0.5; - dout[57]~201 0xc0 5.21144e+06 0.5; - dout[58] 0xc0 7.68002e+06 0.5; - dout[58]~202 0xc0 5.62287e+06 0.5; - dout[58]~203 0xc0 5.21144e+06 0.5; - dout[59] 0xc0 7.68002e+06 0.5; - dout[59]~204 0xc0 5.62287e+06 0.5; - dout[59]~205 0xc0 5.21144e+06 0.5; - dout[60] 0xc0 7.68002e+06 0.5; - dout[60]~206 0xc0 5.62287e+06 0.5; - dout[60]~207 0xc0 5.21144e+06 0.5; - dout[61] 0xc0 7.68002e+06 0.5; - dout[61]~208 0xc0 5.62287e+06 0.5; - dout[61]~209 0xc0 5.21144e+06 0.5; - dout[62] 0xc0 7.68002e+06 0.5; - dout[62]~210 0xc0 5.62287e+06 0.5; - dout[62]~211 0xc0 5.21144e+06 0.5; - dout[63] 0xc0 7.68002e+06 0.5; - dout[63]~212 0xc0 5.62287e+06 0.5; - dout[63]~213 0xc0 5.21144e+06 0.5; - dout[64] 0xc0 7.68002e+06 0.5; - dout[64]~214 0xc0 5.62287e+06 0.5; - dout[64]~215 0xc0 5.21144e+06 0.5; - dout[65] 0xc0 7.68002e+06 0.5; - dout[65]~216 0xc0 5.62287e+06 0.5; - dout[65]~217 0xc0 5.21144e+06 0.5; - dout[66] 0xc0 7.68002e+06 0.5; - dout[66]~218 0xc0 5.62287e+06 0.5; - dout[66]~219 0xc0 5.21144e+06 0.5; - dout[67] 0xc0 7.68002e+06 0.5; - dout[67]~220 0xc0 5.62287e+06 0.5; - dout[67]~221 0xc0 5.21144e+06 0.5; - dout[68] 0xc0 7.68002e+06 0.5; - dout[68]~222 0xc0 5.62287e+06 0.5; - dout[68]~223 0xc0 5.21144e+06 0.5; - dout[69] 0xc0 7.68002e+06 0.5; - dout[69]~224 0xc0 5.62287e+06 0.5; - dout[69]~225 0xc0 5.21144e+06 0.5; - dout[70] 0xc0 7.68002e+06 0.5; - dout[70]~226 0xc0 5.62287e+06 0.5; - dout[70]~227 0xc0 5.21144e+06 0.5; - dout[71] 0xc0 7.68002e+06 0.5; - dout[71]~228 0xc0 5.62287e+06 0.5; - dout[71]~229 0xc0 5.21144e+06 0.5; - dout[72] 0xc0 7.68002e+06 0.5; - dout[72]~230 0xc0 5.62287e+06 0.5; - dout[72]~231 0xc0 5.21144e+06 0.5; - dout[73] 0xc0 7.68002e+06 0.5; - dout[73]~232 0xc0 5.62287e+06 0.5; - dout[73]~233 0xc0 5.21144e+06 0.5; - dout[74] 0xc0 7.68002e+06 0.5; - dout[74]~234 0xc0 5.62287e+06 0.5; - dout[74]~235 0xc0 5.21144e+06 0.5; - dout[75] 0xc0 7.68002e+06 0.5; - dout[75]~236 0xc0 5.62287e+06 0.5; - dout[75]~237 0xc0 5.21144e+06 0.5; - dout[76] 0xc0 7.68002e+06 0.5; - dout[76]~238 0xc0 5.62287e+06 0.5; - dout[76]~239 0xc0 5.21144e+06 0.5; - dout[77] 0xc0 7.68002e+06 0.5; - dout[77]~240 0xc0 5.62287e+06 0.5; - dout[77]~241 0xc0 5.21144e+06 0.5; - dout[78] 0xc0 7.68002e+06 0.5; - dout[78]~242 0xc0 5.62287e+06 0.5; - dout[78]~243 0xc0 5.21144e+06 0.5; - dout[79] 0xc0 7.68002e+06 0.5; - dout[79]~244 0xc0 5.62287e+06 0.5; - dout[79]~245 0xc0 5.21144e+06 0.5; - dout[80] 0xc0 7.68002e+06 0.5; - dout[80]~246 0xc0 5.62287e+06 0.5; - dout[80]~247 0xc0 5.21144e+06 0.5; - dout[81] 0xc0 7.68002e+06 0.5; - dout[81]~248 0xc0 5.62287e+06 0.5; - dout[81]~249 0xc0 5.21144e+06 0.5; - dout[82] 0xc0 7.68002e+06 0.5; - dout[82]~250 0xc0 5.62287e+06 0.5; - dout[82]~251 0xc0 5.21144e+06 0.5; - dout[83] 0xc0 7.68002e+06 0.5; - dout[83]~252 0xc0 5.62287e+06 0.5; - dout[83]~253 0xc0 5.21144e+06 0.5; - dout[84] 0xc0 7.68002e+06 0.5; - dout[84]~254 0xc0 5.62287e+06 0.5; - dout_valid 0xc0 7.68002e+06 0.5; - dout_valid~0 0xc0 4.32001e+06 0.25; - dout~193 0xc0 3.33001e+06 0.625; - dout~256 0xc0 5.76001e+06 0.25; - auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84] 0xc0 7.68002e+06 0.5; - dout[0] 0xc0 7.68002e+06 0.5; - dout[0]~85 0xc0 7.68002e+06 0.5; - dout[0]~86 0xc0 4.32001e+06 0.75; - dout[1] 0xc0 7.68002e+06 0.5; - dout[1]~87 0xc0 6.48002e+06 0.5; - dout[1]~88 0xc0 3.57751e+06 0.375; - dout[2] 0xc0 7.68002e+06 0.5; - dout[2]~89 0xc0 5.48439e+06 0.5; - dout[2]~90 0xc0 4.2122e+06 0.5625; - dout[3] 0xc0 7.68002e+06 0.5; - dout[3]~91 0xc0 5.44056e+06 0.5; - dout[3]~92 0xc0 5.69779e+06 0.46875; - dout[4] 0xc0 7.68002e+06 0.5; - dout[4]~93 0xc0 5.76133e+06 0.5; - dout[4]~94 0xc0 5.02005e+06 0.515625; - dout[5] 0xc0 7.68002e+06 0.5; - dout[5]~95 0xc0 5.57924e+06 0.5; - dout[5]~96 0xc0 5.32697e+06 0.492188; - dout[6] 0xc0 7.68002e+06 0.5; - dout[6]~97 0xc0 5.65281e+06 0.5; - dout[6]~98 0xc0 5.1595e+06 0.503906; - dout[7] 0xc0 7.68002e+06 0.5; - dout[7]~99 0xc0 5.61015e+06 0.5; - dout[7]~100 0xc0 5.23898e+06 0.498047; - dout[8] 0xc0 7.68002e+06 0.5; - dout[8]~101 0xc0 5.62982e+06 0.5; - dout[8]~102 0xc0 5.19808e+06 0.500977; - dout[9] 0xc0 7.68002e+06 0.5; - dout[9]~103 0xc0 5.61955e+06 0.5; - dout[9]~104 0xc0 5.21823e+06 0.499512; - dout[10] 0xc0 7.68002e+06 0.5; - dout[10]~105 0xc0 5.62457e+06 0.5; - dout[10]~106 0xc0 5.20808e+06 0.500244; - dout[11] 0xc0 7.68002e+06 0.5; - dout[11]~107 0xc0 5.62203e+06 0.5; - dout[11]~108 0xc0 5.21313e+06 0.499878; - dout[12] 0xc0 7.68002e+06 0.5; - dout[12]~109 0xc0 5.62329e+06 0.5; - dout[12]~110 0xc0 5.2106e+06 0.500061; - dout[13] 0xc0 7.68002e+06 0.5; - dout[13]~111 0xc0 5.62266e+06 0.5; - dout[13]~112 0xc0 5.21186e+06 0.499969; - dout[14] 0xc0 7.68002e+06 0.5; - dout[14]~113 0xc0 5.62298e+06 0.5; - dout[14]~114 0xc0 5.21123e+06 0.500015; - dout[15] 0xc0 7.68002e+06 0.5; - dout[15]~115 0xc0 5.62282e+06 0.5; - dout[15]~116 0xc0 5.21155e+06 0.499992; - dout[16] 0xc0 7.68002e+06 0.5; - dout[16]~117 0xc0 5.6229e+06 0.5; - dout[16]~118 0xc0 5.21139e+06 0.500004; - dout[17] 0xc0 7.68002e+06 0.5; - dout[17]~119 0xc0 5.62286e+06 0.5; - dout[17]~120 0xc0 5.21147e+06 0.499998; - dout[18] 0xc0 7.68002e+06 0.5; - dout[18]~121 0xc0 5.62288e+06 0.5; - dout[18]~122 0xc0 5.21143e+06 0.500001; - dout[19] 0xc0 7.68002e+06 0.5; - dout[19]~123 0xc0 5.62287e+06 0.5; - dout[19]~124 0xc0 5.21145e+06 0.5; - dout[20] 0xc0 7.68002e+06 0.5; - dout[20]~125 0xc0 5.62287e+06 0.5; - dout[20]~126 0xc0 5.21144e+06 0.5; - dout[21] 0xc0 7.68002e+06 0.5; - dout[21]~127 0xc0 5.62287e+06 0.5; - dout[21]~128 0xc0 5.21144e+06 0.5; - dout[22] 0xc0 7.68002e+06 0.5; - dout[22]~129 0xc0 5.62287e+06 0.5; - dout[22]~130 0xc0 5.21144e+06 0.5; - dout[23] 0xc0 7.68002e+06 0.5; - dout[23]~131 0xc0 5.62287e+06 0.5; - dout[23]~132 0xc0 5.21144e+06 0.5; - dout[24] 0xc0 7.68002e+06 0.5; - dout[24]~133 0xc0 5.62287e+06 0.5; - dout[24]~134 0xc0 5.21144e+06 0.5; - dout[25] 0xc0 7.68002e+06 0.5; - dout[25]~135 0xc0 5.62287e+06 0.5; - dout[25]~136 0xc0 5.21144e+06 0.5; - dout[26] 0xc0 7.68002e+06 0.5; - dout[26]~137 0xc0 5.62287e+06 0.5; - dout[26]~138 0xc0 5.21144e+06 0.5; - dout[27] 0xc0 7.68002e+06 0.5; - dout[27]~139 0xc0 5.62287e+06 0.5; - dout[27]~140 0xc0 5.21144e+06 0.5; - dout[28] 0xc0 7.68002e+06 0.5; - dout[28]~141 0xc0 5.62287e+06 0.5; - dout[28]~142 0xc0 5.21144e+06 0.5; - dout[29] 0xc0 7.68002e+06 0.5; - dout[29]~143 0xc0 5.62287e+06 0.5; - dout[29]~144 0xc0 5.21144e+06 0.5; - dout[30] 0xc0 7.68002e+06 0.5; - dout[30]~145 0xc0 5.62287e+06 0.5; - dout[30]~146 0xc0 5.21144e+06 0.5; - dout[31] 0xc0 7.68002e+06 0.5; - dout[31]~147 0xc0 5.62287e+06 0.5; - dout[31]~148 0xc0 5.21144e+06 0.5; - dout[32] 0xc0 7.68002e+06 0.5; - dout[32]~149 0xc0 5.62287e+06 0.5; - dout[32]~150 0xc0 5.21144e+06 0.5; - dout[33] 0xc0 7.68002e+06 0.5; - dout[33]~151 0xc0 5.62287e+06 0.5; - dout[33]~152 0xc0 5.21144e+06 0.5; - dout[34] 0xc0 7.68002e+06 0.5; - dout[34]~153 0xc0 5.62287e+06 0.5; - dout[34]~154 0xc0 5.21144e+06 0.5; - dout[35] 0xc0 7.68002e+06 0.5; - dout[35]~155 0xc0 5.62287e+06 0.5; - dout[35]~156 0xc0 5.21144e+06 0.5; - dout[36] 0xc0 7.68002e+06 0.5; - dout[36]~157 0xc0 5.62287e+06 0.5; - dout[36]~158 0xc0 5.21144e+06 0.5; - dout[37] 0xc0 7.68002e+06 0.5; - dout[37]~159 0xc0 5.62287e+06 0.5; - dout[37]~160 0xc0 5.21144e+06 0.5; - dout[38] 0xc0 7.68002e+06 0.5; - dout[38]~161 0xc0 5.62287e+06 0.5; - dout[38]~162 0xc0 5.21144e+06 0.5; - dout[39] 0xc0 7.68002e+06 0.5; - dout[39]~163 0xc0 5.62287e+06 0.5; - dout[39]~164 0xc0 5.21144e+06 0.5; - dout[40] 0xc0 7.68002e+06 0.5; - dout[40]~165 0xc0 5.62287e+06 0.5; - dout[40]~166 0xc0 5.21144e+06 0.5; - dout[41] 0xc0 7.68002e+06 0.5; - dout[41]~167 0xc0 5.62287e+06 0.5; - dout[41]~168 0xc0 5.21144e+06 0.5; - dout[42] 0xc0 7.68002e+06 0.5; - dout[42]~169 0xc0 5.62287e+06 0.5; - dout[42]~170 0xc0 5.21144e+06 0.5; - dout[43] 0xc0 7.68002e+06 0.5; - dout[43]~171 0xc0 5.62287e+06 0.5; - dout[43]~172 0xc0 5.21144e+06 0.5; - dout[44] 0xc0 7.68002e+06 0.5; - dout[44]~173 0xc0 5.62287e+06 0.5; - dout[44]~174 0xc0 5.21144e+06 0.5; - dout[45] 0xc0 7.68002e+06 0.5; - dout[45]~175 0xc0 5.62287e+06 0.5; - dout[45]~176 0xc0 5.21144e+06 0.5; - dout[46] 0xc0 7.68002e+06 0.5; - dout[46]~177 0xc0 5.62287e+06 0.5; - dout[46]~178 0xc0 5.21144e+06 0.5; - dout[47] 0xc0 7.68002e+06 0.5; - dout[47]~179 0xc0 5.62287e+06 0.5; - dout[47]~180 0xc0 5.21144e+06 0.5; - dout[48] 0xc0 7.68002e+06 0.5; - dout[48]~181 0xc0 5.62287e+06 0.5; - dout[48]~182 0xc0 5.21144e+06 0.5; - dout[49] 0xc0 7.68002e+06 0.5; - dout[49]~183 0xc0 5.62287e+06 0.5; - dout[49]~184 0xc0 5.21144e+06 0.5; - dout[50] 0xc0 7.68002e+06 0.5; - dout[50]~185 0xc0 5.62287e+06 0.5; - dout[50]~186 0xc0 5.21144e+06 0.5; - dout[51] 0xc0 7.68002e+06 0.5; - dout[51]~187 0xc0 5.62287e+06 0.5; - dout[51]~188 0xc0 5.21144e+06 0.5; - dout[52] 0xc0 7.68002e+06 0.5; - dout[52]~189 0xc0 5.62287e+06 0.5; - dout[52]~190 0xc0 5.21144e+06 0.5; - dout[53] 0xc0 7.68002e+06 0.5; - dout[53]~191 0xc0 5.62287e+06 0.5; - dout[53]~192 0xc0 5.21144e+06 0.5; - dout[54] 0xc0 7.68002e+06 0.5; - dout[54]~194 0xc0 5.62287e+06 0.5; - dout[54]~195 0xc0 5.21144e+06 0.5; - dout[55] 0xc0 7.68002e+06 0.5; - dout[55]~196 0xc0 5.62287e+06 0.5; - dout[55]~197 0xc0 5.21144e+06 0.5; - dout[56] 0xc0 7.68002e+06 0.5; - dout[56]~198 0xc0 5.62287e+06 0.5; - dout[56]~199 0xc0 5.21144e+06 0.5; - dout[57] 0xc0 7.68002e+06 0.5; - dout[57]~200 0xc0 5.62287e+06 0.5; - dout[57]~201 0xc0 5.21144e+06 0.5; - dout[58] 0xc0 7.68002e+06 0.5; - dout[58]~202 0xc0 5.62287e+06 0.5; - dout[58]~203 0xc0 5.21144e+06 0.5; - dout[59] 0xc0 7.68002e+06 0.5; - dout[59]~204 0xc0 5.62287e+06 0.5; - dout[59]~205 0xc0 5.21144e+06 0.5; - dout[60] 0xc0 7.68002e+06 0.5; - dout[60]~206 0xc0 5.62287e+06 0.5; - dout[60]~207 0xc0 5.21144e+06 0.5; - dout[61] 0xc0 7.68002e+06 0.5; - dout[61]~208 0xc0 5.62287e+06 0.5; - dout[61]~209 0xc0 5.21144e+06 0.5; - dout[62] 0xc0 7.68002e+06 0.5; - dout[62]~210 0xc0 5.62287e+06 0.5; - dout[62]~211 0xc0 5.21144e+06 0.5; - dout[63] 0xc0 7.68002e+06 0.5; - dout[63]~212 0xc0 5.62287e+06 0.5; - dout[63]~213 0xc0 5.21144e+06 0.5; - dout[64] 0xc0 7.68002e+06 0.5; - dout[64]~214 0xc0 5.62287e+06 0.5; - dout[64]~215 0xc0 5.21144e+06 0.5; - dout[65] 0xc0 7.68002e+06 0.5; - dout[65]~216 0xc0 5.62287e+06 0.5; - dout[65]~217 0xc0 5.21144e+06 0.5; - dout[66] 0xc0 7.68002e+06 0.5; - dout[66]~218 0xc0 5.62287e+06 0.5; - dout[66]~219 0xc0 5.21144e+06 0.5; - dout[67] 0xc0 7.68002e+06 0.5; - dout[67]~220 0xc0 5.62287e+06 0.5; - dout[67]~221 0xc0 5.21144e+06 0.5; - dout[68] 0xc0 7.68002e+06 0.5; - dout[68]~222 0xc0 5.62287e+06 0.5; - dout[68]~223 0xc0 5.21144e+06 0.5; - dout[69] 0xc0 7.68002e+06 0.5; - dout[69]~224 0xc0 5.62287e+06 0.5; - dout[69]~225 0xc0 5.21144e+06 0.5; - dout[70] 0xc0 7.68002e+06 0.5; - dout[70]~226 0xc0 5.62287e+06 0.5; - dout[70]~227 0xc0 5.21144e+06 0.5; - dout[71] 0xc0 7.68002e+06 0.5; - dout[71]~228 0xc0 5.62287e+06 0.5; - dout[71]~229 0xc0 5.21144e+06 0.5; - dout[72] 0xc0 7.68002e+06 0.5; - dout[72]~230 0xc0 5.62287e+06 0.5; - dout[72]~231 0xc0 5.21144e+06 0.5; - dout[73] 0xc0 7.68002e+06 0.5; - dout[73]~232 0xc0 5.62287e+06 0.5; - dout[73]~233 0xc0 5.21144e+06 0.5; - dout[74] 0xc0 7.68002e+06 0.5; - dout[74]~234 0xc0 5.62287e+06 0.5; - dout[74]~235 0xc0 5.21144e+06 0.5; - dout[75] 0xc0 7.68002e+06 0.5; - dout[75]~236 0xc0 5.62287e+06 0.5; - dout[75]~237 0xc0 5.21144e+06 0.5; - dout[76] 0xc0 7.68002e+06 0.5; - dout[76]~238 0xc0 5.62287e+06 0.5; - dout[76]~239 0xc0 5.21144e+06 0.5; - dout[77] 0xc0 7.68002e+06 0.5; - dout[77]~240 0xc0 5.62287e+06 0.5; - dout[77]~241 0xc0 5.21144e+06 0.5; - dout[78] 0xc0 7.68002e+06 0.5; - dout[78]~242 0xc0 5.62287e+06 0.5; - dout[78]~243 0xc0 5.21144e+06 0.5; - dout[79] 0xc0 7.68002e+06 0.5; - dout[79]~244 0xc0 5.62287e+06 0.5; - dout[79]~245 0xc0 5.21144e+06 0.5; - dout[80] 0xc0 7.68002e+06 0.5; - dout[80]~246 0xc0 5.62287e+06 0.5; - dout[80]~247 0xc0 5.21144e+06 0.5; - dout[81] 0xc0 7.68002e+06 0.5; - dout[81]~248 0xc0 5.62287e+06 0.5; - dout[81]~249 0xc0 5.21144e+06 0.5; - dout[82] 0xc0 7.68002e+06 0.5; - dout[82]~250 0xc0 5.62287e+06 0.5; - dout[82]~251 0xc0 5.21144e+06 0.5; - dout[83] 0xc0 7.68002e+06 0.5; - dout[83]~252 0xc0 5.62287e+06 0.5; - dout[83]~253 0xc0 5.21144e+06 0.5; - dout[84] 0xc0 7.68002e+06 0.5; - dout[84]~254 0xc0 7.06288e+06 0.5; - dout_valid 0xc0 7.68002e+06 0.5; - dout_valid~0 0xc0 4.32001e+06 0.25; - dout~193 0xc0 3.33001e+06 0.625; - dout~256 0xc0 5.76001e+06 0.25; - auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84] 0xc0 7.68002e+06 0.5; - dout[53] 0xc0 7.68002e+06 0.5; - dout[53]~33 0xc0 4.32001e+06 0.75; - dout[53]~35 0xc0 3.57751e+06 0.375; - dout[53]~37 0xc0 4.2122e+06 0.5625; - dout[53]~39 0xc0 5.69779e+06 0.46875; - dout[53]~41 0xc0 5.02005e+06 0.515625; - dout[53]~43 0xc0 5.32697e+06 0.492188; - dout[53]~45 0xc0 5.1595e+06 0.503906; - dout[53]~47 0xc0 5.23898e+06 0.498047; - dout[53]~49 0xc0 5.19808e+06 0.500977; - dout[53]~51 0xc0 5.21823e+06 0.499512; - dout[53]~53 0xc0 5.20808e+06 0.500244; - dout[53]~55 0xc0 5.21313e+06 0.499878; - dout[53]~57 0xc0 5.2106e+06 0.500061; - dout[53]~59 0xc0 5.21186e+06 0.499969; - dout[53]~61 0xc0 5.21123e+06 0.500015; - dout[53]~63 0xc0 5.21155e+06 0.499992; - dout[53]~65 0xc0 5.21139e+06 0.500004; - dout[53]~67 0xc0 5.21147e+06 0.499998; - dout[53]~69 0xc0 5.21143e+06 0.500001; - dout[53]~71 0xc0 5.21145e+06 0.5; - dout[53]~73 0xc0 5.21144e+06 0.5; - dout[53]~75 0xc0 5.21144e+06 0.5; - dout[53]~77 0xc0 5.21144e+06 0.5; - dout[53]~79 0xc0 5.21144e+06 0.5; - dout[53]~81 0xc0 5.21144e+06 0.5; - dout[53]~83 0xc0 5.21144e+06 0.5; - dout[53]~85 0xc0 5.21144e+06 0.5; - dout[53]~87 0xc0 5.21144e+06 0.5; - dout[53]~89 0xc0 5.21144e+06 0.5; - dout[53]~91 0xc0 5.21144e+06 0.5; - dout[53]~93 0xc0 5.21144e+06 0.5; - dout[53]~95 0xc0 5.21144e+06 0.5; - dout[53]~97 0xc0 5.21144e+06 0.5; - dout[53]~99 0xc0 5.21144e+06 0.5; - dout[53]~101 0xc0 5.21144e+06 0.5; - dout[53]~103 0xc0 5.21144e+06 0.5; - dout[53]~105 0xc0 5.21144e+06 0.5; - dout[53]~107 0xc0 5.21144e+06 0.5; - dout[53]~109 0xc0 5.21144e+06 0.5; - dout[53]~111 0xc0 5.21144e+06 0.5; - dout[53]~113 0xc0 5.21144e+06 0.5; - dout[53]~115 0xc0 5.21144e+06 0.5; - dout[53]~117 0xc0 5.21144e+06 0.5; - dout[53]~119 0xc0 5.21144e+06 0.5; - dout[53]~121 0xc0 5.21144e+06 0.5; - dout[53]~123 0xc0 5.21144e+06 0.5; - dout[53]~125 0xc0 5.21144e+06 0.5; - dout[53]~127 0xc0 5.21144e+06 0.5; - dout[53]~129 0xc0 5.21144e+06 0.5; - dout[53]~131 0xc0 5.21144e+06 0.5; - dout[53]~133 0xc0 5.21144e+06 0.5; - dout[53]~135 0xc0 5.21144e+06 0.5; - dout[53]~137 0xc0 5.21144e+06 0.5; - dout[53]~138 0xc0 5.62287e+06 0.5; - dout[53]~139 0xc0 5.21144e+06 0.5; - dout[54] 0xc0 7.68002e+06 0.5; - dout[54]~141 0xc0 5.62287e+06 0.5; - dout[54]~142 0xc0 5.21144e+06 0.5; - dout[55] 0xc0 7.68002e+06 0.5; - dout[55]~143 0xc0 5.62287e+06 0.5; - dout[55]~144 0xc0 5.21144e+06 0.5; - dout[56] 0xc0 7.68002e+06 0.5; - dout[56]~145 0xc0 5.62287e+06 0.5; - dout[56]~146 0xc0 5.21144e+06 0.5; - dout[57] 0xc0 7.68002e+06 0.5; - dout[57]~147 0xc0 5.62287e+06 0.5; - dout[57]~148 0xc0 5.21144e+06 0.5; - dout[58] 0xc0 7.68002e+06 0.5; - dout[58]~149 0xc0 5.62287e+06 0.5; - dout[58]~150 0xc0 5.21144e+06 0.5; - dout[59] 0xc0 7.68002e+06 0.5; - dout[59]~151 0xc0 5.62287e+06 0.5; - dout[59]~152 0xc0 5.21144e+06 0.5; - dout[60] 0xc0 7.68002e+06 0.5; - dout[60]~153 0xc0 5.62287e+06 0.5; - dout[60]~154 0xc0 5.21144e+06 0.5; - dout[61] 0xc0 7.68002e+06 0.5; - dout[61]~155 0xc0 5.62287e+06 0.5; - dout[61]~156 0xc0 5.21144e+06 0.5; - dout[62] 0xc0 7.68002e+06 0.5; - dout[62]~157 0xc0 5.62287e+06 0.5; - dout[62]~158 0xc0 5.21144e+06 0.5; - dout[63] 0xc0 7.68002e+06 0.5; - dout[63]~159 0xc0 5.62287e+06 0.5; - dout[63]~160 0xc0 5.21144e+06 0.5; - dout[64] 0xc0 7.68002e+06 0.5; - dout[64]~161 0xc0 5.62287e+06 0.5; - dout[64]~162 0xc0 5.21144e+06 0.5; - dout[65] 0xc0 7.68002e+06 0.5; - dout[65]~163 0xc0 5.62287e+06 0.5; - dout[65]~164 0xc0 5.21144e+06 0.5; - dout[66] 0xc0 7.68002e+06 0.5; - dout[66]~165 0xc0 5.62287e+06 0.5; - dout[66]~166 0xc0 5.21144e+06 0.5; - dout[67] 0xc0 7.68002e+06 0.5; - dout[67]~167 0xc0 5.62287e+06 0.5; - dout[67]~168 0xc0 5.21144e+06 0.5; - dout[68] 0xc0 7.68002e+06 0.5; - dout[68]~169 0xc0 5.62287e+06 0.5; - dout[68]~170 0xc0 5.21144e+06 0.5; - dout[69] 0xc0 7.68002e+06 0.5; - dout[69]~171 0xc0 5.62287e+06 0.5; - dout[69]~172 0xc0 5.21144e+06 0.5; - dout[70] 0xc0 7.68002e+06 0.5; - dout[70]~173 0xc0 5.62287e+06 0.5; - dout[70]~174 0xc0 5.21144e+06 0.5; - dout[71] 0xc0 7.68002e+06 0.5; - dout[71]~175 0xc0 5.62287e+06 0.5; - dout[71]~176 0xc0 5.21144e+06 0.5; - dout[72] 0xc0 7.68002e+06 0.5; - dout[72]~177 0xc0 5.62287e+06 0.5; - dout[72]~178 0xc0 5.21144e+06 0.5; - dout[73] 0xc0 7.68002e+06 0.5; - dout[73]~179 0xc0 5.62287e+06 0.5; - dout[73]~180 0xc0 5.21144e+06 0.5; - dout[74] 0xc0 7.68002e+06 0.5; - dout[74]~181 0xc0 5.62287e+06 0.5; - dout[74]~182 0xc0 5.21144e+06 0.5; - dout[75] 0xc0 7.68002e+06 0.5; - dout[75]~183 0xc0 5.62287e+06 0.5; - dout[75]~184 0xc0 5.21144e+06 0.5; - dout[76] 0xc0 7.68002e+06 0.5; - dout[76]~185 0xc0 5.62287e+06 0.5; - dout[76]~186 0xc0 5.21144e+06 0.5; - dout[77] 0xc0 7.68002e+06 0.5; - dout[77]~187 0xc0 5.62287e+06 0.5; - dout[77]~188 0xc0 5.21144e+06 0.5; - dout[78] 0xc0 7.68002e+06 0.5; - dout[78]~189 0xc0 5.62287e+06 0.5; - dout[78]~190 0xc0 5.21144e+06 0.5; - dout[79] 0xc0 7.68002e+06 0.5; - dout[79]~191 0xc0 5.62287e+06 0.5; - dout[79]~192 0xc0 5.21144e+06 0.5; - dout[80] 0xc0 7.68002e+06 0.5; - dout[80]~193 0xc0 5.62287e+06 0.5; - dout[80]~194 0xc0 5.21144e+06 0.5; - dout[81] 0xc0 7.68002e+06 0.5; - dout[81]~195 0xc0 5.62287e+06 0.5; - dout[81]~196 0xc0 5.21144e+06 0.5; - dout[82] 0xc0 7.68002e+06 0.5; - dout[82]~197 0xc0 5.62287e+06 0.5; - dout[82]~198 0xc0 5.21144e+06 0.5; - dout[83] 0xc0 7.68002e+06 0.5; - dout[83]~199 0xc0 5.62287e+06 0.5; - dout[83]~200 0xc0 5.21144e+06 0.5; - dout[84] 0xc0 7.68002e+06 0.5; - dout[84]~201 0xc0 5.62287e+06 0.5; - dout_valid 0xc0 7.68002e+06 0.5; - dout_valid~0 0xc0 4.32001e+06 0.25; - dout~140 0xc0 3.33001e+06 0.625; - dout~203 0xc0 5.76001e+06 0.25; - ena_diff_s[0] 0xc0 7.68002e+06 0.5; - ena_diff_s[1] 0xc0 7.68002e+06 0.5; - ena_diff_s[1]~feeder 0xc0 5.76001e+06 0.25; - ena_diff_s~0 0xc0 6.11854e+06 0.375076; - fifo_rdreq 0xc0 7.68002e+06 0.5; - fifo_rdreq~0 0xc0 5.76001e+06 0.25; - auk_dspip_channel_buffer:fifo_regulator; - scfifo:buffer_FIFO; - scfifo_pm51:auto_generated; - a_dpfifo_4ku:dpfifo; - _~0 0xc0 1.01376e+07 0.125046; - _~1 0xc0 3.47166e+06 0.0624962; - _~2 0xc0 4.32001e+06 0.25; - _~3 0xc0 8.28646e+06 0.437513; - empty_dff 0xc0 7.68002e+06 0.5; - empty_dff~0 0xc0 4.5449e+06 0.263684; - empty_dff~1 0xc0 3.26047e+06 0.26368; - altsyncram_j7h1:FIFOram; - altsyncram:ram_block1a0; - altsyncram_lci3:auto_generated; - decode_msa:address_decoder; - w_anode19w[2]~0 0xc0 1.83e+06 0.125; - w_anode32w[2]~0 0xc0 1.83e+06 0.125; - w_anode40w[2]~0 0xc0 1.83e+06 0.125; - w_anode48w[2]~0 0xc0 1.83e+06 0.125; - address_reg[0] 0xc0 7.68002e+06 0.5; - address_reg[1] 0xc0 7.68002e+06 0.5; - address_reg[1]~feeder 0xc0 7.68002e+06 0.5; - data_reg[0] 0xc0 7.68002e+06 0.5; - data_reg[0]~feeder 0xc0 7.68002e+06 0.5; - data_reg[1] 0xc0 7.68002e+06 0.5; - data_reg[2] 0xc0 7.68002e+06 0.5; - data_reg[2]~feeder 0xc0 7.68002e+06 0.5; - data_reg[3] 0xc0 7.68002e+06 0.5; - data_reg[4] 0xc0 7.68002e+06 0.5; - data_reg[5] 0xc0 7.68002e+06 0.5; - data_reg[5]~feeder 0xc0 7.68002e+06 0.5; - data_reg[6] 0xc0 7.68002e+06 0.5; - data_reg[6]~feeder 0xc0 7.68002e+06 0.5; - data_reg[7] 0xc0 7.68002e+06 0.5; - data_reg[7]~feeder 0xc0 7.68002e+06 0.5; - data_reg[8] 0xc0 7.68002e+06 0.5; - data_reg[8]~feeder 0xc0 7.68002e+06 0.5; - data_reg[9] 0xc0 7.68002e+06 0.5; - data_reg[9]~feeder 0xc0 7.68002e+06 0.5; - data_reg[10] 0xc0 7.68002e+06 0.5; - data_reg[11] 0xc0 7.68002e+06 0.5; - data_reg[11]~feeder 0xc0 7.68002e+06 0.5; - data_reg[12] 0xc0 7.68002e+06 0.5; - data_reg[13] 0xc0 7.68002e+06 0.5; - data_reg[13]~feeder 0xc0 7.68002e+06 0.5; - data_reg[14] 0xc0 7.68002e+06 0.5; - data_reg[14]~feeder 0xc0 7.68002e+06 0.5; - data_reg[15] 0xc0 7.68002e+06 0.5; - data_reg[15]~feeder 0xc0 7.68002e+06 0.5; - data_reg[16] 0xc0 7.68002e+06 0.5; - data_reg[17] 0xc0 7.68002e+06 0.5; - data_reg[17]~feeder 0xc0 7.68002e+06 0.5; - data_reg[18] 0xc0 7.68002e+06 0.5; - data_reg[19] 0xc0 7.68002e+06 0.5; - data_reg[19]~feeder 0xc0 7.68002e+06 0.5; - data_reg[20] 0xc0 7.68002e+06 0.5; - data_reg[20]~feeder 0xc0 7.68002e+06 0.5; - data_reg[21] 0xc0 7.68002e+06 0.5; - data_reg[22] 0xc0 7.68002e+06 0.5; - data_reg[22]~feeder 0xc0 7.68002e+06 0.5; - data_reg[23] 0xc0 7.68002e+06 0.5; - data_reg[23]~feeder 0xc0 7.68002e+06 0.5; - data_reg[24] 0xc0 7.68002e+06 0.5; - data_reg[24]~feeder 0xc0 7.68002e+06 0.5; - data_reg[25] 0xc0 7.68002e+06 0.5; - data_reg[25]~feeder 0xc0 7.68002e+06 0.5; - data_reg[26] 0xc0 7.68002e+06 0.5; - data_reg[26]~feeder 0xc0 7.68002e+06 0.5; - data_reg[27] 0xc0 7.68002e+06 0.5; - data_reg[27]~feeder 0xc0 7.68002e+06 0.5; - data_reg[28] 0xc0 7.68002e+06 0.5; - data_reg[29] 0xc0 7.68002e+06 0.5; - data_reg[29]~feeder 0xc0 7.68002e+06 0.5; - data_reg[30] 0xc0 7.68002e+06 0.5; - data_reg[30]~feeder 0xc0 7.68002e+06 0.5; - data_reg[31] 0xc0 7.68002e+06 0.5; - data_reg[32] 0xc0 7.68002e+06 0.5; - data_reg[32]~feeder 0xc0 7.68002e+06 0.5; - data_reg[33] 0xc0 7.68002e+06 0.5; - data_reg[33]~feeder 0xc0 7.68002e+06 0.5; - data_reg[34] 0xc0 7.68002e+06 0.5; - data_reg[35] 0xc0 7.68002e+06 0.5; - data_reg[36] 0xc0 7.68002e+06 0.5; - data_reg[37] 0xc0 7.68002e+06 0.5; - data_reg[38] 0xc0 7.68002e+06 0.5; - data_reg[38]~feeder 0xc0 7.68002e+06 0.5; - data_reg[39] 0xc0 7.68002e+06 0.5; - data_reg[39]~feeder 0xc0 7.68002e+06 0.5; - data_reg[40] 0xc0 7.68002e+06 0.5; - data_reg[40]~feeder 0xc0 7.68002e+06 0.5; - data_reg[41] 0xc0 7.68002e+06 0.5; - data_reg[41]~feeder 0xc0 7.68002e+06 0.5; - data_reg[42] 0xc0 7.68002e+06 0.5; - data_reg[42]~feeder 0xc0 7.68002e+06 0.5; - data_reg[43] 0xc0 7.68002e+06 0.5; - data_reg[44] 0xc0 7.68002e+06 0.5; - data_reg[45] 0xc0 7.68002e+06 0.5; - data_reg[46] 0xc0 7.68002e+06 0.5; - data_reg[47] 0xc0 7.68002e+06 0.5; - data_reg[48] 0xc0 7.68002e+06 0.5; - data_reg[48]~feeder 0xc0 7.68002e+06 0.5; - data_reg[49] 0xc0 7.68002e+06 0.5; - data_reg[49]~feeder 0xc0 7.68002e+06 0.5; - data_reg[50] 0xc0 7.68002e+06 0.5; - data_reg[50]~feeder 0xc0 7.68002e+06 0.5; - data_reg[51] 0xc0 7.68002e+06 0.5; - data_reg[51]~feeder 0xc0 7.68002e+06 0.5; - data_reg[52] 0xc0 7.68002e+06 0.5; - data_reg[52]~feeder 0xc0 7.68002e+06 0.5; - data_reg[53] 0xc0 7.68002e+06 0.5; - data_reg[53]~feeder 0xc0 7.68002e+06 0.5; - data_reg[54] 0xc0 7.68002e+06 0.5; - data_reg[54]~feeder 0xc0 7.68002e+06 0.5; - data_reg[55] 0xc0 7.68002e+06 0.5; - data_reg[55]~feeder 0xc0 7.68002e+06 0.5; - data_reg[56] 0xc0 7.68002e+06 0.5; - data_reg[56]~feeder 0xc0 7.68002e+06 0.5; - data_reg[57] 0xc0 7.68002e+06 0.5; - data_reg[57]~feeder 0xc0 7.68002e+06 0.5; - data_reg[58] 0xc0 7.68002e+06 0.5; - data_reg[59] 0xc0 7.68002e+06 0.5; - data_reg[59]~feeder 0xc0 7.68002e+06 0.5; - data_reg[60] 0xc0 7.68002e+06 0.5; - data_reg[60]~feeder 0xc0 7.68002e+06 0.5; - data_reg[61] 0xc0 7.68002e+06 0.5; - data_reg[61]~feeder 0xc0 7.68002e+06 0.5; - data_reg[62] 0xc0 7.68002e+06 0.5; - data_reg[62]~feeder 0xc0 7.68002e+06 0.5; - data_reg[63] 0xc0 7.68002e+06 0.5; - data_reg[63]~feeder 0xc0 7.68002e+06 0.5; - data_reg[64] 0xc0 7.68002e+06 0.5; - data_reg[64]~feeder 0xc0 7.68002e+06 0.5; - data_reg[65] 0xc0 7.68002e+06 0.5; - data_reg[66] 0xc0 7.68002e+06 0.5; - data_reg[67] 0xc0 7.68002e+06 0.5; - data_reg[68] 0xc0 7.68002e+06 0.5; - data_reg[69] 0xc0 7.68002e+06 0.5; - data_reg[69]~feeder 0xc0 7.68002e+06 0.5; - data_reg[70] 0xc0 7.68002e+06 0.5; - data_reg[71] 0xc0 7.68002e+06 0.5; - data_reg[71]~feeder 0xc0 7.68002e+06 0.5; - data_reg[72] 0xc0 7.68002e+06 0.5; - data_reg[72]~feeder 0xc0 7.68002e+06 0.5; - data_reg[73] 0xc0 7.68002e+06 0.5; - data_reg[73]~feeder 0xc0 7.68002e+06 0.5; - data_reg[74] 0xc0 7.68002e+06 0.5; - data_reg[75] 0xc0 7.68002e+06 0.5; - data_reg[76] 0xc0 7.68002e+06 0.5; - data_reg[76]~feeder 0xc0 7.68002e+06 0.5; - data_reg[77] 0xc0 7.68002e+06 0.5; - data_reg[77]~feeder 0xc0 7.68002e+06 0.5; - data_reg[78] 0xc0 7.68002e+06 0.5; - data_reg[79] 0xc0 7.68002e+06 0.5; - data_reg[79]~feeder 0xc0 7.68002e+06 0.5; - data_reg[80] 0xc0 7.68002e+06 0.5; - data_reg[81] 0xc0 7.68002e+06 0.5; - data_reg[82] 0xc0 7.68002e+06 0.5; - data_reg[82]~feeder 0xc0 7.68002e+06 0.5; - data_reg[83] 0xc0 7.68002e+06 0.5; - data_reg[83]~feeder 0xc0 7.68002e+06 0.5; - data_reg[84] 0xc0 7.68002e+06 0.5; - outdata_reg[0] 0xc0 7.68002e+06 0.5; - outdata_reg[0]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[1] 0xc0 7.68002e+06 0.5; - outdata_reg[2] 0xc0 7.68002e+06 0.5; - outdata_reg[3] 0xc0 7.68002e+06 0.5; - outdata_reg[3]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[4] 0xc0 7.68002e+06 0.5; - outdata_reg[4]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[5] 0xc0 7.68002e+06 0.5; - outdata_reg[5]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[6] 0xc0 7.68002e+06 0.5; - outdata_reg[6]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[7] 0xc0 7.68002e+06 0.5; - outdata_reg[7]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[8] 0xc0 7.68002e+06 0.5; - outdata_reg[9] 0xc0 7.68002e+06 0.5; - outdata_reg[9]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[10] 0xc0 7.68002e+06 0.5; - outdata_reg[10]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[11] 0xc0 7.68002e+06 0.5; - outdata_reg[12] 0xc0 7.68002e+06 0.5; - outdata_reg[12]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[13] 0xc0 7.68002e+06 0.5; - outdata_reg[14] 0xc0 7.68002e+06 0.5; - outdata_reg[15] 0xc0 7.68002e+06 0.5; - outdata_reg[15]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[16] 0xc0 7.68002e+06 0.5; - outdata_reg[17] 0xc0 7.68002e+06 0.5; - outdata_reg[18] 0xc0 7.68002e+06 0.5; - outdata_reg[18]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[19] 0xc0 7.68002e+06 0.5; - outdata_reg[19]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[20] 0xc0 7.68002e+06 0.5; - outdata_reg[20]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[21] 0xc0 7.68002e+06 0.5; - outdata_reg[21]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[22] 0xc0 7.68002e+06 0.5; - outdata_reg[22]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[23] 0xc0 7.68002e+06 0.5; - outdata_reg[23]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[24] 0xc0 7.68002e+06 0.5; - outdata_reg[24]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[25] 0xc0 7.68002e+06 0.5; - outdata_reg[26] 0xc0 7.68002e+06 0.5; - outdata_reg[26]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[27] 0xc0 7.68002e+06 0.5; - outdata_reg[27]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[28] 0xc0 7.68002e+06 0.5; - outdata_reg[28]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[29] 0xc0 7.68002e+06 0.5; - outdata_reg[30] 0xc0 7.68002e+06 0.5; - outdata_reg[30]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[31] 0xc0 7.68002e+06 0.5; - outdata_reg[32] 0xc0 7.68002e+06 0.5; - outdata_reg[33] 0xc0 7.68002e+06 0.5; - outdata_reg[33]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[34] 0xc0 7.68002e+06 0.5; - outdata_reg[34]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[35] 0xc0 7.68002e+06 0.5; - outdata_reg[35]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[36] 0xc0 7.68002e+06 0.5; - outdata_reg[36]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[37] 0xc0 7.68002e+06 0.5; - outdata_reg[37]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[38] 0xc0 7.68002e+06 0.5; - outdata_reg[38]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[39] 0xc0 7.68002e+06 0.5; - outdata_reg[39]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[40] 0xc0 7.68002e+06 0.5; - outdata_reg[40]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[41] 0xc0 7.68002e+06 0.5; - outdata_reg[41]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[42] 0xc0 7.68002e+06 0.5; - outdata_reg[43] 0xc0 7.68002e+06 0.5; - outdata_reg[43]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[44] 0xc0 7.68002e+06 0.5; - outdata_reg[44]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[45] 0xc0 7.68002e+06 0.5; - outdata_reg[45]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[46] 0xc0 7.68002e+06 0.5; - outdata_reg[46]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[47] 0xc0 7.68002e+06 0.5; - outdata_reg[47]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[48] 0xc0 7.68002e+06 0.5; - outdata_reg[48]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[49] 0xc0 7.68002e+06 0.5; - outdata_reg[50] 0xc0 7.68002e+06 0.5; - outdata_reg[51] 0xc0 7.68002e+06 0.5; - outdata_reg[51]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[52] 0xc0 7.68002e+06 0.5; - outdata_reg[53] 0xc0 7.68002e+06 0.5; - outdata_reg[53]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[54] 0xc0 7.68002e+06 0.5; - outdata_reg[54]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[55] 0xc0 7.68002e+06 0.5; - outdata_reg[55]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[56] 0xc0 7.68002e+06 0.5; - outdata_reg[56]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[57] 0xc0 7.68002e+06 0.5; - outdata_reg[58] 0xc0 7.68002e+06 0.5; - outdata_reg[58]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[59] 0xc0 7.68002e+06 0.5; - outdata_reg[59]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[60] 0xc0 7.68002e+06 0.5; - outdata_reg[60]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[61] 0xc0 7.68002e+06 0.5; - outdata_reg[61]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[62] 0xc0 7.68002e+06 0.5; - outdata_reg[62]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[63] 0xc0 7.68002e+06 0.5; - outdata_reg[63]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[64] 0xc0 7.68002e+06 0.5; - outdata_reg[64]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[65] 0xc0 7.68002e+06 0.5; - outdata_reg[65]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[66] 0xc0 7.68002e+06 0.5; - outdata_reg[66]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[67] 0xc0 7.68002e+06 0.5; - outdata_reg[67]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[68] 0xc0 7.68002e+06 0.5; - outdata_reg[68]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[69] 0xc0 7.68002e+06 0.5; - outdata_reg[70] 0xc0 7.68002e+06 0.5; - outdata_reg[70]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[71] 0xc0 7.68002e+06 0.5; - outdata_reg[71]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[72] 0xc0 7.68002e+06 0.5; - outdata_reg[72]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[73] 0xc0 7.68002e+06 0.5; - outdata_reg[73]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[74] 0xc0 7.68002e+06 0.5; - outdata_reg[75] 0xc0 7.68002e+06 0.5; - outdata_reg[75]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[76] 0xc0 7.68002e+06 0.5; - outdata_reg[77] 0xc0 7.68002e+06 0.5; - outdata_reg[77]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[78] 0xc0 7.68002e+06 0.5; - outdata_reg[78]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[79] 0xc0 7.68002e+06 0.5; - outdata_reg[79]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[80] 0xc0 7.68002e+06 0.5; - outdata_reg[80]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[81] 0xc0 7.68002e+06 0.5; - outdata_reg[81]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[82] 0xc0 7.68002e+06 0.5; - outdata_reg[82]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[83] 0xc0 7.68002e+06 0.5; - outdata_reg[83]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[84] 0xc0 7.68002e+06 0.5; - mux_rob:output_mux; - result_node[0]~106 0xc0 3.27355e+06 0.5; - result_node[0]~107 0xc0 2.67375e+06 0.5; - result_node[1]~104 0xc0 3.27355e+06 0.5; - result_node[1]~105 0xc0 2.67375e+06 0.5; - result_node[2]~102 0xc0 3.27355e+06 0.5; - result_node[2]~103 0xc0 2.90392e+06 0.5; - result_node[3]~100 0xc0 3.27355e+06 0.5; - result_node[3]~101 0xc0 3.42181e+06 0.5; - result_node[4]~98 0xc0 4.85893e+06 0.5; - result_node[4]~99 0xc0 5.1743e+06 0.5; - result_node[5]~96 0xc0 4.31803e+06 0.5; - result_node[5]~97 0xc0 4.30675e+06 0.5; - result_node[6]~94 0xc0 4.13106e+06 0.5; - result_node[6]~95 0xc0 3.93463e+06 0.5; - result_node[7]~92 0xc0 4.88893e+06 0.5; - result_node[7]~93 0xc0 3.80455e+06 0.5; - result_node[8]~90 0xc0 4.13106e+06 0.5; - result_node[8]~91 0xc0 4.57596e+06 0.5; - result_node[9]~88 0xc0 4.13106e+06 0.5; - result_node[9]~89 0xc0 5.31799e+06 0.5; - result_node[10]~86 0xc0 3.27355e+06 0.5; - result_node[10]~87 0xc0 2.67375e+06 0.5; - result_node[11]~84 0xc0 4.13106e+06 0.5; - result_node[11]~85 0xc0 3.93463e+06 0.5; - result_node[12]~82 0xc0 3.08711e+06 0.5; - result_node[12]~83 0xc0 3.71445e+06 0.5; - result_node[13]~80 0xc0 4.13106e+06 0.5; - result_node[13]~81 0xc0 3.60192e+06 0.5; - result_node[14]~78 0xc0 4.84179e+06 0.5; - result_node[14]~79 0xc0 4.0099e+06 0.5; - result_node[15]~76 0xc0 3.08711e+06 0.5; - result_node[15]~77 0xc0 2.82575e+06 0.5; - result_node[16]~74 0xc0 3.28961e+06 0.5; - result_node[16]~75 0xc0 4.37606e+06 0.5; - result_node[17]~72 0xc0 3.08711e+06 0.5; - result_node[17]~73 0xc0 4.24973e+06 0.5; - result_node[18]~70 0xc0 3.27355e+06 0.5; - result_node[18]~71 0xc0 4.40227e+06 0.5; - result_node[19]~68 0xc0 4.88893e+06 0.5; - result_node[19]~69 0xc0 5.02809e+06 0.5; - result_node[20]~66 0xc0 4.85893e+06 0.5; - result_node[20]~67 0xc0 5.1743e+06 0.5; - result_node[21]~64 0xc0 3.27355e+06 0.5; - result_node[21]~65 0xc0 4.40227e+06 0.5; - result_node[22]~62 0xc0 4.31803e+06 0.5; - result_node[22]~63 0xc0 4.72867e+06 0.5; - result_node[23]~60 0xc0 3.27355e+06 0.5; - result_node[23]~61 0xc0 2.90392e+06 0.5; - result_node[24]~58 0xc0 4.13106e+06 0.5; - result_node[24]~59 0xc0 3.60192e+06 0.5; - result_node[25]~56 0xc0 3.27355e+06 0.5; - result_node[25]~57 0xc0 2.67375e+06 0.5; - result_node[26]~54 0xc0 3.27355e+06 0.5; - result_node[26]~55 0xc0 2.67375e+06 0.5; - result_node[27]~52 0xc0 4.84179e+06 0.5; - result_node[27]~53 0xc0 5.33582e+06 0.5; - result_node[28]~50 0xc0 3.28961e+06 0.5; - result_node[28]~51 0xc0 3.8237e+06 0.5; - result_node[29]~48 0xc0 3.27355e+06 0.5; - result_node[29]~49 0xc0 4.40227e+06 0.5; - result_node[30]~46 0xc0 4.31803e+06 0.5; - result_node[30]~47 0xc0 4.30675e+06 0.5; - result_node[31]~44 0xc0 4.85893e+06 0.5; - result_node[31]~45 0xc0 5.1743e+06 0.5; - result_node[32]~42 0xc0 4.85893e+06 0.5; - result_node[32]~43 0xc0 4.99092e+06 0.5; - result_node[33]~40 0xc0 4.13106e+06 0.5; - result_node[33]~41 0xc0 4.76347e+06 0.5; - result_node[34]~38 0xc0 4.31803e+06 0.5; - result_node[34]~39 0xc0 4.09588e+06 0.5; - result_node[35]~36 0xc0 4.84179e+06 0.5; - result_node[35]~37 0xc0 4.0099e+06 0.5; - result_node[36]~34 0xc0 3.28961e+06 0.5; - result_node[36]~35 0xc0 4.02851e+06 0.5; - result_node[37]~32 0xc0 4.85893e+06 0.5; - result_node[37]~33 0xc0 5.1743e+06 0.5; - result_node[38]~30 0xc0 4.31803e+06 0.5; - result_node[38]~31 0xc0 4.57805e+06 0.5; - result_node[39]~28 0xc0 3.08711e+06 0.5; - result_node[39]~29 0xc0 4.43723e+06 0.5; - result_node[40]~26 0xc0 3.28961e+06 0.5; - result_node[40]~27 0xc0 4.02851e+06 0.5; - result_node[41]~24 0xc0 4.13106e+06 0.5; - result_node[41]~25 0xc0 4.76347e+06 0.5; - result_node[42]~22 0xc0 4.88893e+06 0.5; - result_node[42]~23 0xc0 5.0003e+06 0.5; - result_node[43]~20 0xc0 3.5773e+06 0.5; - result_node[43]~21 0xc0 4.49719e+06 0.5; - result_node[44]~18 0xc0 3.08711e+06 0.5; - result_node[44]~19 0xc0 3.39222e+06 0.5; - result_node[45]~16 0xc0 4.13106e+06 0.5; - result_node[45]~17 0xc0 4.57596e+06 0.5; - result_node[46]~14 0xc0 3.08711e+06 0.5; - result_node[46]~15 0xc0 3.09958e+06 0.5; - result_node[47]~12 0xc0 4.31803e+06 0.5; - result_node[47]~13 0xc0 5.25398e+06 0.5; - result_node[48]~10 0xc0 4.13106e+06 0.5; - result_node[48]~11 0xc0 4.55442e+06 0.5; - result_node[49]~8 0xc0 3.5773e+06 0.5; - result_node[49]~9 0xc0 4.20035e+06 0.5; - result_node[50]~6 0xc0 4.88893e+06 0.5; - result_node[50]~7 0xc0 5.02809e+06 0.5; - result_node[51]~4 0xc0 3.28961e+06 0.5; - result_node[51]~5 0xc0 5.01223e+06 0.5; - result_node[52]~2 0xc0 4.31803e+06 0.5; - result_node[52]~3 0xc0 3.90386e+06 0.5; - result_node[53]~0 0xc0 4.88893e+06 0.5; - result_node[53]~1 0xc0 4.03455e+06 0.5; - result_node[54]~108 0xc0 3.27355e+06 0.5; - result_node[54]~109 0xc0 2.67849e+06 0.5; - result_node[55]~110 0xc0 3.27355e+06 0.5; - result_node[55]~111 0xc0 2.90392e+06 0.5; - result_node[56]~112 0xc0 3.08711e+06 0.5; - result_node[56]~113 0xc0 4.43723e+06 0.5; - result_node[57]~114 0xc0 4.13106e+06 0.5; - result_node[57]~115 0xc0 4.36692e+06 0.5; - result_node[58]~116 0xc0 3.28961e+06 0.5; - result_node[58]~117 0xc0 4.37606e+06 0.5; - result_node[59]~118 0xc0 3.08711e+06 0.5; - result_node[59]~119 0xc0 3.60928e+06 0.5; - result_node[60]~120 0xc0 3.5773e+06 0.5; - result_node[60]~121 0xc0 3.53571e+06 0.5; - result_node[61]~122 0xc0 3.5773e+06 0.5; - result_node[61]~123 0xc0 4.20035e+06 0.5; - result_node[62]~124 0xc0 4.85893e+06 0.5; - result_node[62]~125 0xc0 3.79216e+06 0.5; - result_node[63]~126 0xc0 4.80429e+06 0.5; - result_node[63]~127 0xc0 4.39979e+06 0.5; - result_node[64]~128 0xc0 4.85893e+06 0.5; - result_node[64]~129 0xc0 5.1743e+06 0.5; - result_node[65]~130 0xc0 4.88893e+06 0.5; - result_node[65]~131 0xc0 5.02809e+06 0.5; - result_node[66]~132 0xc0 3.08711e+06 0.5; - result_node[66]~133 0xc0 2.72619e+06 0.5; - result_node[67]~134 0xc0 4.88893e+06 0.5; - result_node[67]~135 0xc0 5.1774e+06 0.5; - result_node[68]~136 0xc0 3.08711e+06 0.5; - result_node[68]~137 0xc0 2.88251e+06 0.5; - result_node[69]~138 0xc0 4.85893e+06 0.5; - result_node[69]~139 0xc0 4.28859e+06 0.5; - result_node[70]~140 0xc0 4.85893e+06 0.5; - result_node[70]~141 0xc0 3.79216e+06 0.5; - result_node[71]~142 0xc0 4.88893e+06 0.5; - result_node[71]~143 0xc0 4.03455e+06 0.5; - result_node[72]~144 0xc0 4.85893e+06 0.5; - result_node[72]~145 0xc0 4.99092e+06 0.5; - result_node[73]~146 0xc0 4.80429e+06 0.5; - result_node[73]~147 0xc0 4.0617e+06 0.5; - result_node[74]~148 0xc0 4.85893e+06 0.5; - result_node[74]~149 0xc0 5.00934e+06 0.5; - result_node[75]~150 0xc0 4.85893e+06 0.5; - result_node[75]~151 0xc0 5.1743e+06 0.5; - result_node[76]~152 0xc0 4.88893e+06 0.5; - result_node[76]~153 0xc0 5.02809e+06 0.5; - result_node[77]~154 0xc0 4.31803e+06 0.5; - result_node[77]~155 0xc0 5.18338e+06 0.5; - result_node[78]~156 0xc0 4.85893e+06 0.5; - result_node[78]~157 0xc0 4.28859e+06 0.5; - result_node[79]~158 0xc0 4.88893e+06 0.5; - result_node[79]~159 0xc0 3.78955e+06 0.5; - result_node[80]~160 0xc0 4.85893e+06 0.5; - result_node[80]~161 0xc0 5.1743e+06 0.5; - result_node[81]~162 0xc0 3.28961e+06 0.5; - result_node[81]~163 0xc0 3.82601e+06 0.5; - result_node[82]~164 0xc0 3.08711e+06 0.5; - result_node[82]~165 0xc0 2.72619e+06 0.5; - result_node[83]~166 0xc0 3.28961e+06 0.5; - result_node[83]~167 0xc0 4.31301e+06 0.5; - result_node[84]~168 0xc0 4.31803e+06 0.5; - result_node[84]~169 0xc0 4.44795e+06 0.5; - ram_block[0] 0xc0 7.68002e+06 0.5; - ram_block[1] 0xc0 7.68002e+06 0.5; - ram_block[2] 0xc0 7.68002e+06 0.5; - ram_block[3] 0xc0 7.68002e+06 0.5; - ram_block[4] 0xc0 7.68002e+06 0.5; - ram_block[4]~feeder 0xc0 7.68002e+06 0.5; - ram_block[5] 0xc0 7.68002e+06 0.5; - ram_block[5]~feeder 0xc0 7.68002e+06 0.5; - ram_block[6] 0xc0 7.68002e+06 0.5; - ram_block[6]~feeder 0xc0 7.68002e+06 0.5; - ram_block[7] 0xc0 7.68002e+06 0.5; - ram_block[8] 0xc0 7.68002e+06 0.5; - ram_block[9] 0xc0 7.68002e+06 0.5; - ram_block[9]~feeder 0xc0 7.68002e+06 0.5; - ram_block[10] 0xc0 7.68002e+06 0.5; - ram_block[11] 0xc0 7.68002e+06 0.5; - ram_block[11]~feeder 0xc0 7.68002e+06 0.5; - ram_block[12] 0xc0 7.68002e+06 0.5; - ram_block[13] 0xc0 7.68002e+06 0.5; - ram_block[13]~feeder 0xc0 7.68002e+06 0.5; - ram_block[14] 0xc0 7.68002e+06 0.5; - ram_block[15] 0xc0 7.68002e+06 0.5; - ram_block[15]~feeder 0xc0 7.68002e+06 0.5; - ram_block[16] 0xc0 7.68002e+06 0.5; - ram_block[16]~feeder 0xc0 7.68002e+06 0.5; - ram_block[17] 0xc0 7.68002e+06 0.5; - ram_block[17]~feeder 0xc0 7.68002e+06 0.5; - ram_block[18] 0xc0 7.68002e+06 0.5; - ram_block[19] 0xc0 7.68002e+06 0.5; - ram_block[19]~feeder 0xc0 7.68002e+06 0.5; - ram_block[20] 0xc0 7.68002e+06 0.5; - ram_block[20]~feeder 0xc0 7.68002e+06 0.5; - ram_block[21] 0xc0 7.68002e+06 0.5; - ram_block[22] 0xc0 7.68002e+06 0.5; - ram_block[23] 0xc0 7.68002e+06 0.5; - ram_block[24] 0xc0 7.68002e+06 0.5; - ram_block[24]~feeder 0xc0 7.68002e+06 0.5; - ram_block[25] 0xc0 7.68002e+06 0.5; - ram_block[26] 0xc0 7.68002e+06 0.5; - ram_block[27] 0xc0 7.68002e+06 0.5; - ram_block[28] 0xc0 7.68002e+06 0.5; - ram_block[28]~feeder 0xc0 7.68002e+06 0.5; - ram_block[29] 0xc0 7.68002e+06 0.5; - ram_block[30] 0xc0 7.68002e+06 0.5; - ram_block[31] 0xc0 7.68002e+06 0.5; - ram_block[31]~feeder 0xc0 7.68002e+06 0.5; - ram_block[32] 0xc0 7.68002e+06 0.5; - ram_block[32]~feeder 0xc0 7.68002e+06 0.5; - ram_block[33] 0xc0 7.68002e+06 0.5; - ram_block[34] 0xc0 7.68002e+06 0.5; - ram_block[35] 0xc0 7.68002e+06 0.5; - ram_block[36] 0xc0 7.68002e+06 0.5; - ram_block[36]~feeder 0xc0 7.68002e+06 0.5; - ram_block[37] 0xc0 7.68002e+06 0.5; - ram_block[37]~feeder 0xc0 7.68002e+06 0.5; - ram_block[38] 0xc0 7.68002e+06 0.5; - ram_block[39] 0xc0 7.68002e+06 0.5; - ram_block[39]~feeder 0xc0 7.68002e+06 0.5; - ram_block[40] 0xc0 7.68002e+06 0.5; - ram_block[40]~feeder 0xc0 7.68002e+06 0.5; - ram_block[41] 0xc0 7.68002e+06 0.5; - ram_block[42] 0xc0 7.68002e+06 0.5; - ram_block[42]~feeder 0xc0 7.68002e+06 0.5; - ram_block[43] 0xc0 7.68002e+06 0.5; - ram_block[44] 0xc0 7.68002e+06 0.5; - ram_block[44]~feeder 0xc0 7.68002e+06 0.5; - ram_block[45] 0xc0 7.68002e+06 0.5; - ram_block[45]~feeder 0xc0 7.68002e+06 0.5; - ram_block[46] 0xc0 7.68002e+06 0.5; - ram_block[46]~feeder 0xc0 7.68002e+06 0.5; - ram_block[47] 0xc0 7.68002e+06 0.5; - ram_block[48] 0xc0 7.68002e+06 0.5; - ram_block[48]~feeder 0xc0 7.68002e+06 0.5; - ram_block[49] 0xc0 7.68002e+06 0.5; - ram_block[50] 0xc0 7.68002e+06 0.5; - ram_block[50]~feeder 0xc0 7.68002e+06 0.5; - ram_block[51] 0xc0 7.68002e+06 0.5; - ram_block[51]~feeder 0xc0 7.68002e+06 0.5; - ram_block[52] 0xc0 7.68002e+06 0.5; - ram_block[53] 0xc0 7.68002e+06 0.5; - ram_block[53]~feeder 0xc0 7.68002e+06 0.5; - ram_block[54] 0xc0 7.68002e+06 0.5; - ram_block[55] 0xc0 7.68002e+06 0.5; - ram_block[56] 0xc0 7.68002e+06 0.5; - ram_block[56]~feeder 0xc0 7.68002e+06 0.5; - ram_block[57] 0xc0 7.68002e+06 0.5; - ram_block[57]~feeder 0xc0 7.68002e+06 0.5; - ram_block[58] 0xc0 7.68002e+06 0.5; - ram_block[58]~feeder 0xc0 7.68002e+06 0.5; - ram_block[59] 0xc0 7.68002e+06 0.5; - ram_block[59]~feeder 0xc0 7.68002e+06 0.5; - ram_block[60] 0xc0 7.68002e+06 0.5; - ram_block[61] 0xc0 7.68002e+06 0.5; - ram_block[62] 0xc0 7.68002e+06 0.5; - ram_block[62]~feeder 0xc0 7.68002e+06 0.5; - ram_block[63] 0xc0 7.68002e+06 0.5; - ram_block[64] 0xc0 7.68002e+06 0.5; - ram_block[64]~feeder 0xc0 7.68002e+06 0.5; - ram_block[65] 0xc0 7.68002e+06 0.5; - ram_block[66] 0xc0 7.68002e+06 0.5; - ram_block[66]~feeder 0xc0 7.68002e+06 0.5; - ram_block[67] 0xc0 7.68002e+06 0.5; - ram_block[67]~feeder 0xc0 7.68002e+06 0.5; - ram_block[68] 0xc0 7.68002e+06 0.5; - ram_block[68]~feeder 0xc0 7.68002e+06 0.5; - ram_block[69] 0xc0 7.68002e+06 0.5; - ram_block[69]~feeder 0xc0 7.68002e+06 0.5; - ram_block[70] 0xc0 7.68002e+06 0.5; - ram_block[70]~feeder 0xc0 7.68002e+06 0.5; - ram_block[71] 0xc0 7.68002e+06 0.5; - ram_block[71]~feeder 0xc0 7.68002e+06 0.5; - ram_block[72] 0xc0 7.68002e+06 0.5; - ram_block[73] 0xc0 7.68002e+06 0.5; - ram_block[74] 0xc0 7.68002e+06 0.5; - ram_block[75] 0xc0 7.68002e+06 0.5; - ram_block[75]~feeder 0xc0 7.68002e+06 0.5; - ram_block[76] 0xc0 7.68002e+06 0.5; - ram_block[76]~feeder 0xc0 7.68002e+06 0.5; - ram_block[77] 0xc0 7.68002e+06 0.5; - ram_block[78] 0xc0 7.68002e+06 0.5; - ram_block[78]~feeder 0xc0 7.68002e+06 0.5; - ram_block[79] 0xc0 7.68002e+06 0.5; - ram_block[79]~feeder 0xc0 7.68002e+06 0.5; - ram_block[80] 0xc0 7.68002e+06 0.5; - ram_block[80]~feeder 0xc0 7.68002e+06 0.5; - ram_block[81] 0xc0 7.68002e+06 0.5; - ram_block[82] 0xc0 7.68002e+06 0.5; - ram_block[82]~feeder 0xc0 7.68002e+06 0.5; - ram_block[83] 0xc0 7.68002e+06 0.5; - ram_block[84] 0xc0 7.68002e+06 0.5; - ram_block[85] 0xc0 7.68002e+06 0.5; - ram_block[85]~feeder 0xc0 7.68002e+06 0.5; - ram_block[86] 0xc0 7.68002e+06 0.5; - ram_block[86]~feeder 0xc0 7.68002e+06 0.5; - ram_block[87] 0xc0 7.68002e+06 0.5; - ram_block[87]~feeder 0xc0 7.68002e+06 0.5; - ram_block[88] 0xc0 7.68002e+06 0.5; - ram_block[89] 0xc0 7.68002e+06 0.5; - ram_block[89]~feeder 0xc0 7.68002e+06 0.5; - ram_block[90] 0xc0 7.68002e+06 0.5; - ram_block[90]~feeder 0xc0 7.68002e+06 0.5; - ram_block[91] 0xc0 7.68002e+06 0.5; - ram_block[91]~feeder 0xc0 7.68002e+06 0.5; - ram_block[92] 0xc0 7.68002e+06 0.5; - ram_block[92]~feeder 0xc0 7.68002e+06 0.5; - ram_block[93] 0xc0 7.68002e+06 0.5; - ram_block[93]~feeder 0xc0 7.68002e+06 0.5; - ram_block[94] 0xc0 7.68002e+06 0.5; - ram_block[94]~feeder 0xc0 7.68002e+06 0.5; - ram_block[95] 0xc0 7.68002e+06 0.5; - ram_block[95]~feeder 0xc0 7.68002e+06 0.5; - ram_block[96] 0xc0 7.68002e+06 0.5; - ram_block[96]~feeder 0xc0 7.68002e+06 0.5; - ram_block[97] 0xc0 7.68002e+06 0.5; - ram_block[97]~feeder 0xc0 7.68002e+06 0.5; - ram_block[98] 0xc0 7.68002e+06 0.5; - ram_block[99] 0xc0 7.68002e+06 0.5; - ram_block[99]~feeder 0xc0 7.68002e+06 0.5; - ram_block[100] 0xc0 7.68002e+06 0.5; - ram_block[100]~feeder 0xc0 7.68002e+06 0.5; - ram_block[101] 0xc0 7.68002e+06 0.5; - ram_block[101]~feeder 0xc0 7.68002e+06 0.5; - ram_block[102] 0xc0 7.68002e+06 0.5; - ram_block[102]~feeder 0xc0 7.68002e+06 0.5; - ram_block[103] 0xc0 7.68002e+06 0.5; - ram_block[103]~feeder 0xc0 7.68002e+06 0.5; - ram_block[104] 0xc0 7.68002e+06 0.5; - ram_block[104]~feeder 0xc0 7.68002e+06 0.5; - ram_block[105] 0xc0 7.68002e+06 0.5; - ram_block[106] 0xc0 7.68002e+06 0.5; - ram_block[106]~feeder 0xc0 7.68002e+06 0.5; - ram_block[107] 0xc0 7.68002e+06 0.5; - ram_block[107]~feeder 0xc0 7.68002e+06 0.5; - ram_block[108] 0xc0 7.68002e+06 0.5; - ram_block[108]~feeder 0xc0 7.68002e+06 0.5; - ram_block[109] 0xc0 7.68002e+06 0.5; - ram_block[109]~feeder 0xc0 7.68002e+06 0.5; - ram_block[110] 0xc0 7.68002e+06 0.5; - ram_block[110]~feeder 0xc0 7.68002e+06 0.5; - ram_block[111] 0xc0 7.68002e+06 0.5; - ram_block[111]~feeder 0xc0 7.68002e+06 0.5; - ram_block[112] 0xc0 7.68002e+06 0.5; - ram_block[112]~feeder 0xc0 7.68002e+06 0.5; - ram_block[113] 0xc0 7.68002e+06 0.5; - ram_block[113]~feeder 0xc0 7.68002e+06 0.5; - ram_block[114] 0xc0 7.68002e+06 0.5; - ram_block[114]~feeder 0xc0 7.68002e+06 0.5; - ram_block[115] 0xc0 7.68002e+06 0.5; - ram_block[115]~feeder 0xc0 7.68002e+06 0.5; - ram_block[116] 0xc0 7.68002e+06 0.5; - ram_block[116]~feeder 0xc0 7.68002e+06 0.5; - ram_block[117] 0xc0 7.68002e+06 0.5; - ram_block[117]~feeder 0xc0 7.68002e+06 0.5; - ram_block[118] 0xc0 7.68002e+06 0.5; - ram_block[118]~feeder 0xc0 7.68002e+06 0.5; - ram_block[119] 0xc0 7.68002e+06 0.5; - ram_block[120] 0xc0 7.68002e+06 0.5; - ram_block[121] 0xc0 7.68002e+06 0.5; - ram_block[121]~feeder 0xc0 7.68002e+06 0.5; - ram_block[122] 0xc0 7.68002e+06 0.5; - ram_block[123] 0xc0 7.68002e+06 0.5; - ram_block[123]~feeder 0xc0 7.68002e+06 0.5; - ram_block[124] 0xc0 7.68002e+06 0.5; - ram_block[124]~feeder 0xc0 7.68002e+06 0.5; - ram_block[125] 0xc0 7.68002e+06 0.5; - ram_block[125]~feeder 0xc0 7.68002e+06 0.5; - ram_block[126] 0xc0 7.68002e+06 0.5; - ram_block[127] 0xc0 7.68002e+06 0.5; - ram_block[127]~feeder 0xc0 7.68002e+06 0.5; - ram_block[128] 0xc0 7.68002e+06 0.5; - ram_block[128]~feeder 0xc0 7.68002e+06 0.5; - ram_block[129] 0xc0 7.68002e+06 0.5; - ram_block[129]~feeder 0xc0 7.68002e+06 0.5; - ram_block[130] 0xc0 7.68002e+06 0.5; - ram_block[131] 0xc0 7.68002e+06 0.5; - ram_block[131]~feeder 0xc0 7.68002e+06 0.5; - ram_block[132] 0xc0 7.68002e+06 0.5; - ram_block[133] 0xc0 7.68002e+06 0.5; - ram_block[133]~feeder 0xc0 7.68002e+06 0.5; - ram_block[134] 0xc0 7.68002e+06 0.5; - ram_block[134]~feeder 0xc0 7.68002e+06 0.5; - ram_block[135] 0xc0 7.68002e+06 0.5; - ram_block[136] 0xc0 7.68002e+06 0.5; - ram_block[137] 0xc0 7.68002e+06 0.5; - ram_block[137]~feeder 0xc0 7.68002e+06 0.5; - ram_block[138] 0xc0 7.68002e+06 0.5; - ram_block[138]~feeder 0xc0 7.68002e+06 0.5; - ram_block[139] 0xc0 7.68002e+06 0.5; - ram_block[139]~feeder 0xc0 7.68002e+06 0.5; - ram_block[140] 0xc0 7.68002e+06 0.5; - ram_block[140]~feeder 0xc0 7.68002e+06 0.5; - ram_block[141] 0xc0 7.68002e+06 0.5; - ram_block[142] 0xc0 7.68002e+06 0.5; - ram_block[143] 0xc0 7.68002e+06 0.5; - ram_block[144] 0xc0 7.68002e+06 0.5; - ram_block[144]~feeder 0xc0 7.68002e+06 0.5; - ram_block[145] 0xc0 7.68002e+06 0.5; - ram_block[145]~feeder 0xc0 7.68002e+06 0.5; - ram_block[146] 0xc0 7.68002e+06 0.5; - ram_block[146]~feeder 0xc0 7.68002e+06 0.5; - ram_block[147] 0xc0 7.68002e+06 0.5; - ram_block[148] 0xc0 7.68002e+06 0.5; - ram_block[148]~feeder 0xc0 7.68002e+06 0.5; - ram_block[149] 0xc0 7.68002e+06 0.5; - ram_block[150] 0xc0 7.68002e+06 0.5; - ram_block[150]~feeder 0xc0 7.68002e+06 0.5; - ram_block[151] 0xc0 7.68002e+06 0.5; - ram_block[151]~feeder 0xc0 7.68002e+06 0.5; - ram_block[152] 0xc0 7.68002e+06 0.5; - ram_block[153] 0xc0 7.68002e+06 0.5; - ram_block[153]~feeder 0xc0 7.68002e+06 0.5; - ram_block[154] 0xc0 7.68002e+06 0.5; - ram_block[155] 0xc0 7.68002e+06 0.5; - ram_block[156] 0xc0 7.68002e+06 0.5; - ram_block[156]~feeder 0xc0 7.68002e+06 0.5; - ram_block[157] 0xc0 7.68002e+06 0.5; - ram_block[157]~feeder 0xc0 7.68002e+06 0.5; - ram_block[158] 0xc0 7.68002e+06 0.5; - ram_block[158]~feeder 0xc0 7.68002e+06 0.5; - ram_block[159] 0xc0 7.68002e+06 0.5; - ram_block[159]~feeder 0xc0 7.68002e+06 0.5; - ram_block[160] 0xc0 7.68002e+06 0.5; - ram_block[161] 0xc0 7.68002e+06 0.5; - ram_block[161]~feeder 0xc0 7.68002e+06 0.5; - ram_block[162] 0xc0 7.68002e+06 0.5; - ram_block[163] 0xc0 7.68002e+06 0.5; - ram_block[163]~feeder 0xc0 7.68002e+06 0.5; - ram_block[164] 0xc0 7.68002e+06 0.5; - ram_block[164]~feeder 0xc0 7.68002e+06 0.5; - ram_block[165] 0xc0 7.68002e+06 0.5; - ram_block[165]~feeder 0xc0 7.68002e+06 0.5; - ram_block[166] 0xc0 7.68002e+06 0.5; - ram_block[166]~feeder 0xc0 7.68002e+06 0.5; - ram_block[167] 0xc0 7.68002e+06 0.5; - ram_block[167]~feeder 0xc0 7.68002e+06 0.5; - ram_block[168] 0xc0 7.68002e+06 0.5; - ram_block[169] 0xc0 7.68002e+06 0.5; - ram_block[169]~feeder 0xc0 7.68002e+06 0.5; - ram_block[170] 0xc0 7.68002e+06 0.5; - ram_block[170]~feeder 0xc0 7.68002e+06 0.5; - ram_block[171] 0xc0 7.68002e+06 0.5; - ram_block[171]~feeder 0xc0 7.68002e+06 0.5; - ram_block[172] 0xc0 7.68002e+06 0.5; - ram_block[172]~feeder 0xc0 7.68002e+06 0.5; - ram_block[173] 0xc0 7.68002e+06 0.5; - ram_block[174] 0xc0 7.68002e+06 0.5; - ram_block[175] 0xc0 7.68002e+06 0.5; - ram_block[176] 0xc0 7.68002e+06 0.5; - ram_block[177] 0xc0 7.68002e+06 0.5; - ram_block[178] 0xc0 7.68002e+06 0.5; - ram_block[178]~feeder 0xc0 7.68002e+06 0.5; - ram_block[179] 0xc0 7.68002e+06 0.5; - ram_block[180] 0xc0 7.68002e+06 0.5; - ram_block[180]~feeder 0xc0 7.68002e+06 0.5; - ram_block[181] 0xc0 7.68002e+06 0.5; - ram_block[182] 0xc0 7.68002e+06 0.5; - ram_block[182]~feeder 0xc0 7.68002e+06 0.5; - ram_block[183] 0xc0 7.68002e+06 0.5; - ram_block[183]~feeder 0xc0 7.68002e+06 0.5; - ram_block[184] 0xc0 7.68002e+06 0.5; - ram_block[184]~feeder 0xc0 7.68002e+06 0.5; - ram_block[185] 0xc0 7.68002e+06 0.5; - ram_block[186] 0xc0 7.68002e+06 0.5; - ram_block[187] 0xc0 7.68002e+06 0.5; - ram_block[188] 0xc0 7.68002e+06 0.5; - ram_block[188]~feeder 0xc0 7.68002e+06 0.5; - ram_block[189] 0xc0 7.68002e+06 0.5; - ram_block[189]~feeder 0xc0 7.68002e+06 0.5; - ram_block[190] 0xc0 7.68002e+06 0.5; - ram_block[190]~feeder 0xc0 7.68002e+06 0.5; - ram_block[191] 0xc0 7.68002e+06 0.5; - ram_block[192] 0xc0 7.68002e+06 0.5; - ram_block[192]~feeder 0xc0 7.68002e+06 0.5; - ram_block[193] 0xc0 7.68002e+06 0.5; - ram_block[193]~feeder 0xc0 7.68002e+06 0.5; - ram_block[194] 0xc0 7.68002e+06 0.5; - ram_block[194]~feeder 0xc0 7.68002e+06 0.5; - ram_block[195] 0xc0 7.68002e+06 0.5; - ram_block[195]~feeder 0xc0 7.68002e+06 0.5; - ram_block[196] 0xc0 7.68002e+06 0.5; - ram_block[196]~feeder 0xc0 7.68002e+06 0.5; - ram_block[197] 0xc0 7.68002e+06 0.5; - ram_block[197]~feeder 0xc0 7.68002e+06 0.5; - ram_block[198] 0xc0 7.68002e+06 0.5; - ram_block[199] 0xc0 7.68002e+06 0.5; - ram_block[199]~feeder 0xc0 7.68002e+06 0.5; - ram_block[200] 0xc0 7.68002e+06 0.5; - ram_block[200]~feeder 0xc0 7.68002e+06 0.5; - ram_block[201] 0xc0 7.68002e+06 0.5; - ram_block[202] 0xc0 7.68002e+06 0.5; - ram_block[203] 0xc0 7.68002e+06 0.5; - ram_block[203]~feeder 0xc0 7.68002e+06 0.5; - ram_block[204] 0xc0 7.68002e+06 0.5; - ram_block[204]~feeder 0xc0 7.68002e+06 0.5; - ram_block[205] 0xc0 7.68002e+06 0.5; - ram_block[205]~feeder 0xc0 7.68002e+06 0.5; - ram_block[206] 0xc0 7.68002e+06 0.5; - ram_block[207] 0xc0 7.68002e+06 0.5; - ram_block[207]~feeder 0xc0 7.68002e+06 0.5; - ram_block[208] 0xc0 7.68002e+06 0.5; - ram_block[208]~feeder 0xc0 7.68002e+06 0.5; - ram_block[209] 0xc0 7.68002e+06 0.5; - ram_block[209]~feeder 0xc0 7.68002e+06 0.5; - ram_block[210] 0xc0 7.68002e+06 0.5; - ram_block[211] 0xc0 7.68002e+06 0.5; - ram_block[211]~feeder 0xc0 7.68002e+06 0.5; - ram_block[212] 0xc0 7.68002e+06 0.5; - ram_block[213] 0xc0 7.68002e+06 0.5; - ram_block[213]~feeder 0xc0 7.68002e+06 0.5; - ram_block[214] 0xc0 7.68002e+06 0.5; - ram_block[214]~feeder 0xc0 7.68002e+06 0.5; - ram_block[215] 0xc0 7.68002e+06 0.5; - ram_block[216] 0xc0 7.68002e+06 0.5; - ram_block[217] 0xc0 7.68002e+06 0.5; - ram_block[218] 0xc0 7.68002e+06 0.5; - ram_block[219] 0xc0 7.68002e+06 0.5; - ram_block[219]~feeder 0xc0 7.68002e+06 0.5; - ram_block[220] 0xc0 7.68002e+06 0.5; - ram_block[221] 0xc0 7.68002e+06 0.5; - ram_block[221]~feeder 0xc0 7.68002e+06 0.5; - ram_block[222] 0xc0 7.68002e+06 0.5; - ram_block[223] 0xc0 7.68002e+06 0.5; - ram_block[224] 0xc0 7.68002e+06 0.5; - ram_block[225] 0xc0 7.68002e+06 0.5; - ram_block[225]~feeder 0xc0 7.68002e+06 0.5; - ram_block[226] 0xc0 7.68002e+06 0.5; - ram_block[226]~feeder 0xc0 7.68002e+06 0.5; - ram_block[227] 0xc0 7.68002e+06 0.5; - ram_block[228] 0xc0 7.68002e+06 0.5; - ram_block[228]~feeder 0xc0 7.68002e+06 0.5; - ram_block[229] 0xc0 7.68002e+06 0.5; - ram_block[229]~feeder 0xc0 7.68002e+06 0.5; - ram_block[230] 0xc0 7.68002e+06 0.5; - ram_block[230]~feeder 0xc0 7.68002e+06 0.5; - ram_block[231] 0xc0 7.68002e+06 0.5; - ram_block[231]~feeder 0xc0 7.68002e+06 0.5; - ram_block[232] 0xc0 7.68002e+06 0.5; - ram_block[232]~feeder 0xc0 7.68002e+06 0.5; - ram_block[233] 0xc0 7.68002e+06 0.5; - ram_block[233]~feeder 0xc0 7.68002e+06 0.5; - ram_block[234] 0xc0 7.68002e+06 0.5; - ram_block[234]~feeder 0xc0 7.68002e+06 0.5; - ram_block[235] 0xc0 7.68002e+06 0.5; - ram_block[236] 0xc0 7.68002e+06 0.5; - ram_block[236]~feeder 0xc0 7.68002e+06 0.5; - ram_block[237] 0xc0 7.68002e+06 0.5; - ram_block[237]~feeder 0xc0 7.68002e+06 0.5; - ram_block[238] 0xc0 7.68002e+06 0.5; - ram_block[239] 0xc0 7.68002e+06 0.5; - ram_block[239]~feeder 0xc0 7.68002e+06 0.5; - ram_block[240] 0xc0 7.68002e+06 0.5; - ram_block[240]~feeder 0xc0 7.68002e+06 0.5; - ram_block[241] 0xc0 7.68002e+06 0.5; - ram_block[242] 0xc0 7.68002e+06 0.5; - ram_block[242]~feeder 0xc0 7.68002e+06 0.5; - ram_block[243] 0xc0 7.68002e+06 0.5; - ram_block[243]~feeder 0xc0 7.68002e+06 0.5; - ram_block[244] 0xc0 7.68002e+06 0.5; - ram_block[244]~feeder 0xc0 7.68002e+06 0.5; - ram_block[245] 0xc0 7.68002e+06 0.5; - ram_block[245]~feeder 0xc0 7.68002e+06 0.5; - ram_block[246] 0xc0 7.68002e+06 0.5; - ram_block[246]~feeder 0xc0 7.68002e+06 0.5; - ram_block[247] 0xc0 7.68002e+06 0.5; - ram_block[247]~feeder 0xc0 7.68002e+06 0.5; - ram_block[248] 0xc0 7.68002e+06 0.5; - ram_block[249] 0xc0 7.68002e+06 0.5; - ram_block[249]~feeder 0xc0 7.68002e+06 0.5; - ram_block[250] 0xc0 7.68002e+06 0.5; - ram_block[251] 0xc0 7.68002e+06 0.5; - ram_block[252] 0xc0 7.68002e+06 0.5; - ram_block[252]~feeder 0xc0 7.68002e+06 0.5; - ram_block[253] 0xc0 7.68002e+06 0.5; - ram_block[253]~feeder 0xc0 7.68002e+06 0.5; - ram_block[254] 0xc0 7.68002e+06 0.5; - ram_block[254]~feeder 0xc0 7.68002e+06 0.5; - ram_block[255] 0xc0 7.68002e+06 0.5; - ram_block[255]~feeder 0xc0 7.68002e+06 0.5; - ram_block[256] 0xc0 7.68002e+06 0.5; - ram_block[256]~feeder 0xc0 7.68002e+06 0.5; - ram_block[257] 0xc0 7.68002e+06 0.5; - ram_block[257]~feeder 0xc0 7.68002e+06 0.5; - ram_block[258] 0xc0 7.68002e+06 0.5; - ram_block[259] 0xc0 7.68002e+06 0.5; - ram_block[259]~feeder 0xc0 7.68002e+06 0.5; - ram_block[260] 0xc0 7.68002e+06 0.5; - ram_block[260]~feeder 0xc0 7.68002e+06 0.5; - ram_block[261] 0xc0 7.68002e+06 0.5; - ram_block[261]~feeder 0xc0 7.68002e+06 0.5; - ram_block[262] 0xc0 7.68002e+06 0.5; - ram_block[262]~feeder 0xc0 7.68002e+06 0.5; - ram_block[263] 0xc0 7.68002e+06 0.5; - ram_block[263]~feeder 0xc0 7.68002e+06 0.5; - ram_block[264] 0xc0 7.68002e+06 0.5; - ram_block[264]~feeder 0xc0 7.68002e+06 0.5; - ram_block[265] 0xc0 7.68002e+06 0.5; - ram_block[265]~feeder 0xc0 7.68002e+06 0.5; - ram_block[266] 0xc0 7.68002e+06 0.5; - ram_block[266]~feeder 0xc0 7.68002e+06 0.5; - ram_block[267] 0xc0 7.68002e+06 0.5; - ram_block[268] 0xc0 7.68002e+06 0.5; - ram_block[269] 0xc0 7.68002e+06 0.5; - ram_block[269]~feeder 0xc0 7.68002e+06 0.5; - ram_block[270] 0xc0 7.68002e+06 0.5; - ram_block[270]~feeder 0xc0 7.68002e+06 0.5; - ram_block[271] 0xc0 7.68002e+06 0.5; - ram_block[271]~feeder 0xc0 7.68002e+06 0.5; - ram_block[272] 0xc0 7.68002e+06 0.5; - ram_block[272]~feeder 0xc0 7.68002e+06 0.5; - ram_block[273] 0xc0 7.68002e+06 0.5; - ram_block[273]~feeder 0xc0 7.68002e+06 0.5; - ram_block[274] 0xc0 7.68002e+06 0.5; - ram_block[275] 0xc0 7.68002e+06 0.5; - ram_block[275]~feeder 0xc0 7.68002e+06 0.5; - ram_block[276] 0xc0 7.68002e+06 0.5; - ram_block[276]~feeder 0xc0 7.68002e+06 0.5; - ram_block[277] 0xc0 7.68002e+06 0.5; - ram_block[277]~feeder 0xc0 7.68002e+06 0.5; - ram_block[278] 0xc0 7.68002e+06 0.5; - ram_block[278]~feeder 0xc0 7.68002e+06 0.5; - ram_block[279] 0xc0 7.68002e+06 0.5; - ram_block[280] 0xc0 7.68002e+06 0.5; - ram_block[280]~feeder 0xc0 7.68002e+06 0.5; - ram_block[281] 0xc0 7.68002e+06 0.5; - ram_block[281]~feeder 0xc0 7.68002e+06 0.5; - ram_block[282] 0xc0 7.68002e+06 0.5; - ram_block[282]~feeder 0xc0 7.68002e+06 0.5; - ram_block[283] 0xc0 7.68002e+06 0.5; - ram_block[283]~feeder 0xc0 7.68002e+06 0.5; - ram_block[284] 0xc0 7.68002e+06 0.5; - ram_block[284]~feeder 0xc0 7.68002e+06 0.5; - ram_block[285] 0xc0 7.68002e+06 0.5; - ram_block[285]~feeder 0xc0 7.68002e+06 0.5; - ram_block[286] 0xc0 7.68002e+06 0.5; - ram_block[286]~feeder 0xc0 7.68002e+06 0.5; - ram_block[287] 0xc0 7.68002e+06 0.5; - ram_block[287]~feeder 0xc0 7.68002e+06 0.5; - ram_block[288] 0xc0 7.68002e+06 0.5; - ram_block[288]~feeder 0xc0 7.68002e+06 0.5; - ram_block[289] 0xc0 7.68002e+06 0.5; - ram_block[289]~feeder 0xc0 7.68002e+06 0.5; - ram_block[290] 0xc0 7.68002e+06 0.5; - ram_block[290]~feeder 0xc0 7.68002e+06 0.5; - ram_block[291] 0xc0 7.68002e+06 0.5; - ram_block[291]~feeder 0xc0 7.68002e+06 0.5; - ram_block[292] 0xc0 7.68002e+06 0.5; - ram_block[292]~feeder 0xc0 7.68002e+06 0.5; - ram_block[293] 0xc0 7.68002e+06 0.5; - ram_block[293]~feeder 0xc0 7.68002e+06 0.5; - ram_block[294] 0xc0 7.68002e+06 0.5; - ram_block[295] 0xc0 7.68002e+06 0.5; - ram_block[295]~feeder 0xc0 7.68002e+06 0.5; - ram_block[296] 0xc0 7.68002e+06 0.5; - ram_block[296]~feeder 0xc0 7.68002e+06 0.5; - ram_block[297] 0xc0 7.68002e+06 0.5; - ram_block[297]~feeder 0xc0 7.68002e+06 0.5; - ram_block[298] 0xc0 7.68002e+06 0.5; - ram_block[298]~feeder 0xc0 7.68002e+06 0.5; - ram_block[299] 0xc0 7.68002e+06 0.5; - ram_block[300] 0xc0 7.68002e+06 0.5; - ram_block[300]~feeder 0xc0 7.68002e+06 0.5; - ram_block[301] 0xc0 7.68002e+06 0.5; - ram_block[302] 0xc0 7.68002e+06 0.5; - ram_block[302]~feeder 0xc0 7.68002e+06 0.5; - ram_block[303] 0xc0 7.68002e+06 0.5; - ram_block[303]~feeder 0xc0 7.68002e+06 0.5; - ram_block[304] 0xc0 7.68002e+06 0.5; - ram_block[304]~feeder 0xc0 7.68002e+06 0.5; - ram_block[305] 0xc0 7.68002e+06 0.5; - ram_block[306] 0xc0 7.68002e+06 0.5; - ram_block[306]~feeder 0xc0 7.68002e+06 0.5; - ram_block[307] 0xc0 7.68002e+06 0.5; - ram_block[307]~feeder 0xc0 7.68002e+06 0.5; - ram_block[308] 0xc0 7.68002e+06 0.5; - ram_block[308]~feeder 0xc0 7.68002e+06 0.5; - ram_block[309] 0xc0 7.68002e+06 0.5; - ram_block[309]~feeder 0xc0 7.68002e+06 0.5; - ram_block[310] 0xc0 7.68002e+06 0.5; - ram_block[310]~feeder 0xc0 7.68002e+06 0.5; - ram_block[311] 0xc0 7.68002e+06 0.5; - ram_block[312] 0xc0 7.68002e+06 0.5; - ram_block[312]~feeder 0xc0 7.68002e+06 0.5; - ram_block[313] 0xc0 7.68002e+06 0.5; - ram_block[313]~feeder 0xc0 7.68002e+06 0.5; - ram_block[314] 0xc0 7.68002e+06 0.5; - ram_block[315] 0xc0 7.68002e+06 0.5; - ram_block[315]~feeder 0xc0 7.68002e+06 0.5; - ram_block[316] 0xc0 7.68002e+06 0.5; - ram_block[316]~feeder 0xc0 7.68002e+06 0.5; - ram_block[317] 0xc0 7.68002e+06 0.5; - ram_block[317]~feeder 0xc0 7.68002e+06 0.5; - ram_block[318] 0xc0 7.68002e+06 0.5; - ram_block[318]~feeder 0xc0 7.68002e+06 0.5; - ram_block[319] 0xc0 7.68002e+06 0.5; - ram_block[319]~feeder 0xc0 7.68002e+06 0.5; - ram_block[320] 0xc0 7.68002e+06 0.5; - ram_block[321] 0xc0 7.68002e+06 0.5; - ram_block[322] 0xc0 7.68002e+06 0.5; - ram_block[323] 0xc0 7.68002e+06 0.5; - ram_block[324] 0xc0 7.68002e+06 0.5; - ram_block[324]~feeder 0xc0 7.68002e+06 0.5; - ram_block[325] 0xc0 7.68002e+06 0.5; - ram_block[325]~feeder 0xc0 7.68002e+06 0.5; - ram_block[326] 0xc0 7.68002e+06 0.5; - ram_block[327] 0xc0 7.68002e+06 0.5; - ram_block[327]~feeder 0xc0 7.68002e+06 0.5; - ram_block[328] 0xc0 7.68002e+06 0.5; - ram_block[328]~feeder 0xc0 7.68002e+06 0.5; - ram_block[329] 0xc0 7.68002e+06 0.5; - ram_block[329]~feeder 0xc0 7.68002e+06 0.5; - ram_block[330] 0xc0 7.68002e+06 0.5; - ram_block[330]~feeder 0xc0 7.68002e+06 0.5; - ram_block[331] 0xc0 7.68002e+06 0.5; - ram_block[332] 0xc0 7.68002e+06 0.5; - ram_block[332]~feeder 0xc0 7.68002e+06 0.5; - ram_block[333] 0xc0 7.68002e+06 0.5; - ram_block[333]~feeder 0xc0 7.68002e+06 0.5; - ram_block[334] 0xc0 7.68002e+06 0.5; - ram_block[335] 0xc0 7.68002e+06 0.5; - ram_block[335]~feeder 0xc0 7.68002e+06 0.5; - ram_block[336] 0xc0 7.68002e+06 0.5; - ram_block[336]~feeder 0xc0 7.68002e+06 0.5; - ram_block[337] 0xc0 7.68002e+06 0.5; - ram_block[338] 0xc0 7.68002e+06 0.5; - ram_block[338]~feeder 0xc0 7.68002e+06 0.5; - ram_block[339] 0xc0 7.68002e+06 0.5; - ram_block[339]~feeder 0xc0 7.68002e+06 0.5; - rd_data_out_latch[0] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[1] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[2] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[3] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[4] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[5] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[6] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[7] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[8] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[9] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[10] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[11] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[12] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[13] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[14] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[15] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[16] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[17] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[18] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[19] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[20] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[21] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[22] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[23] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[24] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[25] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[26] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[27] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[28] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[29] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[30] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[31] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[32] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[33] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[34] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[35] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[36] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[37] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[38] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[39] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[40] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[41] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[42] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[43] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[44] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[45] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[46] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[47] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[48] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[49] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[50] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[51] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[52] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[53] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[54] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[55] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[56] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[57] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[58] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[59] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[60] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[61] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[62] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[63] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[64] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[65] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[66] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[67] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[68] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[69] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[70] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[71] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[72] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[73] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[74] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[75] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[76] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[77] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[78] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[79] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[80] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[81] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[82] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[83] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[84] 0xc0 7.68002e+06 0.5; - wren_reg 0xc0 7.68002e+06 0.5; - wren_reg~feeder 0xc0 32.9248 6.10352e-05; - full_dff 0xc0 7.68002e+06 0.5; - low_addressa[0] 0xc0 7.68002e+06 0.5; - low_addressa[0]~1 0xc0 2.35547e+06 0.25; - low_addressa[1] 0xc0 7.68002e+06 0.5; - low_addressa[1]~0 0xc0 2.35547e+06 0.25; - ram_read_address[0]~1 0xc0 3.18845e+06 0.5; - ram_read_address[1]~0 0xc0 4.68001e+06 0.5; - rd_ptr_lsb 0xc0 7.68002e+06 0.5; - rd_ptr_lsb~0 0xc0 4.32001e+06 0.25; - rd_ptr_lsb~1 0xc0 2.09813e+06 0.5625; - cntr_q9b:rd_ptr_msb; - _~0 0xc0 5.29501e+06 0.53125; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - cntr_7a7:usedw_counter; - _~0 0xc0 8.81789e+06 0.562523; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.6791e+06 0.5; - counter_comb_bita1 0xc0 7.67956e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - usedw_is_0_dff 0xc0 7.68002e+06 0.5; - usedw_is_1_dff 0xc0 7.68002e+06 0.5; - usedw_will_be_1~0 0xc0 3.58458e+06 0.0312748; - usedw_will_be_1~1 0xc0 4.52133e+06 0.227535; - valid_rreq 0xc0 3.36001e+06 0.125; - valid_rreq~0 0xc0 5.76001e+06 0.25; - valid_wreq~0 0xc0 1.125e+06 0.0625; - valid_wreq~1 0xc0 945002 0.0625; - valid_wreq~2 0xc0 945002 0.0625; - valid_wreq~3 0xc0 65.6207 0.00012207; - valid_wreq~4 0xc0 32.9248 6.10352e-05; - cntr_r9b:wr_ptr; - _~0 0xc0 7.67818e+06 0.500031; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.68002e+06 0.5; - counter_comb_bita1 0xc0 7.68002e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - auk_dspip_integrator:integrator[0].integration; - auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1; - \register_fifo:fifo_data[0][0] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][0]~1 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][0]~2 0xc0 4.32001e+06 0.25; - \register_fifo:fifo_data[0][1] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1]~1 0xc0 6.48002e+06 0.5; - \register_fifo:fifo_data[0][1]~2 0xc0 3.57751e+06 0.625; - \register_fifo:fifo_data[0][2] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2]~1 0xc0 5.48439e+06 0.5; - \register_fifo:fifo_data[0][2]~2 0xc0 6.3722e+06 0.4375; - \register_fifo:fifo_data[0][3] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3]~1 0xc0 5.98056e+06 0.5; - \register_fifo:fifo_data[0][3]~2 0xc0 4.88779e+06 0.53125; - \register_fifo:fifo_data[0][4] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4]~1 0xc0 5.55883e+06 0.5; - \register_fifo:fifo_data[0][4]~2 0xc0 5.4588e+06 0.484375; - \register_fifo:fifo_data[0][5] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5]~1 0xc0 5.68893e+06 0.5; - \register_fifo:fifo_data[0][5]~2 0xc0 5.11181e+06 0.507813; - \register_fifo:fifo_data[0][6] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6]~1 0xc0 5.59902e+06 0.5; - \register_fifo:fifo_data[0][6]~2 0xc0 5.2676e+06 0.496094; - \register_fifo:fifo_data[0][7] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7]~1 0xc0 5.63718e+06 0.5; - \register_fifo:fifo_data[0][7]~2 0xc0 5.18499e+06 0.501953; - \register_fifo:fifo_data[0][8] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8]~1 0xc0 5.61632e+06 0.5; - \register_fifo:fifo_data[0][8]~2 0xc0 5.22508e+06 0.499023; - \register_fifo:fifo_data[0][9] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9]~1 0xc0 5.6263e+06 0.5; - \register_fifo:fifo_data[0][9]~2 0xc0 5.20473e+06 0.500488; - \register_fifo:fifo_data[0][10] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10]~1 0xc0 5.6212e+06 0.5; - \register_fifo:fifo_data[0][10]~2 0xc0 5.21483e+06 0.499756; - \register_fifo:fifo_data[0][11] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11]~1 0xc0 5.62372e+06 0.5; - \register_fifo:fifo_data[0][11]~2 0xc0 5.20976e+06 0.500122; - \register_fifo:fifo_data[0][12] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12]~1 0xc0 5.62245e+06 0.5; - \register_fifo:fifo_data[0][12]~2 0xc0 5.21229e+06 0.499939; - \register_fifo:fifo_data[0][13] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13]~1 0xc0 5.62308e+06 0.5; - \register_fifo:fifo_data[0][13]~2 0xc0 5.21102e+06 0.500031; - \register_fifo:fifo_data[0][14] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14]~1 0xc0 5.62277e+06 0.5; - \register_fifo:fifo_data[0][14]~2 0xc0 5.21165e+06 0.499985; - \register_fifo:fifo_data[0][15] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15]~1 0xc0 5.62292e+06 0.5; - \register_fifo:fifo_data[0][15]~2 0xc0 5.21134e+06 0.500008; - \register_fifo:fifo_data[0][16] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16]~1 0xc0 5.62285e+06 0.5; - \register_fifo:fifo_data[0][16]~2 0xc0 5.21149e+06 0.499996; - \register_fifo:fifo_data[0][17] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17]~1 0xc0 5.62289e+06 0.5; - \register_fifo:fifo_data[0][17]~2 0xc0 5.21142e+06 0.500002; - \register_fifo:fifo_data[0][18] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18]~1 0xc0 5.62286e+06 0.5; - \register_fifo:fifo_data[0][18]~2 0xc0 5.21146e+06 0.499999; - \register_fifo:fifo_data[0][19] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][19]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][20] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][20]~2 0xc0 5.21145e+06 0.5; - \register_fifo:fifo_data[0][21] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][21]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][22] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22]~1 0xc0 7.06287e+06 0.5; - \register_fifo:fifo_data[0][22]~2 0xc0 7.37145e+06 0.5; - \register_fifo:fifo_data[0][23] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23]~1 0xc0 7.60288e+06 0.5; - \register_fifo:fifo_data[0][23]~2 0xc0 7.64145e+06 0.5; - \register_fifo:fifo_data[0][24] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24]~1 0xc0 7.67038e+06 0.5; - \register_fifo:fifo_data[0][24]~2 0xc0 7.6752e+06 0.5; - \register_fifo:fifo_data[0][25] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25]~1 0xc0 7.67881e+06 0.5; - \register_fifo:fifo_data[0][25]~2 0xc0 7.67942e+06 0.5; - \register_fifo:fifo_data[0][26] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26]~1 0xc0 7.67987e+06 0.5; - \register_fifo:fifo_data[0][26]~2 0xc0 7.67994e+06 0.5; - \register_fifo:fifo_data[0][27] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27]~1 0xc0 7.68e+06 0.5; - \register_fifo:fifo_data[0][27]~2 0xc0 7.68001e+06 0.5; - \register_fifo:fifo_data[0][28] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28]~1 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28]~2 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29]~1 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29]~2 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30]~1 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30]~2 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31] 0xc0 7.68002e+06 0.5; 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- \register_fifo:fifo_data[0][36] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][36]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][37] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][37]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][38] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][38]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][39] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][39]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][40] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][40]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][41] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][41]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][42] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][42]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][43] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][43]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][44] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][44]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][45] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][45]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][46] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][46]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][47] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][47]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][48] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][48]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][49] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][49]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][50] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][50]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][51] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][51]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][52] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][52]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][53] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][53]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][54] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][54]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][55] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][55]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][56] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][56]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][57] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][57]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][58] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][58]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][59] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][59]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][60] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][60]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][61] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][61]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][62] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][62]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][63] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][63]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][64] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][64]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][65] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][65]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][66] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][66]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][67] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][67]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][68] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][68]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][69] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][69]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][70] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][70]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][71] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][71]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][72] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][72]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][73] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][73]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][74] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][74]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][75] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][75]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][76] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][76]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][77] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][77]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][78] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][78]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][79] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][79]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][80] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][80]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][81] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][81]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][82] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][82]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][83] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][83]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][84] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84]~1 0xc0 7.06288e+06 0.5; - counter_module:latency_cnt_inst; - Add0~0 0xc0 4.32001e+06 0.25; - Add0~1 0xc0 1.83e+06 0.125; - count[0] 0xc0 7.68002e+06 0.5; - count[1] 0xc0 7.68002e+06 0.5; - count[1]~4 0xc0 7.43486e+06 0.46875; - count[2] 0xc0 7.68002e+06 0.5; - count[2]~1 0xc0 3.67936e+06 0.397217; - count[3] 0xc0 7.68002e+06 0.5; - count[3]~0 0xc0 4.50001e+06 0.4375; - count[3]~2 0xc0 4.06435e+06 0.38269; - count~3 0xc0 7.00455e+06 0.46875; - sample_state[0] 0xc0 7.68002e+06 0.5; - sample_state~0 0xc0 3.33001e+06 0.625; - sample_state~1 0xc0 5.04573e+06 0.671875; - state[0] 0xc0 7.68002e+06 0.5; - state~0 0xc0 8.68362e+06 0.515625; - auk_dspip_downsample:vrc_en_0.first_dsample; - counter_module:counter_fs_inst; - Add0~0 0xc0 7.68002e+06 0.5; - Add0~1 0xc0 7.68002e+06 0.5; - Add0~2 0xc0 7.68002e+06 0.5; - Add0~3 0xc0 4.32001e+06 0.75; - Add0~4 0xc0 6.96002e+06 0.5; - Add0~5 0xc0 5.88002e+06 0.125; - Add0~6 0xc0 8.94002e+06 0.5; - Add0~7 0xc0 1.71e+06 0.9375; - Add0~8 0xc0 7.63502e+06 0.5; - Add0~9 0xc0 7.20752e+06 0.03125; - Add0~10 0xc0 1.08188e+07 0.5; - Add0~11 0xc0 1.81688e+06 0.984375; - Add0~12 0xc0 8.35221e+06 0.5; - Add0~13 0xc0 7.89799e+06 0.0078125; - Add0~14 0xc0 1.151e+07 0.5; - Add0~15 0xc0 1.97543e+06 0.996094; - Add0~16 0xc0 8.60797e+06 0.5; - Add0~17 0xc0 8.11411e+06 0.00195313; - Add0~18 0xc0 1.17071e+07 0.5; - Add0~19 0xc0 2.02859e+06 0.999023; - Add0~20 0xc0 8.67933e+06 0.5; - Equal0~0 0xc0 691877 0.0625; - Equal0~1 0xc0 691877 0.0625; - Equal0~2 0xc0 4.32001e+06 0.25; - Equal0~3 0xc0 462.757 0.000488281; - count[0] 0xc0 7.68002e+06 0.5; - count[1] 0xc0 7.68002e+06 0.5; - count[2] 0xc0 7.68002e+06 0.5; - count[3] 0xc0 7.68002e+06 0.5; - count[4] 0xc0 7.68002e+06 0.5; - count[5] 0xc0 7.68002e+06 0.5; - count[6] 0xc0 7.68002e+06 0.5; - count[7] 0xc0 7.68002e+06 0.5; - count[8] 0xc0 7.68002e+06 0.5; - count[9] 0xc0 7.68002e+06 0.5; - count[10] 0xc0 7.68002e+06 0.5; - count~0 0xc0 1.71992e+07 0.499756; - count~1 0xc0 3.33001e+06 0.625; - count~2 0xc0 8.671e+06 0.499756; - auk_dspip_avalon_streaming_sink:input_sink; - scfifo:sink_FIFO; - scfifo_ef71:auto_generated; - dffe_nae 0xc0 7.68002e+06 0.5; - dffe_nae~0 0xc0 1.38e+06 0.125; - dffe_nae~1 0xc0 3.22121e+06 0.524597; - a_dpfifo_vkv:dpfifo; - _~0 0xc0 1.4175e+06 0.0625; - _~1 0xc0 3.70743e+06 0.502975; - _~2 0xc0 3.63189e+06 0.276611; - empty_dff 0xc0 7.68002e+06 0.5; - empty_dff~0 0xc0 2.00438e+06 0.3125; - empty_dff~1 0xc0 4.06256e+06 0.859583; - empty_dff~2 0xc0 2.85165e+06 0.593491; - empty_dff~3 0xc0 2.91536e+06 0.242495; - empty_dff~4 0xc0 3.76901e+06 0.441508; - empty_dff~5 0xc0 4.56251e+06 0.40721; - altsyncram_h7h1:FIFOram; - q_b[0] 0xc0 7.68002e+06 0.5; - q_b[1] 0xc0 7.68002e+06 0.5; - q_b[2] 0xc0 7.68002e+06 0.5; - q_b[3] 0xc0 7.68002e+06 0.5; - q_b[4] 0xc0 7.68002e+06 0.5; - q_b[5] 0xc0 7.68002e+06 0.5; - q_b[6] 0xc0 7.68002e+06 0.5; - q_b[7] 0xc0 7.68002e+06 0.5; - q_b[8] 0xc0 7.68002e+06 0.5; - q_b[9] 0xc0 7.68002e+06 0.5; - q_b[10] 0xc0 7.68002e+06 0.5; - q_b[11] 0xc0 7.68002e+06 0.5; - q_b[12] 0xc0 7.68002e+06 0.5; - q_b[13] 0xc0 7.68002e+06 0.5; - q_b[14] 0xc0 7.68002e+06 0.5; - q_b[15] 0xc0 7.68002e+06 0.5; - q_b[16] 0xc0 7.68002e+06 0.5; - q_b[17] 0xc0 7.68002e+06 0.5; - q_b[18] 0xc0 7.68002e+06 0.5; - q_b[19] 0xc0 7.68002e+06 0.5; - q_b[20] 0xc0 7.68002e+06 0.5; - q_b[21] 0xc0 7.68002e+06 0.5; - q_b[22] 0xc0 7.68002e+06 0.5; - full_dff 0xc0 7.68002e+06 0.5; - low_addressa[0] 0xc0 7.68002e+06 0.5; - low_addressa[0]~0 0xc0 2.44739e+06 0.25; - low_addressa[1] 0xc0 7.68002e+06 0.5; - low_addressa[1]~1 0xc0 2.44739e+06 0.25; - low_addressa[2] 0xc0 7.68002e+06 0.5; - low_addressa[2]~2 0xc0 2.44739e+06 0.25; - ram_read_address[0]~0 0xc0 8.30576e+06 0.5; - ram_read_address[1]~1 0xc0 8.30576e+06 0.5; - ram_read_address[2]~2 0xc0 4.61701e+06 0.5; - rd_ptr_lsb 0xc0 7.68002e+06 0.5; - rd_ptr_lsb~0 0xc0 1.09613e+07 0.526611; - rd_ptr_lsb~1 0xc0 4.32001e+06 0.25; - cntr_r9b:rd_ptr_msb; - _~0 0xc0 7.60652e+06 0.513306; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.68002e+06 0.5; - counter_comb_bita1 0xc0 7.68002e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - cntr_8a7:usedw_counter; - _~0 0xc0 6.00431e+06 0.638306; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.68002e+06 0.5; - counter_comb_bita1 0xc0 7.68002e+06 0.5; - counter_comb_bita1~COUT 0xc0 4.44001e+06 0.75; - counter_comb_bita2 0xc0 7.02002e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - counter_reg_bit[2] 0xc0 7.68002e+06 0.5; - usedw_is_0_dff 0xc0 7.68002e+06 0.5; - usedw_is_1_dff 0xc0 7.68002e+06 0.5; - usedw_will_be_1~0 0xc0 1.74938e+06 0.09375; - usedw_will_be_1~1 0xc0 2.19001e+06 0.125; - usedw_will_be_1~2 0xc0 1.17006e+06 0.123337; - usedw_will_be_1~3 0xc0 2.17075e+06 0.22021; - valid_rreq 0xc0 266092 0.0532227; - valid_wreq 0xc0 5.76001e+06 0.25; - cntr_s9b:wr_ptr; - _~0 0xc0 5.76001e+06 0.625; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.68002e+06 0.5; - counter_comb_bita1 0xc0 7.68002e+06 0.5; - counter_comb_bita1~COUT 0xc0 4.32001e+06 0.75; - counter_comb_bita2 0xc0 6.96002e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - counter_reg_bit[2] 0xc0 7.68002e+06 0.5; - auk_dspip_avalon_streaming_source:output_source_0; - scfifo:source_FIFO; - scfifo_ai71:auto_generated; - a_dpfifo_7qv:dpfifo; - _~0 0xc0 296837 0.03125; - _~1 0xc0 8.27419e+06 0.250488; - empty_dff 0xc0 7.68002e+06 0.5; - empty_dff~2 0xc0 4.59142e+06 0.515625; - empty_dff~3 0xc0 3.4767e+06 0.257813; - empty_dff~4 0xc0 5.13559e+06 0.255586; - altsyncram_dah1:FIFOram; - q_b[0] 0xc0 7.68002e+06 0.5; - q_b[1] 0xc0 7.68002e+06 0.5; - q_b[2] 0xc0 7.68002e+06 0.5; - q_b[3] 0xc0 7.68002e+06 0.5; - q_b[4] 0xc0 7.68002e+06 0.5; - q_b[5] 0xc0 7.68002e+06 0.5; - q_b[6] 0xc0 7.68002e+06 0.5; - q_b[7] 0xc0 7.68002e+06 0.5; - q_b[8] 0xc0 7.68002e+06 0.5; - q_b[9] 0xc0 7.68002e+06 0.5; - q_b[10] 0xc0 7.68002e+06 0.5; - q_b[11] 0xc0 7.68002e+06 0.5; - q_b[12] 0xc0 7.68002e+06 0.5; - q_b[13] 0xc0 7.68002e+06 0.5; - q_b[14] 0xc0 7.68002e+06 0.5; - q_b[15] 0xc0 7.68002e+06 0.5; - q_b[16] 0xc0 7.68002e+06 0.5; - q_b[17] 0xc0 7.68002e+06 0.5; - q_b[18] 0xc0 7.68002e+06 0.5; - q_b[19] 0xc0 7.68002e+06 0.5; - q_b[20] 0xc0 7.68002e+06 0.5; - q_b[21] 0xc0 7.68002e+06 0.5; - q_b[22] 0xc0 7.68002e+06 0.5; - q_b[23] 0xc0 7.68002e+06 0.5; - q_b[24] 0xc0 7.68002e+06 0.5; - q_b[25] 0xc0 7.68002e+06 0.5; - q_b[26] 0xc0 7.68002e+06 0.5; - q_b[27] 0xc0 7.68002e+06 0.5; - q_b[28] 0xc0 7.68002e+06 0.5; - q_b[29] 0xc0 7.68002e+06 0.5; - q_b[30] 0xc0 7.68002e+06 0.5; - q_b[31] 0xc0 7.68002e+06 0.5; - full_dff 0xc0 7.68002e+06 0.5; - low_addressa[0] 0xc0 7.68002e+06 0.5; - low_addressa[0]~0 0xc0 1.9125e+06 0.25; - low_addressa[1] 0xc0 7.68002e+06 0.5; - low_addressa[1]~1 0xc0 1.9125e+06 0.25; - low_addressa[2] 0xc0 7.68002e+06 0.5; - low_addressa[2]~2 0xc0 1.9125e+06 0.25; - low_addressa[3] 0xc0 7.68002e+06 0.5; - low_addressa[3]~3 0xc0 1.9125e+06 0.25; - low_addressa[4] 0xc0 7.68002e+06 0.5; - low_addressa[4]~4 0xc0 1.9125e+06 0.25; - ram_read_address[0]~0 0xc0 7.68002e+06 0.5; - ram_read_address[1]~1 0xc0 6.24002e+06 0.5; - ram_read_address[2]~2 0xc0 5.52001e+06 0.5; - ram_read_address[3]~3 0xc0 5.52001e+06 0.5; - ram_read_address[4]~4 0xc0 5.52001e+06 0.5; - rd_ptr_lsb 0xc0 7.68002e+06 0.5; - rd_ptr_lsb~0 0xc0 4.32001e+06 0.25; - rd_ptr_lsb~1 0xc0 4.32001e+06 0.75; - cntr_t9b:rd_ptr_msb; - _~0 0xc0 7.20002e+06 0.625; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.68002e+06 0.5; - counter_comb_bita1 0xc0 7.68002e+06 0.5; - counter_comb_bita1~COUT 0xc0 4.32001e+06 0.75; - counter_comb_bita2 0xc0 6.96002e+06 0.5; - counter_comb_bita2~COUT 0xc0 5.88002e+06 0.125; - counter_comb_bita3 0xc0 8.94002e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - counter_reg_bit[2] 0xc0 7.68002e+06 0.5; - counter_reg_bit[3] 0xc0 7.68002e+06 0.5; - cntr_aa7:usedw_counter; - _~0 0xc0 6.94174e+06 0.75; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.29752e+06 0.5; - counter_comb_bita1 0xc0 7.48877e+06 0.5; - counter_comb_bita1~COUT 0xc0 4.36963e+06 0.75; - counter_comb_bita2 0xc0 6.98483e+06 0.5; - counter_comb_bita2~COUT 0xc0 5.27105e+06 0.125; - counter_comb_bita3 0xc0 8.63554e+06 0.5; - counter_comb_bita3~COUT 0xc0 1.51144e+06 0.9375; - counter_comb_bita4 0xc0 7.53574e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - counter_reg_bit[2] 0xc0 7.68002e+06 0.5; - counter_reg_bit[3] 0xc0 7.68002e+06 0.5; - counter_reg_bit[4] 0xc0 7.68002e+06 0.5; - usedw_is_0_dff 0xc0 7.68002e+06 0.5; - usedw_is_1_dff 0xc0 7.68002e+06 0.5; - usedw_will_be_1~0 0xc0 945002 0.0625; - usedw_will_be_1~1 0xc0 105039 0.0146484; - usedw_will_be_1~2 0xc0 3.54142e+06 0.265625; - usedw_will_be_1~3 0xc0 1.94891e+06 0.138191; - usedw_will_be_1~4 0xc0 4.32001e+06 0.25; - valid_wreq~0 0xc0 1.035e+06 0.0625; - cntr_u9b:wr_ptr; - _~0 0xc0 7.26752e+06 0.53125; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.68002e+06 0.5; - counter_comb_bita1 0xc0 7.68002e+06 0.5; - counter_comb_bita1~COUT 0xc0 4.32001e+06 0.75; - counter_comb_bita2 0xc0 6.96002e+06 0.5; - counter_comb_bita2~COUT 0xc0 5.88002e+06 0.125; - counter_comb_bita3 0xc0 8.94002e+06 0.5; - counter_comb_bita3~COUT 0xc0 1.71e+06 0.9375; - counter_comb_bita4 0xc0 7.63502e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - counter_reg_bit[2] 0xc0 7.68002e+06 0.5; - counter_reg_bit[3] 0xc0 7.68002e+06 0.5; - counter_reg_bit[4] 0xc0 7.68002e+06 0.5; - source_valid_s 0xc0 7.68002e+06 0.5; - source_valid_s~0 0xc0 4.32001e+06 0.25; - rx_cic:RX_CIC_Q; - rx_cic_cic_ii_0:cic_ii_0; - alt_cic_core:core; - auk_dspip_avalon_streaming_controller:avalon_controller; - auk_dspip_avalon_streaming_small_fifo:ready_FIFO; - Decoder0~0 0xc0 381380 0.0512695; - Decoder0~1 0xc0 381380 0.0512695; - Decoder0~2 0xc0 381380 0.0512695; - Equal2~0 0xc0 2.28001e+06 0.125; - Equal3~0 0xc0 2.28001e+06 0.125; - fifo_array[0][0] 0xc0 7.68002e+06 0.5; - fifo_array[1][0] 0xc0 7.68002e+06 0.5; - fifo_array[2][0] 0xc0 7.68002e+06 0.5; - fifo_array[3][0] 0xc0 7.68002e+06 0.5; - fifo_array[4][0] 0xc0 7.68002e+06 0.5; - fifo_array[5][0] 0xc0 7.68002e+06 0.5; - fifo_array~0 0xc0 4.52249e+06 0.512817; - fifo_array~1 0xc0 4.52249e+06 0.512817; - fifo_array~2 0xc0 4.52249e+06 0.512817; - fifo_array~3 0xc0 4.52249e+06 0.512817; - fifo_array~4 0xc0 4.38394e+06 0.512817; - fifo_array~5 0xc0 4.52249e+06 0.512817; - fifo_usedw[0] 0xc0 7.68002e+06 0.5; - fifo_usedw[1] 0xc0 7.68002e+06 0.5; - fifo_usedw[2] 0xc0 7.68002e+06 0.5; - fifo_usedw~0 0xc0 5.07189e+06 0.28125; - fifo_usedw~1 0xc0 2.94312e+06 0.437378; - fifo_usedw~2 0xc0 5.31615e+06 0.5; - fifo_usedw~3 0xc0 2.49789e+06 0.123047; - fifo_usedw~4 0xc0 9.09726e+06 0.5; - Mux0~0 0xc0 3.45001e+06 0.5; - Mux0~1 0xc0 1.9396e+06 0.5; - rd_addr_ptr[0] 0xc0 7.68002e+06 0.5; - rd_addr_ptr[1] 0xc0 7.68002e+06 0.5; - rd_addr_ptr[2] 0xc0 7.68002e+06 0.5; - rd_addr_ptr~0 0xc0 2.1555e+06 0.472656; - rd_addr_ptr~1 0xc0 3.7789e+06 0.5; - rd_addr_ptr~2 0xc0 2.1555e+06 0.472656; - usedw_process~0 0xc0 1.47068e+06 0.109375; - usedw_process~1 0xc0 857764 0.794922; - wr_addr_ptr[0] 0xc0 7.68002e+06 0.5; - wr_addr_ptr[1] 0xc0 7.68002e+06 0.5; - wr_addr_ptr[2] 0xc0 7.68002e+06 0.5; - wr_addr_ptr~0 0xc0 4.9545e+06 0.5; - wr_addr_ptr~1 0xc0 2.92616e+06 0.474365; - wr_addr_ptr~2 0xc0 2.82564e+06 0.474365; - ready_fifo_rdreq~0 0xc0 1.1761e+06 0.78125; - ready_fifo_wrreq~0 0xc0 2.21546e+06 0.234375; - sink_ready_ctrl~0 0xc0 4.32001e+06 0.25; - sink_ready_ctrl~1 0xc0 3.90001e+06 0.5; - sink_ready_ctrl~2 0xc0 2.6975e+06 0.234375; - sink_ready_ctrl~3 0xc0 605954 0.106445; - stall_reg 0xc0 7.68002e+06 0.5; - stall_reg~0 0xc0 1.83e+06 0.875; - alt_cic_dec_siso:dec_one; - Equal2~0 0xc0 804377 0.0625; - Equal2~1 0xc0 4.32001e+06 0.25; - comb~0 0xc0 8.82612e+06 0.53125; - auk_dspip_differentiator:differentiate_stages[0].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84]~feeder 0xc0 7.68002e+06 0.5; - dout[0] 0xc0 7.68002e+06 0.5; - dout[0]~85 0xc0 7.68002e+06 0.5; - dout[0]~86 0xc0 4.32001e+06 0.75; - dout[1] 0xc0 7.68002e+06 0.5; - dout[1]~87 0xc0 6.48002e+06 0.5; - dout[1]~88 0xc0 3.57751e+06 0.375; - dout[2] 0xc0 7.68002e+06 0.5; - dout[2]~89 0xc0 5.48439e+06 0.5; - dout[2]~90 0xc0 4.2122e+06 0.5625; - dout[3] 0xc0 7.68002e+06 0.5; - dout[3]~91 0xc0 5.44056e+06 0.5; - dout[3]~92 0xc0 5.69779e+06 0.46875; - dout[4] 0xc0 7.68002e+06 0.5; - dout[4]~93 0xc0 5.76133e+06 0.5; - dout[4]~94 0xc0 5.02005e+06 0.515625; - dout[5] 0xc0 7.68002e+06 0.5; - dout[5]~95 0xc0 5.57924e+06 0.5; - dout[5]~96 0xc0 5.32697e+06 0.492188; - dout[6] 0xc0 7.68002e+06 0.5; - dout[6]~97 0xc0 5.65281e+06 0.5; - dout[6]~98 0xc0 5.1595e+06 0.503906; - dout[7] 0xc0 7.68002e+06 0.5; - dout[7]~99 0xc0 5.61015e+06 0.5; - dout[7]~100 0xc0 5.23898e+06 0.498047; - dout[8] 0xc0 7.68002e+06 0.5; - dout[8]~101 0xc0 5.62982e+06 0.5; - dout[8]~102 0xc0 5.19808e+06 0.500977; - dout[9] 0xc0 7.68002e+06 0.5; - dout[9]~103 0xc0 5.61955e+06 0.5; - dout[9]~104 0xc0 5.21823e+06 0.499512; - dout[10] 0xc0 7.68002e+06 0.5; - dout[10]~105 0xc0 5.62457e+06 0.5; - dout[10]~106 0xc0 5.20808e+06 0.500244; - dout[11] 0xc0 7.68002e+06 0.5; - dout[11]~107 0xc0 5.62203e+06 0.5; - dout[11]~108 0xc0 5.21313e+06 0.499878; - dout[12] 0xc0 7.68002e+06 0.5; - dout[12]~109 0xc0 5.62329e+06 0.5; - dout[12]~110 0xc0 5.2106e+06 0.500061; - dout[13] 0xc0 7.68002e+06 0.5; - dout[13]~111 0xc0 5.62266e+06 0.5; - dout[13]~112 0xc0 5.21186e+06 0.499969; - dout[14] 0xc0 7.68002e+06 0.5; - dout[14]~113 0xc0 5.62298e+06 0.5; - dout[14]~114 0xc0 5.21123e+06 0.500015; - dout[15] 0xc0 7.68002e+06 0.5; - dout[15]~115 0xc0 5.62282e+06 0.5; - dout[15]~116 0xc0 5.21155e+06 0.499992; - dout[16] 0xc0 7.68002e+06 0.5; - dout[16]~117 0xc0 5.6229e+06 0.5; - dout[16]~118 0xc0 5.21139e+06 0.500004; - dout[17] 0xc0 7.68002e+06 0.5; - dout[17]~119 0xc0 5.62286e+06 0.5; - dout[17]~120 0xc0 5.21147e+06 0.499998; - dout[18] 0xc0 7.68002e+06 0.5; - dout[18]~121 0xc0 5.62288e+06 0.5; - dout[18]~122 0xc0 5.21143e+06 0.500001; - dout[19] 0xc0 7.68002e+06 0.5; - dout[19]~123 0xc0 5.62287e+06 0.5; - dout[19]~124 0xc0 5.21145e+06 0.5; - dout[20] 0xc0 7.68002e+06 0.5; - dout[20]~125 0xc0 5.62287e+06 0.5; - dout[20]~126 0xc0 5.21144e+06 0.5; - dout[21] 0xc0 7.68002e+06 0.5; - dout[21]~127 0xc0 5.62287e+06 0.5; - dout[21]~128 0xc0 5.21144e+06 0.5; - dout[22] 0xc0 7.68002e+06 0.5; - dout[22]~129 0xc0 5.62287e+06 0.5; - dout[22]~130 0xc0 5.21144e+06 0.5; - dout[23] 0xc0 7.68002e+06 0.5; - dout[23]~131 0xc0 5.62287e+06 0.5; - dout[23]~132 0xc0 5.21144e+06 0.5; - dout[24] 0xc0 7.68002e+06 0.5; - dout[24]~133 0xc0 5.62287e+06 0.5; - dout[24]~134 0xc0 5.21144e+06 0.5; - dout[25] 0xc0 7.68002e+06 0.5; - dout[25]~135 0xc0 5.62287e+06 0.5; - dout[25]~136 0xc0 5.21144e+06 0.5; - dout[26] 0xc0 7.68002e+06 0.5; - dout[26]~137 0xc0 5.62287e+06 0.5; - dout[26]~138 0xc0 5.21144e+06 0.5; - dout[27] 0xc0 7.68002e+06 0.5; - dout[27]~139 0xc0 5.62287e+06 0.5; - dout[27]~140 0xc0 5.21144e+06 0.5; - dout[28] 0xc0 7.68002e+06 0.5; - dout[28]~141 0xc0 5.62287e+06 0.5; - dout[28]~142 0xc0 5.21144e+06 0.5; - dout[29] 0xc0 7.68002e+06 0.5; - dout[29]~143 0xc0 5.62287e+06 0.5; - dout[29]~144 0xc0 5.21144e+06 0.5; - dout[30] 0xc0 7.68002e+06 0.5; - dout[30]~145 0xc0 5.62287e+06 0.5; - dout[30]~146 0xc0 5.21144e+06 0.5; - dout[31] 0xc0 7.68002e+06 0.5; - dout[31]~147 0xc0 5.62287e+06 0.5; - dout[31]~148 0xc0 5.21144e+06 0.5; - dout[32] 0xc0 7.68002e+06 0.5; - dout[32]~149 0xc0 5.62287e+06 0.5; - dout[32]~150 0xc0 5.21144e+06 0.5; - dout[33] 0xc0 7.68002e+06 0.5; - dout[33]~151 0xc0 5.62287e+06 0.5; - dout[33]~152 0xc0 5.21144e+06 0.5; - dout[34] 0xc0 7.68002e+06 0.5; - dout[34]~153 0xc0 5.62287e+06 0.5; - dout[34]~154 0xc0 5.21144e+06 0.5; - dout[35] 0xc0 7.68002e+06 0.5; - dout[35]~155 0xc0 5.62287e+06 0.5; - dout[35]~156 0xc0 5.21144e+06 0.5; - dout[36] 0xc0 7.68002e+06 0.5; - dout[36]~157 0xc0 5.62287e+06 0.5; - dout[36]~158 0xc0 5.21144e+06 0.5; - dout[37] 0xc0 7.68002e+06 0.5; - dout[37]~159 0xc0 5.62287e+06 0.5; - dout[37]~160 0xc0 5.21144e+06 0.5; - dout[38] 0xc0 7.68002e+06 0.5; - dout[38]~161 0xc0 5.62287e+06 0.5; - dout[38]~162 0xc0 5.21144e+06 0.5; - dout[39] 0xc0 7.68002e+06 0.5; - dout[39]~163 0xc0 5.62287e+06 0.5; - dout[39]~164 0xc0 5.21144e+06 0.5; - dout[40] 0xc0 7.68002e+06 0.5; - dout[40]~165 0xc0 5.62287e+06 0.5; - dout[40]~166 0xc0 5.21144e+06 0.5; - dout[41] 0xc0 7.68002e+06 0.5; - dout[41]~167 0xc0 5.62287e+06 0.5; - dout[41]~168 0xc0 5.21144e+06 0.5; - dout[42] 0xc0 7.68002e+06 0.5; - dout[42]~169 0xc0 5.62287e+06 0.5; - dout[42]~170 0xc0 5.21144e+06 0.5; - dout[43] 0xc0 7.68002e+06 0.5; - dout[43]~171 0xc0 5.62287e+06 0.5; - dout[43]~172 0xc0 5.21144e+06 0.5; - dout[44] 0xc0 7.68002e+06 0.5; - dout[44]~173 0xc0 5.62287e+06 0.5; - dout[44]~174 0xc0 5.21144e+06 0.5; - dout[45] 0xc0 7.68002e+06 0.5; - dout[45]~175 0xc0 5.62287e+06 0.5; - dout[45]~176 0xc0 5.21144e+06 0.5; - dout[46] 0xc0 7.68002e+06 0.5; - dout[46]~177 0xc0 5.62287e+06 0.5; - dout[46]~178 0xc0 5.21144e+06 0.5; - dout[47] 0xc0 7.68002e+06 0.5; - dout[47]~179 0xc0 5.62287e+06 0.5; - dout[47]~180 0xc0 5.21144e+06 0.5; - dout[48] 0xc0 7.68002e+06 0.5; - dout[48]~181 0xc0 5.62287e+06 0.5; - dout[48]~182 0xc0 5.21144e+06 0.5; - dout[49] 0xc0 7.68002e+06 0.5; - dout[49]~183 0xc0 5.62287e+06 0.5; - dout[49]~184 0xc0 5.21144e+06 0.5; - dout[50] 0xc0 7.68002e+06 0.5; - dout[50]~185 0xc0 5.62287e+06 0.5; - dout[50]~186 0xc0 5.21144e+06 0.5; - dout[51] 0xc0 7.68002e+06 0.5; - dout[51]~187 0xc0 5.62287e+06 0.5; - dout[51]~188 0xc0 5.21144e+06 0.5; - dout[52] 0xc0 7.68002e+06 0.5; - dout[52]~189 0xc0 5.62287e+06 0.5; - dout[52]~190 0xc0 5.21144e+06 0.5; - dout[53] 0xc0 7.68002e+06 0.5; - dout[53]~191 0xc0 5.62287e+06 0.5; - dout[53]~192 0xc0 5.21144e+06 0.5; - dout[54] 0xc0 7.68002e+06 0.5; - dout[54]~194 0xc0 5.62287e+06 0.5; - dout[54]~195 0xc0 5.21144e+06 0.5; - dout[55] 0xc0 7.68002e+06 0.5; - dout[55]~196 0xc0 5.62287e+06 0.5; - dout[55]~197 0xc0 5.21144e+06 0.5; - dout[56] 0xc0 7.68002e+06 0.5; - dout[56]~198 0xc0 5.62287e+06 0.5; - dout[56]~199 0xc0 5.21144e+06 0.5; - dout[57] 0xc0 7.68002e+06 0.5; - dout[57]~200 0xc0 5.62287e+06 0.5; - dout[57]~201 0xc0 5.21144e+06 0.5; - dout[58] 0xc0 7.68002e+06 0.5; - dout[58]~202 0xc0 5.62287e+06 0.5; - dout[58]~203 0xc0 5.21144e+06 0.5; - dout[59] 0xc0 7.68002e+06 0.5; - dout[59]~204 0xc0 5.62287e+06 0.5; - dout[59]~205 0xc0 5.21144e+06 0.5; - dout[60] 0xc0 7.68002e+06 0.5; - dout[60]~206 0xc0 5.62287e+06 0.5; - dout[60]~207 0xc0 5.21144e+06 0.5; - dout[61] 0xc0 7.68002e+06 0.5; - dout[61]~208 0xc0 5.62287e+06 0.5; - dout[61]~209 0xc0 5.21144e+06 0.5; - dout[62] 0xc0 7.68002e+06 0.5; - dout[62]~210 0xc0 5.62287e+06 0.5; - dout[62]~211 0xc0 5.21144e+06 0.5; - dout[63] 0xc0 7.68002e+06 0.5; - dout[63]~212 0xc0 5.62287e+06 0.5; - dout[63]~213 0xc0 5.21144e+06 0.5; - dout[64] 0xc0 7.68002e+06 0.5; - dout[64]~214 0xc0 5.62287e+06 0.5; - dout[64]~215 0xc0 5.21144e+06 0.5; - dout[65] 0xc0 7.68002e+06 0.5; - dout[65]~216 0xc0 5.62287e+06 0.5; - dout[65]~217 0xc0 5.21144e+06 0.5; - dout[66] 0xc0 7.68002e+06 0.5; - dout[66]~218 0xc0 5.62287e+06 0.5; - dout[66]~219 0xc0 5.21144e+06 0.5; - dout[67] 0xc0 7.68002e+06 0.5; - dout[67]~220 0xc0 5.62287e+06 0.5; - dout[67]~221 0xc0 5.21144e+06 0.5; - dout[68] 0xc0 7.68002e+06 0.5; - dout[68]~222 0xc0 5.62287e+06 0.5; - dout[68]~223 0xc0 5.21144e+06 0.5; - dout[69] 0xc0 7.68002e+06 0.5; - dout[69]~224 0xc0 5.62287e+06 0.5; - dout[69]~225 0xc0 5.21144e+06 0.5; - dout[70] 0xc0 7.68002e+06 0.5; - dout[70]~226 0xc0 5.62287e+06 0.5; - dout[70]~227 0xc0 5.21144e+06 0.5; - dout[71] 0xc0 7.68002e+06 0.5; - dout[71]~228 0xc0 5.62287e+06 0.5; - dout[71]~229 0xc0 5.21144e+06 0.5; - dout[72] 0xc0 7.68002e+06 0.5; - dout[72]~230 0xc0 5.62287e+06 0.5; - dout[72]~231 0xc0 5.21144e+06 0.5; - dout[73] 0xc0 7.68002e+06 0.5; - dout[73]~232 0xc0 5.62287e+06 0.5; - dout[73]~233 0xc0 5.21144e+06 0.5; - dout[74] 0xc0 7.68002e+06 0.5; - dout[74]~234 0xc0 5.62287e+06 0.5; - dout[74]~235 0xc0 5.21144e+06 0.5; - dout[75] 0xc0 7.68002e+06 0.5; - dout[75]~236 0xc0 5.62287e+06 0.5; - dout[75]~237 0xc0 5.21144e+06 0.5; - dout[76] 0xc0 7.68002e+06 0.5; - dout[76]~238 0xc0 5.62287e+06 0.5; - dout[76]~239 0xc0 5.21144e+06 0.5; - dout[77] 0xc0 7.68002e+06 0.5; - dout[77]~240 0xc0 5.62287e+06 0.5; - dout[77]~241 0xc0 5.21144e+06 0.5; - dout[78] 0xc0 7.68002e+06 0.5; - dout[78]~242 0xc0 5.62287e+06 0.5; - dout[78]~243 0xc0 5.21144e+06 0.5; - dout[79] 0xc0 7.68002e+06 0.5; - dout[79]~244 0xc0 5.62287e+06 0.5; - dout[79]~245 0xc0 5.21144e+06 0.5; - dout[80] 0xc0 7.68002e+06 0.5; - dout[80]~246 0xc0 5.62287e+06 0.5; - dout[80]~247 0xc0 5.21144e+06 0.5; - dout[81] 0xc0 7.68002e+06 0.5; - dout[81]~248 0xc0 5.62287e+06 0.5; - dout[81]~249 0xc0 5.21144e+06 0.5; - dout[82] 0xc0 7.68002e+06 0.5; - dout[82]~250 0xc0 5.62287e+06 0.5; - dout[82]~251 0xc0 5.21144e+06 0.5; - dout[83] 0xc0 7.68002e+06 0.5; - dout[83]~252 0xc0 5.62287e+06 0.5; - dout[83]~253 0xc0 5.21144e+06 0.5; - dout[84] 0xc0 7.68002e+06 0.5; - dout[84]~254 0xc0 7.06288e+06 0.5; - dout_valid 0xc0 7.68002e+06 0.5; - dout_valid~0 0xc0 4.32001e+06 0.25; - dout~193 0xc0 3.33001e+06 0.625; - dout~256 0xc0 5.76001e+06 0.25; - auk_dspip_differentiator:differentiate_stages[1].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84]~feeder 0xc0 7.68002e+06 0.5; - dout[0] 0xc0 7.68002e+06 0.5; - dout[0]~85 0xc0 7.68002e+06 0.5; - dout[0]~86 0xc0 4.32001e+06 0.75; - dout[1] 0xc0 7.68002e+06 0.5; - dout[1]~87 0xc0 6.48002e+06 0.5; - dout[1]~88 0xc0 3.57751e+06 0.375; - dout[2] 0xc0 7.68002e+06 0.5; - dout[2]~89 0xc0 5.48439e+06 0.5; - dout[2]~90 0xc0 4.2122e+06 0.5625; - dout[3] 0xc0 7.68002e+06 0.5; - dout[3]~91 0xc0 5.44056e+06 0.5; - dout[3]~92 0xc0 5.69779e+06 0.46875; - dout[4] 0xc0 7.68002e+06 0.5; - dout[4]~93 0xc0 5.76133e+06 0.5; - dout[4]~94 0xc0 5.02005e+06 0.515625; - dout[5] 0xc0 7.68002e+06 0.5; - dout[5]~95 0xc0 5.57924e+06 0.5; - dout[5]~96 0xc0 5.32697e+06 0.492188; - dout[6] 0xc0 7.68002e+06 0.5; - dout[6]~97 0xc0 5.65281e+06 0.5; - dout[6]~98 0xc0 5.1595e+06 0.503906; - dout[7] 0xc0 7.68002e+06 0.5; - dout[7]~99 0xc0 5.61015e+06 0.5; - dout[7]~100 0xc0 5.23898e+06 0.498047; - dout[8] 0xc0 7.68002e+06 0.5; - dout[8]~101 0xc0 5.62982e+06 0.5; - dout[8]~102 0xc0 5.19808e+06 0.500977; - dout[9] 0xc0 7.68002e+06 0.5; - dout[9]~103 0xc0 5.61955e+06 0.5; - dout[9]~104 0xc0 5.21823e+06 0.499512; - dout[10] 0xc0 7.68002e+06 0.5; - dout[10]~105 0xc0 5.62457e+06 0.5; - dout[10]~106 0xc0 5.20808e+06 0.500244; - dout[11] 0xc0 7.68002e+06 0.5; - dout[11]~107 0xc0 5.62203e+06 0.5; - dout[11]~108 0xc0 5.21313e+06 0.499878; - dout[12] 0xc0 7.68002e+06 0.5; - dout[12]~109 0xc0 5.62329e+06 0.5; - dout[12]~110 0xc0 5.2106e+06 0.500061; - dout[13] 0xc0 7.68002e+06 0.5; - dout[13]~111 0xc0 5.62266e+06 0.5; - dout[13]~112 0xc0 5.21186e+06 0.499969; - dout[14] 0xc0 7.68002e+06 0.5; - dout[14]~113 0xc0 5.62298e+06 0.5; - dout[14]~114 0xc0 5.21123e+06 0.500015; - dout[15] 0xc0 7.68002e+06 0.5; - dout[15]~115 0xc0 5.62282e+06 0.5; - dout[15]~116 0xc0 5.21155e+06 0.499992; - dout[16] 0xc0 7.68002e+06 0.5; - dout[16]~117 0xc0 5.6229e+06 0.5; - dout[16]~118 0xc0 5.21139e+06 0.500004; - dout[17] 0xc0 7.68002e+06 0.5; - dout[17]~119 0xc0 5.62286e+06 0.5; - dout[17]~120 0xc0 5.21147e+06 0.499998; - dout[18] 0xc0 7.68002e+06 0.5; - dout[18]~121 0xc0 5.62288e+06 0.5; - dout[18]~122 0xc0 5.21143e+06 0.500001; - dout[19] 0xc0 7.68002e+06 0.5; - dout[19]~123 0xc0 5.62287e+06 0.5; - dout[19]~124 0xc0 5.21145e+06 0.5; - dout[20] 0xc0 7.68002e+06 0.5; - dout[20]~125 0xc0 5.62287e+06 0.5; - dout[20]~126 0xc0 5.21144e+06 0.5; - dout[21] 0xc0 7.68002e+06 0.5; - dout[21]~127 0xc0 5.62287e+06 0.5; - dout[21]~128 0xc0 5.21144e+06 0.5; - dout[22] 0xc0 7.68002e+06 0.5; - dout[22]~129 0xc0 5.62287e+06 0.5; - dout[22]~130 0xc0 5.21144e+06 0.5; - dout[23] 0xc0 7.68002e+06 0.5; - dout[23]~131 0xc0 5.62287e+06 0.5; - dout[23]~132 0xc0 5.21144e+06 0.5; - dout[24] 0xc0 7.68002e+06 0.5; - dout[24]~133 0xc0 5.62287e+06 0.5; - dout[24]~134 0xc0 5.21144e+06 0.5; - dout[25] 0xc0 7.68002e+06 0.5; - dout[25]~135 0xc0 5.62287e+06 0.5; - dout[25]~136 0xc0 5.21144e+06 0.5; - dout[26] 0xc0 7.68002e+06 0.5; - dout[26]~137 0xc0 5.62287e+06 0.5; - dout[26]~138 0xc0 5.21144e+06 0.5; - dout[27] 0xc0 7.68002e+06 0.5; - dout[27]~139 0xc0 5.62287e+06 0.5; - dout[27]~140 0xc0 5.21144e+06 0.5; - dout[28] 0xc0 7.68002e+06 0.5; - dout[28]~141 0xc0 5.62287e+06 0.5; - dout[28]~142 0xc0 5.21144e+06 0.5; - dout[29] 0xc0 7.68002e+06 0.5; - dout[29]~143 0xc0 5.62287e+06 0.5; - dout[29]~144 0xc0 5.21144e+06 0.5; - dout[30] 0xc0 7.68002e+06 0.5; - dout[30]~145 0xc0 5.62287e+06 0.5; - dout[30]~146 0xc0 5.21144e+06 0.5; - dout[31] 0xc0 7.68002e+06 0.5; - dout[31]~147 0xc0 5.62287e+06 0.5; - dout[31]~148 0xc0 5.21144e+06 0.5; - dout[32] 0xc0 7.68002e+06 0.5; - dout[32]~149 0xc0 5.62287e+06 0.5; - dout[32]~150 0xc0 5.21144e+06 0.5; - dout[33] 0xc0 7.68002e+06 0.5; - dout[33]~151 0xc0 5.62287e+06 0.5; - dout[33]~152 0xc0 5.21144e+06 0.5; - dout[34] 0xc0 7.68002e+06 0.5; - dout[34]~153 0xc0 5.62287e+06 0.5; - dout[34]~154 0xc0 5.21144e+06 0.5; - dout[35] 0xc0 7.68002e+06 0.5; - dout[35]~155 0xc0 5.62287e+06 0.5; - dout[35]~156 0xc0 5.21144e+06 0.5; - dout[36] 0xc0 7.68002e+06 0.5; - dout[36]~157 0xc0 5.62287e+06 0.5; - dout[36]~158 0xc0 5.21144e+06 0.5; - dout[37] 0xc0 7.68002e+06 0.5; - dout[37]~159 0xc0 5.62287e+06 0.5; - dout[37]~160 0xc0 5.21144e+06 0.5; - dout[38] 0xc0 7.68002e+06 0.5; - dout[38]~161 0xc0 5.62287e+06 0.5; - dout[38]~162 0xc0 5.21144e+06 0.5; - dout[39] 0xc0 7.68002e+06 0.5; - dout[39]~163 0xc0 5.62287e+06 0.5; - dout[39]~164 0xc0 5.21144e+06 0.5; - dout[40] 0xc0 7.68002e+06 0.5; - dout[40]~165 0xc0 5.62287e+06 0.5; - dout[40]~166 0xc0 5.21144e+06 0.5; - dout[41] 0xc0 7.68002e+06 0.5; - dout[41]~167 0xc0 5.62287e+06 0.5; - dout[41]~168 0xc0 5.21144e+06 0.5; - dout[42] 0xc0 7.68002e+06 0.5; - dout[42]~169 0xc0 5.62287e+06 0.5; - dout[42]~170 0xc0 5.21144e+06 0.5; - dout[43] 0xc0 7.68002e+06 0.5; - dout[43]~171 0xc0 5.62287e+06 0.5; - dout[43]~172 0xc0 5.21144e+06 0.5; - dout[44] 0xc0 7.68002e+06 0.5; - dout[44]~173 0xc0 5.62287e+06 0.5; - dout[44]~174 0xc0 5.21144e+06 0.5; - dout[45] 0xc0 7.68002e+06 0.5; - dout[45]~175 0xc0 5.62287e+06 0.5; - dout[45]~176 0xc0 5.21144e+06 0.5; - dout[46] 0xc0 7.68002e+06 0.5; - dout[46]~177 0xc0 5.62287e+06 0.5; - dout[46]~178 0xc0 5.21144e+06 0.5; - dout[47] 0xc0 7.68002e+06 0.5; - dout[47]~179 0xc0 5.62287e+06 0.5; - dout[47]~180 0xc0 5.21144e+06 0.5; - dout[48] 0xc0 7.68002e+06 0.5; - dout[48]~181 0xc0 5.62287e+06 0.5; - dout[48]~182 0xc0 5.21144e+06 0.5; - dout[49] 0xc0 7.68002e+06 0.5; - dout[49]~183 0xc0 5.62287e+06 0.5; - dout[49]~184 0xc0 5.21144e+06 0.5; - dout[50] 0xc0 7.68002e+06 0.5; - dout[50]~185 0xc0 5.62287e+06 0.5; - dout[50]~186 0xc0 5.21144e+06 0.5; - dout[51] 0xc0 7.68002e+06 0.5; - dout[51]~187 0xc0 5.62287e+06 0.5; - dout[51]~188 0xc0 5.21144e+06 0.5; - dout[52] 0xc0 7.68002e+06 0.5; - dout[52]~189 0xc0 5.62287e+06 0.5; - dout[52]~190 0xc0 5.21144e+06 0.5; - dout[53] 0xc0 7.68002e+06 0.5; - dout[53]~191 0xc0 5.62287e+06 0.5; - dout[53]~192 0xc0 5.21144e+06 0.5; - dout[54] 0xc0 7.68002e+06 0.5; - dout[54]~194 0xc0 5.62287e+06 0.5; - dout[54]~195 0xc0 5.21144e+06 0.5; - dout[55] 0xc0 7.68002e+06 0.5; - dout[55]~196 0xc0 5.62287e+06 0.5; - dout[55]~197 0xc0 5.21144e+06 0.5; - dout[56] 0xc0 7.68002e+06 0.5; - dout[56]~198 0xc0 5.62287e+06 0.5; - dout[56]~199 0xc0 5.21144e+06 0.5; - dout[57] 0xc0 7.68002e+06 0.5; - dout[57]~200 0xc0 5.62287e+06 0.5; - dout[57]~201 0xc0 5.21144e+06 0.5; - dout[58] 0xc0 7.68002e+06 0.5; - dout[58]~202 0xc0 5.62287e+06 0.5; - dout[58]~203 0xc0 5.21144e+06 0.5; - dout[59] 0xc0 7.68002e+06 0.5; - dout[59]~204 0xc0 5.62287e+06 0.5; - dout[59]~205 0xc0 5.21144e+06 0.5; - dout[60] 0xc0 7.68002e+06 0.5; - dout[60]~206 0xc0 5.62287e+06 0.5; - dout[60]~207 0xc0 5.21144e+06 0.5; - dout[61] 0xc0 7.68002e+06 0.5; - dout[61]~208 0xc0 5.62287e+06 0.5; - dout[61]~209 0xc0 5.21144e+06 0.5; - dout[62] 0xc0 7.68002e+06 0.5; - dout[62]~210 0xc0 5.62287e+06 0.5; - dout[62]~211 0xc0 5.21144e+06 0.5; - dout[63] 0xc0 7.68002e+06 0.5; - dout[63]~212 0xc0 5.62287e+06 0.5; - dout[63]~213 0xc0 5.21144e+06 0.5; - dout[64] 0xc0 7.68002e+06 0.5; - dout[64]~214 0xc0 5.62287e+06 0.5; - dout[64]~215 0xc0 5.21144e+06 0.5; - dout[65] 0xc0 7.68002e+06 0.5; - dout[65]~216 0xc0 5.62287e+06 0.5; - dout[65]~217 0xc0 5.21144e+06 0.5; - dout[66] 0xc0 7.68002e+06 0.5; - dout[66]~218 0xc0 5.62287e+06 0.5; - dout[66]~219 0xc0 5.21144e+06 0.5; - dout[67] 0xc0 7.68002e+06 0.5; - dout[67]~220 0xc0 5.62287e+06 0.5; - dout[67]~221 0xc0 5.21144e+06 0.5; - dout[68] 0xc0 7.68002e+06 0.5; - dout[68]~222 0xc0 5.62287e+06 0.5; - dout[68]~223 0xc0 5.21144e+06 0.5; - dout[69] 0xc0 7.68002e+06 0.5; - dout[69]~224 0xc0 5.62287e+06 0.5; - dout[69]~225 0xc0 5.21144e+06 0.5; - dout[70] 0xc0 7.68002e+06 0.5; - dout[70]~226 0xc0 5.62287e+06 0.5; - dout[70]~227 0xc0 5.21144e+06 0.5; - dout[71] 0xc0 7.68002e+06 0.5; - dout[71]~228 0xc0 5.62287e+06 0.5; - dout[71]~229 0xc0 5.21144e+06 0.5; - dout[72] 0xc0 7.68002e+06 0.5; - dout[72]~230 0xc0 5.62287e+06 0.5; - dout[72]~231 0xc0 5.21144e+06 0.5; - dout[73] 0xc0 7.68002e+06 0.5; - dout[73]~232 0xc0 5.62287e+06 0.5; - dout[73]~233 0xc0 5.21144e+06 0.5; - dout[74] 0xc0 7.68002e+06 0.5; - dout[74]~234 0xc0 5.62287e+06 0.5; - dout[74]~235 0xc0 5.21144e+06 0.5; - dout[75] 0xc0 7.68002e+06 0.5; - dout[75]~236 0xc0 5.62287e+06 0.5; - dout[75]~237 0xc0 5.21144e+06 0.5; - dout[76] 0xc0 7.68002e+06 0.5; - dout[76]~238 0xc0 5.62287e+06 0.5; - dout[76]~239 0xc0 5.21144e+06 0.5; - dout[77] 0xc0 7.68002e+06 0.5; - dout[77]~240 0xc0 5.62287e+06 0.5; - dout[77]~241 0xc0 5.21144e+06 0.5; - dout[78] 0xc0 7.68002e+06 0.5; - dout[78]~242 0xc0 5.62287e+06 0.5; - dout[78]~243 0xc0 5.21144e+06 0.5; - dout[79] 0xc0 7.68002e+06 0.5; - dout[79]~244 0xc0 5.62287e+06 0.5; - dout[79]~245 0xc0 5.21144e+06 0.5; - dout[80] 0xc0 7.68002e+06 0.5; - dout[80]~246 0xc0 5.62287e+06 0.5; - dout[80]~247 0xc0 5.21144e+06 0.5; - dout[81] 0xc0 7.68002e+06 0.5; - dout[81]~248 0xc0 5.62287e+06 0.5; - dout[81]~249 0xc0 5.21144e+06 0.5; - dout[82] 0xc0 7.68002e+06 0.5; - dout[82]~250 0xc0 5.62287e+06 0.5; - dout[82]~251 0xc0 5.21144e+06 0.5; - dout[83] 0xc0 7.68002e+06 0.5; - dout[83]~252 0xc0 5.62287e+06 0.5; - dout[83]~253 0xc0 5.21144e+06 0.5; - dout[84] 0xc0 7.68002e+06 0.5; - dout[84]~254 0xc0 7.06288e+06 0.5; - dout_valid 0xc0 7.68002e+06 0.5; - dout_valid~0 0xc0 4.32001e+06 0.25; - dout~193 0xc0 3.33001e+06 0.625; - dout~256 0xc0 5.76001e+06 0.25; - auk_dspip_differentiator:differentiate_stages[2].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84]~feeder 0xc0 7.68002e+06 0.5; - dout[0] 0xc0 7.68002e+06 0.5; - dout[0]~85 0xc0 7.68002e+06 0.5; - dout[0]~86 0xc0 4.32001e+06 0.75; - dout[1] 0xc0 7.68002e+06 0.5; - dout[1]~87 0xc0 6.48002e+06 0.5; - dout[1]~88 0xc0 3.57751e+06 0.375; - dout[2] 0xc0 7.68002e+06 0.5; - dout[2]~89 0xc0 5.48439e+06 0.5; - dout[2]~90 0xc0 4.2122e+06 0.5625; - dout[3] 0xc0 7.68002e+06 0.5; - dout[3]~91 0xc0 5.44056e+06 0.5; - dout[3]~92 0xc0 5.69779e+06 0.46875; - dout[4] 0xc0 7.68002e+06 0.5; - dout[4]~93 0xc0 5.76133e+06 0.5; - dout[4]~94 0xc0 5.02005e+06 0.515625; - dout[5] 0xc0 7.68002e+06 0.5; - dout[5]~95 0xc0 5.57924e+06 0.5; - dout[5]~96 0xc0 5.32697e+06 0.492188; - dout[6] 0xc0 7.68002e+06 0.5; - dout[6]~97 0xc0 5.65281e+06 0.5; - dout[6]~98 0xc0 5.1595e+06 0.503906; - dout[7] 0xc0 7.68002e+06 0.5; - dout[7]~99 0xc0 5.61015e+06 0.5; - dout[7]~100 0xc0 5.23898e+06 0.498047; - dout[8] 0xc0 7.68002e+06 0.5; - dout[8]~101 0xc0 5.62982e+06 0.5; - dout[8]~102 0xc0 5.19808e+06 0.500977; - dout[9] 0xc0 7.68002e+06 0.5; - dout[9]~103 0xc0 5.61955e+06 0.5; - dout[9]~104 0xc0 5.21823e+06 0.499512; - dout[10] 0xc0 7.68002e+06 0.5; - dout[10]~105 0xc0 5.62457e+06 0.5; - dout[10]~106 0xc0 5.20808e+06 0.500244; - dout[11] 0xc0 7.68002e+06 0.5; - dout[11]~107 0xc0 5.62203e+06 0.5; - dout[11]~108 0xc0 5.21313e+06 0.499878; - dout[12] 0xc0 7.68002e+06 0.5; - dout[12]~109 0xc0 5.62329e+06 0.5; - dout[12]~110 0xc0 5.2106e+06 0.500061; - dout[13] 0xc0 7.68002e+06 0.5; - dout[13]~111 0xc0 5.62266e+06 0.5; - dout[13]~112 0xc0 5.21186e+06 0.499969; - dout[14] 0xc0 7.68002e+06 0.5; - dout[14]~113 0xc0 5.62298e+06 0.5; - dout[14]~114 0xc0 5.21123e+06 0.500015; - dout[15] 0xc0 7.68002e+06 0.5; - dout[15]~115 0xc0 5.62282e+06 0.5; - dout[15]~116 0xc0 5.21155e+06 0.499992; - dout[16] 0xc0 7.68002e+06 0.5; - dout[16]~117 0xc0 5.6229e+06 0.5; - dout[16]~118 0xc0 5.21139e+06 0.500004; - dout[17] 0xc0 7.68002e+06 0.5; - dout[17]~119 0xc0 5.62286e+06 0.5; - dout[17]~120 0xc0 5.21147e+06 0.499998; - dout[18] 0xc0 7.68002e+06 0.5; - dout[18]~121 0xc0 5.62288e+06 0.5; - dout[18]~122 0xc0 5.21143e+06 0.500001; - dout[19] 0xc0 7.68002e+06 0.5; - dout[19]~123 0xc0 5.62287e+06 0.5; - dout[19]~124 0xc0 5.21145e+06 0.5; - dout[20] 0xc0 7.68002e+06 0.5; - dout[20]~125 0xc0 5.62287e+06 0.5; - dout[20]~126 0xc0 5.21144e+06 0.5; - dout[21] 0xc0 7.68002e+06 0.5; - dout[21]~127 0xc0 5.62287e+06 0.5; - dout[21]~128 0xc0 5.21144e+06 0.5; - dout[22] 0xc0 7.68002e+06 0.5; - dout[22]~129 0xc0 5.62287e+06 0.5; - dout[22]~130 0xc0 5.21144e+06 0.5; - dout[23] 0xc0 7.68002e+06 0.5; - dout[23]~131 0xc0 5.62287e+06 0.5; - dout[23]~132 0xc0 5.21144e+06 0.5; - dout[24] 0xc0 7.68002e+06 0.5; - dout[24]~133 0xc0 5.62287e+06 0.5; - dout[24]~134 0xc0 5.21144e+06 0.5; - dout[25] 0xc0 7.68002e+06 0.5; - dout[25]~135 0xc0 5.62287e+06 0.5; - dout[25]~136 0xc0 5.21144e+06 0.5; - dout[26] 0xc0 7.68002e+06 0.5; - dout[26]~137 0xc0 5.62287e+06 0.5; - dout[26]~138 0xc0 5.21144e+06 0.5; - dout[27] 0xc0 7.68002e+06 0.5; - dout[27]~139 0xc0 5.62287e+06 0.5; - dout[27]~140 0xc0 5.21144e+06 0.5; - dout[28] 0xc0 7.68002e+06 0.5; - dout[28]~141 0xc0 5.62287e+06 0.5; - dout[28]~142 0xc0 5.21144e+06 0.5; - dout[29] 0xc0 7.68002e+06 0.5; - dout[29]~143 0xc0 5.62287e+06 0.5; - dout[29]~144 0xc0 5.21144e+06 0.5; - dout[30] 0xc0 7.68002e+06 0.5; - dout[30]~145 0xc0 5.62287e+06 0.5; - dout[30]~146 0xc0 5.21144e+06 0.5; - dout[31] 0xc0 7.68002e+06 0.5; - dout[31]~147 0xc0 5.62287e+06 0.5; - dout[31]~148 0xc0 5.21144e+06 0.5; - dout[32] 0xc0 7.68002e+06 0.5; - dout[32]~149 0xc0 5.62287e+06 0.5; - dout[32]~150 0xc0 5.21144e+06 0.5; - dout[33] 0xc0 7.68002e+06 0.5; - dout[33]~151 0xc0 5.62287e+06 0.5; - dout[33]~152 0xc0 5.21144e+06 0.5; - dout[34] 0xc0 7.68002e+06 0.5; - dout[34]~153 0xc0 5.62287e+06 0.5; - dout[34]~154 0xc0 5.21144e+06 0.5; - dout[35] 0xc0 7.68002e+06 0.5; - dout[35]~155 0xc0 5.62287e+06 0.5; - dout[35]~156 0xc0 5.21144e+06 0.5; - dout[36] 0xc0 7.68002e+06 0.5; - dout[36]~157 0xc0 5.62287e+06 0.5; - dout[36]~158 0xc0 5.21144e+06 0.5; - dout[37] 0xc0 7.68002e+06 0.5; - dout[37]~159 0xc0 5.62287e+06 0.5; - dout[37]~160 0xc0 5.21144e+06 0.5; - dout[38] 0xc0 7.68002e+06 0.5; - dout[38]~161 0xc0 5.62287e+06 0.5; - dout[38]~162 0xc0 5.21144e+06 0.5; - dout[39] 0xc0 7.68002e+06 0.5; - dout[39]~163 0xc0 5.62287e+06 0.5; - dout[39]~164 0xc0 5.21144e+06 0.5; - dout[40] 0xc0 7.68002e+06 0.5; - dout[40]~165 0xc0 5.62287e+06 0.5; - dout[40]~166 0xc0 5.21144e+06 0.5; - dout[41] 0xc0 7.68002e+06 0.5; - dout[41]~167 0xc0 5.62287e+06 0.5; - dout[41]~168 0xc0 5.21144e+06 0.5; - dout[42] 0xc0 7.68002e+06 0.5; - dout[42]~169 0xc0 5.62287e+06 0.5; - dout[42]~170 0xc0 5.21144e+06 0.5; - dout[43] 0xc0 7.68002e+06 0.5; - dout[43]~171 0xc0 5.62287e+06 0.5; - dout[43]~172 0xc0 5.21144e+06 0.5; - dout[44] 0xc0 7.68002e+06 0.5; - dout[44]~173 0xc0 5.62287e+06 0.5; - dout[44]~174 0xc0 5.21144e+06 0.5; - dout[45] 0xc0 7.68002e+06 0.5; - dout[45]~175 0xc0 5.62287e+06 0.5; - dout[45]~176 0xc0 5.21144e+06 0.5; - dout[46] 0xc0 7.68002e+06 0.5; - dout[46]~177 0xc0 5.62287e+06 0.5; - dout[46]~178 0xc0 5.21144e+06 0.5; - dout[47] 0xc0 7.68002e+06 0.5; - dout[47]~179 0xc0 5.62287e+06 0.5; - dout[47]~180 0xc0 5.21144e+06 0.5; - dout[48] 0xc0 7.68002e+06 0.5; - dout[48]~181 0xc0 5.62287e+06 0.5; - dout[48]~182 0xc0 5.21144e+06 0.5; - dout[49] 0xc0 7.68002e+06 0.5; - dout[49]~183 0xc0 5.62287e+06 0.5; - dout[49]~184 0xc0 5.21144e+06 0.5; - dout[50] 0xc0 7.68002e+06 0.5; - dout[50]~185 0xc0 5.62287e+06 0.5; - dout[50]~186 0xc0 5.21144e+06 0.5; - dout[51] 0xc0 7.68002e+06 0.5; - dout[51]~187 0xc0 5.62287e+06 0.5; - dout[51]~188 0xc0 5.21144e+06 0.5; - dout[52] 0xc0 7.68002e+06 0.5; - dout[52]~189 0xc0 5.62287e+06 0.5; - dout[52]~190 0xc0 5.21144e+06 0.5; - dout[53] 0xc0 7.68002e+06 0.5; - dout[53]~191 0xc0 5.62287e+06 0.5; - dout[53]~192 0xc0 5.21144e+06 0.5; - dout[54] 0xc0 7.68002e+06 0.5; - dout[54]~194 0xc0 5.62287e+06 0.5; - dout[54]~195 0xc0 5.21144e+06 0.5; - dout[55] 0xc0 7.68002e+06 0.5; - dout[55]~196 0xc0 5.62287e+06 0.5; - dout[55]~197 0xc0 5.21144e+06 0.5; - dout[56] 0xc0 7.68002e+06 0.5; - dout[56]~198 0xc0 5.62287e+06 0.5; - dout[56]~199 0xc0 5.21144e+06 0.5; - dout[57] 0xc0 7.68002e+06 0.5; - dout[57]~200 0xc0 5.62287e+06 0.5; - dout[57]~201 0xc0 5.21144e+06 0.5; - dout[58] 0xc0 7.68002e+06 0.5; - dout[58]~202 0xc0 5.62287e+06 0.5; - dout[58]~203 0xc0 5.21144e+06 0.5; - dout[59] 0xc0 7.68002e+06 0.5; - dout[59]~204 0xc0 5.62287e+06 0.5; - dout[59]~205 0xc0 5.21144e+06 0.5; - dout[60] 0xc0 7.68002e+06 0.5; - dout[60]~206 0xc0 5.62287e+06 0.5; - dout[60]~207 0xc0 5.21144e+06 0.5; - dout[61] 0xc0 7.68002e+06 0.5; - dout[61]~208 0xc0 5.62287e+06 0.5; - dout[61]~209 0xc0 5.21144e+06 0.5; - dout[62] 0xc0 7.68002e+06 0.5; - dout[62]~210 0xc0 5.62287e+06 0.5; - dout[62]~211 0xc0 5.21144e+06 0.5; - dout[63] 0xc0 7.68002e+06 0.5; - dout[63]~212 0xc0 5.62287e+06 0.5; - dout[63]~213 0xc0 5.21144e+06 0.5; - dout[64] 0xc0 7.68002e+06 0.5; - dout[64]~214 0xc0 5.62287e+06 0.5; - dout[64]~215 0xc0 5.21144e+06 0.5; - dout[65] 0xc0 7.68002e+06 0.5; - dout[65]~216 0xc0 5.62287e+06 0.5; - dout[65]~217 0xc0 5.21144e+06 0.5; - dout[66] 0xc0 7.68002e+06 0.5; - dout[66]~218 0xc0 5.62287e+06 0.5; - dout[66]~219 0xc0 5.21144e+06 0.5; - dout[67] 0xc0 7.68002e+06 0.5; - dout[67]~220 0xc0 5.62287e+06 0.5; - dout[67]~221 0xc0 5.21144e+06 0.5; - dout[68] 0xc0 7.68002e+06 0.5; - dout[68]~222 0xc0 5.62287e+06 0.5; - dout[68]~223 0xc0 5.21144e+06 0.5; - dout[69] 0xc0 7.68002e+06 0.5; - dout[69]~224 0xc0 5.62287e+06 0.5; - dout[69]~225 0xc0 5.21144e+06 0.5; - dout[70] 0xc0 7.68002e+06 0.5; - dout[70]~226 0xc0 5.62287e+06 0.5; - dout[70]~227 0xc0 5.21144e+06 0.5; - dout[71] 0xc0 7.68002e+06 0.5; - dout[71]~228 0xc0 5.62287e+06 0.5; - dout[71]~229 0xc0 5.21144e+06 0.5; - dout[72] 0xc0 7.68002e+06 0.5; - dout[72]~230 0xc0 5.62287e+06 0.5; - dout[72]~231 0xc0 5.21144e+06 0.5; - dout[73] 0xc0 7.68002e+06 0.5; - dout[73]~232 0xc0 5.62287e+06 0.5; - dout[73]~233 0xc0 5.21144e+06 0.5; - dout[74] 0xc0 7.68002e+06 0.5; - dout[74]~234 0xc0 5.62287e+06 0.5; - dout[74]~235 0xc0 5.21144e+06 0.5; - dout[75] 0xc0 7.68002e+06 0.5; - dout[75]~236 0xc0 5.62287e+06 0.5; - dout[75]~237 0xc0 5.21144e+06 0.5; - dout[76] 0xc0 7.68002e+06 0.5; - dout[76]~238 0xc0 5.62287e+06 0.5; - dout[76]~239 0xc0 5.21144e+06 0.5; - dout[77] 0xc0 7.68002e+06 0.5; - dout[77]~240 0xc0 5.62287e+06 0.5; - dout[77]~241 0xc0 5.21144e+06 0.5; - dout[78] 0xc0 7.68002e+06 0.5; - dout[78]~242 0xc0 5.62287e+06 0.5; - dout[78]~243 0xc0 5.21144e+06 0.5; - dout[79] 0xc0 7.68002e+06 0.5; - dout[79]~244 0xc0 5.62287e+06 0.5; - dout[79]~245 0xc0 5.21144e+06 0.5; - dout[80] 0xc0 7.68002e+06 0.5; - dout[80]~246 0xc0 5.62287e+06 0.5; - dout[80]~247 0xc0 5.21144e+06 0.5; - dout[81] 0xc0 7.68002e+06 0.5; - dout[81]~248 0xc0 5.62287e+06 0.5; - dout[81]~249 0xc0 5.21144e+06 0.5; - dout[82] 0xc0 7.68002e+06 0.5; - dout[82]~250 0xc0 5.62287e+06 0.5; - dout[82]~251 0xc0 5.21144e+06 0.5; - dout[83] 0xc0 7.68002e+06 0.5; - dout[83]~252 0xc0 5.62287e+06 0.5; - dout[83]~253 0xc0 5.21144e+06 0.5; - dout[84] 0xc0 7.68002e+06 0.5; - dout[84]~254 0xc0 5.62287e+06 0.5; - dout_valid 0xc0 7.68002e+06 0.5; - dout_valid~0 0xc0 4.32001e+06 0.25; - dout~193 0xc0 3.33001e+06 0.625; - dout~256 0xc0 5.76001e+06 0.25; - auk_dspip_differentiator:differentiate_stages[3].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84] 0xc0 7.68002e+06 0.5; - dout[0] 0xc0 7.68002e+06 0.5; - dout[0]~85 0xc0 7.68002e+06 0.5; - dout[0]~86 0xc0 4.32001e+06 0.75; - dout[1] 0xc0 7.68002e+06 0.5; - dout[1]~87 0xc0 6.48002e+06 0.5; - dout[1]~88 0xc0 3.57751e+06 0.375; - dout[2] 0xc0 7.68002e+06 0.5; - dout[2]~89 0xc0 5.48439e+06 0.5; - dout[2]~90 0xc0 4.2122e+06 0.5625; - dout[3] 0xc0 7.68002e+06 0.5; - dout[3]~91 0xc0 5.44056e+06 0.5; - dout[3]~92 0xc0 5.69779e+06 0.46875; - dout[4] 0xc0 7.68002e+06 0.5; - dout[4]~93 0xc0 5.76133e+06 0.5; - dout[4]~94 0xc0 5.02005e+06 0.515625; - dout[5] 0xc0 7.68002e+06 0.5; - dout[5]~95 0xc0 5.57924e+06 0.5; - dout[5]~96 0xc0 5.32697e+06 0.492188; - dout[6] 0xc0 7.68002e+06 0.5; - dout[6]~97 0xc0 5.65281e+06 0.5; - dout[6]~98 0xc0 5.1595e+06 0.503906; - dout[7] 0xc0 7.68002e+06 0.5; - dout[7]~99 0xc0 5.61015e+06 0.5; - dout[7]~100 0xc0 5.23898e+06 0.498047; - dout[8] 0xc0 7.68002e+06 0.5; - dout[8]~101 0xc0 5.62982e+06 0.5; - dout[8]~102 0xc0 5.19808e+06 0.500977; - dout[9] 0xc0 7.68002e+06 0.5; - dout[9]~103 0xc0 5.61955e+06 0.5; - dout[9]~104 0xc0 5.21823e+06 0.499512; - dout[10] 0xc0 7.68002e+06 0.5; - dout[10]~105 0xc0 5.62457e+06 0.5; - dout[10]~106 0xc0 5.20808e+06 0.500244; - dout[11] 0xc0 7.68002e+06 0.5; - dout[11]~107 0xc0 5.62203e+06 0.5; - dout[11]~108 0xc0 5.21313e+06 0.499878; - dout[12] 0xc0 7.68002e+06 0.5; - dout[12]~109 0xc0 5.62329e+06 0.5; - dout[12]~110 0xc0 5.2106e+06 0.500061; - dout[13] 0xc0 7.68002e+06 0.5; - dout[13]~111 0xc0 5.62266e+06 0.5; - dout[13]~112 0xc0 5.21186e+06 0.499969; - dout[14] 0xc0 7.68002e+06 0.5; - dout[14]~113 0xc0 5.62298e+06 0.5; - dout[14]~114 0xc0 5.21123e+06 0.500015; - dout[15] 0xc0 7.68002e+06 0.5; - dout[15]~115 0xc0 5.62282e+06 0.5; - dout[15]~116 0xc0 5.21155e+06 0.499992; - dout[16] 0xc0 7.68002e+06 0.5; - dout[16]~117 0xc0 5.6229e+06 0.5; - dout[16]~118 0xc0 5.21139e+06 0.500004; - dout[17] 0xc0 7.68002e+06 0.5; - dout[17]~119 0xc0 5.62286e+06 0.5; - dout[17]~120 0xc0 5.21147e+06 0.499998; - dout[18] 0xc0 7.68002e+06 0.5; - dout[18]~121 0xc0 5.62288e+06 0.5; - dout[18]~122 0xc0 5.21143e+06 0.500001; - dout[19] 0xc0 7.68002e+06 0.5; - dout[19]~123 0xc0 5.62287e+06 0.5; - dout[19]~124 0xc0 5.21145e+06 0.5; - dout[20] 0xc0 7.68002e+06 0.5; - dout[20]~125 0xc0 5.62287e+06 0.5; - dout[20]~126 0xc0 5.21144e+06 0.5; - dout[21] 0xc0 7.68002e+06 0.5; - dout[21]~127 0xc0 5.62287e+06 0.5; - dout[21]~128 0xc0 5.21144e+06 0.5; - dout[22] 0xc0 7.68002e+06 0.5; - dout[22]~129 0xc0 5.62287e+06 0.5; - dout[22]~130 0xc0 5.21144e+06 0.5; - dout[23] 0xc0 7.68002e+06 0.5; - dout[23]~131 0xc0 5.62287e+06 0.5; - dout[23]~132 0xc0 5.21144e+06 0.5; - dout[24] 0xc0 7.68002e+06 0.5; - dout[24]~133 0xc0 5.62287e+06 0.5; - dout[24]~134 0xc0 5.21144e+06 0.5; - dout[25] 0xc0 7.68002e+06 0.5; - dout[25]~135 0xc0 5.62287e+06 0.5; - dout[25]~136 0xc0 5.21144e+06 0.5; - dout[26] 0xc0 7.68002e+06 0.5; - dout[26]~137 0xc0 5.62287e+06 0.5; - dout[26]~138 0xc0 5.21144e+06 0.5; - dout[27] 0xc0 7.68002e+06 0.5; - dout[27]~139 0xc0 5.62287e+06 0.5; - dout[27]~140 0xc0 5.21144e+06 0.5; - dout[28] 0xc0 7.68002e+06 0.5; - dout[28]~141 0xc0 5.62287e+06 0.5; - dout[28]~142 0xc0 5.21144e+06 0.5; - dout[29] 0xc0 7.68002e+06 0.5; - dout[29]~143 0xc0 5.62287e+06 0.5; - dout[29]~144 0xc0 5.21144e+06 0.5; - dout[30] 0xc0 7.68002e+06 0.5; - dout[30]~145 0xc0 5.62287e+06 0.5; - dout[30]~146 0xc0 5.21144e+06 0.5; - dout[31] 0xc0 7.68002e+06 0.5; - dout[31]~147 0xc0 5.62287e+06 0.5; - dout[31]~148 0xc0 5.21144e+06 0.5; - dout[32] 0xc0 7.68002e+06 0.5; - dout[32]~149 0xc0 5.62287e+06 0.5; - dout[32]~150 0xc0 5.21144e+06 0.5; - dout[33] 0xc0 7.68002e+06 0.5; - dout[33]~151 0xc0 5.62287e+06 0.5; - dout[33]~152 0xc0 5.21144e+06 0.5; - dout[34] 0xc0 7.68002e+06 0.5; - dout[34]~153 0xc0 5.62287e+06 0.5; - dout[34]~154 0xc0 5.21144e+06 0.5; - dout[35] 0xc0 7.68002e+06 0.5; - dout[35]~155 0xc0 5.62287e+06 0.5; - dout[35]~156 0xc0 5.21144e+06 0.5; - dout[36] 0xc0 7.68002e+06 0.5; - dout[36]~157 0xc0 5.62287e+06 0.5; - dout[36]~158 0xc0 5.21144e+06 0.5; - dout[37] 0xc0 7.68002e+06 0.5; - dout[37]~159 0xc0 5.62287e+06 0.5; - dout[37]~160 0xc0 5.21144e+06 0.5; - dout[38] 0xc0 7.68002e+06 0.5; - dout[38]~161 0xc0 5.62287e+06 0.5; - dout[38]~162 0xc0 5.21144e+06 0.5; - dout[39] 0xc0 7.68002e+06 0.5; - dout[39]~163 0xc0 5.62287e+06 0.5; - dout[39]~164 0xc0 5.21144e+06 0.5; - dout[40] 0xc0 7.68002e+06 0.5; - dout[40]~165 0xc0 5.62287e+06 0.5; - dout[40]~166 0xc0 5.21144e+06 0.5; - dout[41] 0xc0 7.68002e+06 0.5; - dout[41]~167 0xc0 5.62287e+06 0.5; - dout[41]~168 0xc0 5.21144e+06 0.5; - dout[42] 0xc0 7.68002e+06 0.5; - dout[42]~169 0xc0 5.62287e+06 0.5; - dout[42]~170 0xc0 5.21144e+06 0.5; - dout[43] 0xc0 7.68002e+06 0.5; - dout[43]~171 0xc0 5.62287e+06 0.5; - dout[43]~172 0xc0 5.21144e+06 0.5; - dout[44] 0xc0 7.68002e+06 0.5; - dout[44]~173 0xc0 5.62287e+06 0.5; - dout[44]~174 0xc0 5.21144e+06 0.5; - dout[45] 0xc0 7.68002e+06 0.5; - dout[45]~175 0xc0 5.62287e+06 0.5; - dout[45]~176 0xc0 5.21144e+06 0.5; - dout[46] 0xc0 7.68002e+06 0.5; - dout[46]~177 0xc0 5.62287e+06 0.5; - dout[46]~178 0xc0 5.21144e+06 0.5; - dout[47] 0xc0 7.68002e+06 0.5; - dout[47]~179 0xc0 5.62287e+06 0.5; - dout[47]~180 0xc0 5.21144e+06 0.5; - dout[48] 0xc0 7.68002e+06 0.5; - dout[48]~181 0xc0 5.62287e+06 0.5; - dout[48]~182 0xc0 5.21144e+06 0.5; - dout[49] 0xc0 7.68002e+06 0.5; - dout[49]~183 0xc0 5.62287e+06 0.5; - dout[49]~184 0xc0 5.21144e+06 0.5; - dout[50] 0xc0 7.68002e+06 0.5; - dout[50]~185 0xc0 5.62287e+06 0.5; - dout[50]~186 0xc0 5.21144e+06 0.5; - dout[51] 0xc0 7.68002e+06 0.5; - dout[51]~187 0xc0 5.62287e+06 0.5; - dout[51]~188 0xc0 5.21144e+06 0.5; - dout[52] 0xc0 7.68002e+06 0.5; - dout[52]~189 0xc0 5.62287e+06 0.5; - dout[52]~190 0xc0 5.21144e+06 0.5; - dout[53] 0xc0 7.68002e+06 0.5; - dout[53]~191 0xc0 5.62287e+06 0.5; - dout[53]~192 0xc0 5.21144e+06 0.5; - dout[54] 0xc0 7.68002e+06 0.5; - dout[54]~194 0xc0 5.62287e+06 0.5; - dout[54]~195 0xc0 5.21144e+06 0.5; - dout[55] 0xc0 7.68002e+06 0.5; - dout[55]~196 0xc0 5.62287e+06 0.5; - dout[55]~197 0xc0 5.21144e+06 0.5; - dout[56] 0xc0 7.68002e+06 0.5; - dout[56]~198 0xc0 5.62287e+06 0.5; - dout[56]~199 0xc0 5.21144e+06 0.5; - dout[57] 0xc0 7.68002e+06 0.5; - dout[57]~200 0xc0 5.62287e+06 0.5; - dout[57]~201 0xc0 5.21144e+06 0.5; - dout[58] 0xc0 7.68002e+06 0.5; - dout[58]~202 0xc0 5.62287e+06 0.5; - dout[58]~203 0xc0 5.21144e+06 0.5; - dout[59] 0xc0 7.68002e+06 0.5; - dout[59]~204 0xc0 5.62287e+06 0.5; - dout[59]~205 0xc0 5.21144e+06 0.5; - dout[60] 0xc0 7.68002e+06 0.5; - dout[60]~206 0xc0 5.62287e+06 0.5; - dout[60]~207 0xc0 5.21144e+06 0.5; - dout[61] 0xc0 7.68002e+06 0.5; - dout[61]~208 0xc0 5.62287e+06 0.5; - dout[61]~209 0xc0 5.21144e+06 0.5; - dout[62] 0xc0 7.68002e+06 0.5; - dout[62]~210 0xc0 5.62287e+06 0.5; - dout[62]~211 0xc0 5.21144e+06 0.5; - dout[63] 0xc0 7.68002e+06 0.5; - dout[63]~212 0xc0 5.62287e+06 0.5; - dout[63]~213 0xc0 5.21144e+06 0.5; - dout[64] 0xc0 7.68002e+06 0.5; - dout[64]~214 0xc0 5.62287e+06 0.5; - dout[64]~215 0xc0 5.21144e+06 0.5; - dout[65] 0xc0 7.68002e+06 0.5; - dout[65]~216 0xc0 5.62287e+06 0.5; - dout[65]~217 0xc0 5.21144e+06 0.5; - dout[66] 0xc0 7.68002e+06 0.5; - dout[66]~218 0xc0 5.62287e+06 0.5; - dout[66]~219 0xc0 5.21144e+06 0.5; - dout[67] 0xc0 7.68002e+06 0.5; - dout[67]~220 0xc0 5.62287e+06 0.5; - dout[67]~221 0xc0 5.21144e+06 0.5; - dout[68] 0xc0 7.68002e+06 0.5; - dout[68]~222 0xc0 5.62287e+06 0.5; - dout[68]~223 0xc0 5.21144e+06 0.5; - dout[69] 0xc0 7.68002e+06 0.5; - dout[69]~224 0xc0 5.62287e+06 0.5; - dout[69]~225 0xc0 5.21144e+06 0.5; - dout[70] 0xc0 7.68002e+06 0.5; - dout[70]~226 0xc0 5.62287e+06 0.5; - dout[70]~227 0xc0 5.21144e+06 0.5; - dout[71] 0xc0 7.68002e+06 0.5; - dout[71]~228 0xc0 5.62287e+06 0.5; - dout[71]~229 0xc0 5.21144e+06 0.5; - dout[72] 0xc0 7.68002e+06 0.5; - dout[72]~230 0xc0 5.62287e+06 0.5; - dout[72]~231 0xc0 5.21144e+06 0.5; - dout[73] 0xc0 7.68002e+06 0.5; - dout[73]~232 0xc0 5.62287e+06 0.5; - dout[73]~233 0xc0 5.21144e+06 0.5; - dout[74] 0xc0 7.68002e+06 0.5; - dout[74]~234 0xc0 5.62287e+06 0.5; - dout[74]~235 0xc0 5.21144e+06 0.5; - dout[75] 0xc0 7.68002e+06 0.5; - dout[75]~236 0xc0 5.62287e+06 0.5; - dout[75]~237 0xc0 5.21144e+06 0.5; - dout[76] 0xc0 7.68002e+06 0.5; - dout[76]~238 0xc0 5.62287e+06 0.5; - dout[76]~239 0xc0 5.21144e+06 0.5; - dout[77] 0xc0 7.68002e+06 0.5; - dout[77]~240 0xc0 5.62287e+06 0.5; - dout[77]~241 0xc0 5.21144e+06 0.5; - dout[78] 0xc0 7.68002e+06 0.5; - dout[78]~242 0xc0 5.62287e+06 0.5; - dout[78]~243 0xc0 5.21144e+06 0.5; - dout[79] 0xc0 7.68002e+06 0.5; - dout[79]~244 0xc0 5.62287e+06 0.5; - dout[79]~245 0xc0 5.21144e+06 0.5; - dout[80] 0xc0 7.68002e+06 0.5; - dout[80]~246 0xc0 5.62287e+06 0.5; - dout[80]~247 0xc0 5.21144e+06 0.5; - dout[81] 0xc0 7.68002e+06 0.5; - dout[81]~248 0xc0 5.62287e+06 0.5; - dout[81]~249 0xc0 5.21144e+06 0.5; - dout[82] 0xc0 7.68002e+06 0.5; - dout[82]~250 0xc0 5.62287e+06 0.5; - dout[82]~251 0xc0 5.21144e+06 0.5; - dout[83] 0xc0 7.68002e+06 0.5; - dout[83]~252 0xc0 5.62287e+06 0.5; - dout[83]~253 0xc0 5.21144e+06 0.5; - dout[84] 0xc0 7.68002e+06 0.5; - dout[84]~254 0xc0 7.06288e+06 0.5; - dout_valid 0xc0 7.68002e+06 0.5; - dout_valid~0 0xc0 4.32001e+06 0.25; - dout~193 0xc0 3.33001e+06 0.625; - dout~256 0xc0 5.76001e+06 0.25; - auk_dspip_differentiator:differentiate_stages[4].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84]~feeder 0xc0 7.68002e+06 0.5; - dout[0] 0xc0 7.68002e+06 0.5; - dout[0]~85 0xc0 7.68002e+06 0.5; - dout[0]~86 0xc0 4.32001e+06 0.75; - dout[1] 0xc0 7.68002e+06 0.5; - dout[1]~87 0xc0 6.48002e+06 0.5; - dout[1]~88 0xc0 3.57751e+06 0.375; - dout[2] 0xc0 7.68002e+06 0.5; - dout[2]~89 0xc0 5.48439e+06 0.5; - dout[2]~90 0xc0 4.2122e+06 0.5625; - dout[3] 0xc0 7.68002e+06 0.5; - dout[3]~91 0xc0 5.44056e+06 0.5; - dout[3]~92 0xc0 5.69779e+06 0.46875; - dout[4] 0xc0 7.68002e+06 0.5; - dout[4]~93 0xc0 5.76133e+06 0.5; - dout[4]~94 0xc0 5.02005e+06 0.515625; - dout[5] 0xc0 7.68002e+06 0.5; - dout[5]~95 0xc0 5.57924e+06 0.5; - dout[5]~96 0xc0 5.32697e+06 0.492188; - dout[6] 0xc0 7.68002e+06 0.5; - dout[6]~97 0xc0 5.65281e+06 0.5; - dout[6]~98 0xc0 5.1595e+06 0.503906; - dout[7] 0xc0 7.68002e+06 0.5; - dout[7]~99 0xc0 5.61015e+06 0.5; - dout[7]~100 0xc0 5.23898e+06 0.498047; - dout[8] 0xc0 7.68002e+06 0.5; - dout[8]~101 0xc0 5.62982e+06 0.5; - dout[8]~102 0xc0 5.19808e+06 0.500977; - dout[9] 0xc0 7.68002e+06 0.5; - dout[9]~103 0xc0 5.61955e+06 0.5; - dout[9]~104 0xc0 5.21823e+06 0.499512; - dout[10] 0xc0 7.68002e+06 0.5; - dout[10]~105 0xc0 5.62457e+06 0.5; - dout[10]~106 0xc0 5.20808e+06 0.500244; - dout[11] 0xc0 7.68002e+06 0.5; - dout[11]~107 0xc0 5.62203e+06 0.5; - dout[11]~108 0xc0 5.21313e+06 0.499878; - dout[12] 0xc0 7.68002e+06 0.5; - dout[12]~109 0xc0 5.62329e+06 0.5; - dout[12]~110 0xc0 5.2106e+06 0.500061; - dout[13] 0xc0 7.68002e+06 0.5; - dout[13]~111 0xc0 5.62266e+06 0.5; - dout[13]~112 0xc0 5.21186e+06 0.499969; - dout[14] 0xc0 7.68002e+06 0.5; - dout[14]~113 0xc0 5.62298e+06 0.5; - dout[14]~114 0xc0 5.21123e+06 0.500015; - dout[15] 0xc0 7.68002e+06 0.5; - dout[15]~115 0xc0 5.62282e+06 0.5; - dout[15]~116 0xc0 5.21155e+06 0.499992; - dout[16] 0xc0 7.68002e+06 0.5; - dout[16]~117 0xc0 5.6229e+06 0.5; - dout[16]~118 0xc0 5.21139e+06 0.500004; - dout[17] 0xc0 7.68002e+06 0.5; - dout[17]~119 0xc0 5.62286e+06 0.5; - dout[17]~120 0xc0 5.21147e+06 0.499998; - dout[18] 0xc0 7.68002e+06 0.5; - dout[18]~121 0xc0 5.62288e+06 0.5; - dout[18]~122 0xc0 5.21143e+06 0.500001; - dout[19] 0xc0 7.68002e+06 0.5; - dout[19]~123 0xc0 5.62287e+06 0.5; - dout[19]~124 0xc0 5.21145e+06 0.5; - dout[20] 0xc0 7.68002e+06 0.5; - dout[20]~125 0xc0 5.62287e+06 0.5; - dout[20]~126 0xc0 5.21144e+06 0.5; - dout[21] 0xc0 7.68002e+06 0.5; - dout[21]~127 0xc0 5.62287e+06 0.5; - dout[21]~128 0xc0 5.21144e+06 0.5; - dout[22] 0xc0 7.68002e+06 0.5; - dout[22]~129 0xc0 5.62287e+06 0.5; - dout[22]~130 0xc0 5.21144e+06 0.5; - dout[23] 0xc0 7.68002e+06 0.5; - dout[23]~131 0xc0 5.62287e+06 0.5; - dout[23]~132 0xc0 5.21144e+06 0.5; - dout[24] 0xc0 7.68002e+06 0.5; - dout[24]~133 0xc0 5.62287e+06 0.5; - dout[24]~134 0xc0 5.21144e+06 0.5; - dout[25] 0xc0 7.68002e+06 0.5; - dout[25]~135 0xc0 5.62287e+06 0.5; - dout[25]~136 0xc0 5.21144e+06 0.5; - dout[26] 0xc0 7.68002e+06 0.5; - dout[26]~137 0xc0 5.62287e+06 0.5; - dout[26]~138 0xc0 5.21144e+06 0.5; - dout[27] 0xc0 7.68002e+06 0.5; - dout[27]~139 0xc0 5.62287e+06 0.5; - dout[27]~140 0xc0 5.21144e+06 0.5; - dout[28] 0xc0 7.68002e+06 0.5; - dout[28]~141 0xc0 5.62287e+06 0.5; - dout[28]~142 0xc0 5.21144e+06 0.5; - dout[29] 0xc0 7.68002e+06 0.5; - dout[29]~143 0xc0 5.62287e+06 0.5; - dout[29]~144 0xc0 5.21144e+06 0.5; - dout[30] 0xc0 7.68002e+06 0.5; - dout[30]~145 0xc0 5.62287e+06 0.5; - dout[30]~146 0xc0 5.21144e+06 0.5; - dout[31] 0xc0 7.68002e+06 0.5; - dout[31]~147 0xc0 5.62287e+06 0.5; - dout[31]~148 0xc0 5.21144e+06 0.5; - dout[32] 0xc0 7.68002e+06 0.5; - dout[32]~149 0xc0 5.62287e+06 0.5; - dout[32]~150 0xc0 5.21144e+06 0.5; - dout[33] 0xc0 7.68002e+06 0.5; - dout[33]~151 0xc0 5.62287e+06 0.5; - dout[33]~152 0xc0 5.21144e+06 0.5; - dout[34] 0xc0 7.68002e+06 0.5; - dout[34]~153 0xc0 5.62287e+06 0.5; - dout[34]~154 0xc0 5.21144e+06 0.5; - dout[35] 0xc0 7.68002e+06 0.5; - dout[35]~155 0xc0 5.62287e+06 0.5; - dout[35]~156 0xc0 5.21144e+06 0.5; - dout[36] 0xc0 7.68002e+06 0.5; - dout[36]~157 0xc0 5.62287e+06 0.5; - dout[36]~158 0xc0 5.21144e+06 0.5; - dout[37] 0xc0 7.68002e+06 0.5; - dout[37]~159 0xc0 5.62287e+06 0.5; - dout[37]~160 0xc0 5.21144e+06 0.5; - dout[38] 0xc0 7.68002e+06 0.5; - dout[38]~161 0xc0 5.62287e+06 0.5; - dout[38]~162 0xc0 5.21144e+06 0.5; - dout[39] 0xc0 7.68002e+06 0.5; - dout[39]~163 0xc0 5.62287e+06 0.5; - dout[39]~164 0xc0 5.21144e+06 0.5; - dout[40] 0xc0 7.68002e+06 0.5; - dout[40]~165 0xc0 5.62287e+06 0.5; - dout[40]~166 0xc0 5.21144e+06 0.5; - dout[41] 0xc0 7.68002e+06 0.5; - dout[41]~167 0xc0 5.62287e+06 0.5; - dout[41]~168 0xc0 5.21144e+06 0.5; - dout[42] 0xc0 7.68002e+06 0.5; - dout[42]~169 0xc0 5.62287e+06 0.5; - dout[42]~170 0xc0 5.21144e+06 0.5; - dout[43] 0xc0 7.68002e+06 0.5; - dout[43]~171 0xc0 5.62287e+06 0.5; - dout[43]~172 0xc0 5.21144e+06 0.5; - dout[44] 0xc0 7.68002e+06 0.5; - dout[44]~173 0xc0 5.62287e+06 0.5; - dout[44]~174 0xc0 5.21144e+06 0.5; - dout[45] 0xc0 7.68002e+06 0.5; - dout[45]~175 0xc0 5.62287e+06 0.5; - dout[45]~176 0xc0 5.21144e+06 0.5; - dout[46] 0xc0 7.68002e+06 0.5; - dout[46]~177 0xc0 5.62287e+06 0.5; - dout[46]~178 0xc0 5.21144e+06 0.5; - dout[47] 0xc0 7.68002e+06 0.5; - dout[47]~179 0xc0 5.62287e+06 0.5; - dout[47]~180 0xc0 5.21144e+06 0.5; - dout[48] 0xc0 7.68002e+06 0.5; - dout[48]~181 0xc0 5.62287e+06 0.5; - dout[48]~182 0xc0 5.21144e+06 0.5; - dout[49] 0xc0 7.68002e+06 0.5; - dout[49]~183 0xc0 5.62287e+06 0.5; - dout[49]~184 0xc0 5.21144e+06 0.5; - dout[50] 0xc0 7.68002e+06 0.5; - dout[50]~185 0xc0 5.62287e+06 0.5; - dout[50]~186 0xc0 5.21144e+06 0.5; - dout[51] 0xc0 7.68002e+06 0.5; - dout[51]~187 0xc0 5.62287e+06 0.5; - dout[51]~188 0xc0 5.21144e+06 0.5; - dout[52] 0xc0 7.68002e+06 0.5; - dout[52]~189 0xc0 5.62287e+06 0.5; - dout[52]~190 0xc0 5.21144e+06 0.5; - dout[53] 0xc0 7.68002e+06 0.5; - dout[53]~191 0xc0 5.62287e+06 0.5; - dout[53]~192 0xc0 5.21144e+06 0.5; - dout[54] 0xc0 7.68002e+06 0.5; - dout[54]~194 0xc0 5.62287e+06 0.5; - dout[54]~195 0xc0 5.21144e+06 0.5; - dout[55] 0xc0 7.68002e+06 0.5; - dout[55]~196 0xc0 5.62287e+06 0.5; - dout[55]~197 0xc0 5.21144e+06 0.5; - dout[56] 0xc0 7.68002e+06 0.5; - dout[56]~198 0xc0 5.62287e+06 0.5; - dout[56]~199 0xc0 5.21144e+06 0.5; - dout[57] 0xc0 7.68002e+06 0.5; - dout[57]~200 0xc0 5.62287e+06 0.5; - dout[57]~201 0xc0 5.21144e+06 0.5; - dout[58] 0xc0 7.68002e+06 0.5; - dout[58]~202 0xc0 5.62287e+06 0.5; - dout[58]~203 0xc0 5.21144e+06 0.5; - dout[59] 0xc0 7.68002e+06 0.5; - dout[59]~204 0xc0 5.62287e+06 0.5; - dout[59]~205 0xc0 5.21144e+06 0.5; - dout[60] 0xc0 7.68002e+06 0.5; - dout[60]~206 0xc0 5.62287e+06 0.5; - dout[60]~207 0xc0 5.21144e+06 0.5; - dout[61] 0xc0 7.68002e+06 0.5; - dout[61]~208 0xc0 5.62287e+06 0.5; - dout[61]~209 0xc0 5.21144e+06 0.5; - dout[62] 0xc0 7.68002e+06 0.5; - dout[62]~210 0xc0 5.62287e+06 0.5; - dout[62]~211 0xc0 5.21144e+06 0.5; - dout[63] 0xc0 7.68002e+06 0.5; - dout[63]~212 0xc0 5.62287e+06 0.5; - dout[63]~213 0xc0 5.21144e+06 0.5; - dout[64] 0xc0 7.68002e+06 0.5; - dout[64]~214 0xc0 5.62287e+06 0.5; - dout[64]~215 0xc0 5.21144e+06 0.5; - dout[65] 0xc0 7.68002e+06 0.5; - dout[65]~216 0xc0 5.62287e+06 0.5; - dout[65]~217 0xc0 5.21144e+06 0.5; - dout[66] 0xc0 7.68002e+06 0.5; - dout[66]~218 0xc0 5.62287e+06 0.5; - dout[66]~219 0xc0 5.21144e+06 0.5; - dout[67] 0xc0 7.68002e+06 0.5; - dout[67]~220 0xc0 5.62287e+06 0.5; - dout[67]~221 0xc0 5.21144e+06 0.5; - dout[68] 0xc0 7.68002e+06 0.5; - dout[68]~222 0xc0 5.62287e+06 0.5; - dout[68]~223 0xc0 5.21144e+06 0.5; - dout[69] 0xc0 7.68002e+06 0.5; - dout[69]~224 0xc0 5.62287e+06 0.5; - dout[69]~225 0xc0 5.21144e+06 0.5; - dout[70] 0xc0 7.68002e+06 0.5; - dout[70]~226 0xc0 5.62287e+06 0.5; - dout[70]~227 0xc0 5.21144e+06 0.5; - dout[71] 0xc0 7.68002e+06 0.5; - dout[71]~228 0xc0 5.62287e+06 0.5; - dout[71]~229 0xc0 5.21144e+06 0.5; - dout[72] 0xc0 7.68002e+06 0.5; - dout[72]~230 0xc0 5.62287e+06 0.5; - dout[72]~231 0xc0 5.21144e+06 0.5; - dout[73] 0xc0 7.68002e+06 0.5; - dout[73]~232 0xc0 5.62287e+06 0.5; - dout[73]~233 0xc0 5.21144e+06 0.5; - dout[74] 0xc0 7.68002e+06 0.5; - dout[74]~234 0xc0 5.62287e+06 0.5; - dout[74]~235 0xc0 5.21144e+06 0.5; - dout[75] 0xc0 7.68002e+06 0.5; - dout[75]~236 0xc0 5.62287e+06 0.5; - dout[75]~237 0xc0 5.21144e+06 0.5; - dout[76] 0xc0 7.68002e+06 0.5; - dout[76]~238 0xc0 5.62287e+06 0.5; - dout[76]~239 0xc0 5.21144e+06 0.5; - dout[77] 0xc0 7.68002e+06 0.5; - dout[77]~240 0xc0 5.62287e+06 0.5; - dout[77]~241 0xc0 5.21144e+06 0.5; - dout[78] 0xc0 7.68002e+06 0.5; - dout[78]~242 0xc0 5.62287e+06 0.5; - dout[78]~243 0xc0 5.21144e+06 0.5; - dout[79] 0xc0 7.68002e+06 0.5; - dout[79]~244 0xc0 5.62287e+06 0.5; - dout[79]~245 0xc0 5.21144e+06 0.5; - dout[80] 0xc0 7.68002e+06 0.5; - dout[80]~246 0xc0 5.62287e+06 0.5; - dout[80]~247 0xc0 5.21144e+06 0.5; - dout[81] 0xc0 7.68002e+06 0.5; - dout[81]~248 0xc0 5.62287e+06 0.5; - dout[81]~249 0xc0 5.21144e+06 0.5; - dout[82] 0xc0 7.68002e+06 0.5; - dout[82]~250 0xc0 5.62287e+06 0.5; - dout[82]~251 0xc0 5.21144e+06 0.5; - dout[83] 0xc0 7.68002e+06 0.5; - dout[83]~252 0xc0 5.62287e+06 0.5; - dout[83]~253 0xc0 5.21144e+06 0.5; - dout[84] 0xc0 7.68002e+06 0.5; - dout[84]~254 0xc0 5.62287e+06 0.5; - dout_valid 0xc0 7.68002e+06 0.5; - dout_valid~0 0xc0 4.32001e+06 0.75; - dout_valid~1 0xc0 4.32001e+06 0.25; - dout~193 0xc0 3.33001e+06 0.625; - dout~256 0xc0 5.76001e+06 0.25; - auk_dspip_differentiator:differentiate_stages[5].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][11] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][12] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][13] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][14] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][15] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][16] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][17] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][18] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][19] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][20] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][21] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][22] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][23] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][24] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][25] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][26] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][27] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][28] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][29] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][30] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][31] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][32] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][33] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][34] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][35] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][36] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][37] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][38] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][39] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][40] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][41] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][42] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][43] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][44] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][45] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][46] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][47] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][48] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][49] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][50] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][51] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][52] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][53] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][54] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][55] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][56] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][57] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][58] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][59] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][60] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][61]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][62] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][63]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][64]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][65] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][66] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][67]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][68] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][69]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][70]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][71]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][72] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][73]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][75] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82]~feeder 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84] 0xc0 7.68002e+06 0.5; - dout[53] 0xc0 7.68002e+06 0.5; - dout[53]~33 0xc0 4.32001e+06 0.75; - dout[53]~35 0xc0 3.57751e+06 0.375; - dout[53]~37 0xc0 4.2122e+06 0.5625; - dout[53]~39 0xc0 5.69779e+06 0.46875; - dout[53]~41 0xc0 5.02005e+06 0.515625; - dout[53]~43 0xc0 5.32697e+06 0.492188; - dout[53]~45 0xc0 5.1595e+06 0.503906; - dout[53]~47 0xc0 5.23898e+06 0.498047; - dout[53]~49 0xc0 5.19808e+06 0.500977; - dout[53]~51 0xc0 5.21823e+06 0.499512; - dout[53]~53 0xc0 5.20808e+06 0.500244; - dout[53]~55 0xc0 5.21313e+06 0.499878; - dout[53]~57 0xc0 5.2106e+06 0.500061; - dout[53]~59 0xc0 5.21186e+06 0.499969; - dout[53]~61 0xc0 5.21123e+06 0.500015; - dout[53]~63 0xc0 5.21155e+06 0.499992; - dout[53]~65 0xc0 5.21139e+06 0.500004; - dout[53]~67 0xc0 5.21147e+06 0.499998; - dout[53]~69 0xc0 5.21143e+06 0.500001; - dout[53]~71 0xc0 5.21145e+06 0.5; - dout[53]~73 0xc0 5.21144e+06 0.5; - dout[53]~75 0xc0 5.21144e+06 0.5; - dout[53]~77 0xc0 5.21144e+06 0.5; - dout[53]~79 0xc0 5.21144e+06 0.5; - dout[53]~81 0xc0 5.21144e+06 0.5; - dout[53]~83 0xc0 5.21144e+06 0.5; - dout[53]~85 0xc0 5.21144e+06 0.5; - dout[53]~87 0xc0 5.21144e+06 0.5; - dout[53]~89 0xc0 5.21144e+06 0.5; - dout[53]~91 0xc0 5.21144e+06 0.5; - dout[53]~93 0xc0 5.21144e+06 0.5; - dout[53]~95 0xc0 5.21144e+06 0.5; - dout[53]~97 0xc0 5.21144e+06 0.5; - dout[53]~99 0xc0 5.21144e+06 0.5; - dout[53]~101 0xc0 5.21144e+06 0.5; - dout[53]~103 0xc0 5.21144e+06 0.5; - dout[53]~105 0xc0 5.21144e+06 0.5; - dout[53]~107 0xc0 5.21144e+06 0.5; - dout[53]~109 0xc0 5.21144e+06 0.5; - dout[53]~111 0xc0 5.21144e+06 0.5; - dout[53]~113 0xc0 5.21144e+06 0.5; - dout[53]~115 0xc0 5.21144e+06 0.5; - dout[53]~117 0xc0 5.21144e+06 0.5; - dout[53]~119 0xc0 5.21144e+06 0.5; - dout[53]~121 0xc0 5.21144e+06 0.5; - dout[53]~123 0xc0 5.21144e+06 0.5; - dout[53]~125 0xc0 5.21144e+06 0.5; - dout[53]~127 0xc0 5.21144e+06 0.5; - dout[53]~129 0xc0 5.21144e+06 0.5; - dout[53]~131 0xc0 5.21144e+06 0.5; - dout[53]~133 0xc0 5.21144e+06 0.5; - dout[53]~135 0xc0 5.21144e+06 0.5; - dout[53]~137 0xc0 5.21144e+06 0.5; - dout[53]~138 0xc0 5.62287e+06 0.5; - dout[53]~139 0xc0 5.21144e+06 0.5; - dout[54] 0xc0 7.68002e+06 0.5; - dout[54]~141 0xc0 5.62287e+06 0.5; - dout[54]~142 0xc0 5.21144e+06 0.5; - dout[55] 0xc0 7.68002e+06 0.5; - dout[55]~143 0xc0 5.62287e+06 0.5; - dout[55]~144 0xc0 5.21144e+06 0.5; - dout[56] 0xc0 7.68002e+06 0.5; - dout[56]~145 0xc0 5.62287e+06 0.5; - dout[56]~146 0xc0 5.21144e+06 0.5; - dout[57] 0xc0 7.68002e+06 0.5; - dout[57]~147 0xc0 5.62287e+06 0.5; - dout[57]~148 0xc0 5.21144e+06 0.5; - dout[58] 0xc0 7.68002e+06 0.5; - dout[58]~149 0xc0 5.62287e+06 0.5; - dout[58]~150 0xc0 5.21144e+06 0.5; - dout[59] 0xc0 7.68002e+06 0.5; - dout[59]~151 0xc0 5.62287e+06 0.5; - dout[59]~152 0xc0 5.21144e+06 0.5; - dout[60] 0xc0 7.68002e+06 0.5; - dout[60]~153 0xc0 5.62287e+06 0.5; - dout[60]~154 0xc0 5.21144e+06 0.5; - dout[61] 0xc0 7.68002e+06 0.5; - dout[61]~155 0xc0 5.62287e+06 0.5; - dout[61]~156 0xc0 5.21144e+06 0.5; - dout[62] 0xc0 7.68002e+06 0.5; - dout[62]~157 0xc0 5.62287e+06 0.5; - dout[62]~158 0xc0 5.21144e+06 0.5; - dout[63] 0xc0 7.68002e+06 0.5; - dout[63]~159 0xc0 5.62287e+06 0.5; - dout[63]~160 0xc0 5.21144e+06 0.5; - dout[64] 0xc0 7.68002e+06 0.5; - dout[64]~161 0xc0 5.62287e+06 0.5; - dout[64]~162 0xc0 5.21144e+06 0.5; - dout[65] 0xc0 7.68002e+06 0.5; - dout[65]~163 0xc0 5.62287e+06 0.5; - dout[65]~164 0xc0 5.21144e+06 0.5; - dout[66] 0xc0 7.68002e+06 0.5; - dout[66]~165 0xc0 5.62287e+06 0.5; - dout[66]~166 0xc0 5.21144e+06 0.5; - dout[67] 0xc0 7.68002e+06 0.5; - dout[67]~167 0xc0 5.62287e+06 0.5; - dout[67]~168 0xc0 5.21144e+06 0.5; - dout[68] 0xc0 7.68002e+06 0.5; - dout[68]~169 0xc0 5.62287e+06 0.5; - dout[68]~170 0xc0 5.21144e+06 0.5; - dout[69] 0xc0 7.68002e+06 0.5; - dout[69]~171 0xc0 5.62287e+06 0.5; - dout[69]~172 0xc0 5.21144e+06 0.5; - dout[70] 0xc0 7.68002e+06 0.5; - dout[70]~173 0xc0 5.62287e+06 0.5; - dout[70]~174 0xc0 5.21144e+06 0.5; - dout[71] 0xc0 7.68002e+06 0.5; - dout[71]~175 0xc0 5.62287e+06 0.5; - dout[71]~176 0xc0 5.21144e+06 0.5; - dout[72] 0xc0 7.68002e+06 0.5; - dout[72]~177 0xc0 5.62287e+06 0.5; - dout[72]~178 0xc0 5.21144e+06 0.5; - dout[73] 0xc0 7.68002e+06 0.5; - dout[73]~179 0xc0 5.62287e+06 0.5; - dout[73]~180 0xc0 5.21144e+06 0.5; - dout[74] 0xc0 7.68002e+06 0.5; - dout[74]~181 0xc0 5.62287e+06 0.5; - dout[74]~182 0xc0 5.21144e+06 0.5; - dout[75] 0xc0 7.68002e+06 0.5; - dout[75]~183 0xc0 5.62287e+06 0.5; - dout[75]~184 0xc0 5.21144e+06 0.5; - dout[76] 0xc0 7.68002e+06 0.5; - dout[76]~185 0xc0 5.62287e+06 0.5; - dout[76]~186 0xc0 5.21144e+06 0.5; - dout[77] 0xc0 7.68002e+06 0.5; - dout[77]~187 0xc0 5.62287e+06 0.5; - dout[77]~188 0xc0 5.21144e+06 0.5; - dout[78] 0xc0 7.68002e+06 0.5; - dout[78]~189 0xc0 5.62287e+06 0.5; - dout[78]~190 0xc0 5.21144e+06 0.5; - dout[79] 0xc0 7.68002e+06 0.5; - dout[79]~191 0xc0 5.62287e+06 0.5; - dout[79]~192 0xc0 5.21144e+06 0.5; - dout[80] 0xc0 7.68002e+06 0.5; - dout[80]~193 0xc0 5.62287e+06 0.5; - dout[80]~194 0xc0 5.21144e+06 0.5; - dout[81] 0xc0 7.68002e+06 0.5; - dout[81]~195 0xc0 5.62287e+06 0.5; - dout[81]~196 0xc0 5.21144e+06 0.5; - dout[82] 0xc0 7.68002e+06 0.5; - dout[82]~197 0xc0 5.62287e+06 0.5; - dout[82]~198 0xc0 5.21144e+06 0.5; - dout[83] 0xc0 7.68002e+06 0.5; - dout[83]~199 0xc0 5.62287e+06 0.5; - dout[83]~200 0xc0 5.21144e+06 0.5; - dout[84] 0xc0 7.68002e+06 0.5; - dout[84]~201 0xc0 7.06288e+06 0.5; - dout_valid 0xc0 7.68002e+06 0.5; - dout_valid~0 0xc0 4.32001e+06 0.25; - dout~140 0xc0 3.33001e+06 0.625; - dout~203 0xc0 5.76001e+06 0.25; - ena_diff_s[0] 0xc0 7.68002e+06 0.5; - ena_diff_s[1] 0xc0 7.68002e+06 0.5; - ena_diff_s[1]~feeder 0xc0 5.76001e+06 0.25; - ena_diff_s~0 0xc0 1.10374e+07 0.375076; - fifo_rdreq 0xc0 7.68002e+06 0.5; - fifo_rdreq~0 0xc0 5.76001e+06 0.25; - auk_dspip_channel_buffer:fifo_regulator; - scfifo:buffer_FIFO; - scfifo_pm51:auto_generated; - a_dpfifo_4ku:dpfifo; - _~0 0xc0 1.4247e+06 0.125046; - _~1 0xc0 4.58894e+06 0.0624962; - _~2 0xc0 5.76001e+06 0.25; - _~3 0xc0 8.42424e+06 0.437513; - empty_dff 0xc0 7.68002e+06 0.5; - empty_dff~0 0xc0 3.67585e+06 0.271499; - empty_dff~1 0xc0 36.5972 5.55505e-05; - empty_dff~2 0xc0 2.65553e+06 0.328636; - empty_dff~3 0xc0 3.51655e+06 0.263684; - altsyncram_j7h1:FIFOram; - altsyncram:ram_block1a0; - altsyncram_lci3:auto_generated; - decode_msa:address_decoder; - w_anode19w[2]~0 0xc0 2.28001e+06 0.125; - w_anode32w[2]~0 0xc0 1.83e+06 0.125; - w_anode40w[2]~0 0xc0 1.83e+06 0.125; - w_anode48w[2]~0 0xc0 1.83e+06 0.125; - address_reg[0] 0xc0 7.68002e+06 0.5; - address_reg[0]~feeder 0xc0 7.68002e+06 0.5; - address_reg[1] 0xc0 7.68002e+06 0.5; - address_reg[1]~feeder 0xc0 7.68002e+06 0.5; - data_reg[0] 0xc0 7.68002e+06 0.5; - data_reg[0]~feeder 0xc0 7.68002e+06 0.5; - data_reg[1] 0xc0 7.68002e+06 0.5; - data_reg[2] 0xc0 7.68002e+06 0.5; - data_reg[2]~feeder 0xc0 7.68002e+06 0.5; - data_reg[3] 0xc0 7.68002e+06 0.5; - data_reg[3]~feeder 0xc0 7.68002e+06 0.5; - data_reg[4] 0xc0 7.68002e+06 0.5; - data_reg[4]~feeder 0xc0 7.68002e+06 0.5; - data_reg[5] 0xc0 7.68002e+06 0.5; - data_reg[6] 0xc0 7.68002e+06 0.5; - data_reg[6]~feeder 0xc0 7.68002e+06 0.5; - data_reg[7] 0xc0 7.68002e+06 0.5; - data_reg[7]~feeder 0xc0 7.68002e+06 0.5; - data_reg[8] 0xc0 7.68002e+06 0.5; - data_reg[8]~feeder 0xc0 7.68002e+06 0.5; - data_reg[9] 0xc0 7.68002e+06 0.5; - data_reg[9]~feeder 0xc0 7.68002e+06 0.5; - data_reg[10] 0xc0 7.68002e+06 0.5; - data_reg[11] 0xc0 7.68002e+06 0.5; - data_reg[11]~feeder 0xc0 7.68002e+06 0.5; - data_reg[12] 0xc0 7.68002e+06 0.5; - data_reg[13] 0xc0 7.68002e+06 0.5; - data_reg[14] 0xc0 7.68002e+06 0.5; - data_reg[14]~feeder 0xc0 7.68002e+06 0.5; - data_reg[15] 0xc0 7.68002e+06 0.5; - data_reg[16] 0xc0 7.68002e+06 0.5; - data_reg[16]~feeder 0xc0 7.68002e+06 0.5; - data_reg[17] 0xc0 7.68002e+06 0.5; - data_reg[17]~feeder 0xc0 7.68002e+06 0.5; - data_reg[18] 0xc0 7.68002e+06 0.5; - data_reg[19] 0xc0 7.68002e+06 0.5; - data_reg[19]~feeder 0xc0 7.68002e+06 0.5; - data_reg[20] 0xc0 7.68002e+06 0.5; - data_reg[20]~feeder 0xc0 7.68002e+06 0.5; - data_reg[21] 0xc0 7.68002e+06 0.5; - data_reg[21]~feeder 0xc0 7.68002e+06 0.5; - data_reg[22] 0xc0 7.68002e+06 0.5; - data_reg[23] 0xc0 7.68002e+06 0.5; - data_reg[23]~feeder 0xc0 7.68002e+06 0.5; - data_reg[24] 0xc0 7.68002e+06 0.5; - data_reg[24]~feeder 0xc0 7.68002e+06 0.5; - data_reg[25] 0xc0 7.68002e+06 0.5; - data_reg[25]~feeder 0xc0 7.68002e+06 0.5; - data_reg[26] 0xc0 7.68002e+06 0.5; - data_reg[26]~feeder 0xc0 7.68002e+06 0.5; - data_reg[27] 0xc0 7.68002e+06 0.5; - data_reg[28] 0xc0 7.68002e+06 0.5; - data_reg[28]~feeder 0xc0 7.68002e+06 0.5; - data_reg[29] 0xc0 7.68002e+06 0.5; - data_reg[29]~feeder 0xc0 7.68002e+06 0.5; - data_reg[30] 0xc0 7.68002e+06 0.5; - data_reg[30]~feeder 0xc0 7.68002e+06 0.5; - data_reg[31] 0xc0 7.68002e+06 0.5; - data_reg[31]~feeder 0xc0 7.68002e+06 0.5; - data_reg[32] 0xc0 7.68002e+06 0.5; - data_reg[32]~feeder 0xc0 7.68002e+06 0.5; - data_reg[33] 0xc0 7.68002e+06 0.5; - data_reg[33]~feeder 0xc0 7.68002e+06 0.5; - data_reg[34] 0xc0 7.68002e+06 0.5; - data_reg[35] 0xc0 7.68002e+06 0.5; - data_reg[35]~feeder 0xc0 7.68002e+06 0.5; - data_reg[36] 0xc0 7.68002e+06 0.5; - data_reg[37] 0xc0 7.68002e+06 0.5; - data_reg[37]~feeder 0xc0 7.68002e+06 0.5; - data_reg[38] 0xc0 7.68002e+06 0.5; - data_reg[38]~feeder 0xc0 7.68002e+06 0.5; - data_reg[39] 0xc0 7.68002e+06 0.5; - data_reg[39]~feeder 0xc0 7.68002e+06 0.5; - data_reg[40] 0xc0 7.68002e+06 0.5; - data_reg[40]~feeder 0xc0 7.68002e+06 0.5; - data_reg[41] 0xc0 7.68002e+06 0.5; - data_reg[41]~feeder 0xc0 7.68002e+06 0.5; - data_reg[42] 0xc0 7.68002e+06 0.5; - data_reg[42]~feeder 0xc0 7.68002e+06 0.5; - data_reg[43] 0xc0 7.68002e+06 0.5; - data_reg[43]~feeder 0xc0 7.68002e+06 0.5; - data_reg[44] 0xc0 7.68002e+06 0.5; - data_reg[44]~feeder 0xc0 7.68002e+06 0.5; - data_reg[45] 0xc0 7.68002e+06 0.5; - data_reg[46] 0xc0 7.68002e+06 0.5; - data_reg[46]~feeder 0xc0 7.68002e+06 0.5; - data_reg[47] 0xc0 7.68002e+06 0.5; - data_reg[47]~feeder 0xc0 7.68002e+06 0.5; - data_reg[48] 0xc0 7.68002e+06 0.5; - data_reg[48]~feeder 0xc0 7.68002e+06 0.5; - data_reg[49] 0xc0 7.68002e+06 0.5; - data_reg[49]~feeder 0xc0 7.68002e+06 0.5; - data_reg[50] 0xc0 7.68002e+06 0.5; - data_reg[51] 0xc0 7.68002e+06 0.5; - data_reg[51]~feeder 0xc0 7.68002e+06 0.5; - data_reg[52] 0xc0 7.68002e+06 0.5; - data_reg[52]~feeder 0xc0 7.68002e+06 0.5; - data_reg[53] 0xc0 7.68002e+06 0.5; - data_reg[53]~feeder 0xc0 7.68002e+06 0.5; - data_reg[54] 0xc0 7.68002e+06 0.5; - data_reg[55] 0xc0 7.68002e+06 0.5; - data_reg[55]~feeder 0xc0 7.68002e+06 0.5; - data_reg[56] 0xc0 7.68002e+06 0.5; - data_reg[56]~feeder 0xc0 7.68002e+06 0.5; - data_reg[57] 0xc0 7.68002e+06 0.5; - data_reg[58] 0xc0 7.68002e+06 0.5; - data_reg[59] 0xc0 7.68002e+06 0.5; - data_reg[60] 0xc0 7.68002e+06 0.5; - data_reg[60]~feeder 0xc0 7.68002e+06 0.5; - data_reg[61] 0xc0 7.68002e+06 0.5; - data_reg[61]~feeder 0xc0 7.68002e+06 0.5; - data_reg[62] 0xc0 7.68002e+06 0.5; - data_reg[62]~feeder 0xc0 7.68002e+06 0.5; - data_reg[63] 0xc0 7.68002e+06 0.5; - data_reg[64] 0xc0 7.68002e+06 0.5; - data_reg[65] 0xc0 7.68002e+06 0.5; - data_reg[65]~feeder 0xc0 7.68002e+06 0.5; - data_reg[66] 0xc0 7.68002e+06 0.5; - data_reg[67] 0xc0 7.68002e+06 0.5; - data_reg[68] 0xc0 7.68002e+06 0.5; - data_reg[68]~feeder 0xc0 7.68002e+06 0.5; - data_reg[69] 0xc0 7.68002e+06 0.5; - data_reg[69]~feeder 0xc0 7.68002e+06 0.5; - data_reg[70] 0xc0 7.68002e+06 0.5; - data_reg[70]~feeder 0xc0 7.68002e+06 0.5; - data_reg[71] 0xc0 7.68002e+06 0.5; - data_reg[71]~feeder 0xc0 7.68002e+06 0.5; - data_reg[72] 0xc0 7.68002e+06 0.5; - data_reg[72]~feeder 0xc0 7.68002e+06 0.5; - data_reg[73] 0xc0 7.68002e+06 0.5; - data_reg[73]~feeder 0xc0 7.68002e+06 0.5; - data_reg[74] 0xc0 7.68002e+06 0.5; - data_reg[74]~feeder 0xc0 7.68002e+06 0.5; - data_reg[75] 0xc0 7.68002e+06 0.5; - data_reg[75]~feeder 0xc0 7.68002e+06 0.5; - data_reg[76] 0xc0 7.68002e+06 0.5; - data_reg[77] 0xc0 7.68002e+06 0.5; - data_reg[78] 0xc0 7.68002e+06 0.5; - data_reg[79] 0xc0 7.68002e+06 0.5; - data_reg[79]~feeder 0xc0 7.68002e+06 0.5; - data_reg[80] 0xc0 7.68002e+06 0.5; - data_reg[80]~feeder 0xc0 7.68002e+06 0.5; - data_reg[81] 0xc0 7.68002e+06 0.5; - data_reg[82] 0xc0 7.68002e+06 0.5; - data_reg[83] 0xc0 7.68002e+06 0.5; - data_reg[83]~feeder 0xc0 7.68002e+06 0.5; - data_reg[84] 0xc0 7.68002e+06 0.5; - data_reg[84]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[0] 0xc0 7.68002e+06 0.5; - outdata_reg[0]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[1] 0xc0 7.68002e+06 0.5; - outdata_reg[1]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[2] 0xc0 7.68002e+06 0.5; - outdata_reg[3] 0xc0 7.68002e+06 0.5; - outdata_reg[3]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[4] 0xc0 7.68002e+06 0.5; - outdata_reg[5] 0xc0 7.68002e+06 0.5; - outdata_reg[5]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[6] 0xc0 7.68002e+06 0.5; - outdata_reg[7] 0xc0 7.68002e+06 0.5; - outdata_reg[7]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[8] 0xc0 7.68002e+06 0.5; - outdata_reg[8]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[9] 0xc0 7.68002e+06 0.5; - outdata_reg[10] 0xc0 7.68002e+06 0.5; - outdata_reg[10]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[11] 0xc0 7.68002e+06 0.5; - outdata_reg[11]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[12] 0xc0 7.68002e+06 0.5; - outdata_reg[13] 0xc0 7.68002e+06 0.5; - outdata_reg[13]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[14] 0xc0 7.68002e+06 0.5; - outdata_reg[14]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[15] 0xc0 7.68002e+06 0.5; - outdata_reg[15]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[16] 0xc0 7.68002e+06 0.5; - outdata_reg[16]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[17] 0xc0 7.68002e+06 0.5; - outdata_reg[18] 0xc0 7.68002e+06 0.5; - outdata_reg[19] 0xc0 7.68002e+06 0.5; - outdata_reg[19]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[20] 0xc0 7.68002e+06 0.5; - outdata_reg[20]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[21] 0xc0 7.68002e+06 0.5; - outdata_reg[21]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[22] 0xc0 7.68002e+06 0.5; - outdata_reg[22]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[23] 0xc0 7.68002e+06 0.5; - outdata_reg[23]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[24] 0xc0 7.68002e+06 0.5; - outdata_reg[24]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[25] 0xc0 7.68002e+06 0.5; - outdata_reg[26] 0xc0 7.68002e+06 0.5; - outdata_reg[26]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[27] 0xc0 7.68002e+06 0.5; - outdata_reg[28] 0xc0 7.68002e+06 0.5; - outdata_reg[29] 0xc0 7.68002e+06 0.5; - outdata_reg[29]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[30] 0xc0 7.68002e+06 0.5; - outdata_reg[30]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[31] 0xc0 7.68002e+06 0.5; - outdata_reg[31]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[32] 0xc0 7.68002e+06 0.5; - outdata_reg[32]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[33] 0xc0 7.68002e+06 0.5; - outdata_reg[33]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[34] 0xc0 7.68002e+06 0.5; - outdata_reg[35] 0xc0 7.68002e+06 0.5; - outdata_reg[36] 0xc0 7.68002e+06 0.5; - outdata_reg[36]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[37] 0xc0 7.68002e+06 0.5; - outdata_reg[37]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[38] 0xc0 7.68002e+06 0.5; - outdata_reg[38]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[39] 0xc0 7.68002e+06 0.5; - outdata_reg[39]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[40] 0xc0 7.68002e+06 0.5; - outdata_reg[40]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[41] 0xc0 7.68002e+06 0.5; - outdata_reg[41]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[42] 0xc0 7.68002e+06 0.5; - outdata_reg[43] 0xc0 7.68002e+06 0.5; - outdata_reg[43]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[44] 0xc0 7.68002e+06 0.5; - outdata_reg[44]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[45] 0xc0 7.68002e+06 0.5; - outdata_reg[45]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[46] 0xc0 7.68002e+06 0.5; - outdata_reg[47] 0xc0 7.68002e+06 0.5; - outdata_reg[48] 0xc0 7.68002e+06 0.5; - outdata_reg[48]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[49] 0xc0 7.68002e+06 0.5; - outdata_reg[50] 0xc0 7.68002e+06 0.5; - outdata_reg[50]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[51] 0xc0 7.68002e+06 0.5; - outdata_reg[51]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[52] 0xc0 7.68002e+06 0.5; - outdata_reg[52]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[53] 0xc0 7.68002e+06 0.5; - outdata_reg[53]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[54] 0xc0 7.68002e+06 0.5; - outdata_reg[54]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[55] 0xc0 7.68002e+06 0.5; - outdata_reg[55]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[56] 0xc0 7.68002e+06 0.5; - outdata_reg[57] 0xc0 7.68002e+06 0.5; - outdata_reg[57]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[58] 0xc0 7.68002e+06 0.5; - outdata_reg[59] 0xc0 7.68002e+06 0.5; - outdata_reg[59]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[60] 0xc0 7.68002e+06 0.5; - outdata_reg[61] 0xc0 7.68002e+06 0.5; - outdata_reg[61]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[62] 0xc0 7.68002e+06 0.5; - outdata_reg[62]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[63] 0xc0 7.68002e+06 0.5; - outdata_reg[63]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[64] 0xc0 7.68002e+06 0.5; - outdata_reg[64]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[65] 0xc0 7.68002e+06 0.5; - outdata_reg[65]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[66] 0xc0 7.68002e+06 0.5; - outdata_reg[67] 0xc0 7.68002e+06 0.5; - outdata_reg[67]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[68] 0xc0 7.68002e+06 0.5; - outdata_reg[69] 0xc0 7.68002e+06 0.5; - outdata_reg[69]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[70] 0xc0 7.68002e+06 0.5; - outdata_reg[70]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[71] 0xc0 7.68002e+06 0.5; - outdata_reg[71]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[72] 0xc0 7.68002e+06 0.5; - outdata_reg[72]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[73] 0xc0 7.68002e+06 0.5; - outdata_reg[74] 0xc0 7.68002e+06 0.5; - outdata_reg[74]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[75] 0xc0 7.68002e+06 0.5; - outdata_reg[76] 0xc0 7.68002e+06 0.5; - outdata_reg[76]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[77] 0xc0 7.68002e+06 0.5; - outdata_reg[77]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[78] 0xc0 7.68002e+06 0.5; - outdata_reg[79] 0xc0 7.68002e+06 0.5; - outdata_reg[79]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[80] 0xc0 7.68002e+06 0.5; - outdata_reg[80]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[81] 0xc0 7.68002e+06 0.5; - outdata_reg[81]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[82] 0xc0 7.68002e+06 0.5; - outdata_reg[82]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[83] 0xc0 7.68002e+06 0.5; - outdata_reg[83]~feeder 0xc0 7.68002e+06 0.5; - outdata_reg[84] 0xc0 7.68002e+06 0.5; - outdata_reg[84]~feeder 0xc0 7.68002e+06 0.5; - mux_rob:output_mux; - result_node[0]~106 0xc0 4.5497e+06 0.5; - result_node[0]~107 0xc0 4.81865e+06 0.5; - result_node[1]~104 0xc0 4.98986e+06 0.5; - result_node[1]~105 0xc0 4.79773e+06 0.5; - result_node[2]~102 0xc0 4.84923e+06 0.5; - result_node[2]~103 0xc0 4.70984e+06 0.5; - result_node[3]~100 0xc0 5.06017e+06 0.5; - result_node[3]~101 0xc0 5.41019e+06 0.5; - result_node[4]~98 0xc0 4.69876e+06 0.5; - result_node[4]~99 0xc0 3.26858e+06 0.5; - result_node[5]~96 0xc0 4.84923e+06 0.5; - result_node[5]~97 0xc0 4.33472e+06 0.5; - result_node[6]~94 0xc0 5.06017e+06 0.5; - result_node[6]~95 0xc0 5.08214e+06 0.5; - result_node[7]~92 0xc0 4.40064e+06 0.5; - result_node[7]~93 0xc0 2.99391e+06 0.5; - result_node[8]~90 0xc0 4.69173e+06 0.5; - result_node[8]~91 0xc0 4.7943e+06 0.5; - result_node[9]~88 0xc0 5.06017e+06 0.5; - result_node[9]~89 0xc0 3.81035e+06 0.5; - result_node[10]~86 0xc0 4.98986e+06 0.5; - result_node[10]~87 0xc0 4.19248e+06 0.5; - result_node[11]~84 0xc0 5.06017e+06 0.5; - result_node[11]~85 0xc0 5.00084e+06 0.5; - result_node[12]~82 0xc0 4.40064e+06 0.5; - result_node[12]~83 0xc0 3.16088e+06 0.5; - result_node[13]~80 0xc0 4.69876e+06 0.5; - result_node[13]~81 0xc0 4.85626e+06 0.5; - result_node[14]~78 0xc0 4.84923e+06 0.5; - result_node[14]~79 0xc0 4.59088e+06 0.5; - result_node[15]~76 0xc0 4.69876e+06 0.5; - result_node[15]~77 0xc0 3.06669e+06 0.5; - result_node[16]~74 0xc0 5.06017e+06 0.5; - result_node[16]~75 0xc0 3.81035e+06 0.5; - result_node[17]~72 0xc0 4.69876e+06 0.5; - result_node[17]~73 0xc0 3.06669e+06 0.5; - result_node[18]~70 0xc0 5.06017e+06 0.5; - result_node[18]~71 0xc0 3.81035e+06 0.5; - result_node[19]~68 0xc0 4.5497e+06 0.5; - result_node[19]~69 0xc0 3.77897e+06 0.5; - result_node[20]~66 0xc0 4.84923e+06 0.5; - result_node[20]~67 0xc0 4.56737e+06 0.5; - result_node[21]~64 0xc0 4.98986e+06 0.5; - result_node[21]~65 0xc0 5.12625e+06 0.5; - result_node[22]~62 0xc0 5.06017e+06 0.5; - result_node[22]~63 0xc0 5.41019e+06 0.5; - result_node[23]~60 0xc0 4.69876e+06 0.5; - result_node[23]~61 0xc0 4.85626e+06 0.5; - result_node[24]~58 0xc0 4.84923e+06 0.5; - result_node[24]~59 0xc0 4.69446e+06 0.5; - result_node[25]~56 0xc0 4.40064e+06 0.5; - result_node[25]~57 0xc0 2.99391e+06 0.5; - result_node[26]~54 0xc0 4.25157e+06 0.5; - result_node[26]~55 0xc0 3.08039e+06 0.5; - result_node[27]~52 0xc0 4.40064e+06 0.5; - result_node[27]~53 0xc0 4.30853e+06 0.5; - result_node[28]~50 0xc0 4.69876e+06 0.5; - result_node[28]~51 0xc0 4.64743e+06 0.5; - result_node[29]~48 0xc0 4.69876e+06 0.5; - result_node[29]~49 0xc0 4.64743e+06 0.5; - result_node[30]~46 0xc0 4.25157e+06 0.5; - result_node[30]~47 0xc0 3.16208e+06 0.5; - result_node[31]~44 0xc0 4.25157e+06 0.5; - result_node[31]~45 0xc0 4.51349e+06 0.5; - result_node[32]~42 0xc0 4.69876e+06 0.5; - result_node[32]~43 0xc0 4.61579e+06 0.5; - result_node[33]~40 0xc0 4.25157e+06 0.5; - result_node[33]~41 0xc0 4.51349e+06 0.5; - result_node[34]~38 0xc0 4.40064e+06 0.5; - result_node[34]~39 0xc0 4.55427e+06 0.5; - result_node[35]~36 0xc0 4.25157e+06 0.5; - result_node[35]~37 0xc0 3.46102e+06 0.5; - result_node[36]~34 0xc0 4.69876e+06 0.5; - result_node[36]~35 0xc0 4.64743e+06 0.5; - result_node[37]~32 0xc0 4.25157e+06 0.5; - result_node[37]~33 0xc0 3.16208e+06 0.5; - result_node[38]~30 0xc0 4.40064e+06 0.5; - result_node[38]~31 0xc0 2.8887e+06 0.5; - result_node[39]~28 0xc0 4.60736e+06 0.5; - result_node[39]~29 0xc0 4.43773e+06 0.5; - result_node[40]~26 0xc0 4.5497e+06 0.5; - result_node[40]~27 0xc0 4.09887e+06 0.5; - result_node[41]~24 0xc0 4.40064e+06 0.5; - result_node[41]~25 0xc0 2.8887e+06 0.5; - result_node[42]~22 0xc0 4.69876e+06 0.5; - result_node[42]~23 0xc0 4.61579e+06 0.5; - result_node[43]~20 0xc0 4.69876e+06 0.5; - result_node[43]~21 0xc0 4.64743e+06 0.5; - result_node[44]~18 0xc0 4.60736e+06 0.5; - result_node[44]~19 0xc0 4.28014e+06 0.5; - result_node[45]~16 0xc0 4.25157e+06 0.5; - result_node[45]~17 0xc0 4.51349e+06 0.5; - result_node[46]~14 0xc0 4.25157e+06 0.5; - result_node[46]~15 0xc0 3.08039e+06 0.5; - result_node[47]~12 0xc0 4.69876e+06 0.5; - result_node[47]~13 0xc0 3.20455e+06 0.5; - result_node[48]~10 0xc0 4.69173e+06 0.5; - result_node[48]~11 0xc0 4.30376e+06 0.5; - result_node[49]~8 0xc0 4.69876e+06 0.5; - result_node[49]~9 0xc0 4.27829e+06 0.5; - result_node[50]~6 0xc0 4.84923e+06 0.5; - result_node[50]~7 0xc0 4.70984e+06 0.5; - result_node[51]~4 0xc0 4.69173e+06 0.5; - result_node[51]~5 0xc0 4.78859e+06 0.5; - result_node[52]~2 0xc0 4.69173e+06 0.5; - result_node[52]~3 0xc0 4.58392e+06 0.5; - result_node[53]~0 0xc0 4.25157e+06 0.5; - result_node[53]~1 0xc0 3.08039e+06 0.5; - result_node[54]~108 0xc0 4.25157e+06 0.5; - result_node[54]~109 0xc0 3.46102e+06 0.5; - result_node[55]~110 0xc0 4.40064e+06 0.5; - result_node[55]~111 0xc0 4.42946e+06 0.5; - result_node[56]~112 0xc0 4.98986e+06 0.5; - result_node[56]~113 0xc0 5.12625e+06 0.5; - result_node[57]~114 0xc0 4.69876e+06 0.5; - result_node[57]~115 0xc0 4.8879e+06 0.5; - result_node[58]~116 0xc0 4.40064e+06 0.5; - result_node[58]~117 0xc0 2.9584e+06 0.5; - result_node[59]~118 0xc0 4.98986e+06 0.5; - result_node[59]~119 0xc0 5.39921e+06 0.5; - result_node[60]~120 0xc0 4.60736e+06 0.5; - result_node[60]~121 0xc0 5.33944e+06 0.5; - result_node[61]~122 0xc0 4.98986e+06 0.5; - result_node[61]~123 0xc0 5.39921e+06 0.5; - result_node[62]~124 0xc0 4.5497e+06 0.5; - result_node[62]~125 0xc0 3.10483e+06 0.5; - result_node[63]~126 0xc0 4.98986e+06 0.5; - result_node[63]~127 0xc0 5.12625e+06 0.5; - result_node[64]~128 0xc0 4.5497e+06 0.5; - result_node[64]~129 0xc0 4.09887e+06 0.5; - result_node[65]~130 0xc0 4.84923e+06 0.5; - result_node[65]~131 0xc0 4.69446e+06 0.5; - result_node[66]~132 0xc0 4.84923e+06 0.5; - result_node[66]~133 0xc0 4.5889e+06 0.5; - result_node[67]~134 0xc0 4.98986e+06 0.5; - result_node[67]~135 0xc0 5.39921e+06 0.5; - result_node[68]~136 0xc0 4.5497e+06 0.5; - result_node[68]~137 0xc0 3.53148e+06 0.5; - result_node[69]~138 0xc0 4.38939e+06 0.5; - result_node[69]~139 0xc0 5.37992e+06 0.5; - result_node[70]~140 0xc0 5.06017e+06 0.5; - result_node[70]~141 0xc0 4.84167e+06 0.5; - result_node[71]~142 0xc0 4.25157e+06 0.5; - result_node[71]~143 0xc0 3.08039e+06 0.5; - result_node[72]~144 0xc0 4.69876e+06 0.5; - result_node[72]~145 0xc0 3.01255e+06 0.5; - result_node[73]~146 0xc0 4.69173e+06 0.5; - result_node[73]~147 0xc0 4.30376e+06 0.5; - result_node[74]~148 0xc0 5.03556e+06 0.5; - result_node[74]~149 0xc0 5.48022e+06 0.5; - result_node[75]~150 0xc0 4.84923e+06 0.5; - result_node[75]~151 0xc0 4.40439e+06 0.5; - result_node[76]~152 0xc0 4.69173e+06 0.5; - result_node[76]~153 0xc0 4.58392e+06 0.5; - result_node[77]~154 0xc0 4.69173e+06 0.5; - result_node[77]~155 0xc0 4.7943e+06 0.5; - result_node[78]~156 0xc0 4.84923e+06 0.5; - result_node[78]~157 0xc0 4.70984e+06 0.5; - result_node[79]~158 0xc0 4.69876e+06 0.5; - result_node[79]~159 0xc0 3.01255e+06 0.5; - result_node[80]~160 0xc0 4.69173e+06 0.5; - result_node[80]~161 0xc0 4.76046e+06 0.5; - result_node[81]~162 0xc0 4.84923e+06 0.5; - result_node[81]~163 0xc0 5.31369e+06 0.5; - result_node[82]~164 0xc0 4.84923e+06 0.5; - result_node[82]~165 0xc0 4.70984e+06 0.5; - result_node[83]~166 0xc0 4.38939e+06 0.5; - result_node[83]~167 0xc0 4.54939e+06 0.5; - result_node[84]~168 0xc0 4.84923e+06 0.5; - result_node[84]~169 0xc0 5.31369e+06 0.5; - ram_block[0] 0xc0 7.68002e+06 0.5; - ram_block[1] 0xc0 7.68002e+06 0.5; - ram_block[1]~feeder 0xc0 7.68002e+06 0.5; - ram_block[2] 0xc0 7.68002e+06 0.5; - ram_block[3] 0xc0 7.68002e+06 0.5; - ram_block[3]~feeder 0xc0 7.68002e+06 0.5; - ram_block[4] 0xc0 7.68002e+06 0.5; - ram_block[4]~feeder 0xc0 7.68002e+06 0.5; - ram_block[5] 0xc0 7.68002e+06 0.5; - ram_block[5]~feeder 0xc0 7.68002e+06 0.5; - ram_block[6] 0xc0 7.68002e+06 0.5; - ram_block[7] 0xc0 7.68002e+06 0.5; - ram_block[7]~feeder 0xc0 7.68002e+06 0.5; - ram_block[8] 0xc0 7.68002e+06 0.5; - ram_block[9] 0xc0 7.68002e+06 0.5; - ram_block[9]~feeder 0xc0 7.68002e+06 0.5; - ram_block[10] 0xc0 7.68002e+06 0.5; - ram_block[10]~feeder 0xc0 7.68002e+06 0.5; - ram_block[11] 0xc0 7.68002e+06 0.5; - ram_block[11]~feeder 0xc0 7.68002e+06 0.5; - ram_block[12] 0xc0 7.68002e+06 0.5; - ram_block[13] 0xc0 7.68002e+06 0.5; - ram_block[14] 0xc0 7.68002e+06 0.5; - ram_block[15] 0xc0 7.68002e+06 0.5; - ram_block[15]~feeder 0xc0 7.68002e+06 0.5; - ram_block[16] 0xc0 7.68002e+06 0.5; - ram_block[16]~feeder 0xc0 7.68002e+06 0.5; - ram_block[17] 0xc0 7.68002e+06 0.5; - ram_block[17]~feeder 0xc0 7.68002e+06 0.5; - ram_block[18] 0xc0 7.68002e+06 0.5; - ram_block[18]~feeder 0xc0 7.68002e+06 0.5; - ram_block[19] 0xc0 7.68002e+06 0.5; - ram_block[20] 0xc0 7.68002e+06 0.5; - ram_block[21] 0xc0 7.68002e+06 0.5; - ram_block[21]~feeder 0xc0 7.68002e+06 0.5; - ram_block[22] 0xc0 7.68002e+06 0.5; - ram_block[22]~feeder 0xc0 7.68002e+06 0.5; - ram_block[23] 0xc0 7.68002e+06 0.5; - ram_block[23]~feeder 0xc0 7.68002e+06 0.5; - ram_block[24] 0xc0 7.68002e+06 0.5; - ram_block[24]~feeder 0xc0 7.68002e+06 0.5; - ram_block[25] 0xc0 7.68002e+06 0.5; - ram_block[25]~feeder 0xc0 7.68002e+06 0.5; - ram_block[26] 0xc0 7.68002e+06 0.5; - ram_block[27] 0xc0 7.68002e+06 0.5; - ram_block[27]~feeder 0xc0 7.68002e+06 0.5; - ram_block[28] 0xc0 7.68002e+06 0.5; - ram_block[28]~feeder 0xc0 7.68002e+06 0.5; - ram_block[29] 0xc0 7.68002e+06 0.5; - ram_block[30] 0xc0 7.68002e+06 0.5; - ram_block[31] 0xc0 7.68002e+06 0.5; - ram_block[32] 0xc0 7.68002e+06 0.5; - ram_block[32]~feeder 0xc0 7.68002e+06 0.5; - ram_block[33] 0xc0 7.68002e+06 0.5; - ram_block[34] 0xc0 7.68002e+06 0.5; - ram_block[34]~feeder 0xc0 7.68002e+06 0.5; - ram_block[35] 0xc0 7.68002e+06 0.5; - ram_block[36] 0xc0 7.68002e+06 0.5; - ram_block[37] 0xc0 7.68002e+06 0.5; - ram_block[38] 0xc0 7.68002e+06 0.5; - ram_block[38]~feeder 0xc0 7.68002e+06 0.5; - ram_block[39] 0xc0 7.68002e+06 0.5; - ram_block[39]~feeder 0xc0 7.68002e+06 0.5; - ram_block[40] 0xc0 7.68002e+06 0.5; - ram_block[41] 0xc0 7.68002e+06 0.5; - ram_block[42] 0xc0 7.68002e+06 0.5; - ram_block[42]~feeder 0xc0 7.68002e+06 0.5; - ram_block[43] 0xc0 7.68002e+06 0.5; - ram_block[43]~feeder 0xc0 7.68002e+06 0.5; - ram_block[44] 0xc0 7.68002e+06 0.5; - ram_block[44]~feeder 0xc0 7.68002e+06 0.5; - ram_block[45] 0xc0 7.68002e+06 0.5; - ram_block[46] 0xc0 7.68002e+06 0.5; - ram_block[47] 0xc0 7.68002e+06 0.5; - ram_block[48] 0xc0 7.68002e+06 0.5; - ram_block[49] 0xc0 7.68002e+06 0.5; - ram_block[49]~feeder 0xc0 7.68002e+06 0.5; - ram_block[50] 0xc0 7.68002e+06 0.5; - ram_block[51] 0xc0 7.68002e+06 0.5; - ram_block[52] 0xc0 7.68002e+06 0.5; - ram_block[53] 0xc0 7.68002e+06 0.5; - ram_block[54] 0xc0 7.68002e+06 0.5; - ram_block[55] 0xc0 7.68002e+06 0.5; - ram_block[55]~feeder 0xc0 7.68002e+06 0.5; - ram_block[56] 0xc0 7.68002e+06 0.5; - ram_block[56]~feeder 0xc0 7.68002e+06 0.5; - ram_block[57] 0xc0 7.68002e+06 0.5; - ram_block[57]~feeder 0xc0 7.68002e+06 0.5; - ram_block[58] 0xc0 7.68002e+06 0.5; - ram_block[58]~feeder 0xc0 7.68002e+06 0.5; - ram_block[59] 0xc0 7.68002e+06 0.5; - ram_block[59]~feeder 0xc0 7.68002e+06 0.5; - ram_block[60] 0xc0 7.68002e+06 0.5; - ram_block[60]~feeder 0xc0 7.68002e+06 0.5; - ram_block[61] 0xc0 7.68002e+06 0.5; - ram_block[61]~feeder 0xc0 7.68002e+06 0.5; - ram_block[62] 0xc0 7.68002e+06 0.5; - ram_block[63] 0xc0 7.68002e+06 0.5; - ram_block[63]~feeder 0xc0 7.68002e+06 0.5; - ram_block[64] 0xc0 7.68002e+06 0.5; - ram_block[65] 0xc0 7.68002e+06 0.5; - ram_block[65]~feeder 0xc0 7.68002e+06 0.5; - ram_block[66] 0xc0 7.68002e+06 0.5; - ram_block[66]~feeder 0xc0 7.68002e+06 0.5; - ram_block[67] 0xc0 7.68002e+06 0.5; - ram_block[67]~feeder 0xc0 7.68002e+06 0.5; - ram_block[68] 0xc0 7.68002e+06 0.5; - ram_block[69] 0xc0 7.68002e+06 0.5; - ram_block[70] 0xc0 7.68002e+06 0.5; - ram_block[70]~feeder 0xc0 7.68002e+06 0.5; - ram_block[71] 0xc0 7.68002e+06 0.5; - ram_block[72] 0xc0 7.68002e+06 0.5; - ram_block[73] 0xc0 7.68002e+06 0.5; - ram_block[74] 0xc0 7.68002e+06 0.5; - ram_block[75] 0xc0 7.68002e+06 0.5; - ram_block[75]~feeder 0xc0 7.68002e+06 0.5; - ram_block[76] 0xc0 7.68002e+06 0.5; - ram_block[77] 0xc0 7.68002e+06 0.5; - ram_block[78] 0xc0 7.68002e+06 0.5; - ram_block[79] 0xc0 7.68002e+06 0.5; - ram_block[79]~feeder 0xc0 7.68002e+06 0.5; - ram_block[80] 0xc0 7.68002e+06 0.5; - ram_block[81] 0xc0 7.68002e+06 0.5; - ram_block[81]~feeder 0xc0 7.68002e+06 0.5; - ram_block[82] 0xc0 7.68002e+06 0.5; - ram_block[83] 0xc0 7.68002e+06 0.5; - ram_block[84] 0xc0 7.68002e+06 0.5; - ram_block[84]~feeder 0xc0 7.68002e+06 0.5; - ram_block[85] 0xc0 7.68002e+06 0.5; - ram_block[85]~feeder 0xc0 7.68002e+06 0.5; - ram_block[86] 0xc0 7.68002e+06 0.5; - ram_block[86]~feeder 0xc0 7.68002e+06 0.5; - ram_block[87] 0xc0 7.68002e+06 0.5; - ram_block[88] 0xc0 7.68002e+06 0.5; - ram_block[88]~feeder 0xc0 7.68002e+06 0.5; - ram_block[89] 0xc0 7.68002e+06 0.5; - ram_block[89]~feeder 0xc0 7.68002e+06 0.5; - ram_block[90] 0xc0 7.68002e+06 0.5; - ram_block[91] 0xc0 7.68002e+06 0.5; - ram_block[91]~feeder 0xc0 7.68002e+06 0.5; - ram_block[92] 0xc0 7.68002e+06 0.5; - ram_block[92]~feeder 0xc0 7.68002e+06 0.5; - ram_block[93] 0xc0 7.68002e+06 0.5; - ram_block[93]~feeder 0xc0 7.68002e+06 0.5; - ram_block[94] 0xc0 7.68002e+06 0.5; - ram_block[94]~feeder 0xc0 7.68002e+06 0.5; - ram_block[95] 0xc0 7.68002e+06 0.5; - ram_block[95]~feeder 0xc0 7.68002e+06 0.5; - ram_block[96] 0xc0 7.68002e+06 0.5; - ram_block[96]~feeder 0xc0 7.68002e+06 0.5; - ram_block[97] 0xc0 7.68002e+06 0.5; - ram_block[97]~feeder 0xc0 7.68002e+06 0.5; - ram_block[98] 0xc0 7.68002e+06 0.5; - ram_block[99] 0xc0 7.68002e+06 0.5; - ram_block[100] 0xc0 7.68002e+06 0.5; - ram_block[100]~feeder 0xc0 7.68002e+06 0.5; - ram_block[101] 0xc0 7.68002e+06 0.5; - ram_block[101]~feeder 0xc0 7.68002e+06 0.5; - ram_block[102] 0xc0 7.68002e+06 0.5; - ram_block[102]~feeder 0xc0 7.68002e+06 0.5; - ram_block[103] 0xc0 7.68002e+06 0.5; - ram_block[103]~feeder 0xc0 7.68002e+06 0.5; - ram_block[104] 0xc0 7.68002e+06 0.5; - ram_block[104]~feeder 0xc0 7.68002e+06 0.5; - ram_block[105] 0xc0 7.68002e+06 0.5; - ram_block[105]~feeder 0xc0 7.68002e+06 0.5; - ram_block[106] 0xc0 7.68002e+06 0.5; - ram_block[106]~feeder 0xc0 7.68002e+06 0.5; - ram_block[107] 0xc0 7.68002e+06 0.5; - ram_block[107]~feeder 0xc0 7.68002e+06 0.5; - ram_block[108] 0xc0 7.68002e+06 0.5; - ram_block[108]~feeder 0xc0 7.68002e+06 0.5; - ram_block[109] 0xc0 7.68002e+06 0.5; - ram_block[109]~feeder 0xc0 7.68002e+06 0.5; - ram_block[110] 0xc0 7.68002e+06 0.5; - ram_block[110]~feeder 0xc0 7.68002e+06 0.5; - ram_block[111] 0xc0 7.68002e+06 0.5; - ram_block[111]~feeder 0xc0 7.68002e+06 0.5; - ram_block[112] 0xc0 7.68002e+06 0.5; - ram_block[112]~feeder 0xc0 7.68002e+06 0.5; - ram_block[113] 0xc0 7.68002e+06 0.5; - ram_block[114] 0xc0 7.68002e+06 0.5; - ram_block[114]~feeder 0xc0 7.68002e+06 0.5; - ram_block[115] 0xc0 7.68002e+06 0.5; - ram_block[116] 0xc0 7.68002e+06 0.5; - ram_block[116]~feeder 0xc0 7.68002e+06 0.5; - ram_block[117] 0xc0 7.68002e+06 0.5; - ram_block[118] 0xc0 7.68002e+06 0.5; - ram_block[118]~feeder 0xc0 7.68002e+06 0.5; - ram_block[119] 0xc0 7.68002e+06 0.5; - ram_block[119]~feeder 0xc0 7.68002e+06 0.5; - ram_block[120] 0xc0 7.68002e+06 0.5; - ram_block[121] 0xc0 7.68002e+06 0.5; - ram_block[121]~feeder 0xc0 7.68002e+06 0.5; - ram_block[122] 0xc0 7.68002e+06 0.5; - ram_block[122]~feeder 0xc0 7.68002e+06 0.5; - ram_block[123] 0xc0 7.68002e+06 0.5; - ram_block[123]~feeder 0xc0 7.68002e+06 0.5; - ram_block[124] 0xc0 7.68002e+06 0.5; - ram_block[125] 0xc0 7.68002e+06 0.5; - ram_block[125]~feeder 0xc0 7.68002e+06 0.5; - ram_block[126] 0xc0 7.68002e+06 0.5; - ram_block[126]~feeder 0xc0 7.68002e+06 0.5; - ram_block[127] 0xc0 7.68002e+06 0.5; - ram_block[128] 0xc0 7.68002e+06 0.5; - ram_block[128]~feeder 0xc0 7.68002e+06 0.5; - ram_block[129] 0xc0 7.68002e+06 0.5; - ram_block[129]~feeder 0xc0 7.68002e+06 0.5; - ram_block[130] 0xc0 7.68002e+06 0.5; - ram_block[130]~feeder 0xc0 7.68002e+06 0.5; - ram_block[131] 0xc0 7.68002e+06 0.5; - ram_block[131]~feeder 0xc0 7.68002e+06 0.5; - ram_block[132] 0xc0 7.68002e+06 0.5; - ram_block[133] 0xc0 7.68002e+06 0.5; - ram_block[133]~feeder 0xc0 7.68002e+06 0.5; - ram_block[134] 0xc0 7.68002e+06 0.5; - ram_block[134]~feeder 0xc0 7.68002e+06 0.5; - ram_block[135] 0xc0 7.68002e+06 0.5; - ram_block[135]~feeder 0xc0 7.68002e+06 0.5; - ram_block[136] 0xc0 7.68002e+06 0.5; - ram_block[137] 0xc0 7.68002e+06 0.5; - ram_block[137]~feeder 0xc0 7.68002e+06 0.5; - ram_block[138] 0xc0 7.68002e+06 0.5; - ram_block[138]~feeder 0xc0 7.68002e+06 0.5; - ram_block[139] 0xc0 7.68002e+06 0.5; - ram_block[139]~feeder 0xc0 7.68002e+06 0.5; - ram_block[140] 0xc0 7.68002e+06 0.5; - ram_block[140]~feeder 0xc0 7.68002e+06 0.5; - ram_block[141] 0xc0 7.68002e+06 0.5; - ram_block[141]~feeder 0xc0 7.68002e+06 0.5; - ram_block[142] 0xc0 7.68002e+06 0.5; - ram_block[142]~feeder 0xc0 7.68002e+06 0.5; - ram_block[143] 0xc0 7.68002e+06 0.5; - ram_block[143]~feeder 0xc0 7.68002e+06 0.5; - ram_block[144] 0xc0 7.68002e+06 0.5; - ram_block[145] 0xc0 7.68002e+06 0.5; - ram_block[145]~feeder 0xc0 7.68002e+06 0.5; - ram_block[146] 0xc0 7.68002e+06 0.5; - ram_block[147] 0xc0 7.68002e+06 0.5; - ram_block[147]~feeder 0xc0 7.68002e+06 0.5; - ram_block[148] 0xc0 7.68002e+06 0.5; - ram_block[148]~feeder 0xc0 7.68002e+06 0.5; - ram_block[149] 0xc0 7.68002e+06 0.5; - ram_block[149]~feeder 0xc0 7.68002e+06 0.5; - ram_block[150] 0xc0 7.68002e+06 0.5; - ram_block[150]~feeder 0xc0 7.68002e+06 0.5; - ram_block[151] 0xc0 7.68002e+06 0.5; - ram_block[151]~feeder 0xc0 7.68002e+06 0.5; - ram_block[152] 0xc0 7.68002e+06 0.5; - ram_block[152]~feeder 0xc0 7.68002e+06 0.5; - ram_block[153] 0xc0 7.68002e+06 0.5; - ram_block[153]~feeder 0xc0 7.68002e+06 0.5; - ram_block[154] 0xc0 7.68002e+06 0.5; - ram_block[154]~feeder 0xc0 7.68002e+06 0.5; - ram_block[155] 0xc0 7.68002e+06 0.5; - ram_block[155]~feeder 0xc0 7.68002e+06 0.5; - ram_block[156] 0xc0 7.68002e+06 0.5; - ram_block[156]~feeder 0xc0 7.68002e+06 0.5; - ram_block[157] 0xc0 7.68002e+06 0.5; - ram_block[158] 0xc0 7.68002e+06 0.5; - ram_block[159] 0xc0 7.68002e+06 0.5; - ram_block[159]~feeder 0xc0 7.68002e+06 0.5; - ram_block[160] 0xc0 7.68002e+06 0.5; - ram_block[160]~feeder 0xc0 7.68002e+06 0.5; - ram_block[161] 0xc0 7.68002e+06 0.5; - ram_block[161]~feeder 0xc0 7.68002e+06 0.5; - ram_block[162] 0xc0 7.68002e+06 0.5; - ram_block[162]~feeder 0xc0 7.68002e+06 0.5; - ram_block[163] 0xc0 7.68002e+06 0.5; - ram_block[163]~feeder 0xc0 7.68002e+06 0.5; - ram_block[164] 0xc0 7.68002e+06 0.5; - ram_block[164]~feeder 0xc0 7.68002e+06 0.5; - ram_block[165] 0xc0 7.68002e+06 0.5; - ram_block[165]~feeder 0xc0 7.68002e+06 0.5; - ram_block[166] 0xc0 7.68002e+06 0.5; - ram_block[166]~feeder 0xc0 7.68002e+06 0.5; - ram_block[167] 0xc0 7.68002e+06 0.5; - ram_block[168] 0xc0 7.68002e+06 0.5; - ram_block[168]~feeder 0xc0 7.68002e+06 0.5; - ram_block[169] 0xc0 7.68002e+06 0.5; - ram_block[170] 0xc0 7.68002e+06 0.5; - ram_block[170]~feeder 0xc0 7.68002e+06 0.5; - ram_block[171] 0xc0 7.68002e+06 0.5; - ram_block[172] 0xc0 7.68002e+06 0.5; - ram_block[173] 0xc0 7.68002e+06 0.5; - ram_block[173]~feeder 0xc0 7.68002e+06 0.5; - ram_block[174] 0xc0 7.68002e+06 0.5; - ram_block[174]~feeder 0xc0 7.68002e+06 0.5; - ram_block[175] 0xc0 7.68002e+06 0.5; - ram_block[175]~feeder 0xc0 7.68002e+06 0.5; - ram_block[176] 0xc0 7.68002e+06 0.5; - ram_block[177] 0xc0 7.68002e+06 0.5; - ram_block[177]~feeder 0xc0 7.68002e+06 0.5; - ram_block[178] 0xc0 7.68002e+06 0.5; - ram_block[178]~feeder 0xc0 7.68002e+06 0.5; - ram_block[179] 0xc0 7.68002e+06 0.5; - ram_block[180] 0xc0 7.68002e+06 0.5; - ram_block[181] 0xc0 7.68002e+06 0.5; - ram_block[182] 0xc0 7.68002e+06 0.5; - ram_block[183] 0xc0 7.68002e+06 0.5; - ram_block[183]~feeder 0xc0 7.68002e+06 0.5; - ram_block[184] 0xc0 7.68002e+06 0.5; - ram_block[184]~feeder 0xc0 7.68002e+06 0.5; - ram_block[185] 0xc0 7.68002e+06 0.5; - ram_block[185]~feeder 0xc0 7.68002e+06 0.5; - ram_block[186] 0xc0 7.68002e+06 0.5; - ram_block[187] 0xc0 7.68002e+06 0.5; - ram_block[187]~feeder 0xc0 7.68002e+06 0.5; - ram_block[188] 0xc0 7.68002e+06 0.5; - ram_block[189] 0xc0 7.68002e+06 0.5; - ram_block[189]~feeder 0xc0 7.68002e+06 0.5; - ram_block[190] 0xc0 7.68002e+06 0.5; - ram_block[190]~feeder 0xc0 7.68002e+06 0.5; - ram_block[191] 0xc0 7.68002e+06 0.5; - ram_block[191]~feeder 0xc0 7.68002e+06 0.5; - ram_block[192] 0xc0 7.68002e+06 0.5; - ram_block[193] 0xc0 7.68002e+06 0.5; - ram_block[193]~feeder 0xc0 7.68002e+06 0.5; - ram_block[194] 0xc0 7.68002e+06 0.5; - ram_block[195] 0xc0 7.68002e+06 0.5; - ram_block[195]~feeder 0xc0 7.68002e+06 0.5; - ram_block[196] 0xc0 7.68002e+06 0.5; - ram_block[196]~feeder 0xc0 7.68002e+06 0.5; - ram_block[197] 0xc0 7.68002e+06 0.5; - ram_block[197]~feeder 0xc0 7.68002e+06 0.5; - ram_block[198] 0xc0 7.68002e+06 0.5; - ram_block[199] 0xc0 7.68002e+06 0.5; - ram_block[200] 0xc0 7.68002e+06 0.5; - ram_block[200]~feeder 0xc0 7.68002e+06 0.5; - ram_block[201] 0xc0 7.68002e+06 0.5; - ram_block[202] 0xc0 7.68002e+06 0.5; - ram_block[203] 0xc0 7.68002e+06 0.5; - ram_block[204] 0xc0 7.68002e+06 0.5; - ram_block[205] 0xc0 7.68002e+06 0.5; - ram_block[205]~feeder 0xc0 7.68002e+06 0.5; - ram_block[206] 0xc0 7.68002e+06 0.5; - ram_block[207] 0xc0 7.68002e+06 0.5; - ram_block[208] 0xc0 7.68002e+06 0.5; - ram_block[208]~feeder 0xc0 7.68002e+06 0.5; - ram_block[209] 0xc0 7.68002e+06 0.5; - ram_block[209]~feeder 0xc0 7.68002e+06 0.5; - ram_block[210] 0xc0 7.68002e+06 0.5; - ram_block[210]~feeder 0xc0 7.68002e+06 0.5; - ram_block[211] 0xc0 7.68002e+06 0.5; - ram_block[211]~feeder 0xc0 7.68002e+06 0.5; - ram_block[212] 0xc0 7.68002e+06 0.5; - ram_block[213] 0xc0 7.68002e+06 0.5; - ram_block[214] 0xc0 7.68002e+06 0.5; - ram_block[215] 0xc0 7.68002e+06 0.5; - ram_block[215]~feeder 0xc0 7.68002e+06 0.5; - ram_block[216] 0xc0 7.68002e+06 0.5; - ram_block[217] 0xc0 7.68002e+06 0.5; - ram_block[218] 0xc0 7.68002e+06 0.5; - ram_block[218]~feeder 0xc0 7.68002e+06 0.5; - ram_block[219] 0xc0 7.68002e+06 0.5; - ram_block[220] 0xc0 7.68002e+06 0.5; - ram_block[220]~feeder 0xc0 7.68002e+06 0.5; - ram_block[221] 0xc0 7.68002e+06 0.5; - ram_block[221]~feeder 0xc0 7.68002e+06 0.5; - ram_block[222] 0xc0 7.68002e+06 0.5; - ram_block[222]~feeder 0xc0 7.68002e+06 0.5; - ram_block[223] 0xc0 7.68002e+06 0.5; - ram_block[223]~feeder 0xc0 7.68002e+06 0.5; - ram_block[224] 0xc0 7.68002e+06 0.5; - ram_block[224]~feeder 0xc0 7.68002e+06 0.5; - ram_block[225] 0xc0 7.68002e+06 0.5; - ram_block[225]~feeder 0xc0 7.68002e+06 0.5; - ram_block[226] 0xc0 7.68002e+06 0.5; - ram_block[227] 0xc0 7.68002e+06 0.5; - ram_block[227]~feeder 0xc0 7.68002e+06 0.5; - ram_block[228] 0xc0 7.68002e+06 0.5; - ram_block[228]~feeder 0xc0 7.68002e+06 0.5; - ram_block[229] 0xc0 7.68002e+06 0.5; - ram_block[230] 0xc0 7.68002e+06 0.5; - ram_block[230]~feeder 0xc0 7.68002e+06 0.5; - ram_block[231] 0xc0 7.68002e+06 0.5; - ram_block[232] 0xc0 7.68002e+06 0.5; - ram_block[232]~feeder 0xc0 7.68002e+06 0.5; - ram_block[233] 0xc0 7.68002e+06 0.5; - ram_block[234] 0xc0 7.68002e+06 0.5; - ram_block[234]~feeder 0xc0 7.68002e+06 0.5; - ram_block[235] 0xc0 7.68002e+06 0.5; - ram_block[235]~feeder 0xc0 7.68002e+06 0.5; - ram_block[236] 0xc0 7.68002e+06 0.5; - ram_block[237] 0xc0 7.68002e+06 0.5; - ram_block[238] 0xc0 7.68002e+06 0.5; - ram_block[238]~feeder 0xc0 7.68002e+06 0.5; - ram_block[239] 0xc0 7.68002e+06 0.5; - ram_block[239]~feeder 0xc0 7.68002e+06 0.5; - ram_block[240] 0xc0 7.68002e+06 0.5; - ram_block[241] 0xc0 7.68002e+06 0.5; - ram_block[242] 0xc0 7.68002e+06 0.5; - ram_block[242]~feeder 0xc0 7.68002e+06 0.5; - ram_block[243] 0xc0 7.68002e+06 0.5; - ram_block[243]~feeder 0xc0 7.68002e+06 0.5; - ram_block[244] 0xc0 7.68002e+06 0.5; - ram_block[245] 0xc0 7.68002e+06 0.5; - ram_block[246] 0xc0 7.68002e+06 0.5; - ram_block[247] 0xc0 7.68002e+06 0.5; - ram_block[247]~feeder 0xc0 7.68002e+06 0.5; - ram_block[248] 0xc0 7.68002e+06 0.5; - ram_block[248]~feeder 0xc0 7.68002e+06 0.5; - ram_block[249] 0xc0 7.68002e+06 0.5; - ram_block[249]~feeder 0xc0 7.68002e+06 0.5; - ram_block[250] 0xc0 7.68002e+06 0.5; - ram_block[250]~feeder 0xc0 7.68002e+06 0.5; - ram_block[251] 0xc0 7.68002e+06 0.5; - ram_block[252] 0xc0 7.68002e+06 0.5; - ram_block[252]~feeder 0xc0 7.68002e+06 0.5; - ram_block[253] 0xc0 7.68002e+06 0.5; - ram_block[253]~feeder 0xc0 7.68002e+06 0.5; - ram_block[254] 0xc0 7.68002e+06 0.5; - ram_block[255] 0xc0 7.68002e+06 0.5; - ram_block[255]~feeder 0xc0 7.68002e+06 0.5; - ram_block[256] 0xc0 7.68002e+06 0.5; - ram_block[256]~feeder 0xc0 7.68002e+06 0.5; - ram_block[257] 0xc0 7.68002e+06 0.5; - ram_block[258] 0xc0 7.68002e+06 0.5; - ram_block[259] 0xc0 7.68002e+06 0.5; - ram_block[260] 0xc0 7.68002e+06 0.5; - ram_block[260]~feeder 0xc0 7.68002e+06 0.5; - ram_block[261] 0xc0 7.68002e+06 0.5; - ram_block[262] 0xc0 7.68002e+06 0.5; - ram_block[263] 0xc0 7.68002e+06 0.5; - ram_block[263]~feeder 0xc0 7.68002e+06 0.5; - ram_block[264] 0xc0 7.68002e+06 0.5; - ram_block[264]~feeder 0xc0 7.68002e+06 0.5; - ram_block[265] 0xc0 7.68002e+06 0.5; - ram_block[265]~feeder 0xc0 7.68002e+06 0.5; - ram_block[266] 0xc0 7.68002e+06 0.5; - ram_block[266]~feeder 0xc0 7.68002e+06 0.5; - ram_block[267] 0xc0 7.68002e+06 0.5; - ram_block[267]~feeder 0xc0 7.68002e+06 0.5; - ram_block[268] 0xc0 7.68002e+06 0.5; - ram_block[269] 0xc0 7.68002e+06 0.5; - ram_block[269]~feeder 0xc0 7.68002e+06 0.5; - ram_block[270] 0xc0 7.68002e+06 0.5; - ram_block[271] 0xc0 7.68002e+06 0.5; - ram_block[271]~feeder 0xc0 7.68002e+06 0.5; - ram_block[272] 0xc0 7.68002e+06 0.5; - ram_block[273] 0xc0 7.68002e+06 0.5; - ram_block[273]~feeder 0xc0 7.68002e+06 0.5; - ram_block[274] 0xc0 7.68002e+06 0.5; - ram_block[274]~feeder 0xc0 7.68002e+06 0.5; - ram_block[275] 0xc0 7.68002e+06 0.5; - ram_block[275]~feeder 0xc0 7.68002e+06 0.5; - ram_block[276] 0xc0 7.68002e+06 0.5; - ram_block[277] 0xc0 7.68002e+06 0.5; - ram_block[277]~feeder 0xc0 7.68002e+06 0.5; - ram_block[278] 0xc0 7.68002e+06 0.5; - ram_block[279] 0xc0 7.68002e+06 0.5; - ram_block[279]~feeder 0xc0 7.68002e+06 0.5; - ram_block[280] 0xc0 7.68002e+06 0.5; - ram_block[281] 0xc0 7.68002e+06 0.5; - ram_block[281]~feeder 0xc0 7.68002e+06 0.5; - ram_block[282] 0xc0 7.68002e+06 0.5; - ram_block[283] 0xc0 7.68002e+06 0.5; - ram_block[283]~feeder 0xc0 7.68002e+06 0.5; - ram_block[284] 0xc0 7.68002e+06 0.5; - ram_block[284]~feeder 0xc0 7.68002e+06 0.5; - ram_block[285] 0xc0 7.68002e+06 0.5; - ram_block[286] 0xc0 7.68002e+06 0.5; - ram_block[286]~feeder 0xc0 7.68002e+06 0.5; - ram_block[287] 0xc0 7.68002e+06 0.5; - ram_block[287]~feeder 0xc0 7.68002e+06 0.5; - ram_block[288] 0xc0 7.68002e+06 0.5; - ram_block[288]~feeder 0xc0 7.68002e+06 0.5; - ram_block[289] 0xc0 7.68002e+06 0.5; - ram_block[290] 0xc0 7.68002e+06 0.5; - ram_block[291] 0xc0 7.68002e+06 0.5; - ram_block[292] 0xc0 7.68002e+06 0.5; - ram_block[292]~feeder 0xc0 7.68002e+06 0.5; - ram_block[293] 0xc0 7.68002e+06 0.5; - ram_block[294] 0xc0 7.68002e+06 0.5; - ram_block[295] 0xc0 7.68002e+06 0.5; - ram_block[295]~feeder 0xc0 7.68002e+06 0.5; - ram_block[296] 0xc0 7.68002e+06 0.5; - ram_block[297] 0xc0 7.68002e+06 0.5; - ram_block[297]~feeder 0xc0 7.68002e+06 0.5; - ram_block[298] 0xc0 7.68002e+06 0.5; - ram_block[298]~feeder 0xc0 7.68002e+06 0.5; - ram_block[299] 0xc0 7.68002e+06 0.5; - ram_block[300] 0xc0 7.68002e+06 0.5; - ram_block[300]~feeder 0xc0 7.68002e+06 0.5; - ram_block[301] 0xc0 7.68002e+06 0.5; - ram_block[302] 0xc0 7.68002e+06 0.5; - ram_block[302]~feeder 0xc0 7.68002e+06 0.5; - ram_block[303] 0xc0 7.68002e+06 0.5; - ram_block[303]~feeder 0xc0 7.68002e+06 0.5; - ram_block[304] 0xc0 7.68002e+06 0.5; - ram_block[304]~feeder 0xc0 7.68002e+06 0.5; - ram_block[305] 0xc0 7.68002e+06 0.5; - ram_block[305]~feeder 0xc0 7.68002e+06 0.5; - ram_block[306] 0xc0 7.68002e+06 0.5; - ram_block[306]~feeder 0xc0 7.68002e+06 0.5; - ram_block[307] 0xc0 7.68002e+06 0.5; - ram_block[307]~feeder 0xc0 7.68002e+06 0.5; - ram_block[308] 0xc0 7.68002e+06 0.5; - ram_block[308]~feeder 0xc0 7.68002e+06 0.5; - ram_block[309] 0xc0 7.68002e+06 0.5; - ram_block[309]~feeder 0xc0 7.68002e+06 0.5; - ram_block[310] 0xc0 7.68002e+06 0.5; - ram_block[311] 0xc0 7.68002e+06 0.5; - ram_block[311]~feeder 0xc0 7.68002e+06 0.5; - ram_block[312] 0xc0 7.68002e+06 0.5; - ram_block[313] 0xc0 7.68002e+06 0.5; - ram_block[314] 0xc0 7.68002e+06 0.5; - ram_block[314]~feeder 0xc0 7.68002e+06 0.5; - ram_block[315] 0xc0 7.68002e+06 0.5; - ram_block[316] 0xc0 7.68002e+06 0.5; - ram_block[317] 0xc0 7.68002e+06 0.5; - ram_block[317]~feeder 0xc0 7.68002e+06 0.5; - ram_block[318] 0xc0 7.68002e+06 0.5; - ram_block[319] 0xc0 7.68002e+06 0.5; - ram_block[319]~feeder 0xc0 7.68002e+06 0.5; - ram_block[320] 0xc0 7.68002e+06 0.5; - ram_block[321] 0xc0 7.68002e+06 0.5; - ram_block[321]~feeder 0xc0 7.68002e+06 0.5; - ram_block[322] 0xc0 7.68002e+06 0.5; - ram_block[322]~feeder 0xc0 7.68002e+06 0.5; - ram_block[323] 0xc0 7.68002e+06 0.5; - ram_block[323]~feeder 0xc0 7.68002e+06 0.5; - ram_block[324] 0xc0 7.68002e+06 0.5; - ram_block[324]~feeder 0xc0 7.68002e+06 0.5; - ram_block[325] 0xc0 7.68002e+06 0.5; - ram_block[325]~feeder 0xc0 7.68002e+06 0.5; - ram_block[326] 0xc0 7.68002e+06 0.5; - ram_block[326]~feeder 0xc0 7.68002e+06 0.5; - ram_block[327] 0xc0 7.68002e+06 0.5; - ram_block[328] 0xc0 7.68002e+06 0.5; - ram_block[329] 0xc0 7.68002e+06 0.5; - ram_block[329]~feeder 0xc0 7.68002e+06 0.5; - ram_block[330] 0xc0 7.68002e+06 0.5; - ram_block[330]~feeder 0xc0 7.68002e+06 0.5; - ram_block[331] 0xc0 7.68002e+06 0.5; - ram_block[331]~feeder 0xc0 7.68002e+06 0.5; - ram_block[332] 0xc0 7.68002e+06 0.5; - ram_block[332]~feeder 0xc0 7.68002e+06 0.5; - ram_block[333] 0xc0 7.68002e+06 0.5; - ram_block[333]~feeder 0xc0 7.68002e+06 0.5; - ram_block[334] 0xc0 7.68002e+06 0.5; - ram_block[335] 0xc0 7.68002e+06 0.5; - ram_block[335]~feeder 0xc0 7.68002e+06 0.5; - ram_block[336] 0xc0 7.68002e+06 0.5; - ram_block[336]~feeder 0xc0 7.68002e+06 0.5; - ram_block[337] 0xc0 7.68002e+06 0.5; - ram_block[337]~feeder 0xc0 7.68002e+06 0.5; - ram_block[338] 0xc0 7.68002e+06 0.5; - ram_block[339] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[0] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[1] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[2] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[3] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[4] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[5] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[6] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[7] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[8] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[9] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[10] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[11] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[12] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[13] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[14] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[15] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[16] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[17] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[18] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[19] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[20] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[21] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[22] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[23] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[24] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[25] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[26] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[27] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[28] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[29] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[30] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[31] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[32] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[33] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[34] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[35] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[36] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[37] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[38] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[39] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[40] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[41] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[42] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[43] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[44] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[45] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[46] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[47] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[48] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[49] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[50] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[51] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[52] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[53] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[54] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[55] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[56] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[57] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[58] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[59] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[60] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[61] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[62] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[63] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[64] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[65] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[66] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[67] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[68] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[69] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[70] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[71] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[72] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[73] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[74] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[75] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[76] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[77] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[78] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[79] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[80] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[81] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[82] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[83] 0xc0 7.68002e+06 0.5; - rd_data_out_latch[84] 0xc0 7.68002e+06 0.5; - wren_reg 0xc0 7.68002e+06 0.5; - wren_reg~feeder 0xc0 39.5439 6.10352e-05; - full_dff 0xc0 7.68002e+06 0.5; - low_addressa[0] 0xc0 7.68002e+06 0.5; - low_addressa[0]~0 0xc0 2.35547e+06 0.25; - low_addressa[1] 0xc0 7.68002e+06 0.5; - low_addressa[1]~1 0xc0 2.35547e+06 0.25; - ram_read_address[0]~0 0xc0 5.02501e+06 0.5; - ram_read_address[1]~1 0xc0 3.83251e+06 0.5; - rd_ptr_lsb 0xc0 7.68002e+06 0.5; - rd_ptr_lsb~0 0xc0 4.32001e+06 0.25; - rd_ptr_lsb~1 0xc0 5.49001e+06 0.5625; - cntr_q9b:rd_ptr_msb; - _~0 0xc0 9.09002e+06 0.53125; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - cntr_7a7:usedw_counter; - _~0 0xc0 6.83841e+06 0.562523; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.6791e+06 0.5; - counter_comb_bita1 0xc0 7.67956e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - usedw_is_0_dff 0xc0 7.68002e+06 0.5; - usedw_is_1_dff 0xc0 7.68002e+06 0.5; - usedw_will_be_1~0 0xc0 9.89133e+06 0.0312748; - usedw_will_be_1~1 0xc0 4.34143e+06 0.227535; - valid_rreq 0xc0 3.36001e+06 0.125; - valid_rreq~0 0xc0 5.76001e+06 0.25; - valid_wreq~0 0xc0 1.44e+06 0.0625; - valid_wreq~1 0xc0 945002 0.0625; - valid_wreq~2 0xc0 945002 0.0625; - valid_wreq~3 0xc0 78.8589 0.00012207; - valid_wreq~4 0xc0 39.5439 6.10352e-05; - cntr_r9b:wr_ptr; - _~0 0xc0 7.67819e+06 0.500031; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.68002e+06 0.5; - counter_comb_bita1 0xc0 7.68002e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - auk_dspip_integrator:integrator[0].integration; - auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1; - \register_fifo:fifo_data[0][0] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][0]~1 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][0]~2 0xc0 4.32001e+06 0.25; - \register_fifo:fifo_data[0][1] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][1]~1 0xc0 6.48002e+06 0.5; - \register_fifo:fifo_data[0][1]~2 0xc0 3.57751e+06 0.625; - \register_fifo:fifo_data[0][2] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][2]~1 0xc0 5.48439e+06 0.5; - \register_fifo:fifo_data[0][2]~2 0xc0 6.3722e+06 0.4375; - \register_fifo:fifo_data[0][3] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][3]~1 0xc0 5.98056e+06 0.5; - \register_fifo:fifo_data[0][3]~2 0xc0 4.88779e+06 0.53125; - \register_fifo:fifo_data[0][4] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][4]~1 0xc0 5.55883e+06 0.5; - \register_fifo:fifo_data[0][4]~2 0xc0 5.4588e+06 0.484375; - \register_fifo:fifo_data[0][5] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][5]~1 0xc0 5.68893e+06 0.5; - \register_fifo:fifo_data[0][5]~2 0xc0 5.11181e+06 0.507813; - \register_fifo:fifo_data[0][6] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][6]~1 0xc0 5.59902e+06 0.5; - \register_fifo:fifo_data[0][6]~2 0xc0 5.2676e+06 0.496094; - \register_fifo:fifo_data[0][7] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][7]~1 0xc0 5.63718e+06 0.5; - \register_fifo:fifo_data[0][7]~2 0xc0 5.18499e+06 0.501953; - \register_fifo:fifo_data[0][8] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][8]~1 0xc0 5.61632e+06 0.5; - \register_fifo:fifo_data[0][8]~2 0xc0 5.22508e+06 0.499023; - \register_fifo:fifo_data[0][9] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][9]~1 0xc0 5.6263e+06 0.5; - \register_fifo:fifo_data[0][9]~2 0xc0 5.20473e+06 0.500488; - \register_fifo:fifo_data[0][10] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][10]~1 0xc0 5.6212e+06 0.5; - \register_fifo:fifo_data[0][10]~2 0xc0 5.21483e+06 0.499756; - \register_fifo:fifo_data[0][11] 0xc0 7.68002e+06 0.5; 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- \register_fifo:fifo_data[0][75]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][75]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][76] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][76]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][76]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][77] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][77]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][77]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][78] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][78]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][78]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][79] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][79]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][79]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][80] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][80]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][80]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][81] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][81]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][81]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][82] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][82]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][82]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][83] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][83]~1 0xc0 5.62287e+06 0.5; - \register_fifo:fifo_data[0][83]~2 0xc0 5.21144e+06 0.5; - \register_fifo:fifo_data[0][84] 0xc0 7.68002e+06 0.5; - \register_fifo:fifo_data[0][84]~1 0xc0 7.06288e+06 0.5; - counter_module:latency_cnt_inst; - Add0~0 0xc0 4.32001e+06 0.25; - Add0~1 0xc0 1.83e+06 0.125; - count[0] 0xc0 7.68002e+06 0.5; - count[1] 0xc0 7.68002e+06 0.5; - count[1]~4 0xc0 7.43486e+06 0.46875; - count[2] 0xc0 7.68002e+06 0.5; - count[2]~1 0xc0 5.023e+06 0.397217; - count[3] 0xc0 7.68002e+06 0.5; - count[3]~0 0xc0 4.50001e+06 0.4375; - count[3]~2 0xc0 5.08109e+06 0.38269; - count~3 0xc0 7.00455e+06 0.46875; - sample_state[0] 0xc0 7.68002e+06 0.5; - sample_state~0 0xc0 3.33001e+06 0.625; - sample_state~1 0xc0 5.52376e+06 0.671875; - state[0] 0xc0 7.68002e+06 0.5; - state~0 0xc0 8.5705e+06 0.515625; - auk_dspip_downsample:vrc_en_0.first_dsample; - counter_module:counter_fs_inst; - Add0~0 0xc0 7.68002e+06 0.5; - Add0~1 0xc0 7.68002e+06 0.5; - Add0~2 0xc0 7.68002e+06 0.5; - Add0~3 0xc0 4.32001e+06 0.75; - Add0~4 0xc0 6.96002e+06 0.5; - Add0~5 0xc0 5.88002e+06 0.125; - Add0~6 0xc0 8.94002e+06 0.5; - Add0~7 0xc0 1.71e+06 0.9375; - Add0~8 0xc0 7.63502e+06 0.5; - Add0~9 0xc0 7.20752e+06 0.03125; - Add0~10 0xc0 1.08188e+07 0.5; - Add0~11 0xc0 1.81688e+06 0.984375; - Add0~12 0xc0 8.35221e+06 0.5; - Add0~13 0xc0 7.89799e+06 0.0078125; - Add0~14 0xc0 1.151e+07 0.5; - Add0~15 0xc0 1.97543e+06 0.996094; - Add0~16 0xc0 8.60797e+06 0.5; - Add0~17 0xc0 8.11411e+06 0.00195313; - Add0~18 0xc0 1.17071e+07 0.5; - Add0~19 0xc0 2.02859e+06 0.999023; - Add0~20 0xc0 8.67933e+06 0.5; - Equal0~0 0xc0 691877 0.0625; - Equal0~1 0xc0 691877 0.0625; - Equal0~2 0xc0 4.32001e+06 0.25; - Equal0~3 0xc0 680.111 0.000488281; - count[0] 0xc0 7.68002e+06 0.5; - count[1] 0xc0 7.68002e+06 0.5; - count[2] 0xc0 7.68002e+06 0.5; - count[3] 0xc0 7.68002e+06 0.5; - count[4] 0xc0 7.68002e+06 0.5; - count[5] 0xc0 7.68002e+06 0.5; - count[6] 0xc0 7.68002e+06 0.5; - count[7] 0xc0 7.68002e+06 0.5; - count[8] 0xc0 7.68002e+06 0.5; - count[9] 0xc0 7.68002e+06 0.5; - count[10] 0xc0 7.68002e+06 0.5; - count~0 0xc0 1.71993e+07 0.499756; - count~1 0xc0 3.33001e+06 0.625; - count~2 0xc0 1.73419e+07 0.499756; - auk_dspip_avalon_streaming_sink:input_sink; - scfifo:sink_FIFO; - scfifo_ef71:auto_generated; - dffe_nae 0xc0 7.68002e+06 0.5; - dffe_nae~0 0xc0 1.38e+06 0.125; - dffe_nae~1 0xc0 3.22338e+06 0.524597; - a_dpfifo_vkv:dpfifo; - _~0 0xc0 1.125e+06 0.0625; - _~1 0xc0 3.96815e+06 0.502975; - _~2 0xc0 4.48034e+06 0.276611; - _~3 0xc0 1.17145e+06 0.0199585; - empty_dff 0xc0 7.68002e+06 0.5; - empty_dff~0 0xc0 3.20227e+06 0.312783; - empty_dff~1 0xc0 3.26241e+06 0.295563; - altsyncram_h7h1:FIFOram; - q_b[0] 0xc0 7.68002e+06 0.5; - q_b[1] 0xc0 7.68002e+06 0.5; - q_b[2] 0xc0 7.68002e+06 0.5; - q_b[3] 0xc0 7.68002e+06 0.5; - q_b[4] 0xc0 7.68002e+06 0.5; - q_b[5] 0xc0 7.68002e+06 0.5; - q_b[6] 0xc0 7.68002e+06 0.5; - q_b[7] 0xc0 7.68002e+06 0.5; - q_b[8] 0xc0 7.68002e+06 0.5; - q_b[9] 0xc0 7.68002e+06 0.5; - q_b[10] 0xc0 7.68002e+06 0.5; - q_b[11] 0xc0 7.68002e+06 0.5; - q_b[12] 0xc0 7.68002e+06 0.5; - q_b[13] 0xc0 7.68002e+06 0.5; - q_b[14] 0xc0 7.68002e+06 0.5; - q_b[15] 0xc0 7.68002e+06 0.5; - q_b[16] 0xc0 7.68002e+06 0.5; - q_b[17] 0xc0 7.68002e+06 0.5; - q_b[18] 0xc0 7.68002e+06 0.5; - q_b[19] 0xc0 7.68002e+06 0.5; - q_b[20] 0xc0 7.68002e+06 0.5; - q_b[21] 0xc0 7.68002e+06 0.5; - q_b[22] 0xc0 7.68002e+06 0.5; - full_dff 0xc0 7.68002e+06 0.5; - low_addressa[0] 0xc0 7.68002e+06 0.5; - low_addressa[0]~0 0xc0 2.45646e+06 0.25; - low_addressa[1] 0xc0 7.68002e+06 0.5; - low_addressa[1]~1 0xc0 2.45646e+06 0.25; - low_addressa[2] 0xc0 7.68002e+06 0.5; - low_addressa[2]~2 0xc0 2.45646e+06 0.25; - ram_read_address[0]~0 0xc0 4.78524e+06 0.5; - ram_read_address[1]~1 0xc0 3.44126e+06 0.5; - ram_read_address[2]~2 0xc0 4.33725e+06 0.5; - rd_ptr_lsb 0xc0 7.68002e+06 0.5; - rd_ptr_lsb~0 0xc0 4.32001e+06 0.25; - rd_ptr_lsb~1 0xc0 3.96432e+06 0.526611; - cntr_r9b:rd_ptr_msb; - _~0 0xc0 9.47158e+06 0.513306; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.68002e+06 0.5; - counter_comb_bita1 0xc0 7.68002e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - cntr_8a7:usedw_counter; - _~0 0xc0 5.94778e+06 0.638306; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.68002e+06 0.5; - counter_comb_bita1 0xc0 7.68002e+06 0.5; - counter_comb_bita1~COUT 0xc0 4.86001e+06 0.75; - counter_comb_bita2 0xc0 7.23002e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - counter_reg_bit[2] 0xc0 7.68002e+06 0.5; - usedw_is_0_dff 0xc0 7.68002e+06 0.5; - usedw_is_1_dff 0xc0 7.68002e+06 0.5; - usedw_will_be_1~0 0xc0 2.00251e+06 0.09375; - usedw_will_be_1~1 0xc0 2.64001e+06 0.125; - usedw_will_be_1~2 0xc0 2.23069e+06 0.123337; - usedw_will_be_1~3 0xc0 2.34269e+06 0.22021; - valid_rreq 0xc0 389996 0.0532227; - valid_wreq 0xc0 5.76001e+06 0.25; - cntr_s9b:wr_ptr; - _~0 0xc0 5.76001e+06 0.625; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.68002e+06 0.5; - counter_comb_bita1 0xc0 7.68002e+06 0.5; - counter_comb_bita1~COUT 0xc0 4.32001e+06 0.75; - counter_comb_bita2 0xc0 6.96002e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - counter_reg_bit[2] 0xc0 7.68002e+06 0.5; - auk_dspip_avalon_streaming_source:output_source_0; - scfifo:source_FIFO; - scfifo_ai71:auto_generated; - a_dpfifo_7qv:dpfifo; - _~0 0xc0 1.00875e+06 0.03125; - _~1 0xc0 8.36006e+06 0.250488; - empty_dff 0xc0 7.68002e+06 0.5; - empty_dff~2 0xc0 8.51346e+06 0.515625; - empty_dff~3 0xc0 4.70234e+06 0.257813; - empty_dff~4 0xc0 7.33864e+06 0.723618; - empty_dff~5 0xc0 1.06878e+07 0.253359; - altsyncram_dah1:FIFOram; - q_b[0] 0xc0 7.68002e+06 0.5; - q_b[1] 0xc0 7.68002e+06 0.5; - q_b[2] 0xc0 7.68002e+06 0.5; - q_b[3] 0xc0 7.68002e+06 0.5; - q_b[4] 0xc0 7.68002e+06 0.5; - q_b[5] 0xc0 7.68002e+06 0.5; - q_b[6] 0xc0 7.68002e+06 0.5; - q_b[7] 0xc0 7.68002e+06 0.5; - q_b[8] 0xc0 7.68002e+06 0.5; - q_b[9] 0xc0 7.68002e+06 0.5; - q_b[10] 0xc0 7.68002e+06 0.5; - q_b[11] 0xc0 7.68002e+06 0.5; - q_b[12] 0xc0 7.68002e+06 0.5; - q_b[13] 0xc0 7.68002e+06 0.5; - q_b[14] 0xc0 7.68002e+06 0.5; - q_b[15] 0xc0 7.68002e+06 0.5; - q_b[16] 0xc0 7.68002e+06 0.5; - q_b[17] 0xc0 7.68002e+06 0.5; - q_b[18] 0xc0 7.68002e+06 0.5; - q_b[19] 0xc0 7.68002e+06 0.5; - q_b[20] 0xc0 7.68002e+06 0.5; - q_b[21] 0xc0 7.68002e+06 0.5; - q_b[22] 0xc0 7.68002e+06 0.5; - q_b[23] 0xc0 7.68002e+06 0.5; - q_b[24] 0xc0 7.68002e+06 0.5; - q_b[25] 0xc0 7.68002e+06 0.5; - q_b[26] 0xc0 7.68002e+06 0.5; - q_b[27] 0xc0 7.68002e+06 0.5; - q_b[28] 0xc0 7.68002e+06 0.5; - q_b[29] 0xc0 7.68002e+06 0.5; - q_b[30] 0xc0 7.68002e+06 0.5; - q_b[31] 0xc0 7.68002e+06 0.5; - full_dff 0xc0 7.68002e+06 0.5; - low_addressa[0] 0xc0 7.68002e+06 0.5; - low_addressa[0]~0 0xc0 1.9125e+06 0.25; - low_addressa[1] 0xc0 7.68002e+06 0.5; - low_addressa[1]~1 0xc0 1.9125e+06 0.25; - low_addressa[2] 0xc0 7.68002e+06 0.5; - low_addressa[2]~2 0xc0 1.9125e+06 0.25; - low_addressa[3] 0xc0 7.68002e+06 0.5; - low_addressa[3]~3 0xc0 1.9125e+06 0.25; - low_addressa[4] 0xc0 7.68002e+06 0.5; - low_addressa[4]~4 0xc0 1.9125e+06 0.25; - ram_read_address[0]~0 0xc0 4.62001e+06 0.5; - ram_read_address[1]~1 0xc0 5.52001e+06 0.5; - ram_read_address[2]~2 0xc0 7.68002e+06 0.5; - ram_read_address[3]~3 0xc0 5.52001e+06 0.5; - ram_read_address[4]~4 0xc0 7.68002e+06 0.5; - rd_ptr_lsb 0xc0 7.68002e+06 0.5; - rd_ptr_lsb~0 0xc0 4.32001e+06 0.25; - rd_ptr_lsb~1 0xc0 4.32001e+06 0.75; - cntr_t9b:rd_ptr_msb; - _~0 0xc0 5.76001e+06 0.625; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.68002e+06 0.5; - counter_comb_bita1 0xc0 7.68002e+06 0.5; - counter_comb_bita1~COUT 0xc0 4.32001e+06 0.75; - counter_comb_bita2 0xc0 6.96002e+06 0.5; - counter_comb_bita2~COUT 0xc0 5.88002e+06 0.125; - counter_comb_bita3 0xc0 8.94002e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - counter_reg_bit[2] 0xc0 7.68002e+06 0.5; - counter_reg_bit[3] 0xc0 7.68002e+06 0.5; - cntr_aa7:usedw_counter; - _~0 0xc0 5.43939e+06 0.75; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.41002e+06 0.5; - counter_comb_bita1 0xc0 7.54502e+06 0.5; - counter_comb_bita1~COUT 0xc0 6.91592e+06 0.75; - counter_comb_bita2 0xc0 8.25797e+06 0.5; - counter_comb_bita2~COUT 0xc0 9.97139e+06 0.125; - counter_comb_bita3 0xc0 1.09857e+07 0.5; - counter_comb_bita3~COUT 0xc0 2.53822e+06 0.9375; - counter_comb_bita4 0xc0 8.04913e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - counter_reg_bit[2] 0xc0 7.68002e+06 0.5; - counter_reg_bit[3] 0xc0 7.68002e+06 0.5; - counter_reg_bit[4] 0xc0 7.68002e+06 0.5; - usedw_is_0_dff 0xc0 7.68002e+06 0.5; - usedw_is_1_dff 0xc0 7.68002e+06 0.5; - usedw_will_be_1~0 0xc0 945002 0.0625; - usedw_will_be_1~1 0xc0 151239 0.0146484; - usedw_will_be_1~2 0xc0 7.46346e+06 0.265625; - usedw_will_be_1~3 0xc0 4.32001e+06 0.25; - usedw_will_be_1~4 0xc0 2.82266e+06 0.138191; - valid_wreq~0 0xc0 1.26e+06 0.0625; - cntr_u9b:wr_ptr; - _~0 0xc0 7.38002e+06 0.53125; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.68002e+06 0.5; - counter_comb_bita1 0xc0 7.68002e+06 0.5; - counter_comb_bita1~COUT 0xc0 4.32001e+06 0.75; - counter_comb_bita2 0xc0 6.96002e+06 0.5; - counter_comb_bita2~COUT 0xc0 5.88002e+06 0.125; - counter_comb_bita3 0xc0 8.94002e+06 0.5; - counter_comb_bita3~COUT 0xc0 1.71e+06 0.9375; - counter_comb_bita4 0xc0 7.63502e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - counter_reg_bit[2] 0xc0 7.68002e+06 0.5; - counter_reg_bit[3] 0xc0 7.68002e+06 0.5; - counter_reg_bit[4] 0xc0 7.68002e+06 0.5; - source_valid_s 0xc0 7.68002e+06 0.5; - source_valid_s~0 0xc0 4.32001e+06 0.25; - rx_ciccomp:RX_CICCOMP_I; - rx_ciccomp_0002:rx_ciccomp_inst; - rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst; - rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[0] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[0]~1 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[0]~2 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[1] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[1]~1 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[1]~2 0xc0 4.32001e+06 0.25; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[2] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[2]~1 0xc0 6.96002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[2]~2 0xc0 2.04001e+06 0.875; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[3] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[3]~1 0xc0 7.02002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[3]~2 0xc0 6.51002e+06 0.0625; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[4] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[4]~1 0xc0 1.0035e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[4]~2 0xc0 1.6875e+06 0.96875; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[5] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[5]~1 0xc0 8.05877e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[5]~2 0xc0 7.63689e+06 0.015625; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[6] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[6]~1 0xc0 1.12622e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[6]~2 0xc0 1.91297e+06 0.992188; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[7] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[7]~1 0xc0 8.51744e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[7]~2 0xc0 8.0392e+06 0.00390625; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8]~1 0xc0 1.16399e+07 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[0] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[1] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[2] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[3] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[4] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[5] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[6] 0xc0 7.68002e+06 0.5; - Add0~0 0xc0 7.68002e+06 0.5; - Add0~1 0xc0 7.68002e+06 0.5; - Add0~2 0xc0 7.68002e+06 0.5; - Add0~3 0xc0 4.32001e+06 0.25; - Add0~4 0xc0 6.96002e+06 0.5; - Add0~5 0xc0 2.04001e+06 0.875; - Add0~6 0xc0 7.02002e+06 0.5; - Add0~7 0xc0 6.51002e+06 0.0625; - Add0~8 0xc0 1.0035e+07 0.5; - Add0~9 0xc0 1.6875e+06 0.96875; - Add0~10 0xc0 8.05877e+06 0.5; - Add0~11 0xc0 7.63689e+06 0.015625; - Add0~12 0xc0 1.12622e+07 0.5; - Add1~0 0xc0 7.68002e+06 0.5; - Add1~1 0xc0 7.68002e+06 0.5; - Add1~2 0xc0 7.68002e+06 0.5; - Add1~3 0xc0 4.32001e+06 0.25; - Add1~4 0xc0 6.96002e+06 0.5; - Add1~5 0xc0 2.04001e+06 0.875; - Add1~6 0xc0 7.02002e+06 0.5; - Add1~7 0xc0 6.51002e+06 0.0625; - Add1~8 0xc0 1.0035e+07 0.5; - Add1~9 0xc0 1.6875e+06 0.96875; - Add1~10 0xc0 8.05877e+06 0.5; - Add1~11 0xc0 7.63689e+06 0.015625; - Add1~12 0xc0 1.12622e+07 0.5; - Add1~14 0xc0 8.13942e+06 0.5; - Add1~15 0xc0 7.8694e+06 0.5; - Add1~16 0xc0 7.16828e+06 0.5; - Add1~17 0xc0 7.35002e+06 0.5; - Add1~18 0xc0 7.32002e+06 0.5; - Add1~19 0xc0 6.24002e+06 0.5; - Add1~20 0xc0 4.80001e+06 0.5; - Add2~0 0xc0 4.39501e+06 0.5; - Add3~0 0xc0 7.68002e+06 0.5; - Add3~1 0xc0 7.68002e+06 0.5; - Add3~2 0xc0 7.68002e+06 0.5; - Add3~3 0xc0 4.32001e+06 0.25; - Add3~4 0xc0 6.96002e+06 0.5; - Add3~5 0xc0 2.04001e+06 0.875; - Add3~6 0xc0 7.02002e+06 0.5; - Add3~7 0xc0 6.51002e+06 0.0625; - Add3~8 0xc0 1.0035e+07 0.5; - Add3~9 0xc0 1.6875e+06 0.96875; - Add3~10 0xc0 8.05877e+06 0.5; - Add3~11 0xc0 7.63689e+06 0.015625; - Add3~12 0xc0 1.12622e+07 0.5; - Add3~13 0xc0 9.35299e+06 0.492188; - Add3~14 0xc0 8.51744e+06 0.5; - Add3~15 0xc0 6.0592e+06 0.753906; - Add3~16 0xc0 7.85984e+06 0.5; - Add7~0 0xc0 7.68002e+06 0.5; - Add7~1 0xc0 7.68002e+06 0.5; - Add7~2 0xc0 7.68002e+06 0.5; - Add7~2_wirecell 0xc0 7.68002e+06 0.5; - Add7~3 0xc0 4.32001e+06 0.25; - Add7~4 0xc0 6.96002e+06 0.5; - Add7~4_wirecell 0xc0 6.96002e+06 0.5; - Add7~5 0xc0 2.04001e+06 0.875; - Add7~6 0xc0 7.02002e+06 0.5; - Add7~6_wirecell 0xc0 7.02002e+06 0.5; - Add7~7 0xc0 6.51002e+06 0.0625; - Add7~8 0xc0 1.0035e+07 0.5; - Add7~8_wirecell 0xc0 1.0035e+07 0.5; - Add7~9 0xc0 1.6875e+06 0.96875; - Add7~10 0xc0 8.05877e+06 0.5; - Add7~10_wirecell 0xc0 8.05877e+06 0.5; - Add7~11 0xc0 7.63689e+06 0.015625; - Add7~12 0xc0 1.12622e+07 0.5; - dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13; - delay_signals[0][0] 0xc0 7.68002e+06 0.5; - delay_signals[0][0]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][0] 0xc0 7.68002e+06 0.5; - delay_signals[1][0]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][0] 0xc0 7.68002e+06 0.5; - dspba_delay:d_u0_m0_wo0_compute_q_15; - delay_signals[0][0] 0xc0 7.68002e+06 0.5; - delay_signals[1][0] 0xc0 7.68002e+06 0.5; - delay_signals[1][0]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][0] 0xc0 7.68002e+06 0.5; - dspba_delay:d_u0_m0_wo0_compute_q_16; - delay_signals[0][0] 0xc0 7.68002e+06 0.5; - delay_signals[0][0]~feeder 0xc0 7.68002e+06 0.5; - dspba_delay:d_xIn_0_13; - delay_signals[0][0] 0xc0 7.68002e+06 0.5; - delay_signals[0][1] 0xc0 7.68002e+06 0.5; - delay_signals[0][1]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][2] 0xc0 7.68002e+06 0.5; - delay_signals[0][3] 0xc0 7.68002e+06 0.5; - delay_signals[0][3]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][4] 0xc0 7.68002e+06 0.5; - delay_signals[0][5] 0xc0 7.68002e+06 0.5; - delay_signals[0][6] 0xc0 7.68002e+06 0.5; - delay_signals[0][6]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][7] 0xc0 7.68002e+06 0.5; - delay_signals[0][7]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][8] 0xc0 7.68002e+06 0.5; - delay_signals[0][9] 0xc0 7.68002e+06 0.5; - delay_signals[0][9]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][10] 0xc0 7.68002e+06 0.5; - delay_signals[0][11] 0xc0 7.68002e+06 0.5; - delay_signals[0][11]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][12] 0xc0 7.68002e+06 0.5; - delay_signals[0][12]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][13] 0xc0 7.68002e+06 0.5; - delay_signals[0][13]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][14] 0xc0 7.68002e+06 0.5; - delay_signals[0][14]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][15] 0xc0 7.68002e+06 0.5; - delay_signals[0][15]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][16] 0xc0 7.68002e+06 0.5; - delay_signals[0][16]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][17] 0xc0 7.68002e+06 0.5; - delay_signals[0][17]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][18] 0xc0 7.68002e+06 0.5; - delay_signals[0][18]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][19] 0xc0 7.68002e+06 0.5; - delay_signals[0][19]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][20] 0xc0 7.68002e+06 0.5; - delay_signals[0][20]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][21] 0xc0 7.68002e+06 0.5; - delay_signals[0][22] 0xc0 7.68002e+06 0.5; - delay_signals[0][22]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][23] 0xc0 7.68002e+06 0.5; - delay_signals[0][24] 0xc0 7.68002e+06 0.5; - delay_signals[0][24]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][25] 0xc0 7.68002e+06 0.5; - delay_signals[0][26] 0xc0 7.68002e+06 0.5; - delay_signals[0][26]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][27] 0xc0 7.68002e+06 0.5; - delay_signals[0][27]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][28] 0xc0 7.68002e+06 0.5; - delay_signals[0][29] 0xc0 7.68002e+06 0.5; - delay_signals[0][30] 0xc0 7.68002e+06 0.5; - delay_signals[0][31] 0xc0 7.68002e+06 0.5; - delay_signals[1][0] 0xc0 7.68002e+06 0.5; - delay_signals[1][1] 0xc0 7.68002e+06 0.5; - delay_signals[1][2] 0xc0 7.68002e+06 0.5; - delay_signals[1][3] 0xc0 7.68002e+06 0.5; - delay_signals[1][3]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][4] 0xc0 7.68002e+06 0.5; - delay_signals[1][5] 0xc0 7.68002e+06 0.5; - delay_signals[1][5]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][6] 0xc0 7.68002e+06 0.5; - delay_signals[1][6]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][7] 0xc0 7.68002e+06 0.5; - delay_signals[1][8] 0xc0 7.68002e+06 0.5; - delay_signals[1][8]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][9] 0xc0 7.68002e+06 0.5; - delay_signals[1][10] 0xc0 7.68002e+06 0.5; - delay_signals[1][10]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][11] 0xc0 7.68002e+06 0.5; - delay_signals[1][12] 0xc0 7.68002e+06 0.5; - delay_signals[1][12]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][13] 0xc0 7.68002e+06 0.5; - delay_signals[1][13]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][14] 0xc0 7.68002e+06 0.5; - delay_signals[1][14]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][15] 0xc0 7.68002e+06 0.5; - delay_signals[1][15]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][16] 0xc0 7.68002e+06 0.5; - delay_signals[1][17] 0xc0 7.68002e+06 0.5; - delay_signals[1][17]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][18] 0xc0 7.68002e+06 0.5; - delay_signals[1][18]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][19] 0xc0 7.68002e+06 0.5; - delay_signals[1][19]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][20] 0xc0 7.68002e+06 0.5; - delay_signals[1][20]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][21] 0xc0 7.68002e+06 0.5; - delay_signals[1][22] 0xc0 7.68002e+06 0.5; - delay_signals[1][22]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][23] 0xc0 7.68002e+06 0.5; - delay_signals[1][23]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][24] 0xc0 7.68002e+06 0.5; - delay_signals[1][25] 0xc0 7.68002e+06 0.5; - delay_signals[1][25]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][26] 0xc0 7.68002e+06 0.5; - delay_signals[1][27] 0xc0 7.68002e+06 0.5; - delay_signals[1][27]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][28] 0xc0 7.68002e+06 0.5; - delay_signals[1][28]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][29] 0xc0 7.68002e+06 0.5; - delay_signals[1][29]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][30] 0xc0 7.68002e+06 0.5; - delay_signals[1][30]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][31] 0xc0 7.68002e+06 0.5; - delay_signals[1][31]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][0] 0xc0 7.68002e+06 0.5; - delay_signals[2][0]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][1] 0xc0 7.68002e+06 0.5; - delay_signals[2][2] 0xc0 7.68002e+06 0.5; - delay_signals[2][2]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][3] 0xc0 7.68002e+06 0.5; - delay_signals[2][3]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][4] 0xc0 7.68002e+06 0.5; - delay_signals[2][5] 0xc0 7.68002e+06 0.5; - delay_signals[2][6] 0xc0 7.68002e+06 0.5; - delay_signals[2][6]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][7] 0xc0 7.68002e+06 0.5; - delay_signals[2][7]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][8] 0xc0 7.68002e+06 0.5; - delay_signals[2][8]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][9] 0xc0 7.68002e+06 0.5; - delay_signals[2][9]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][10] 0xc0 7.68002e+06 0.5; - delay_signals[2][10]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][11] 0xc0 7.68002e+06 0.5; - delay_signals[2][11]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][12] 0xc0 7.68002e+06 0.5; - delay_signals[2][13] 0xc0 7.68002e+06 0.5; - delay_signals[2][14] 0xc0 7.68002e+06 0.5; - delay_signals[2][14]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][15] 0xc0 7.68002e+06 0.5; - delay_signals[2][15]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][16] 0xc0 7.68002e+06 0.5; - delay_signals[2][16]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][17] 0xc0 7.68002e+06 0.5; - delay_signals[2][17]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][18] 0xc0 7.68002e+06 0.5; - delay_signals[2][18]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][19] 0xc0 7.68002e+06 0.5; - delay_signals[2][20] 0xc0 7.68002e+06 0.5; - delay_signals[2][20]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][21] 0xc0 7.68002e+06 0.5; - delay_signals[2][21]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][22] 0xc0 7.68002e+06 0.5; - delay_signals[2][22]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][23] 0xc0 7.68002e+06 0.5; - delay_signals[2][24] 0xc0 7.68002e+06 0.5; - delay_signals[2][25] 0xc0 7.68002e+06 0.5; - delay_signals[2][26] 0xc0 7.68002e+06 0.5; - delay_signals[2][26]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][27] 0xc0 7.68002e+06 0.5; - delay_signals[2][28] 0xc0 7.68002e+06 0.5; - delay_signals[2][29] 0xc0 7.68002e+06 0.5; - delay_signals[2][29]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][30] 0xc0 7.68002e+06 0.5; - delay_signals[2][30]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][31] 0xc0 7.68002e+06 0.5; - delay_signals[2][31]~feeder 0xc0 7.68002e+06 0.5; - Mux2~0 0xc0 6.394e+06 0.125; - Mux2~1 0xc0 8.94859e+06 0.28125; - Mux3~0 0xc0 4.27501e+06 0.4375; - Mux3~1 0xc0 4.27501e+06 0.4375; - Mux3~2 0xc0 1.03761e+07 0.40625; - Mux3~3 0xc0 6.38551e+06 0.382813; - Mux4~0 0xc0 2.89876e+06 0.5; - Mux4~1 0xc0 3.67501e+06 0.5; - Mux4~2 0xc0 1.08121e+07 0.390625; - Mux4~3 0xc0 1.32163e+07 0.359863; - Mux5~0 0xc0 3.82501e+06 0.625; - Mux5~1 0xc0 2.82376e+06 0.625; - Mux5~2 0xc0 7.01707e+06 0.359375; - Mux5~3 0xc0 7.5487e+06 0.311035; - Mux6~0 0xc0 2.93251e+06 0.3125; - Mux6~1 0xc0 3.54001e+06 0.6875; - Mux6~2 0xc0 1.03888e+07 0.4375; - Mux6~3 0xc0 9.54297e+06 0.425781; - Mux7~0 0xc0 3.01126e+06 0.5; - Mux7~1 0xc0 3.50626e+06 0.5; - Mux7~2 0xc0 3.93286e+06 0.390625; - Mux7~3 0xc0 3.67941e+06 0.359863; - Mux8~0 0xc0 3.63001e+06 0.5; - Mux8~1 0xc0 3.29251e+06 0.5; - Mux8~2 0xc0 4.12201e+06 0.40625; - Mux8~3 0xc0 5.40971e+06 0.376953; - Mux9~0 0xc0 4.09501e+06 0.375; - Mux9~1 0xc0 4.09501e+06 0.625; - Mux9~2 0xc0 691877 0.0625; - Mux9~3 0xc0 4.32556e+06 0.359375; - Mux9~4 0xc0 691877 0.0625; - Mux9~5 0xc0 3.98525e+06 0.311035; - Mux9~6 0xc0 1.83e+06 0.125; - Mux9~7 0xc0 2.64001e+06 0.125; - u0_m0_wo0_accum_o[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[0]~46 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[0]~47 0xc0 4.32001e+06 0.25; - u0_m0_wo0_accum_o[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[1]~48 0xc0 6.48002e+06 0.5; - u0_m0_wo0_accum_o[1]~49 0xc0 3.57751e+06 0.625; - u0_m0_wo0_accum_o[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[2]~50 0xc0 5.48439e+06 0.5; - u0_m0_wo0_accum_o[2]~51 0xc0 6.3722e+06 0.4375; - u0_m0_wo0_accum_o[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[3]~52 0xc0 5.98056e+06 0.5; - u0_m0_wo0_accum_o[3]~53 0xc0 4.88779e+06 0.53125; - u0_m0_wo0_accum_o[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[4]~54 0xc0 5.55883e+06 0.5; - u0_m0_wo0_accum_o[4]~55 0xc0 5.4588e+06 0.484375; - u0_m0_wo0_accum_o[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[5]~56 0xc0 5.68893e+06 0.5; - u0_m0_wo0_accum_o[5]~57 0xc0 5.11181e+06 0.507813; - u0_m0_wo0_accum_o[6] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[6]~58 0xc0 5.59902e+06 0.5; - u0_m0_wo0_accum_o[6]~59 0xc0 5.2676e+06 0.496094; - u0_m0_wo0_accum_o[7] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[7]~60 0xc0 5.63718e+06 0.5; - u0_m0_wo0_accum_o[7]~61 0xc0 5.18499e+06 0.501953; - u0_m0_wo0_accum_o[8] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[8]~62 0xc0 5.61632e+06 0.5; - u0_m0_wo0_accum_o[8]~63 0xc0 5.22508e+06 0.499023; - u0_m0_wo0_accum_o[9] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[9]~64 0xc0 5.6263e+06 0.5; - u0_m0_wo0_accum_o[9]~65 0xc0 5.20473e+06 0.500488; - u0_m0_wo0_accum_o[10] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[10]~66 0xc0 5.6212e+06 0.5; - u0_m0_wo0_accum_o[10]~67 0xc0 5.21483e+06 0.499756; - u0_m0_wo0_accum_o[11] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[11]~68 0xc0 5.62372e+06 0.5; - u0_m0_wo0_accum_o[11]~69 0xc0 5.20976e+06 0.500122; - u0_m0_wo0_accum_o[12] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[12]~70 0xc0 5.62245e+06 0.5; - u0_m0_wo0_accum_o[12]~71 0xc0 5.21229e+06 0.499939; - u0_m0_wo0_accum_o[13] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[13]~72 0xc0 5.62308e+06 0.5; - u0_m0_wo0_accum_o[13]~73 0xc0 5.21102e+06 0.500031; - u0_m0_wo0_accum_o[14] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[14]~74 0xc0 5.62277e+06 0.5; - u0_m0_wo0_accum_o[14]~75 0xc0 5.21165e+06 0.499985; - u0_m0_wo0_accum_o[15] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[15]~76 0xc0 5.62292e+06 0.5; - u0_m0_wo0_accum_o[15]~77 0xc0 5.21134e+06 0.500008; - u0_m0_wo0_accum_o[16] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[16]~78 0xc0 5.62285e+06 0.5; - u0_m0_wo0_accum_o[16]~79 0xc0 5.21149e+06 0.499996; - u0_m0_wo0_accum_o[17] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[17]~80 0xc0 5.62289e+06 0.5; - u0_m0_wo0_accum_o[17]~81 0xc0 5.21142e+06 0.500002; - u0_m0_wo0_accum_o[18] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[18]~82 0xc0 5.62286e+06 0.5; - u0_m0_wo0_accum_o[18]~83 0xc0 5.21146e+06 0.499999; - u0_m0_wo0_accum_o[19] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[19]~84 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[19]~85 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[20] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[20]~86 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[20]~87 0xc0 5.21145e+06 0.5; - u0_m0_wo0_accum_o[21] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[21]~88 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[21]~89 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[22] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[22]~90 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[22]~91 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[23] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[23]~92 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[23]~93 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[24] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[24]~94 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[24]~95 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[25] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[25]~96 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[25]~97 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[26] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[26]~98 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[26]~99 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[27] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[27]~100 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[27]~101 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[28] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[28]~102 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[28]~103 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[29] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[29]~104 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[29]~105 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[30] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[30]~106 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[30]~107 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[31] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[31]~108 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[31]~109 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[32] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[32]~110 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[32]~111 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[33] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[33]~112 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[33]~113 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[34] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[34]~114 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[34]~115 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[35] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[35]~116 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[35]~117 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[36] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[36]~118 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[36]~119 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[37] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[37]~120 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[37]~121 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[38] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[38]~122 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[38]~123 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[39] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[39]~124 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[39]~125 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[40] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[40]~126 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[40]~127 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[41] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[41]~128 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[41]~129 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[42] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[42]~130 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[42]~131 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[43] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[43]~132 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[43]~133 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[44] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[44]~134 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[44]~135 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[45] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[45]~136 0xc0 7.06288e+06 0.5; - u0_m0_wo0_aseq_eq 0xc0 7.68002e+06 0.5; - u0_m0_wo0_aseq_eq~0 0xc0 1.71e+06 0.0625; - u0_m0_wo0_aseq_eq~1 0xc0 945002 0.0625; - u0_m0_wo0_aseq_eq~2 0xc0 253126 0.015625; - u0_m0_wo0_aseq_eq~3 0xc0 3.83028e+06 0.250732; - u0_m0_wo0_ca0_i[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[0]~5 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[1]~6 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[1]~7 0xc0 4.32001e+06 0.25; - u0_m0_wo0_ca0_i[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[2]~8 0xc0 6.96002e+06 0.5; - u0_m0_wo0_ca0_i[2]~9 0xc0 1.83e+06 0.875; - u0_m0_wo0_ca0_i[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[3]~10 0xc0 6.91502e+06 0.5; - u0_m0_wo0_ca0_i[3]~11 0xc0 6.45752e+06 0.0625; - u0_m0_wo0_ca0_i[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[4]~12 0xc0 1.00088e+07 0.5; - u0_m0_wo0_ca0_i[4]~13 0xc0 1.67438e+06 0.96875; - u0_m0_wo0_ca0_i[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[5]~14 0xc0 8.05221e+06 0.5; - u0_m0_wo0_cm0_q[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_cm0_q[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_cm0_q[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_cm0_q[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_cm0_q[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_cm0_q[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_cm0_q[6] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_cm0_q[7] 0xc0 7.68002e+06 0.5; - dspba_delay:u0_m0_wo0_compute; - delay_signals[0][0] 0xc0 7.68002e+06 0.5; - delay_signals[0][0]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][0] 0xc0 7.68002e+06 0.5; - delay_signals[1][0]~feeder 0xc0 7.68002e+06 0.5; - dspba_delay:u0_m0_wo0_memread; - delay_signals[0][0] 0xc0 7.68002e+06 0.5; - lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component; - mult_rcu:auto_generated; - mac_mult1 0xc0 3.07201e+07 0.5; - mac_mult1~10 0xc0 0 0; - mac_mult1~11 0xc0 0 0; - mac_mult1~12 0xc0 0 0; - mac_mult1~13 0xc0 0 0; - mac_mult1~14 0xc0 0 0; - mac_mult1~15 0xc0 0 0; - mac_mult1~16 0xc0 0 0; - mac_mult1~17 0xc0 0 0; - mac_mult1~18 0xc0 0 0; - mac_mult1~19 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT2 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT3 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT4 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT5 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT6 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT7 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT8 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT9 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT10 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT11 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT12 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT13 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT14 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT15 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT16 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT17 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT18 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT19 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT20 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT21 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT22 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT23 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT24 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT25 0xc0 3.07201e+07 0.5; - result[0] 0xc0 7.68002e+06 0.5; - result[1] 0xc0 7.68002e+06 0.5; - result[2] 0xc0 7.68002e+06 0.5; - result[3] 0xc0 7.68002e+06 0.5; - result[4] 0xc0 7.68002e+06 0.5; - result[5] 0xc0 7.68002e+06 0.5; - result[6] 0xc0 7.68002e+06 0.5; - result[7] 0xc0 7.68002e+06 0.5; - result[8] 0xc0 7.68002e+06 0.5; - result[9] 0xc0 7.68002e+06 0.5; - result[10] 0xc0 7.68002e+06 0.5; - result[11] 0xc0 7.68002e+06 0.5; - result[12] 0xc0 7.68002e+06 0.5; - result[13] 0xc0 7.68002e+06 0.5; - result[14] 0xc0 7.68002e+06 0.5; - result[15] 0xc0 7.68002e+06 0.5; - result[16] 0xc0 7.68002e+06 0.5; - result[17] 0xc0 7.68002e+06 0.5; - result[18] 0xc0 7.68002e+06 0.5; - result[19] 0xc0 7.68002e+06 0.5; - result[20] 0xc0 7.68002e+06 0.5; - result[21] 0xc0 7.68002e+06 0.5; - result[22] 0xc0 7.68002e+06 0.5; - result[23] 0xc0 7.68002e+06 0.5; - result[24] 0xc0 7.68002e+06 0.5; - result[25] 0xc0 7.68002e+06 0.5; - lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component; - mult_lcu:auto_generated; - mac_mult1 0xc0 3.07201e+07 0.5; - mac_mult1~13 0xc0 0 0; - mac_mult1~14 0xc0 0 0; - mac_mult1~15 0xc0 0 0; - mac_mult1~16 0xc0 0 0; - mac_mult1~17 0xc0 0 0; - mac_mult1~18 0xc0 0 0; - mac_mult1~19 0xc0 0 0; - mac_mult1~20 0xc0 0 0; - mac_mult1~21 0xc0 0 0; - mac_mult1~22 0xc0 0 0; - mac_mult1~23 0xc0 0 0; - mac_mult1~24 0xc0 0 0; - mac_mult1~25 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT2 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT3 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT4 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT5 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT6 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT7 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT8 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT9 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT10 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT11 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT12 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT13 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT14 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT15 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT16 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT17 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT18 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT19 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT20 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT21 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT22 0xc0 3.07201e+07 0.5; - result[0] 0xc0 7.68002e+06 0.5; - result[1] 0xc0 7.68002e+06 0.5; - result[2] 0xc0 7.68002e+06 0.5; - result[3] 0xc0 7.68002e+06 0.5; - result[4] 0xc0 7.68002e+06 0.5; - result[5] 0xc0 7.68002e+06 0.5; - result[6] 0xc0 7.68002e+06 0.5; - result[7] 0xc0 7.68002e+06 0.5; - result[8] 0xc0 7.68002e+06 0.5; - result[9] 0xc0 7.68002e+06 0.5; - result[10] 0xc0 7.68002e+06 0.5; - result[11] 0xc0 7.68002e+06 0.5; - result[12] 0xc0 7.68002e+06 0.5; - result[13] 0xc0 7.68002e+06 0.5; - result[14] 0xc0 7.68002e+06 0.5; - result[15] 0xc0 7.68002e+06 0.5; - result[16] 0xc0 7.68002e+06 0.5; - result[17] 0xc0 7.68002e+06 0.5; - result[18] 0xc0 7.68002e+06 0.5; - result[19] 0xc0 7.68002e+06 0.5; - result[20] 0xc0 7.68002e+06 0.5; - result[21] 0xc0 7.68002e+06 0.5; - result[22] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[0]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[1]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[2]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[3]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[5]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[6] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[6]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[7] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[7]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[8] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[9] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[9]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[10] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[11] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[12] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[12]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[13] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[14] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[15] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[15]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[16] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[16]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[17] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[17]~24 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[17]~25 0xc0 4.32001e+06 0.25; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[18] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[18]~26 0xc0 6.48002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[18]~27 0xc0 3.57751e+06 0.625; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[19] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[19]~28 0xc0 5.48439e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[19]~29 0xc0 6.3722e+06 0.4375; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[20] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[20]~30 0xc0 5.98056e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[20]~31 0xc0 4.88779e+06 0.53125; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[21] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[21]~32 0xc0 5.55883e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[21]~33 0xc0 5.4588e+06 0.484375; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[22] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[22]~34 0xc0 5.68893e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[22]~35 0xc0 5.11181e+06 0.507813; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[23] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[23]~36 0xc0 5.59902e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[23]~37 0xc0 5.2676e+06 0.496094; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[24] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[24]~38 0xc0 5.63718e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[24]~39 0xc0 5.18499e+06 0.501953; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[25] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[25]~40 0xc0 7.05635e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[25]~41 0xc0 7.39074e+06 0.499023; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[26] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[26]~42 0xc0 7.60772e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[26]~43 0xc0 7.63264e+06 0.500488; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[27] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[27]~44 0xc0 7.66818e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[27]~45 0xc0 7.67973e+06 0.499756; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[28] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[28]~46 0xc0 7.67995e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[28]~47 0xc0 7.67717e+06 0.500122; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[29] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[29]~48 0xc0 7.67931e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[29]~49 0xc0 7.68107e+06 0.499939; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[30] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[30]~50 0xc0 7.68028e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[30]~51 0xc0 7.67945e+06 0.500031; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[31] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[31]~52 0xc0 7.67988e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[31]~53 0xc0 7.6803e+06 0.499985; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[32] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[32]~54 0xc0 7.68009e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[32]~55 0xc0 7.67988e+06 0.500008; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[33] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[33]~56 0xc0 7.67998e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[33]~57 0xc0 7.68009e+06 0.499996; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[34] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[34]~58 0xc0 7.68004e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[34]~59 0xc0 7.67998e+06 0.500002; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[35] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[35]~60 0xc0 7.68001e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[35]~61 0xc0 7.68004e+06 0.499999; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[36] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[36]~62 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[36]~63 0xc0 7.68001e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[37] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[37]~64 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[37]~65 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[38] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[38]~66 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[38]~67 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[39] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[39]~68 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[39]~69 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[40] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[40]~70 0xc0 7.68002e+06 0.5; - u0_m0_wo0_run_count[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_run_count[0]~0 0xc0 3.60751e+06 0.5; - u0_m0_wo0_run_count[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_run_enableQ[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_run_enableQ~0 0xc0 5.96651e+06 0.25; - u0_m0_wo0_run_q[0] 0xc0 7.68002e+06 0.5; - altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem; - altsyncram_sln3:auto_generated; - q_b[0] 0xc0 7.68002e+06 0.5; - q_b[1] 0xc0 7.68002e+06 0.5; - q_b[2] 0xc0 7.68002e+06 0.5; - q_b[3] 0xc0 7.68002e+06 0.5; - q_b[4] 0xc0 7.68002e+06 0.5; - q_b[5] 0xc0 7.68002e+06 0.5; - q_b[6] 0xc0 7.68002e+06 0.5; - q_b[7] 0xc0 7.68002e+06 0.5; - q_b[8] 0xc0 7.68002e+06 0.5; - q_b[9] 0xc0 7.68002e+06 0.5; - q_b[10] 0xc0 7.68002e+06 0.5; - q_b[11] 0xc0 7.68002e+06 0.5; - q_b[12] 0xc0 7.68002e+06 0.5; - q_b[13] 0xc0 7.68002e+06 0.5; - q_b[14] 0xc0 7.68002e+06 0.5; - q_b[15] 0xc0 7.68002e+06 0.5; - q_b[16] 0xc0 7.68002e+06 0.5; - q_b[17] 0xc0 7.68002e+06 0.5; - q_b[18] 0xc0 7.68002e+06 0.5; - q_b[19] 0xc0 7.68002e+06 0.5; - q_b[20] 0xc0 7.68002e+06 0.5; - q_b[21] 0xc0 7.68002e+06 0.5; - q_b[22] 0xc0 7.68002e+06 0.5; - q_b[23] 0xc0 7.68002e+06 0.5; - q_b[24] 0xc0 7.68002e+06 0.5; - q_b[25] 0xc0 7.68002e+06 0.5; - q_b[26] 0xc0 7.68002e+06 0.5; - q_b[27] 0xc0 7.68002e+06 0.5; - q_b[28] 0xc0 7.68002e+06 0.5; - q_b[29] 0xc0 7.68002e+06 0.5; - q_b[30] 0xc0 7.68002e+06 0.5; - q_b[31] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0]~6 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0]~7 0xc0 4.32001e+06 0.25; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1]~8 0xc0 6.48002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1]~9 0xc0 3.57751e+06 0.625; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2]~10 0xc0 5.48439e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2]~11 0xc0 6.3722e+06 0.4375; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3]~12 0xc0 5.98056e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3]~13 0xc0 4.88779e+06 0.53125; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4]~14 0xc0 5.55883e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4]~15 0xc0 5.4588e+06 0.484375; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[5]~16 0xc0 7.13034e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_clkproc~0 0xc0 4.32001e+06 0.25; - u0_m0_wo0_wi0_r0_ra0_count0_i[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[0]~5 0xc0 4.62001e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[1]~6 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[1]~7 0xc0 4.32001e+06 0.25; - u0_m0_wo0_wi0_r0_ra0_count0_i[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[2]~8 0xc0 6.96002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[2]~9 0xc0 1.83e+06 0.875; - u0_m0_wo0_wi0_r0_ra0_count0_i[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[3]~10 0xc0 6.91502e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[3]~11 0xc0 6.45752e+06 0.0625; - u0_m0_wo0_wi0_r0_ra0_count0_i[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[4]~12 0xc0 1.00088e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[4]~13 0xc0 1.67438e+06 0.96875; - u0_m0_wo0_wi0_r0_ra0_count0_i[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[5]~14 0xc0 8.05221e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0]~7 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0]~8 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1]~9 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1]~10 0xc0 4.32001e+06 0.25; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2]~11 0xc0 6.96002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2]~12 0xc0 2.04001e+06 0.875; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3]~13 0xc0 7.02002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3]~14 0xc0 6.51002e+06 0.0625; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4]~15 0xc0 1.0035e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4]~16 0xc0 1.6875e+06 0.96875; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5]~17 0xc0 8.05877e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5]~18 0xc0 7.63689e+06 0.015625; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6]~19 0xc0 1.12622e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[0]~5 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[1]~6 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[1]~7 0xc0 4.32001e+06 0.25; - u0_m0_wo0_wi0_r0_ra0_count1_i[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[2]~8 0xc0 6.96002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[2]~9 0xc0 1.83e+06 0.875; - u0_m0_wo0_wi0_r0_ra0_count1_i[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[3]~10 0xc0 6.91502e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[3]~11 0xc0 6.45752e+06 0.0625; - u0_m0_wo0_wi0_r0_ra0_count1_i[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[4]~12 0xc0 1.00088e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[4]~13 0xc0 1.67438e+06 0.96875; - u0_m0_wo0_wi0_r0_ra0_count1_i[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[5]~14 0xc0 8.05221e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[0]~5 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[0]~_wirecell 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[1]~6 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[1]~7 0xc0 4.32001e+06 0.25; - u0_m0_wo0_wi0_r0_wa0_i[1]~_wirecell 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[2]~8 0xc0 6.96002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[2]~9 0xc0 1.83e+06 0.875; - u0_m0_wo0_wi0_r0_wa0_i[2]~_wirecell 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[3]~10 0xc0 6.91502e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[3]~11 0xc0 6.45752e+06 0.0625; - u0_m0_wo0_wi0_r0_wa0_i[3]~_wirecell 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[4]~12 0xc0 1.00088e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[4]~13 0xc0 1.67438e+06 0.96875; - u0_m0_wo0_wi0_r0_wa0_i[4]~_wirecell 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[5]~14 0xc0 8.05221e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[5]~_wirecell 0xc0 7.68002e+06 0.5; - auk_dspip_avalon_streaming_sink_hpfir:sink; - auk_dspip_avalon_streaming_source_hpfir:source; - data_out[0] 0xc0 7.68002e+06 0.5; - data_out[1] 0xc0 7.68002e+06 0.5; - data_out[2] 0xc0 7.68002e+06 0.5; - data_out[3] 0xc0 7.68002e+06 0.5; - data_out[4] 0xc0 7.68002e+06 0.5; - data_out[5] 0xc0 7.68002e+06 0.5; - data_out[6] 0xc0 7.68002e+06 0.5; - data_out[7] 0xc0 7.68002e+06 0.5; - data_out[8] 0xc0 7.68002e+06 0.5; - data_out[9] 0xc0 7.68002e+06 0.5; - data_out[10] 0xc0 7.68002e+06 0.5; - data_out[11] 0xc0 7.68002e+06 0.5; - data_out[12] 0xc0 7.68002e+06 0.5; - data_out[13] 0xc0 7.68002e+06 0.5; - data_out[14] 0xc0 7.68002e+06 0.5; - data_out[15] 0xc0 7.68002e+06 0.5; - data_out[16] 0xc0 7.68002e+06 0.5; - data_out[17] 0xc0 7.68002e+06 0.5; - data_out[18] 0xc0 7.68002e+06 0.5; - data_out[19] 0xc0 7.68002e+06 0.5; - data_out[20] 0xc0 7.68002e+06 0.5; - data_out[21] 0xc0 7.68002e+06 0.5; - data_out[22] 0xc0 7.68002e+06 0.5; - data_out[23] 0xc0 7.68002e+06 0.5; - data_out[24] 0xc0 7.68002e+06 0.5; - data_out[25] 0xc0 7.68002e+06 0.5; - data_out[26] 0xc0 7.68002e+06 0.5; - data_out[27] 0xc0 7.68002e+06 0.5; - data_out[28] 0xc0 7.68002e+06 0.5; - data_out[29] 0xc0 7.68002e+06 0.5; - data_out[29]~feeder 0xc0 7.68002e+06 0.5; - data_out[30] 0xc0 7.68002e+06 0.5; - data_out[31] 0xc0 7.68002e+06 0.5; - data_out[32] 0xc0 7.68002e+06 0.5; - data_out[33] 0xc0 7.68002e+06 0.5; - data_out[34] 0xc0 7.68002e+06 0.5; - data_out[35] 0xc0 7.68002e+06 0.5; - data_out[36] 0xc0 7.68002e+06 0.5; - data_out[37] 0xc0 7.68002e+06 0.5; - data_out[38] 0xc0 7.68002e+06 0.5; - data_out[39] 0xc0 7.68002e+06 0.5; - data_out[40] 0xc0 7.68002e+06 0.5; - data_out[41] 0xc0 7.68002e+06 0.5; - data_out[42] 0xc0 7.68002e+06 0.5; - data_out[43] 0xc0 7.68002e+06 0.5; - data_out[44] 0xc0 7.68002e+06 0.5; - data_out[45] 0xc0 7.68002e+06 0.5; - data_shifter:RX_CICFIR_GAINER; - Mux0~0 0xc0 1.59709e+06 0.46875; - Mux0~1 0xc0 855888 0.484375; - Mux0~2 0xc0 1.59912e+06 0.5; - Mux0~3 0xc0 1.02257e+06 0.46875; - Mux0~4 0xc0 1.59912e+06 0.5; - Mux0~5 0xc0 853569 0.5; - Mux1~0 0xc0 1.78068e+06 0.4375; - Mux1~1 0xc0 886103 0.46875; - Mux1~2 0xc0 1.59912e+06 0.5; - Mux1~3 0xc0 853569 0.5; - Mux1~4 0xc0 1.59912e+06 0.5; - Mux1~5 0xc0 853569 0.5; - Mux2~0 0xc0 1.59912e+06 0.5; - Mux2~1 0xc0 853569 0.5; - Mux2~2 0xc0 1.59912e+06 0.5; - Mux2~3 0xc0 853569 0.5; - Mux2~4 0xc0 2.13312e+06 0.40625; - Mux2~5 0xc0 942156 0.453125; - Mux2~6 0xc0 1.43351e+06 0.488281; - Mux2~7 0xc0 246212 0.03125; - Mux2~8 0xc0 1.71523e+06 0.3797; - Mux3~0 0xc0 1.59912e+06 0.5; - Mux3~1 0xc0 853569 0.5; - Mux3~2 0xc0 1.59912e+06 0.5; - Mux3~3 0xc0 853569 0.5; - Mux3~4 0xc0 1.5539e+06 0.5; - Mux3~5 0xc0 1.12214e+06 0.375; - Mux3~6 0xc0 1.46388e+06 0.46875; - Mux3~7 0xc0 456769 0.0625; - Mux3~8 0xc0 1.60015e+06 0.381836; - Mux4~0 0xc0 1.59912e+06 0.5; - Mux4~1 0xc0 853569 0.5; - Mux4~2 0xc0 1.59912e+06 0.5; - Mux4~3 0xc0 853569 0.5; - Mux4~4 0xc0 963245 0.21875; - Mux4~5 0xc0 941058 0.316406; - Mux4~6 0xc0 1.50661e+06 0.454102; - Mux4~7 0xc0 786665 0.09375; - Mux4~8 0xc0 1.50957e+06 0.384811; - Mux5~0 0xc0 1.59912e+06 0.5; - Mux5~1 0xc0 853569 0.5; - Mux5~2 0xc0 1.59912e+06 0.5; - Mux5~3 0xc0 853569 0.5; - Mux5~4 0xc0 986735 0.1875; - Mux5~5 0xc0 1.00788e+06 0.289063; - Mux5~6 0xc0 1.55122e+06 0.447266; - Mux5~7 0xc0 1.25627e+06 0.125; - Mux5~8 0xc0 1.44136e+06 0.389771; - Mux6~0 0xc0 1.59912e+06 0.5; - Mux6~1 0xc0 853569 0.5; - Mux6~2 0xc0 1.59912e+06 0.5; - Mux6~3 0xc0 853569 0.5; - Mux6~4 0xc0 1.1182e+06 0.15625; - Mux6~5 0xc0 1.09669e+06 0.261719; - Mux6~6 0xc0 1.60581e+06 0.44043; - Mux6~7 0xc0 1.1182e+06 0.15625; - Mux6~8 0xc0 1.35117e+06 0.394516; - Mux7~0 0xc0 1.59912e+06 0.5; - Mux7~1 0xc0 853569 0.5; - Mux7~2 0xc0 1.59912e+06 0.5; - Mux7~3 0xc0 853569 0.5; - Mux7~4 0xc0 1.06106e+06 0.25; - Mux7~5 0xc0 1.62605e+06 0.4375; - Mux7~6 0xc0 986735 0.1875; - Mux7~7 0xc0 1.26497e+06 0.400391; - Mux8~0 0xc0 2.66251e+06 0.5; - Mux8~1 0xc0 1.80502e+06 0.5; - Mux8~2 0xc0 2.66251e+06 0.5; - Mux8~3 0xc0 1.80502e+06 0.5; - Mux8~4 0xc0 3.90001e+06 0.5; - Mux8~5 0xc0 1.83463e+06 0.375; - Mux8~6 0xc0 2.66251e+06 0.5; - Mux8~7 0xc0 1.80502e+06 0.5; - Mux8~8 0xc0 2.66251e+06 0.5; - Mux8~9 0xc0 1.80502e+06 0.5; - Mux8~10 0xc0 2.66251e+06 0.5; - Mux8~11 0xc0 1.80502e+06 0.5; - Mux8~12 0xc0 2.66251e+06 0.5; - Mux8~13 0xc0 1.80502e+06 0.5; - Mux8~14 0xc0 3.90001e+06 0.5; - Mux8~15 0xc0 1.83463e+06 0.375; - Mux8~16 0xc0 2.66251e+06 0.5; - Mux8~17 0xc0 1.80502e+06 0.5; - Mux8~18 0xc0 2.66251e+06 0.5; - Mux8~19 0xc0 1.80502e+06 0.5; - Mux8~20 0xc0 2.66251e+06 0.5; - Mux8~21 0xc0 1.80502e+06 0.5; - Mux8~22 0xc0 2.66251e+06 0.5; - Mux8~23 0xc0 1.80502e+06 0.5; - Mux8~24 0xc0 1.59912e+06 0.5; - Mux8~25 0xc0 853569 0.5; - Mux8~26 0xc0 1.59912e+06 0.5; - Mux8~27 0xc0 853569 0.5; - Mux8~28 0xc0 963245 0.21875; - Mux8~29 0xc0 1.68724e+06 0.429688; - Mux8~30 0xc0 963245 0.21875; - Mux8~31 0xc0 1.193e+06 0.404419; - Mux9~0 0xc0 2.66251e+06 0.5; - Mux9~1 0xc0 1.80502e+06 0.5; - Mux9~2 0xc0 2.66251e+06 0.5; - Mux9~3 0xc0 1.80502e+06 0.5; - Mux9~4 0xc0 1.9125e+06 0.25; - Mux9~5 0xc0 2.66251e+06 0.5; - Mux9~6 0xc0 1.80502e+06 0.5; - Mux9~7 0xc0 2.66251e+06 0.5; - Mux9~8 0xc0 1.80502e+06 0.5; - Mux9~9 0xc0 2.66251e+06 0.5; - Mux9~10 0xc0 1.80502e+06 0.5; - Mux9~11 0xc0 2.66251e+06 0.5; - Mux9~12 0xc0 1.80502e+06 0.5; - Mux9~13 0xc0 2.66251e+06 0.5; - Mux9~14 0xc0 1.80502e+06 0.5; - Mux9~15 0xc0 2.66251e+06 0.5; - Mux9~16 0xc0 1.80502e+06 0.5; - Mux9~17 0xc0 2.66251e+06 0.5; - Mux9~18 0xc0 1.80502e+06 0.5; - Mux9~19 0xc0 2.66251e+06 0.5; - Mux9~20 0xc0 1.80502e+06 0.5; - Mux9~21 0xc0 2.66251e+06 0.5; - Mux9~22 0xc0 1.80502e+06 0.5; - Mux9~23 0xc0 1.59912e+06 0.5; - Mux9~24 0xc0 853569 0.5; - Mux9~25 0xc0 1.59912e+06 0.5; - Mux9~26 0xc0 853569 0.5; - Mux9~27 0xc0 986735 0.1875; - Mux9~28 0xc0 1.7686e+06 0.421875; - Mux9~29 0xc0 1.06106e+06 0.25; - Mux9~30 0xc0 1.13605e+06 0.408203; - Mux10~0 0xc0 2.66251e+06 0.5; - Mux10~1 0xc0 1.80502e+06 0.5; - Mux10~2 0xc0 2.66251e+06 0.5; - Mux10~3 0xc0 1.80502e+06 0.5; - Mux10~4 0xc0 2.66251e+06 0.5; - Mux10~5 0xc0 1.80502e+06 0.5; - Mux10~6 0xc0 2.66251e+06 0.5; - Mux10~7 0xc0 1.80502e+06 0.5; - Mux10~8 0xc0 2.66251e+06 0.5; - Mux10~9 0xc0 1.80502e+06 0.5; - Mux10~10 0xc0 2.66251e+06 0.5; - Mux10~11 0xc0 1.80502e+06 0.5; - Mux10~12 0xc0 2.66251e+06 0.5; - Mux10~13 0xc0 1.80502e+06 0.5; - Mux10~14 0xc0 2.66251e+06 0.5; - Mux10~15 0xc0 1.80502e+06 0.5; - Mux10~16 0xc0 2.66251e+06 0.5; - Mux10~17 0xc0 1.80502e+06 0.5; - Mux10~18 0xc0 2.66251e+06 0.5; - Mux10~19 0xc0 1.80502e+06 0.5; - Mux10~20 0xc0 1.83e+06 0.125; - Mux10~21 0xc0 2.66251e+06 0.5; - Mux10~22 0xc0 1.80502e+06 0.5; - Mux10~23 0xc0 1.83e+06 0.125; - Mux10~24 0xc0 1.59912e+06 0.5; - Mux10~25 0xc0 853569 0.5; - Mux10~26 0xc0 1.59912e+06 0.5; - Mux10~27 0xc0 853569 0.5; - Mux10~28 0xc0 1.1182e+06 0.15625; - Mux10~29 0xc0 1.8691e+06 0.414063; - Mux10~30 0xc0 1.1182e+06 0.15625; - Mux10~31 0xc0 1.09669e+06 0.261719; - Mux10~32 0xc0 1.12407e+06 0.4077; - Mux11~0 0xc0 2.66251e+06 0.5; - Mux11~1 0xc0 1.80502e+06 0.5; - Mux11~2 0xc0 2.66251e+06 0.5; - Mux11~3 0xc0 1.80502e+06 0.5; - Mux11~4 0xc0 2.66251e+06 0.5; - Mux11~5 0xc0 1.80502e+06 0.5; - Mux11~6 0xc0 2.66251e+06 0.5; - Mux11~7 0xc0 1.80502e+06 0.5; - Mux11~8 0xc0 2.66251e+06 0.5; - Mux11~9 0xc0 1.80502e+06 0.5; - Mux11~10 0xc0 2.66251e+06 0.5; - Mux11~11 0xc0 1.80502e+06 0.5; - Mux11~12 0xc0 2.66251e+06 0.5; - Mux11~13 0xc0 1.80502e+06 0.5; - Mux11~14 0xc0 2.66251e+06 0.5; - Mux11~15 0xc0 1.80502e+06 0.5; - Mux11~16 0xc0 2.66251e+06 0.5; - Mux11~17 0xc0 1.80502e+06 0.5; - Mux11~18 0xc0 2.66251e+06 0.5; - Mux11~19 0xc0 1.80502e+06 0.5; - Mux11~20 0xc0 2.66251e+06 0.5; - Mux11~21 0xc0 1.80502e+06 0.5; - Mux11~22 0xc0 1.9125e+06 0.25; - Mux11~23 0xc0 1.59912e+06 0.5; - Mux11~24 0xc0 853569 0.5; - Mux11~25 0xc0 1.59912e+06 0.5; - Mux11~26 0xc0 853569 0.5; - Mux11~27 0xc0 1.25627e+06 0.125; - Mux11~28 0xc0 1.98091e+06 0.40625; - Mux11~29 0xc0 986735 0.1875; - Mux11~30 0xc0 1.00788e+06 0.289063; - Mux11~31 0xc0 1.07884e+06 0.410278; - Mux12~0 0xc0 1.59912e+06 0.5; - Mux12~1 0xc0 853569 0.5; - Mux12~2 0xc0 1.59912e+06 0.5; - Mux12~3 0xc0 853569 0.5; - Mux12~4 0xc0 786665 0.09375; - Mux12~5 0xc0 2.05665e+06 0.398438; - Mux12~6 0xc0 963245 0.21875; - Mux12~7 0xc0 941058 0.316406; - Mux12~8 0xc0 1.03523e+06 0.412643; - Mux13~0 0xc0 1.59912e+06 0.5; - Mux13~1 0xc0 853569 0.5; - Mux13~2 0xc0 1.59912e+06 0.5; - Mux13~3 0xc0 853569 0.5; - Mux13~4 0xc0 456769 0.0625; - Mux13~5 0xc0 2.15397e+06 0.390625; - Mux13~6 0xc0 1.5539e+06 0.5; - Mux13~7 0xc0 1.12214e+06 0.375; - Mux13~8 0xc0 966423 0.420898; - Mux14~0 0xc0 1.59912e+06 0.5; - Mux14~1 0xc0 853569 0.5; - Mux14~2 0xc0 1.59912e+06 0.5; - Mux14~3 0xc0 853569 0.5; - Mux14~4 0xc0 246212 0.03125; - Mux14~5 0xc0 2.27131e+06 0.382813; - Mux14~6 0xc0 1.59912e+06 0.5; - Mux14~7 0xc0 1.63808e+06 0.40625; - Mux14~8 0xc0 966866 0.423462; - Mux15~0 0xc0 1.59912e+06 0.5; - Mux15~1 0xc0 853569 0.5; - Mux15~2 0xc0 1.59912e+06 0.5; - Mux15~3 0xc0 1.28807e+06 0.4375; - Mux15~4 0xc0 1.59912e+06 0.5; - Mux15~5 0xc0 853569 0.5; - Mux16~0 0xc0 2.66251e+06 0.5; - Mux16~1 0xc0 1.80502e+06 0.5; - Mux16~2 0xc0 2.66251e+06 0.5; - Mux16~3 0xc0 1.80502e+06 0.5; - Mux16~4 0xc0 3.90001e+06 0.5; - Mux16~5 0xc0 1.83463e+06 0.375; - Mux16~6 0xc0 1.59709e+06 0.46875; - Mux16~7 0xc0 2.66251e+06 0.5; - Mux16~8 0xc0 1.80502e+06 0.5; - Mux16~9 0xc0 855888 0.484375; - Mux16~10 0xc0 2.66251e+06 0.5; - Mux16~11 0xc0 1.80502e+06 0.5; - Mux16~12 0xc0 2.66251e+06 0.5; - Mux16~13 0xc0 1.80502e+06 0.5; - Mux16~14 0xc0 2.66251e+06 0.5; - Mux16~15 0xc0 1.80502e+06 0.5; - Mux16~16 0xc0 1.59912e+06 0.5; - Mux16~17 0xc0 3.90001e+06 0.5; - Mux16~18 0xc0 1.83463e+06 0.375; - Mux16~19 0xc0 1.02257e+06 0.46875; - Mux16~20 0xc0 2.66251e+06 0.5; - Mux16~21 0xc0 1.80502e+06 0.5; - Mux16~22 0xc0 2.66251e+06 0.5; - Mux16~23 0xc0 1.80502e+06 0.5; - Mux16~24 0xc0 2.66251e+06 0.5; - Mux16~25 0xc0 1.80502e+06 0.5; - Mux16~26 0xc0 1.59912e+06 0.5; - Mux16~27 0xc0 2.66251e+06 0.5; - Mux16~28 0xc0 1.80502e+06 0.5; - Mux16~29 0xc0 853569 0.5; - Mux17~0 0xc0 2.66251e+06 0.5; - Mux17~1 0xc0 1.80502e+06 0.5; - Mux17~2 0xc0 2.66251e+06 0.5; - Mux17~3 0xc0 1.80502e+06 0.5; - Mux17~4 0xc0 1.9125e+06 0.25; - Mux17~5 0xc0 1.78068e+06 0.4375; - Mux17~6 0xc0 2.66251e+06 0.5; - Mux17~7 0xc0 1.80502e+06 0.5; - Mux17~8 0xc0 886103 0.46875; - Mux17~9 0xc0 2.66251e+06 0.5; - Mux17~10 0xc0 1.80502e+06 0.5; - Mux17~11 0xc0 2.66251e+06 0.5; - Mux17~12 0xc0 1.80502e+06 0.5; - Mux17~13 0xc0 2.66251e+06 0.5; - Mux17~14 0xc0 1.80502e+06 0.5; - Mux17~15 0xc0 1.59912e+06 0.5; - Mux17~16 0xc0 2.66251e+06 0.5; - Mux17~17 0xc0 1.80502e+06 0.5; - Mux17~18 0xc0 853569 0.5; - Mux17~19 0xc0 2.66251e+06 0.5; - Mux17~20 0xc0 1.80502e+06 0.5; - Mux17~21 0xc0 2.66251e+06 0.5; - Mux17~22 0xc0 1.80502e+06 0.5; - Mux17~23 0xc0 2.66251e+06 0.5; - Mux17~24 0xc0 1.80502e+06 0.5; - Mux17~25 0xc0 1.59912e+06 0.5; - Mux17~26 0xc0 2.66251e+06 0.5; - Mux17~27 0xc0 1.80502e+06 0.5; - Mux17~28 0xc0 853569 0.5; - Mux18~0 0xc0 2.66251e+06 0.5; - Mux18~1 0xc0 1.80502e+06 0.5; - Mux18~2 0xc0 2.66251e+06 0.5; - Mux18~3 0xc0 1.80502e+06 0.5; - Mux18~4 0xc0 2.66251e+06 0.5; - Mux18~5 0xc0 1.80502e+06 0.5; - Mux18~6 0xc0 1.59912e+06 0.5; - Mux18~7 0xc0 2.66251e+06 0.5; - Mux18~8 0xc0 1.80502e+06 0.5; - Mux18~9 0xc0 853569 0.5; - Mux18~10 0xc0 2.66251e+06 0.5; - Mux18~11 0xc0 1.80502e+06 0.5; - Mux18~12 0xc0 2.66251e+06 0.5; - Mux18~13 0xc0 1.80502e+06 0.5; - Mux18~14 0xc0 2.66251e+06 0.5; - Mux18~15 0xc0 1.80502e+06 0.5; - Mux18~16 0xc0 1.59912e+06 0.5; - Mux18~17 0xc0 2.66251e+06 0.5; - Mux18~18 0xc0 1.80502e+06 0.5; - Mux18~19 0xc0 853569 0.5; - Mux18~20 0xc0 2.66251e+06 0.5; - Mux18~21 0xc0 1.80502e+06 0.5; - Mux18~22 0xc0 2.66251e+06 0.5; - Mux18~23 0xc0 1.80502e+06 0.5; - Mux18~24 0xc0 1.83e+06 0.125; - Mux18~25 0xc0 2.13312e+06 0.40625; - Mux18~26 0xc0 2.66251e+06 0.5; - Mux18~27 0xc0 1.80502e+06 0.5; - Mux18~28 0xc0 942156 0.453125; - Mux18~29 0xc0 1.43351e+06 0.488281; - Mux18~30 0xc0 246212 0.03125; - Mux18~31 0xc0 1.71523e+06 0.3797; - Mux19~0 0xc0 2.66251e+06 0.5; - Mux19~1 0xc0 1.80502e+06 0.5; - Mux19~2 0xc0 2.66251e+06 0.5; - Mux19~3 0xc0 1.80502e+06 0.5; - Mux19~4 0xc0 2.66251e+06 0.5; - Mux19~5 0xc0 1.80502e+06 0.5; - Mux19~6 0xc0 1.59912e+06 0.5; - Mux19~7 0xc0 2.66251e+06 0.5; - Mux19~8 0xc0 1.80502e+06 0.5; - Mux19~9 0xc0 853569 0.5; - Mux19~10 0xc0 2.66251e+06 0.5; - Mux19~11 0xc0 1.80502e+06 0.5; - Mux19~12 0xc0 2.66251e+06 0.5; - Mux19~13 0xc0 1.80502e+06 0.5; - Mux19~14 0xc0 2.66251e+06 0.5; - Mux19~15 0xc0 1.80502e+06 0.5; - Mux19~16 0xc0 1.59912e+06 0.5; - Mux19~17 0xc0 2.66251e+06 0.5; - Mux19~18 0xc0 1.80502e+06 0.5; - Mux19~19 0xc0 853569 0.5; - Mux19~20 0xc0 2.66251e+06 0.5; - Mux19~21 0xc0 1.80502e+06 0.5; - Mux19~22 0xc0 2.66251e+06 0.5; - Mux19~23 0xc0 1.80502e+06 0.5; - Mux19~24 0xc0 1.5539e+06 0.5; - Mux19~25 0xc0 2.66251e+06 0.5; - Mux19~26 0xc0 1.80502e+06 0.5; - Mux19~27 0xc0 1.12214e+06 0.375; - Mux19~28 0xc0 1.46388e+06 0.46875; - Mux19~29 0xc0 1.9125e+06 0.25; - Mux19~30 0xc0 456769 0.0625; - Mux19~31 0xc0 1.60015e+06 0.381836; - Mux20~0 0xc0 1.59912e+06 0.5; - Mux20~1 0xc0 853569 0.5; - Mux20~2 0xc0 1.59912e+06 0.5; - Mux20~3 0xc0 853569 0.5; - Mux20~4 0xc0 963245 0.21875; - Mux20~5 0xc0 941058 0.316406; - Mux20~6 0xc0 1.50661e+06 0.454102; - Mux20~7 0xc0 786665 0.09375; - Mux20~8 0xc0 1.50957e+06 0.384811; - Mux21~0 0xc0 1.59912e+06 0.5; - Mux21~1 0xc0 853569 0.5; - Mux21~2 0xc0 1.59912e+06 0.5; - Mux21~3 0xc0 853569 0.5; - Mux21~4 0xc0 986735 0.1875; - Mux21~5 0xc0 1.00788e+06 0.289063; - Mux21~6 0xc0 1.55122e+06 0.447266; - Mux21~7 0xc0 1.25627e+06 0.125; - Mux21~8 0xc0 1.44136e+06 0.389771; - Mux22~0 0xc0 1.83e+06 0.125; - Mux22~1 0xc0 1.59912e+06 0.5; - Mux22~2 0xc0 853569 0.5; - Mux22~3 0xc0 1.59912e+06 0.5; - Mux22~4 0xc0 853569 0.5; - Mux22~5 0xc0 1.1182e+06 0.15625; - Mux22~6 0xc0 1.09669e+06 0.261719; - Mux22~7 0xc0 1.60581e+06 0.44043; - Mux22~8 0xc0 1.1182e+06 0.15625; - Mux22~9 0xc0 1.35117e+06 0.394516; - Mux23~0 0xc0 1.59912e+06 0.5; - Mux23~1 0xc0 853569 0.5; - Mux23~2 0xc0 1.59912e+06 0.5; - Mux23~3 0xc0 853569 0.5; - Mux23~4 0xc0 1.06106e+06 0.25; - Mux23~5 0xc0 1.62605e+06 0.4375; - Mux23~6 0xc0 986735 0.1875; - Mux23~7 0xc0 1.26497e+06 0.400391; - Mux24~0 0xc0 1.59912e+06 0.5; - Mux24~1 0xc0 853569 0.5; - Mux24~2 0xc0 1.59912e+06 0.5; - Mux24~3 0xc0 853569 0.5; - Mux24~4 0xc0 963244 0.21875; - Mux24~5 0xc0 1.68724e+06 0.429688; - Mux24~6 0xc0 963245 0.21875; - Mux24~7 0xc0 1.193e+06 0.404419; - Mux25~0 0xc0 1.59912e+06 0.5; - Mux25~1 0xc0 853569 0.5; - Mux25~2 0xc0 1.59912e+06 0.5; - Mux25~3 0xc0 853569 0.5; - Mux25~4 0xc0 986735 0.1875; - Mux25~5 0xc0 1.7686e+06 0.421875; - Mux25~6 0xc0 1.06106e+06 0.25; - Mux25~7 0xc0 1.13605e+06 0.408203; - Mux26~0 0xc0 1.59912e+06 0.5; - Mux26~1 0xc0 853569 0.5; - Mux26~2 0xc0 1.59912e+06 0.5; - Mux26~3 0xc0 853569 0.5; - Mux26~4 0xc0 1.1182e+06 0.15625; - Mux26~5 0xc0 1.8691e+06 0.414063; - Mux26~6 0xc0 1.1182e+06 0.15625; - Mux26~7 0xc0 1.09669e+06 0.261719; - Mux26~8 0xc0 1.12407e+06 0.4077; - Mux27~0 0xc0 1.59912e+06 0.5; - Mux27~1 0xc0 853569 0.5; - Mux27~2 0xc0 1.59912e+06 0.5; - Mux27~3 0xc0 853569 0.5; - Mux27~4 0xc0 1.25627e+06 0.125; - Mux27~5 0xc0 1.98091e+06 0.40625; - Mux27~6 0xc0 986735 0.1875; - Mux27~7 0xc0 1.00788e+06 0.289063; - Mux27~8 0xc0 1.07884e+06 0.410278; - Mux28~0 0xc0 1.59912e+06 0.5; - Mux28~1 0xc0 853569 0.5; - Mux28~2 0xc0 1.59912e+06 0.5; - Mux28~3 0xc0 853569 0.5; - Mux28~4 0xc0 786665 0.09375; - Mux28~5 0xc0 2.05665e+06 0.398438; - Mux28~6 0xc0 963245 0.21875; - Mux28~7 0xc0 941058 0.316406; - Mux28~8 0xc0 1.03523e+06 0.412643; - Mux29~0 0xc0 1.59912e+06 0.5; - Mux29~1 0xc0 853569 0.5; - Mux29~2 0xc0 1.59912e+06 0.5; - Mux29~3 0xc0 853569 0.5; - Mux29~4 0xc0 456769 0.0625; - Mux29~5 0xc0 2.15397e+06 0.390625; - Mux29~6 0xc0 1.5539e+06 0.5; - Mux29~7 0xc0 1.12214e+06 0.375; - Mux29~8 0xc0 966423 0.420898; - Mux30~0 0xc0 1.59912e+06 0.5; - Mux30~1 0xc0 853569 0.5; - Mux30~2 0xc0 1.59912e+06 0.5; - Mux30~3 0xc0 853569 0.5; - Mux30~4 0xc0 246212 0.03125; - Mux30~5 0xc0 2.27131e+06 0.382813; - Mux30~6 0xc0 1.59912e+06 0.5; - Mux30~7 0xc0 1.63808e+06 0.40625; - Mux30~8 0xc0 966866 0.423462; - Mux31~0 0xc0 1.59912e+06 0.5; - Mux31~1 0xc0 853569 0.5; - Mux31~2 0xc0 1.59912e+06 0.5; - Mux31~3 0xc0 1.28807e+06 0.4375; - Mux31~4 0xc0 1.59912e+06 0.5; - Mux31~5 0xc0 853569 0.5; - data_out_I[0]~17 0xc0 905527 0.234375; - data_out_I[0]~18 0xc0 606799 0.165039; - data_out_I[1]~15 0xc0 1.67933e+06 0.211731; - data_out_I[2]~13 0xc0 1.66256e+06 0.210449; - data_out_I[3]~10 0xc0 1.63122e+06 0.206322; - data_out_I[4]~9 0xc0 1.6299e+06 0.205139; - data_out_I[5]~7 0xc0 1.62784e+06 0.20385; - data_out_I[6]~5 0xc0 1.63473e+06 0.204102; - data_out_I[7]~2 0xc0 1.62892e+06 0.202209; - data_out_I[8]~16 0xc0 1.62651e+06 0.200195; - data_out_I[9]~14 0xc0 1.61758e+06 0.197258; - data_out_I[10]~12 0xc0 1.61718e+06 0.194885; - data_out_I[11]~11 0xc0 1.609e+06 0.192406; - data_out_I[12]~8 0xc0 1.61979e+06 0.190918; - data_out_I[13]~6 0xc0 1.64325e+06 0.18985; - data_out_I[14]~3 0xc0 909083 0.242188; - data_out_I[14]~4 0xc0 535885 0.168457; - data_out_I[15]~0 0xc0 897083 0.238281; - data_out_I[15]~1 0xc0 532322 0.166748; - data_out_Q[0]~18 0xc0 2.34375e+06 0.25; - data_out_Q[0]~19 0xc0 905527 0.234375; - data_out_Q[0]~20 0xc0 606799 0.165039; - data_out_Q[1]~17 0xc0 1.67933e+06 0.211731; - data_out_Q[2]~16 0xc0 1.66256e+06 0.210449; - data_out_Q[3]~15 0xc0 1.63122e+06 0.206322; - data_out_Q[4]~14 0xc0 1.6299e+06 0.205139; - data_out_Q[5]~13 0xc0 1.62784e+06 0.20385; - data_out_Q[6]~12 0xc0 1.63473e+06 0.204102; - data_out_Q[7]~11 0xc0 1.62892e+06 0.202209; - data_out_Q[8]~10 0xc0 1.62651e+06 0.200195; - data_out_Q[9]~9 0xc0 1.61758e+06 0.197258; - data_out_Q[10]~8 0xc0 1.61718e+06 0.194885; - data_out_Q[11]~7 0xc0 1.609e+06 0.192406; - data_out_Q[12]~6 0xc0 1.61979e+06 0.190918; - data_out_Q[13]~5 0xc0 1.64325e+06 0.18985; - data_out_Q[14]~3 0xc0 909083 0.242188; - data_out_Q[14]~4 0xc0 535885 0.168457; - data_out_Q[15]~0 0xc0 897083 0.238281; - data_out_Q[15]~1 0xc0 1.75781e+06 0.25; - data_out_Q[15]~2 0xc0 532322 0.166748; - data_valid_out_Q 0xc0 4.32001e+06 0.25; - data_valid_out_Q~clkctrl 0xc0 4.32001e+06 0.25; - rx_ciccomp:RX_CICOMP_Q; - rx_ciccomp_0002:rx_ciccomp_inst; - rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst; - rx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[0] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[0]~1 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[0]~2 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[1] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[1]~1 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[1]~2 0xc0 4.32001e+06 0.25; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[2] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[2]~1 0xc0 6.96002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[2]~2 0xc0 2.04001e+06 0.875; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[3] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[3]~1 0xc0 7.02002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[3]~2 0xc0 6.51002e+06 0.0625; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[4] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[4]~1 0xc0 1.0035e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[4]~2 0xc0 1.6875e+06 0.96875; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[5] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[5]~1 0xc0 8.05877e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[5]~2 0xc0 7.63689e+06 0.015625; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[6] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[6]~1 0xc0 1.12622e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[6]~2 0xc0 1.91297e+06 0.992188; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[7] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[7]~1 0xc0 8.51744e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[7]~2 0xc0 8.0392e+06 0.00390625; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8]~1 0xc0 1.16399e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[0] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[0]~1 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[0]~2 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[0]~_wirecell 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[1] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[1]~1 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[1]~2 0xc0 4.32001e+06 0.25; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[2] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[2]~1 0xc0 6.96002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[2]~2 0xc0 2.04001e+06 0.875; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[3] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[3]~1 0xc0 7.02002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[3]~2 0xc0 6.51002e+06 0.0625; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[4] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[4]~1 0xc0 1.0035e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[4]~2 0xc0 1.6875e+06 0.96875; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[5] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[5]~1 0xc0 8.05877e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[5]~2 0xc0 7.63689e+06 0.015625; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[6] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[6]~1 0xc0 1.12622e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[6]~2 0xc0 1.91297e+06 0.992188; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[7] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[7]~1 0xc0 8.51744e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[7]~2 0xc0 8.0392e+06 0.00390625; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[8] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[8]~1 0xc0 1.16399e+07 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[0] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[1] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[2] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[3] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[4] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[5] 0xc0 7.68002e+06 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[6] 0xc0 7.68002e+06 0.5; - Add0~0 0xc0 7.68002e+06 0.5; - Add0~1 0xc0 7.68002e+06 0.5; - Add0~2 0xc0 7.68002e+06 0.5; - Add0~3 0xc0 4.32001e+06 0.25; - Add0~4 0xc0 6.96002e+06 0.5; - Add0~5 0xc0 2.04001e+06 0.875; - Add0~6 0xc0 7.02002e+06 0.5; - Add0~7 0xc0 6.51002e+06 0.0625; - Add0~8 0xc0 1.0035e+07 0.5; - Add0~9 0xc0 1.6875e+06 0.96875; - Add0~10 0xc0 8.05877e+06 0.5; - Add0~11 0xc0 7.63689e+06 0.015625; - Add0~12 0xc0 1.12622e+07 0.5; - Add1~0 0xc0 7.68002e+06 0.5; - Add1~1 0xc0 7.68002e+06 0.5; - Add1~2 0xc0 7.68002e+06 0.5; - Add1~3 0xc0 4.32001e+06 0.25; - Add1~4 0xc0 6.96002e+06 0.5; - Add1~5 0xc0 2.04001e+06 0.875; - Add1~6 0xc0 7.02002e+06 0.5; - Add1~7 0xc0 6.51002e+06 0.0625; - Add1~8 0xc0 1.0035e+07 0.5; - Add1~9 0xc0 1.6875e+06 0.96875; - Add1~10 0xc0 8.05877e+06 0.5; - Add1~11 0xc0 7.63689e+06 0.015625; - Add1~12 0xc0 1.12622e+07 0.5; - Add1~14 0xc0 7.08358e+06 0.5; - Add1~15 0xc0 5.78216e+06 0.5; - Add1~16 0xc0 7.20678e+06 0.5; - Add1~17 0xc0 5.07158e+06 0.5; - Add1~18 0xc0 5.03134e+06 0.5; - Add1~19 0xc0 5.52001e+06 0.5; - Add1~20 0xc0 3.90001e+06 0.5; - Add2~0 0xc0 4.44001e+06 0.5; - Add3~0 0xc0 7.68002e+06 0.5; - Add3~1 0xc0 7.68002e+06 0.5; - Add3~2 0xc0 7.68002e+06 0.5; - Add3~3 0xc0 4.32001e+06 0.25; - Add3~4 0xc0 6.96002e+06 0.5; - Add3~5 0xc0 2.04001e+06 0.875; - Add3~6 0xc0 7.02002e+06 0.5; - Add3~7 0xc0 6.51002e+06 0.0625; - Add3~8 0xc0 1.0035e+07 0.5; - Add3~9 0xc0 1.6875e+06 0.96875; - Add3~10 0xc0 8.05877e+06 0.5; - Add3~11 0xc0 7.63689e+06 0.015625; - Add3~12 0xc0 1.12622e+07 0.5; - Add3~13 0xc0 9.35299e+06 0.492188; - Add3~14 0xc0 8.51744e+06 0.5; - Add3~15 0xc0 6.0592e+06 0.753906; - Add3~16 0xc0 7.85984e+06 0.5; - Add7~0 0xc0 7.68002e+06 0.5; - Add7~1 0xc0 7.68002e+06 0.5; - Add7~2 0xc0 7.68002e+06 0.5; - Add7~2_wirecell 0xc0 7.68002e+06 0.5; - Add7~3 0xc0 4.32001e+06 0.25; - Add7~4 0xc0 6.96002e+06 0.5; - Add7~4_wirecell 0xc0 6.96002e+06 0.5; - Add7~5 0xc0 2.04001e+06 0.875; - Add7~6 0xc0 7.02002e+06 0.5; - Add7~6_wirecell 0xc0 7.02002e+06 0.5; - Add7~7 0xc0 6.51002e+06 0.0625; - Add7~8 0xc0 1.0035e+07 0.5; - Add7~8_wirecell 0xc0 1.0035e+07 0.5; - Add7~9 0xc0 1.6875e+06 0.96875; - Add7~10 0xc0 8.05877e+06 0.5; - Add7~10_wirecell 0xc0 8.05877e+06 0.5; - Add7~11 0xc0 7.63689e+06 0.015625; - Add7~12 0xc0 1.12622e+07 0.5; - Add14~1 0xc0 7.68002e+06 0.5; - Add14~2 0xc0 7.68002e+06 0.5; - Add14~2_wirecell 0xc0 7.68002e+06 0.5; - Add14~3 0xc0 4.32001e+06 0.25; - Add14~4 0xc0 6.96002e+06 0.5; - Add14~4_wirecell 0xc0 6.96002e+06 0.5; - Add14~5 0xc0 2.04001e+06 0.875; - Add14~6 0xc0 7.02002e+06 0.5; - Add14~6_wirecell 0xc0 7.02002e+06 0.5; - Add14~7 0xc0 6.51002e+06 0.0625; - Add14~8 0xc0 1.0035e+07 0.5; - Add14~8_wirecell 0xc0 1.0035e+07 0.5; - Add14~9 0xc0 1.6875e+06 0.96875; - Add14~10 0xc0 8.05877e+06 0.5; - Add14~10_wirecell 0xc0 8.05877e+06 0.5; - Add14~11 0xc0 7.63689e+06 0.015625; - Add14~12 0xc0 1.12622e+07 0.5; - Add14~13 0xc0 9.35299e+06 0.492188; - Add14~14 0xc0 8.51744e+06 0.5; - Add14~15 0xc0 6.0592e+06 0.753906; - Add14~16 0xc0 7.85984e+06 0.5; - dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13; - delay_signals[0][0] 0xc0 7.68002e+06 0.5; - delay_signals[0][0]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][0] 0xc0 7.68002e+06 0.5; - delay_signals[1][0]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][0] 0xc0 7.68002e+06 0.5; - delay_signals[2][0]~feeder 0xc0 7.68002e+06 0.5; - dspba_delay:d_u0_m0_wo0_compute_q_15; - delay_signals[0][0] 0xc0 7.68002e+06 0.5; - delay_signals[0][0]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][0] 0xc0 7.68002e+06 0.5; - delay_signals[2][0] 0xc0 7.68002e+06 0.5; - delay_signals[2][0]~feeder 0xc0 7.68002e+06 0.5; - dspba_delay:d_u0_m0_wo0_compute_q_16; - delay_signals[0][0] 0xc0 7.68002e+06 0.5; - delay_signals[0][0]~feeder 0xc0 7.68002e+06 0.5; - dspba_delay:d_xIn_0_13; - delay_signals[0][0] 0xc0 7.68002e+06 0.5; - delay_signals[0][1] 0xc0 7.68002e+06 0.5; - delay_signals[0][1]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][2] 0xc0 7.68002e+06 0.5; - delay_signals[0][3] 0xc0 7.68002e+06 0.5; - delay_signals[0][4] 0xc0 7.68002e+06 0.5; - delay_signals[0][4]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][5] 0xc0 7.68002e+06 0.5; - delay_signals[0][6] 0xc0 7.68002e+06 0.5; - delay_signals[0][6]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][7] 0xc0 7.68002e+06 0.5; - delay_signals[0][7]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][8] 0xc0 7.68002e+06 0.5; - delay_signals[0][9] 0xc0 7.68002e+06 0.5; - delay_signals[0][10] 0xc0 7.68002e+06 0.5; - delay_signals[0][11] 0xc0 7.68002e+06 0.5; - delay_signals[0][11]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][12] 0xc0 7.68002e+06 0.5; - delay_signals[0][12]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][13] 0xc0 7.68002e+06 0.5; - delay_signals[0][13]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][14] 0xc0 7.68002e+06 0.5; - delay_signals[0][15] 0xc0 7.68002e+06 0.5; - delay_signals[0][15]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][16] 0xc0 7.68002e+06 0.5; - delay_signals[0][16]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][17] 0xc0 7.68002e+06 0.5; - delay_signals[0][17]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][18] 0xc0 7.68002e+06 0.5; - delay_signals[0][18]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][19] 0xc0 7.68002e+06 0.5; - delay_signals[0][19]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][20] 0xc0 7.68002e+06 0.5; - delay_signals[0][21] 0xc0 7.68002e+06 0.5; - delay_signals[0][22] 0xc0 7.68002e+06 0.5; - delay_signals[0][22]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][23] 0xc0 7.68002e+06 0.5; - delay_signals[0][24] 0xc0 7.68002e+06 0.5; - delay_signals[0][24]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][25] 0xc0 7.68002e+06 0.5; - delay_signals[0][25]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][26] 0xc0 7.68002e+06 0.5; - delay_signals[0][26]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][27] 0xc0 7.68002e+06 0.5; - delay_signals[0][28] 0xc0 7.68002e+06 0.5; - delay_signals[0][28]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][29] 0xc0 7.68002e+06 0.5; - delay_signals[0][29]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][30] 0xc0 7.68002e+06 0.5; - delay_signals[0][30]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[0][31] 0xc0 7.68002e+06 0.5; - delay_signals[1][0] 0xc0 7.68002e+06 0.5; - delay_signals[1][1] 0xc0 7.68002e+06 0.5; - delay_signals[1][1]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][2] 0xc0 7.68002e+06 0.5; - delay_signals[1][2]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][3] 0xc0 7.68002e+06 0.5; - delay_signals[1][4] 0xc0 7.68002e+06 0.5; - delay_signals[1][5] 0xc0 7.68002e+06 0.5; - delay_signals[1][5]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][6] 0xc0 7.68002e+06 0.5; - delay_signals[1][6]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][7] 0xc0 7.68002e+06 0.5; - delay_signals[1][7]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][8] 0xc0 7.68002e+06 0.5; - delay_signals[1][8]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][9] 0xc0 7.68002e+06 0.5; - delay_signals[1][10] 0xc0 7.68002e+06 0.5; - delay_signals[1][10]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][11] 0xc0 7.68002e+06 0.5; - delay_signals[1][11]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][12] 0xc0 7.68002e+06 0.5; - delay_signals[1][12]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][13] 0xc0 7.68002e+06 0.5; - delay_signals[1][13]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][14] 0xc0 7.68002e+06 0.5; - delay_signals[1][14]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][15] 0xc0 7.68002e+06 0.5; - delay_signals[1][15]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][16] 0xc0 7.68002e+06 0.5; - delay_signals[1][16]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][17] 0xc0 7.68002e+06 0.5; - delay_signals[1][17]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][18] 0xc0 7.68002e+06 0.5; - delay_signals[1][18]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][19] 0xc0 7.68002e+06 0.5; - delay_signals[1][19]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][20] 0xc0 7.68002e+06 0.5; - delay_signals[1][21] 0xc0 7.68002e+06 0.5; - delay_signals[1][21]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][22] 0xc0 7.68002e+06 0.5; - delay_signals[1][22]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][23] 0xc0 7.68002e+06 0.5; - delay_signals[1][23]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][24] 0xc0 7.68002e+06 0.5; - delay_signals[1][24]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][25] 0xc0 7.68002e+06 0.5; - delay_signals[1][26] 0xc0 7.68002e+06 0.5; - delay_signals[1][26]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][27] 0xc0 7.68002e+06 0.5; - delay_signals[1][27]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][28] 0xc0 7.68002e+06 0.5; - delay_signals[1][29] 0xc0 7.68002e+06 0.5; - delay_signals[1][29]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][30] 0xc0 7.68002e+06 0.5; - delay_signals[1][30]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][31] 0xc0 7.68002e+06 0.5; - delay_signals[2][0] 0xc0 7.68002e+06 0.5; - delay_signals[2][0]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][1] 0xc0 7.68002e+06 0.5; - delay_signals[2][1]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][2] 0xc0 7.68002e+06 0.5; - delay_signals[2][3] 0xc0 7.68002e+06 0.5; - delay_signals[2][4] 0xc0 7.68002e+06 0.5; - delay_signals[2][5] 0xc0 7.68002e+06 0.5; - delay_signals[2][6] 0xc0 7.68002e+06 0.5; - delay_signals[2][6]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][7] 0xc0 7.68002e+06 0.5; - delay_signals[2][7]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][8] 0xc0 7.68002e+06 0.5; - delay_signals[2][8]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][9] 0xc0 7.68002e+06 0.5; - delay_signals[2][10] 0xc0 7.68002e+06 0.5; - delay_signals[2][10]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][11] 0xc0 7.68002e+06 0.5; - delay_signals[2][11]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][12] 0xc0 7.68002e+06 0.5; - delay_signals[2][13] 0xc0 7.68002e+06 0.5; - delay_signals[2][14] 0xc0 7.68002e+06 0.5; - delay_signals[2][15] 0xc0 7.68002e+06 0.5; - delay_signals[2][16] 0xc0 7.68002e+06 0.5; - delay_signals[2][16]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][17] 0xc0 7.68002e+06 0.5; - delay_signals[2][17]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][18] 0xc0 7.68002e+06 0.5; - delay_signals[2][18]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][19] 0xc0 7.68002e+06 0.5; - delay_signals[2][20] 0xc0 7.68002e+06 0.5; - delay_signals[2][20]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][21] 0xc0 7.68002e+06 0.5; - delay_signals[2][21]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][22] 0xc0 7.68002e+06 0.5; - delay_signals[2][22]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][23] 0xc0 7.68002e+06 0.5; - delay_signals[2][24] 0xc0 7.68002e+06 0.5; - delay_signals[2][24]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][25] 0xc0 7.68002e+06 0.5; - delay_signals[2][25]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][26] 0xc0 7.68002e+06 0.5; - delay_signals[2][27] 0xc0 7.68002e+06 0.5; - delay_signals[2][27]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][28] 0xc0 7.68002e+06 0.5; - delay_signals[2][29] 0xc0 7.68002e+06 0.5; - delay_signals[2][29]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][30] 0xc0 7.68002e+06 0.5; - delay_signals[2][30]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[2][31] 0xc0 7.68002e+06 0.5; - Equal0~0 0xc0 1.53e+06 0.0625; - Equal0~1 0xc0 945002 0.0625; - Equal0~2 0xc0 10834.4 0.00195313; - Equal1~0 0xc0 804377 0.0625; - Equal1~1 0xc0 691877 0.0625; - Equal1~2 0xc0 5304.08 0.00195313; - Mux2~0 0xc0 5.94374e+06 0.125; - Mux2~1 0xc0 8.8022e+06 0.28125; - Mux3~0 0xc0 3.40313e+06 0.4375; - Mux3~1 0xc0 3.39751e+06 0.4375; - Mux3~2 0xc0 3.92256e+06 0.40625; - Mux3~3 0xc0 8.17903e+06 0.382813; - Mux4~0 0xc0 3.48376e+06 0.5; - Mux4~1 0xc0 3.99001e+06 0.5; - Mux4~2 0xc0 9.36263e+06 0.390625; - Mux4~3 0xc0 7.75589e+06 0.359863; - Mux5~0 0xc0 3.82501e+06 0.625; - Mux5~1 0xc0 2.82376e+06 0.625; - Mux5~2 0xc0 4.22461e+06 0.359375; - Mux5~3 0xc0 8.42689e+06 0.311035; - Mux6~0 0xc0 3.33751e+06 0.3125; - Mux6~1 0xc0 3.54001e+06 0.6875; - Mux6~2 0xc0 3.40797e+06 0.4375; - Mux6~3 0xc0 3.73097e+06 0.425781; - Mux7~0 0xc0 3.23626e+06 0.5; - Mux7~1 0xc0 3.85501e+06 0.5; - Mux7~2 0xc0 7.03893e+06 0.390625; - Mux7~3 0xc0 1.17305e+07 0.359863; - Mux8~0 0xc0 3.87751e+06 0.5; - Mux8~1 0xc0 4.44001e+06 0.5; - Mux8~2 0xc0 7.20034e+06 0.40625; - Mux8~3 0xc0 3.71846e+06 0.376953; - Mux9~0 0xc0 3.96001e+06 0.375; - Mux9~1 0xc0 3.96001e+06 0.625; - Mux9~2 0xc0 691877 0.0625; - Mux9~3 0xc0 4.31484e+06 0.359375; - Mux9~4 0xc0 945002 0.0625; - Mux9~5 0xc0 3.75681e+06 0.311035; - Mux9~6 0xc0 1.83e+06 0.125; - Mux9~7 0xc0 2.28001e+06 0.125; - u0_m0_wo0_accum_o[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[0]~46 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[0]~47 0xc0 4.32001e+06 0.25; - u0_m0_wo0_accum_o[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[1]~48 0xc0 6.48002e+06 0.5; - u0_m0_wo0_accum_o[1]~49 0xc0 3.57751e+06 0.625; - u0_m0_wo0_accum_o[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[2]~50 0xc0 5.48439e+06 0.5; - u0_m0_wo0_accum_o[2]~51 0xc0 6.3722e+06 0.4375; - u0_m0_wo0_accum_o[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[3]~52 0xc0 5.98056e+06 0.5; - u0_m0_wo0_accum_o[3]~53 0xc0 4.88779e+06 0.53125; - u0_m0_wo0_accum_o[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[4]~54 0xc0 5.55883e+06 0.5; - u0_m0_wo0_accum_o[4]~55 0xc0 5.4588e+06 0.484375; - u0_m0_wo0_accum_o[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[5]~56 0xc0 5.68893e+06 0.5; - u0_m0_wo0_accum_o[5]~57 0xc0 5.11181e+06 0.507813; - u0_m0_wo0_accum_o[6] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[6]~58 0xc0 5.59902e+06 0.5; - u0_m0_wo0_accum_o[6]~59 0xc0 5.2676e+06 0.496094; - u0_m0_wo0_accum_o[7] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[7]~60 0xc0 5.63718e+06 0.5; - u0_m0_wo0_accum_o[7]~61 0xc0 5.18499e+06 0.501953; - u0_m0_wo0_accum_o[8] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[8]~62 0xc0 5.61632e+06 0.5; - u0_m0_wo0_accum_o[8]~63 0xc0 5.22508e+06 0.499023; - u0_m0_wo0_accum_o[9] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[9]~64 0xc0 5.6263e+06 0.5; - u0_m0_wo0_accum_o[9]~65 0xc0 5.20473e+06 0.500488; - u0_m0_wo0_accum_o[10] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[10]~66 0xc0 5.6212e+06 0.5; - u0_m0_wo0_accum_o[10]~67 0xc0 5.21483e+06 0.499756; - u0_m0_wo0_accum_o[11] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[11]~68 0xc0 5.62372e+06 0.5; - u0_m0_wo0_accum_o[11]~69 0xc0 5.20976e+06 0.500122; - u0_m0_wo0_accum_o[12] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[12]~70 0xc0 5.62245e+06 0.5; - u0_m0_wo0_accum_o[12]~71 0xc0 5.21229e+06 0.499939; - u0_m0_wo0_accum_o[13] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[13]~72 0xc0 5.62308e+06 0.5; - u0_m0_wo0_accum_o[13]~73 0xc0 5.21102e+06 0.500031; - u0_m0_wo0_accum_o[14] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[14]~74 0xc0 5.62277e+06 0.5; - u0_m0_wo0_accum_o[14]~75 0xc0 5.21165e+06 0.499985; - u0_m0_wo0_accum_o[15] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[15]~76 0xc0 5.62292e+06 0.5; - u0_m0_wo0_accum_o[15]~77 0xc0 5.21134e+06 0.500008; - u0_m0_wo0_accum_o[16] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[16]~78 0xc0 5.62285e+06 0.5; - u0_m0_wo0_accum_o[16]~79 0xc0 5.21149e+06 0.499996; - u0_m0_wo0_accum_o[17] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[17]~80 0xc0 5.62289e+06 0.5; - u0_m0_wo0_accum_o[17]~81 0xc0 5.21142e+06 0.500002; - u0_m0_wo0_accum_o[18] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[18]~82 0xc0 5.62286e+06 0.5; - u0_m0_wo0_accum_o[18]~83 0xc0 5.21146e+06 0.499999; - u0_m0_wo0_accum_o[19] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[19]~84 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[19]~85 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[20] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[20]~86 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[20]~87 0xc0 5.21145e+06 0.5; - u0_m0_wo0_accum_o[21] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[21]~88 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[21]~89 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[22] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[22]~90 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[22]~91 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[23] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[23]~92 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[23]~93 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[24] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[24]~94 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[24]~95 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[25] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[25]~96 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[25]~97 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[26] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[26]~98 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[26]~99 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[27] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[27]~100 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[27]~101 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[28] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[28]~102 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[28]~103 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[29] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[29]~104 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[29]~105 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[30] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[30]~106 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[30]~107 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[31] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[31]~108 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[31]~109 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[32] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[32]~110 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[32]~111 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[33] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[33]~112 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[33]~113 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[34] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[34]~114 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[34]~115 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[35] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[35]~116 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[35]~117 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[36] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[36]~118 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[36]~119 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[37] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[37]~120 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[37]~121 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[38] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[38]~122 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[38]~123 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[39] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[39]~124 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[39]~125 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[40] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[40]~126 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[40]~127 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[41] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[41]~128 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[41]~129 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[42] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[42]~130 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[42]~131 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[43] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[43]~132 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[43]~133 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[44] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[44]~134 0xc0 5.62287e+06 0.5; - u0_m0_wo0_accum_o[44]~135 0xc0 5.21144e+06 0.5; - u0_m0_wo0_accum_o[45] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_accum_o[45]~136 0xc0 7.06288e+06 0.5; - u0_m0_wo0_aseq_eq 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[0]~5 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[1]~6 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[1]~7 0xc0 4.32001e+06 0.25; - u0_m0_wo0_ca0_i[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[2]~8 0xc0 6.96002e+06 0.5; - u0_m0_wo0_ca0_i[2]~9 0xc0 1.83e+06 0.875; - u0_m0_wo0_ca0_i[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[3]~10 0xc0 6.91502e+06 0.5; - u0_m0_wo0_ca0_i[3]~11 0xc0 6.45752e+06 0.0625; - u0_m0_wo0_ca0_i[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[4]~12 0xc0 1.00088e+07 0.5; - u0_m0_wo0_ca0_i[4]~13 0xc0 1.67438e+06 0.96875; - u0_m0_wo0_ca0_i[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_ca0_i[5]~14 0xc0 8.05221e+06 0.5; - u0_m0_wo0_cm0_q[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_cm0_q[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_cm0_q[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_cm0_q[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_cm0_q[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_cm0_q[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_cm0_q[6] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_cm0_q[7] 0xc0 7.68002e+06 0.5; - dspba_delay:u0_m0_wo0_compute; - delay_signals[0][0] 0xc0 7.68002e+06 0.5; - delay_signals[0][0]~feeder 0xc0 7.68002e+06 0.5; - delay_signals[1][0] 0xc0 7.68002e+06 0.5; - delay_signals[1][0]~feeder 0xc0 7.68002e+06 0.5; - dspba_delay:u0_m0_wo0_memread; - delay_signals[0][0] 0xc0 7.68002e+06 0.5; - lpm_mult:u0_m0_wo0_mtree_mult1_0_im0_component; - mult_rcu:auto_generated; - mac_mult1 0xc0 3.07201e+07 0.5; - mac_mult1~10 0xc0 0 0; - mac_mult1~11 0xc0 0 0; - mac_mult1~12 0xc0 0 0; - mac_mult1~13 0xc0 0 0; - mac_mult1~14 0xc0 0 0; - mac_mult1~15 0xc0 0 0; - mac_mult1~16 0xc0 0 0; - mac_mult1~17 0xc0 0 0; - mac_mult1~18 0xc0 0 0; - mac_mult1~19 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT2 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT3 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT4 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT5 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT6 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT7 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT8 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT9 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT10 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT11 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT12 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT13 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT14 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT15 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT16 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT17 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT18 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT19 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT20 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT21 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT22 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT23 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT24 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT25 0xc0 3.07201e+07 0.5; - result[0] 0xc0 7.68002e+06 0.5; - result[1] 0xc0 7.68002e+06 0.5; - result[2] 0xc0 7.68002e+06 0.5; - result[3] 0xc0 7.68002e+06 0.5; - result[4] 0xc0 7.68002e+06 0.5; - result[5] 0xc0 7.68002e+06 0.5; - result[6] 0xc0 7.68002e+06 0.5; - result[7] 0xc0 7.68002e+06 0.5; - result[8] 0xc0 7.68002e+06 0.5; - result[9] 0xc0 7.68002e+06 0.5; - result[10] 0xc0 7.68002e+06 0.5; - result[11] 0xc0 7.68002e+06 0.5; - result[12] 0xc0 7.68002e+06 0.5; - result[13] 0xc0 7.68002e+06 0.5; - result[14] 0xc0 7.68002e+06 0.5; - result[15] 0xc0 7.68002e+06 0.5; - result[16] 0xc0 7.68002e+06 0.5; - result[17] 0xc0 7.68002e+06 0.5; - result[18] 0xc0 7.68002e+06 0.5; - result[19] 0xc0 7.68002e+06 0.5; - result[20] 0xc0 7.68002e+06 0.5; - result[21] 0xc0 7.68002e+06 0.5; - result[22] 0xc0 7.68002e+06 0.5; - result[23] 0xc0 7.68002e+06 0.5; - result[24] 0xc0 7.68002e+06 0.5; - result[25] 0xc0 7.68002e+06 0.5; - lpm_mult:u0_m0_wo0_mtree_mult1_0_im4_component; - mult_lcu:auto_generated; - mac_mult1 0xc0 3.07201e+07 0.5; - mac_mult1~13 0xc0 0 0; - mac_mult1~14 0xc0 0 0; - mac_mult1~15 0xc0 0 0; - mac_mult1~16 0xc0 0 0; - mac_mult1~17 0xc0 0 0; - mac_mult1~18 0xc0 0 0; - mac_mult1~19 0xc0 0 0; - mac_mult1~20 0xc0 0 0; - mac_mult1~21 0xc0 0 0; - mac_mult1~22 0xc0 0 0; - mac_mult1~23 0xc0 0 0; - mac_mult1~24 0xc0 0 0; - mac_mult1~25 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT2 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT3 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT4 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT5 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT6 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT7 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT8 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT9 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT10 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT11 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT12 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT13 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT14 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT15 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT16 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT17 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT18 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT19 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT20 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT21 0xc0 3.07201e+07 0.5; - mac_mult1~DATAOUT22 0xc0 3.07201e+07 0.5; - result[0] 0xc0 7.68002e+06 0.5; - result[1] 0xc0 7.68002e+06 0.5; - result[2] 0xc0 7.68002e+06 0.5; - result[3] 0xc0 7.68002e+06 0.5; - result[4] 0xc0 7.68002e+06 0.5; - result[5] 0xc0 7.68002e+06 0.5; - result[6] 0xc0 7.68002e+06 0.5; - result[7] 0xc0 7.68002e+06 0.5; - result[8] 0xc0 7.68002e+06 0.5; - result[9] 0xc0 7.68002e+06 0.5; - result[10] 0xc0 7.68002e+06 0.5; - result[11] 0xc0 7.68002e+06 0.5; - result[12] 0xc0 7.68002e+06 0.5; - result[13] 0xc0 7.68002e+06 0.5; - result[14] 0xc0 7.68002e+06 0.5; - result[15] 0xc0 7.68002e+06 0.5; - result[16] 0xc0 7.68002e+06 0.5; - result[17] 0xc0 7.68002e+06 0.5; - result[18] 0xc0 7.68002e+06 0.5; - result[19] 0xc0 7.68002e+06 0.5; - result[20] 0xc0 7.68002e+06 0.5; - result[21] 0xc0 7.68002e+06 0.5; - result[22] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[2]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[3]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[4]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[5]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[6] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[6]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[7] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[7]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[8] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[8]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[9] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[9]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[10] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[10]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[11] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[11]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[12] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[12]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[13] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[14] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[15] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[15]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[16] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[16]~feeder 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[17] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[17]~24 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[17]~25 0xc0 4.32001e+06 0.25; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[18] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[18]~26 0xc0 6.48002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[18]~27 0xc0 3.57751e+06 0.625; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[19] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[19]~28 0xc0 5.48439e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[19]~29 0xc0 6.3722e+06 0.4375; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[20] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[20]~30 0xc0 5.98056e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[20]~31 0xc0 4.88779e+06 0.53125; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[21] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[21]~32 0xc0 5.55883e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[21]~33 0xc0 5.4588e+06 0.484375; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[22] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[22]~34 0xc0 5.68893e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[22]~35 0xc0 5.11181e+06 0.507813; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[23] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[23]~36 0xc0 5.59902e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[23]~37 0xc0 5.2676e+06 0.496094; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[24] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[24]~38 0xc0 5.63718e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[24]~39 0xc0 5.18499e+06 0.501953; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[25] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[25]~40 0xc0 7.05635e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[25]~41 0xc0 7.39074e+06 0.499023; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[26] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[26]~42 0xc0 7.60772e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[26]~43 0xc0 7.63264e+06 0.500488; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[27] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[27]~44 0xc0 7.66818e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[27]~45 0xc0 7.67973e+06 0.499756; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[28] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[28]~46 0xc0 7.67995e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[28]~47 0xc0 7.67717e+06 0.500122; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[29] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[29]~48 0xc0 7.67931e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[29]~49 0xc0 7.68107e+06 0.499939; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[30] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[30]~50 0xc0 7.68028e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[30]~51 0xc0 7.67945e+06 0.500031; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[31] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[31]~52 0xc0 7.67988e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[31]~53 0xc0 7.6803e+06 0.499985; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[32] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[32]~54 0xc0 7.68009e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[32]~55 0xc0 7.67988e+06 0.500008; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[33] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[33]~56 0xc0 7.67998e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[33]~57 0xc0 7.68009e+06 0.499996; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[34] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[34]~58 0xc0 7.68004e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[34]~59 0xc0 7.67998e+06 0.500002; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[35] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[35]~60 0xc0 7.68001e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[35]~61 0xc0 7.68004e+06 0.499999; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[36] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[36]~62 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[36]~63 0xc0 7.68001e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[37] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[37]~64 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[37]~65 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[38] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[38]~66 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[38]~67 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[39] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[39]~68 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[39]~69 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[40] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_mtree_mult1_0_result_add_0_0_o[40]~70 0xc0 7.68002e+06 0.5; - u0_m0_wo0_oseq_eq 0xc0 7.68002e+06 0.5; - u0_m0_wo0_oseq_gated_q[0] 0xc0 5.76001e+06 0.25; - u0_m0_wo0_oseq_gated_reg_q[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_run_count[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_run_count[0]~0 0xc0 3.60751e+06 0.5; - u0_m0_wo0_run_count[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_run_enableQ[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_run_enableQ~0 0xc0 4.51474e+06 0.25; - u0_m0_wo0_run_q[0] 0xc0 7.68002e+06 0.5; - altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem; - altsyncram_sln3:auto_generated; - q_b[0] 0xc0 7.68002e+06 0.5; - q_b[1] 0xc0 7.68002e+06 0.5; - q_b[2] 0xc0 7.68002e+06 0.5; - q_b[3] 0xc0 7.68002e+06 0.5; - q_b[4] 0xc0 7.68002e+06 0.5; - q_b[5] 0xc0 7.68002e+06 0.5; - q_b[6] 0xc0 7.68002e+06 0.5; - q_b[7] 0xc0 7.68002e+06 0.5; - q_b[8] 0xc0 7.68002e+06 0.5; - q_b[9] 0xc0 7.68002e+06 0.5; - q_b[10] 0xc0 7.68002e+06 0.5; - q_b[11] 0xc0 7.68002e+06 0.5; - q_b[12] 0xc0 7.68002e+06 0.5; - q_b[13] 0xc0 7.68002e+06 0.5; - q_b[14] 0xc0 7.68002e+06 0.5; - q_b[15] 0xc0 7.68002e+06 0.5; - q_b[16] 0xc0 7.68002e+06 0.5; - q_b[17] 0xc0 7.68002e+06 0.5; - q_b[18] 0xc0 7.68002e+06 0.5; - q_b[19] 0xc0 7.68002e+06 0.5; - q_b[20] 0xc0 7.68002e+06 0.5; - q_b[21] 0xc0 7.68002e+06 0.5; - q_b[22] 0xc0 7.68002e+06 0.5; - q_b[23] 0xc0 7.68002e+06 0.5; - q_b[24] 0xc0 7.68002e+06 0.5; - q_b[25] 0xc0 7.68002e+06 0.5; - q_b[26] 0xc0 7.68002e+06 0.5; - q_b[27] 0xc0 7.68002e+06 0.5; - q_b[28] 0xc0 7.68002e+06 0.5; - q_b[29] 0xc0 7.68002e+06 0.5; - q_b[30] 0xc0 7.68002e+06 0.5; - q_b[31] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0]~6 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0]~7 0xc0 4.32001e+06 0.25; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1]~8 0xc0 6.48002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1]~9 0xc0 3.57751e+06 0.625; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2]~10 0xc0 5.48439e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2]~11 0xc0 6.3722e+06 0.4375; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3]~12 0xc0 5.98056e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3]~13 0xc0 4.88779e+06 0.53125; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4]~14 0xc0 5.55883e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4]~15 0xc0 5.4588e+06 0.484375; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[5]~16 0xc0 5.68893e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_clkproc~0 0xc0 4.32001e+06 0.25; - u0_m0_wo0_wi0_r0_ra0_count0_i[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[0]~5 0xc0 5.52001e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[1]~6 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[1]~7 0xc0 4.32001e+06 0.25; - u0_m0_wo0_wi0_r0_ra0_count0_i[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[2]~8 0xc0 6.96002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[2]~9 0xc0 1.83e+06 0.875; - u0_m0_wo0_wi0_r0_ra0_count0_i[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[3]~10 0xc0 6.91502e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[3]~11 0xc0 6.45752e+06 0.0625; - u0_m0_wo0_wi0_r0_ra0_count0_i[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[4]~12 0xc0 1.00088e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[4]~13 0xc0 1.67438e+06 0.96875; - u0_m0_wo0_wi0_r0_ra0_count0_i[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[5]~14 0xc0 8.05221e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0]~7 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0]~8 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1]~9 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1]~10 0xc0 4.32001e+06 0.25; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2]~11 0xc0 6.96002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2]~12 0xc0 2.04001e+06 0.875; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3]~13 0xc0 7.02002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3]~14 0xc0 6.51002e+06 0.0625; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4]~15 0xc0 1.0035e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4]~16 0xc0 1.6875e+06 0.96875; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5]~17 0xc0 8.05877e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5]~18 0xc0 7.63689e+06 0.015625; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6]~19 0xc0 1.12622e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[0]~5 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[1]~6 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[1]~7 0xc0 4.32001e+06 0.25; - u0_m0_wo0_wi0_r0_ra0_count1_i[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[2]~8 0xc0 6.96002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[2]~9 0xc0 1.83e+06 0.875; - u0_m0_wo0_wi0_r0_ra0_count1_i[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[3]~10 0xc0 6.91502e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[3]~11 0xc0 6.45752e+06 0.0625; - u0_m0_wo0_wi0_r0_ra0_count1_i[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[4]~12 0xc0 1.00088e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[4]~13 0xc0 1.67438e+06 0.96875; - u0_m0_wo0_wi0_r0_ra0_count1_i[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[5]~14 0xc0 8.05221e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[0] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[0]~5 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[0]~_wirecell 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[1] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[1]~6 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[1]~7 0xc0 4.32001e+06 0.25; - u0_m0_wo0_wi0_r0_wa0_i[1]~_wirecell 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[2] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[2]~8 0xc0 6.96002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[2]~9 0xc0 1.83e+06 0.875; - u0_m0_wo0_wi0_r0_wa0_i[2]~_wirecell 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[3] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[3]~10 0xc0 6.91502e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[3]~11 0xc0 6.45752e+06 0.0625; - u0_m0_wo0_wi0_r0_wa0_i[3]~_wirecell 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[4] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[4]~12 0xc0 1.00088e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[4]~13 0xc0 1.67438e+06 0.96875; - u0_m0_wo0_wi0_r0_wa0_i[4]~_wirecell 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[5] 0xc0 7.68002e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[5]~14 0xc0 8.05221e+06 0.5; - u0_m0_wo0_wi0_r0_wa0_i[5]~_wirecell 0xc0 7.68002e+06 0.5; - auk_dspip_avalon_streaming_sink_hpfir:sink; - auk_dspip_avalon_streaming_source_hpfir:source; - data_out[0] 0xc0 7.68002e+06 0.5; - data_out[1] 0xc0 7.68002e+06 0.5; - data_out[2] 0xc0 7.68002e+06 0.5; - data_out[3] 0xc0 7.68002e+06 0.5; - data_out[4] 0xc0 7.68002e+06 0.5; - data_out[5] 0xc0 7.68002e+06 0.5; - data_out[6] 0xc0 7.68002e+06 0.5; - data_out[7] 0xc0 7.68002e+06 0.5; - data_out[8] 0xc0 7.68002e+06 0.5; - data_out[9] 0xc0 7.68002e+06 0.5; - data_out[10] 0xc0 7.68002e+06 0.5; - data_out[11] 0xc0 7.68002e+06 0.5; - data_out[12] 0xc0 7.68002e+06 0.5; - data_out[13] 0xc0 7.68002e+06 0.5; - data_out[14] 0xc0 7.68002e+06 0.5; - data_out[15] 0xc0 7.68002e+06 0.5; - data_out[16] 0xc0 7.68002e+06 0.5; - data_out[17] 0xc0 7.68002e+06 0.5; - data_out[18] 0xc0 7.68002e+06 0.5; - data_out[19] 0xc0 7.68002e+06 0.5; - data_out[20] 0xc0 7.68002e+06 0.5; - data_out[21] 0xc0 7.68002e+06 0.5; - data_out[22] 0xc0 7.68002e+06 0.5; - data_out[23] 0xc0 7.68002e+06 0.5; - data_out[24] 0xc0 7.68002e+06 0.5; - data_out[25] 0xc0 7.68002e+06 0.5; - data_out[26] 0xc0 7.68002e+06 0.5; - data_out[27] 0xc0 7.68002e+06 0.5; - data_out[28] 0xc0 7.68002e+06 0.5; - data_out[29] 0xc0 7.68002e+06 0.5; - data_out[30] 0xc0 7.68002e+06 0.5; - data_out[31] 0xc0 7.68002e+06 0.5; - data_out[32] 0xc0 7.68002e+06 0.5; - data_out[32]~feeder 0xc0 7.68002e+06 0.5; - data_out[33] 0xc0 7.68002e+06 0.5; - data_out[34] 0xc0 7.68002e+06 0.5; - data_out[34]~feeder 0xc0 7.68002e+06 0.5; - data_out[35] 0xc0 7.68002e+06 0.5; - data_out[36] 0xc0 7.68002e+06 0.5; - data_out[36]~feeder 0xc0 7.68002e+06 0.5; - data_out[37] 0xc0 7.68002e+06 0.5; - data_out[38] 0xc0 7.68002e+06 0.5; - data_out[39] 0xc0 7.68002e+06 0.5; - data_out[39]~feeder 0xc0 7.68002e+06 0.5; - data_out[40] 0xc0 7.68002e+06 0.5; - data_out[40]~feeder 0xc0 7.68002e+06 0.5; - data_out[41] 0xc0 7.68002e+06 0.5; - data_out[41]~feeder 0xc0 7.68002e+06 0.5; - data_out[42] 0xc0 7.68002e+06 0.5; - data_out[43] 0xc0 7.68002e+06 0.5; - data_out[44] 0xc0 7.68002e+06 0.5; - data_out[45] 0xc0 7.68002e+06 0.5; - data_out[45]~feeder 0xc0 7.68002e+06 0.5; - data_valid 0xc0 7.68002e+06 0.5; - mixer:RX_MIXER_I; - lpm_mult:lpm_mult_component; - mult_jnp:auto_generated; - mac_mult1 0xc0 1.92e+06 0.5; - mac_mult1~0 0xc0 0 0; - mac_mult1~1 0xc0 0 0; - mac_mult1~2 0xc0 0 0; - mac_mult1~3 0xc0 0 0; - mac_mult1~4 0xc0 0 0; - mac_mult1~5 0xc0 0 0; - mac_mult1~6 0xc0 0 0; - mac_mult1~7 0xc0 0 0; - mac_mult1~8 0xc0 0 0; - mac_mult1~9 0xc0 0 0; - mac_mult1~10 0xc0 0 0; - mac_mult1~11 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT2 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT3 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT4 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT5 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT6 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT7 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT8 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT9 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT10 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT11 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT12 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT13 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT14 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT15 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT16 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT17 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT18 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT19 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT20 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT21 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT22 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT23 0xc0 1.92e+06 0.5; - result[0] 0xc0 7.68002e+06 0.5; - result[1] 0xc0 7.68002e+06 0.5; - result[2] 0xc0 7.68002e+06 0.5; - result[3] 0xc0 7.68002e+06 0.5; - result[4] 0xc0 7.68002e+06 0.5; - result[5] 0xc0 7.68002e+06 0.5; - result[6] 0xc0 7.68002e+06 0.5; - result[7] 0xc0 7.68002e+06 0.5; - result[8] 0xc0 7.68002e+06 0.5; - result[9] 0xc0 7.68002e+06 0.5; - result[10] 0xc0 7.68002e+06 0.5; - result[11] 0xc0 7.68002e+06 0.5; - result[12] 0xc0 7.68002e+06 0.5; - result[13] 0xc0 7.68002e+06 0.5; - result[14] 0xc0 7.68002e+06 0.5; - result[15] 0xc0 7.68002e+06 0.5; - result[16] 0xc0 7.68002e+06 0.5; - result[17] 0xc0 7.68002e+06 0.5; - result[18] 0xc0 7.68002e+06 0.5; - result[19] 0xc0 7.68002e+06 0.5; - result[20] 0xc0 7.68002e+06 0.5; - result[21] 0xc0 7.68002e+06 0.5; - result[22] 0xc0 7.68002e+06 0.5; - mixer:RX_MIXER_Q; - lpm_mult:lpm_mult_component; - mult_jnp:auto_generated; - mac_mult1 0xc0 1.92e+06 0.5; - mac_mult1~0 0xc0 0 0; - mac_mult1~1 0xc0 0 0; - mac_mult1~2 0xc0 0 0; - mac_mult1~3 0xc0 0 0; - mac_mult1~4 0xc0 0 0; - mac_mult1~5 0xc0 0 0; - mac_mult1~6 0xc0 0 0; - mac_mult1~7 0xc0 0 0; - mac_mult1~8 0xc0 0 0; - mac_mult1~9 0xc0 0 0; - mac_mult1~10 0xc0 0 0; - mac_mult1~11 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT2 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT3 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT4 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT5 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT6 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT7 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT8 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT9 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT10 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT11 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT12 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT13 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT14 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT15 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT16 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT17 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT18 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT19 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT20 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT21 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT22 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT23 0xc0 1.92e+06 0.5; - result[0] 0xc0 7.68002e+06 0.5; - result[1] 0xc0 7.68002e+06 0.5; - result[2] 0xc0 7.68002e+06 0.5; - result[3] 0xc0 7.68002e+06 0.5; - result[4] 0xc0 7.68002e+06 0.5; - result[5] 0xc0 7.68002e+06 0.5; - result[6] 0xc0 7.68002e+06 0.5; - result[7] 0xc0 7.68002e+06 0.5; - result[8] 0xc0 7.68002e+06 0.5; - result[9] 0xc0 7.68002e+06 0.5; - result[10] 0xc0 7.68002e+06 0.5; - result[11] 0xc0 7.68002e+06 0.5; - result[12] 0xc0 7.68002e+06 0.5; - result[13] 0xc0 7.68002e+06 0.5; - result[14] 0xc0 7.68002e+06 0.5; - result[15] 0xc0 7.68002e+06 0.5; - result[16] 0xc0 7.68002e+06 0.5; - result[17] 0xc0 7.68002e+06 0.5; - result[18] 0xc0 7.68002e+06 0.5; - result[19] 0xc0 7.68002e+06 0.5; - result[20] 0xc0 7.68002e+06 0.5; - result[21] 0xc0 7.68002e+06 0.5; - result[22] 0xc0 7.68002e+06 0.5; - nco:RX_NCO; - nco_nco_ii_0:nco_ii_0; - asj_nco_mob_w:blk0; - Equal0~0 0xc0 945002 0.0625; - Equal0~1 0xc0 945002 0.0625; - Equal0~2 0xc0 945002 0.0625; - Equal0~3 0xc0 89.9113 0.999878; - add_one 0xc0 4.32001e+06 0.25; - data_tmp[0] 0xc0 7.68002e+06 0.5; - data_tmp[1] 0xc0 7.68002e+06 0.5; - data_tmp[2] 0xc0 7.68002e+06 0.5; - data_tmp[3] 0xc0 7.68002e+06 0.5; - data_tmp[4] 0xc0 7.68002e+06 0.5; - data_tmp[5] 0xc0 7.68002e+06 0.5; - data_tmp[6] 0xc0 7.68002e+06 0.5; - data_tmp[7] 0xc0 7.68002e+06 0.5; - data_tmp[8] 0xc0 7.68002e+06 0.5; - data_tmp[9] 0xc0 7.68002e+06 0.5; - data_tmp[10] 0xc0 7.68002e+06 0.5; - data_tmp[11] 0xc0 7.68002e+06 0.5; - data_tmp~0 0xc0 4.32001e+06 0.25; - data_tmp~1 0xc0 4.32001e+06 0.25; - data_tmp~2 0xc0 4.32001e+06 0.25; - data_tmp~3 0xc0 4.32001e+06 0.25; - data_tmp~4 0xc0 4.32001e+06 0.25; - data_tmp~5 0xc0 4.32001e+06 0.25; - data_tmp~6 0xc0 4.32001e+06 0.25; - data_tmp~7 0xc0 4.32001e+06 0.25; - data_tmp~8 0xc0 4.32001e+06 0.25; - data_tmp~9 0xc0 4.32001e+06 0.25; - data_tmp~10 0xc0 4.32001e+06 0.25; - data_tmp~11 0xc0 4.32001e+06 0.25; - is_zero 0xc0 7.68002e+06 0.5; - lpm_add_sub:lpm_add_sub_component; - add_sub_fpk:auto_generated; - pipeline_dffe[0] 0xc0 7.68002e+06 0.5; - pipeline_dffe[0]~12 0xc0 6.96002e+06 0.5; - pipeline_dffe[0]~13 0xc0 5.88002e+06 0.125; - pipeline_dffe[1] 0xc0 7.68002e+06 0.5; - pipeline_dffe[1]~14 0xc0 8.94002e+06 0.5; - pipeline_dffe[1]~15 0xc0 1.71e+06 0.9375; - pipeline_dffe[2] 0xc0 7.68002e+06 0.5; - pipeline_dffe[2]~16 0xc0 7.63502e+06 0.5; - pipeline_dffe[2]~17 0xc0 7.20752e+06 0.03125; - pipeline_dffe[3] 0xc0 7.68002e+06 0.5; - pipeline_dffe[3]~18 0xc0 1.08188e+07 0.5; - pipeline_dffe[3]~19 0xc0 1.81688e+06 0.984375; - pipeline_dffe[4] 0xc0 7.68002e+06 0.5; - pipeline_dffe[4]~20 0xc0 8.35221e+06 0.5; - pipeline_dffe[4]~21 0xc0 7.89799e+06 0.0078125; - pipeline_dffe[5] 0xc0 7.68002e+06 0.5; - pipeline_dffe[5]~22 0xc0 1.151e+07 0.5; - pipeline_dffe[5]~23 0xc0 1.97543e+06 0.996094; - pipeline_dffe[6] 0xc0 7.68002e+06 0.5; - pipeline_dffe[6]~24 0xc0 8.60797e+06 0.5; - pipeline_dffe[6]~25 0xc0 8.11411e+06 0.00195313; - pipeline_dffe[7] 0xc0 7.68002e+06 0.5; - pipeline_dffe[7]~26 0xc0 1.17071e+07 0.5; - pipeline_dffe[7]~27 0xc0 2.02859e+06 0.999023; - pipeline_dffe[8] 0xc0 7.68002e+06 0.5; - pipeline_dffe[8]~28 0xc0 8.67933e+06 0.5; - pipeline_dffe[8]~29 0xc0 8.17218e+06 0.000488281; - pipeline_dffe[9] 0xc0 7.68002e+06 0.5; - pipeline_dffe[9]~30 0xc0 1.17586e+07 0.5; - pipeline_dffe[9]~31 0xc0 2.04305e+06 0.999756; - pipeline_dffe[10] 0xc0 7.68002e+06 0.5; - pipeline_dffe[10]~32 0xc0 8.6978e+06 0.5; - pipeline_dffe[10]~33 0xc0 8.18703e+06 0.00012207; - pipeline_dffe[11] 0xc0 7.68002e+06 0.5; - pipeline_dffe[11]~34 0xc0 1.17717e+07 0.5; - asj_nco_mob_w:blk1; - Equal0~0 0xc0 945002 0.0625; - Equal0~1 0xc0 945002 0.0625; - Equal0~2 0xc0 945002 0.0625; - Equal0~3 0xc0 89.9113 0.999878; - add_one 0xc0 4.32001e+06 0.25; - data_tmp[0] 0xc0 7.68002e+06 0.5; - data_tmp[1] 0xc0 7.68002e+06 0.5; - data_tmp[2] 0xc0 7.68002e+06 0.5; - data_tmp[3] 0xc0 7.68002e+06 0.5; - data_tmp[4] 0xc0 7.68002e+06 0.5; - data_tmp[5] 0xc0 7.68002e+06 0.5; - data_tmp[6] 0xc0 7.68002e+06 0.5; - data_tmp[7] 0xc0 7.68002e+06 0.5; - data_tmp[8] 0xc0 7.68002e+06 0.5; - data_tmp[9] 0xc0 7.68002e+06 0.5; - data_tmp[10] 0xc0 7.68002e+06 0.5; - data_tmp[11] 0xc0 7.68002e+06 0.5; - data_tmp~0 0xc0 4.32001e+06 0.25; - data_tmp~1 0xc0 4.32001e+06 0.25; - data_tmp~2 0xc0 4.32001e+06 0.25; - data_tmp~3 0xc0 4.32001e+06 0.25; - data_tmp~4 0xc0 4.32001e+06 0.25; - data_tmp~5 0xc0 4.32001e+06 0.25; - data_tmp~6 0xc0 4.32001e+06 0.25; - data_tmp~7 0xc0 4.32001e+06 0.25; - data_tmp~8 0xc0 4.32001e+06 0.25; - data_tmp~9 0xc0 4.32001e+06 0.25; - data_tmp~10 0xc0 4.32001e+06 0.25; - data_tmp~11 0xc0 4.32001e+06 0.25; - is_zero 0xc0 7.68002e+06 0.5; - lpm_add_sub:lpm_add_sub_component; - add_sub_fpk:auto_generated; - pipeline_dffe[0] 0xc0 7.68002e+06 0.5; - pipeline_dffe[0]~12 0xc0 6.96002e+06 0.5; - pipeline_dffe[0]~13 0xc0 5.88002e+06 0.125; - pipeline_dffe[1] 0xc0 7.68002e+06 0.5; - pipeline_dffe[1]~14 0xc0 8.94002e+06 0.5; - pipeline_dffe[1]~15 0xc0 1.71e+06 0.9375; - pipeline_dffe[2] 0xc0 7.68002e+06 0.5; - pipeline_dffe[2]~16 0xc0 7.63502e+06 0.5; - pipeline_dffe[2]~17 0xc0 7.20752e+06 0.03125; - pipeline_dffe[3] 0xc0 7.68002e+06 0.5; - pipeline_dffe[3]~18 0xc0 1.08188e+07 0.5; - pipeline_dffe[3]~19 0xc0 1.81688e+06 0.984375; - pipeline_dffe[4] 0xc0 7.68002e+06 0.5; - pipeline_dffe[4]~20 0xc0 8.35221e+06 0.5; - pipeline_dffe[4]~21 0xc0 7.89799e+06 0.0078125; - pipeline_dffe[5] 0xc0 7.68002e+06 0.5; - pipeline_dffe[5]~22 0xc0 1.151e+07 0.5; - pipeline_dffe[5]~23 0xc0 1.97543e+06 0.996094; - pipeline_dffe[6] 0xc0 7.68002e+06 0.5; - pipeline_dffe[6]~24 0xc0 8.60797e+06 0.5; - pipeline_dffe[6]~25 0xc0 8.11411e+06 0.00195313; - pipeline_dffe[7] 0xc0 7.68002e+06 0.5; - pipeline_dffe[7]~26 0xc0 1.17071e+07 0.5; - pipeline_dffe[7]~27 0xc0 2.02859e+06 0.999023; - pipeline_dffe[8] 0xc0 7.68002e+06 0.5; - pipeline_dffe[8]~28 0xc0 8.67933e+06 0.5; - pipeline_dffe[8]~29 0xc0 8.17218e+06 0.000488281; - pipeline_dffe[9] 0xc0 7.68002e+06 0.5; - pipeline_dffe[9]~30 0xc0 1.17586e+07 0.5; - pipeline_dffe[9]~31 0xc0 2.04305e+06 0.999756; - pipeline_dffe[10] 0xc0 7.68002e+06 0.5; - pipeline_dffe[10]~32 0xc0 8.6978e+06 0.5; - pipeline_dffe[10]~33 0xc0 8.18703e+06 0.00012207; - pipeline_dffe[11] 0xc0 7.68002e+06 0.5; - pipeline_dffe[11]~34 0xc0 1.17717e+07 0.5; - asj_nco_mady_cen:m0; - lpm_mult:Mult0; - mult_t5t:auto_generated; - mac_mult1 0xc0 1.92e+06 0.5; - mac_mult1~0 0xc0 0 0; - mac_mult1~1 0xc0 0 0; - mac_mult1~2 0xc0 0 0; - mac_mult1~3 0xc0 0 0; - mac_mult1~4 0xc0 0 0; - mac_mult1~5 0xc0 0 0; - mac_mult1~6 0xc0 0 0; - mac_mult1~7 0xc0 0 0; - mac_mult1~8 0xc0 0 0; - mac_mult1~9 0xc0 0 0; - mac_mult1~10 0xc0 0 0; - mac_mult1~11 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT2 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT3 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT4 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT5 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT6 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT7 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT8 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT9 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT10 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT11 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT12 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT13 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT14 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT15 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT16 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT17 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT18 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT19 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT20 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT21 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT22 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT23 0xc0 1.92e+06 0.5; - mac_out2 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT1 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT2 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT3 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT4 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT5 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT6 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT7 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT8 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT9 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT10 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT11 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT12 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT13 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT14 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT15 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT16 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT17 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT18 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT19 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT20 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT21 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT22 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT23 0xc0 1.92e+06 0.5; - lpm_mult:Mult1; - mult_t5t:auto_generated; - mac_mult1 0xc0 1.92e+06 0.5; - mac_mult1~0 0xc0 0 0; - mac_mult1~1 0xc0 0 0; - mac_mult1~2 0xc0 0 0; - mac_mult1~3 0xc0 0 0; - mac_mult1~4 0xc0 0 0; - mac_mult1~5 0xc0 0 0; - mac_mult1~6 0xc0 0 0; - mac_mult1~7 0xc0 0 0; - mac_mult1~8 0xc0 0 0; - mac_mult1~9 0xc0 0 0; - mac_mult1~10 0xc0 0 0; - mac_mult1~11 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT2 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT3 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT4 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT5 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT6 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT7 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT8 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT9 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT10 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT11 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT12 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT13 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT14 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT15 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT16 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT17 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT18 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT19 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT20 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT21 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT22 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT23 0xc0 1.92e+06 0.5; - mac_out2 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT1 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT2 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT3 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT4 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT5 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT6 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT7 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT8 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT9 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT10 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT11 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT12 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT13 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT14 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT15 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT16 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT17 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT18 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT19 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT20 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT21 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT22 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT23 0xc0 1.92e+06 0.5; - out[11] 0xc0 7.68002e+06 0.5; - out[11]~14 0xc0 990003 0.25; - out[11]~16 0xc0 758938 0.625; - out[11]~18 0xc0 1.41018e+06 0.4375; - out[11]~20 0xc0 1.07323e+06 0.53125; - out[11]~22 0xc0 1.20496e+06 0.484375; - out[11]~24 0xc0 1.12567e+06 0.507813; - out[11]~26 0xc0 1.16142e+06 0.496094; - out[11]~28 0xc0 1.14251e+06 0.501953; - out[11]~30 0xc0 1.1517e+06 0.499023; - out[11]~32 0xc0 1.14704e+06 0.500488; - out[11]~34 0xc0 1.14935e+06 0.499756; - out[11]~35 0xc0 1.27734e+06 0.5; - out[11]~36 0xc0 1.14819e+06 0.500122; - out[12] 0xc0 7.68002e+06 0.5; - out[12]~37 0xc0 1.27705e+06 0.5; - out[12]~38 0xc0 1.14877e+06 0.499939; - out[13] 0xc0 7.68002e+06 0.5; - out[13]~39 0xc0 1.27719e+06 0.5; - out[13]~40 0xc0 1.14848e+06 0.500031; - out[14] 0xc0 7.68002e+06 0.5; - out[14]~41 0xc0 1.27712e+06 0.5; - out[14]~42 0xc0 1.14862e+06 0.499985; - out[15] 0xc0 7.68002e+06 0.5; - out[15]~43 0xc0 1.27716e+06 0.5; - out[15]~44 0xc0 1.14855e+06 0.500008; - out[16] 0xc0 7.68002e+06 0.5; - out[16]~45 0xc0 1.27714e+06 0.5; - out[16]~46 0xc0 1.14859e+06 0.499996; - out[17] 0xc0 7.68002e+06 0.5; - out[17]~47 0xc0 1.27715e+06 0.5; - out[17]~48 0xc0 1.14857e+06 0.500002; - out[18] 0xc0 7.68002e+06 0.5; - out[18]~49 0xc0 1.27714e+06 0.5; - out[18]~50 0xc0 1.14858e+06 0.499999; - out[19] 0xc0 7.68002e+06 0.5; - out[19]~51 0xc0 1.27715e+06 0.5; - out[19]~52 0xc0 1.14857e+06 0.5; - out[20] 0xc0 7.68002e+06 0.5; - out[20]~53 0xc0 1.27715e+06 0.5; - out[20]~54 0xc0 1.14858e+06 0.5; - out[21] 0xc0 7.68002e+06 0.5; - out[21]~55 0xc0 1.27715e+06 0.5; - out[21]~56 0xc0 1.14857e+06 0.5; - out[22] 0xc0 7.68002e+06 0.5; - out[22]~57 0xc0 1.27715e+06 0.5; - out[22]~58 0xc0 1.14857e+06 0.5; - out[23] 0xc0 7.68002e+06 0.5; - out[23]~59 0xc0 1.72715e+06 0.5; - asj_nco_madx_cen:m1; - lpm_mult:Mult0; - mult_t5t:auto_generated; - mac_mult1 0xc0 1.92e+06 0.5; - mac_mult1~0 0xc0 0 0; - mac_mult1~1 0xc0 0 0; - mac_mult1~2 0xc0 0 0; - mac_mult1~3 0xc0 0 0; - mac_mult1~4 0xc0 0 0; - mac_mult1~5 0xc0 0 0; - mac_mult1~6 0xc0 0 0; - mac_mult1~7 0xc0 0 0; - mac_mult1~8 0xc0 0 0; - mac_mult1~9 0xc0 0 0; - mac_mult1~10 0xc0 0 0; - mac_mult1~11 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT2 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT3 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT4 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT5 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT6 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT7 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT8 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT9 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT10 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT11 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT12 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT13 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT14 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT15 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT16 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT17 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT18 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT19 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT20 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT21 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT22 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT23 0xc0 1.92e+06 0.5; - mac_out2 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT1 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT2 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT3 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT4 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT5 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT6 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT7 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT8 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT9 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT10 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT11 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT12 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT13 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT14 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT15 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT16 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT17 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT18 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT19 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT20 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT21 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT22 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT23 0xc0 1.92e+06 0.5; - lpm_mult:Mult1; - mult_t5t:auto_generated; - mac_mult1 0xc0 1.92e+06 0.5; - mac_mult1~0 0xc0 0 0; - mac_mult1~1 0xc0 0 0; - mac_mult1~2 0xc0 0 0; - mac_mult1~3 0xc0 0 0; - mac_mult1~4 0xc0 0 0; - mac_mult1~5 0xc0 0 0; - mac_mult1~6 0xc0 0 0; - mac_mult1~7 0xc0 0 0; - mac_mult1~8 0xc0 0 0; - mac_mult1~9 0xc0 0 0; - mac_mult1~10 0xc0 0 0; - mac_mult1~11 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT2 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT3 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT4 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT5 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT6 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT7 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT8 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT9 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT10 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT11 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT12 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT13 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT14 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT15 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT16 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT17 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT18 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT19 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT20 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT21 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT22 0xc0 1.92e+06 0.5; - mac_mult1~DATAOUT23 0xc0 1.92e+06 0.5; - mac_out2 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT1 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT2 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT3 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT4 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT5 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT6 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT7 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT8 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT9 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT10 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT11 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT12 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT13 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT14 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT15 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT16 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT17 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT18 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT19 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT20 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT21 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT22 0xc0 1.92e+06 0.5; - mac_out2~DATAOUT23 0xc0 1.92e+06 0.5; - out[11] 0xc0 7.68002e+06 0.5; - out[11]~14 0xc0 990003 0.75; - out[11]~16 0xc0 758938 0.375; - out[11]~18 0xc0 915182 0.5625; - out[11]~20 0xc0 1.25885e+06 0.46875; - out[11]~22 0xc0 1.10441e+06 0.515625; - out[11]~24 0xc0 1.17497e+06 0.492188; - out[11]~26 0xc0 1.13665e+06 0.503906; - out[11]~28 0xc0 1.15488e+06 0.498047; - out[11]~30 0xc0 1.14551e+06 0.500977; - out[11]~32 0xc0 1.15013e+06 0.499512; - out[11]~34 0xc0 1.1478e+06 0.500244; - out[11]~35 0xc0 1.27695e+06 0.5; - out[11]~36 0xc0 1.14896e+06 0.499878; - out[12] 0xc0 7.68002e+06 0.5; - out[12]~37 0xc0 1.27724e+06 0.5; - out[12]~38 0xc0 1.14838e+06 0.500061; - out[13] 0xc0 7.68002e+06 0.5; - out[13]~39 0xc0 1.2771e+06 0.5; - out[13]~40 0xc0 1.14867e+06 0.499969; - out[14] 0xc0 7.68002e+06 0.5; - out[14]~41 0xc0 1.27717e+06 0.5; - out[14]~42 0xc0 1.14853e+06 0.500015; - out[15] 0xc0 7.68002e+06 0.5; - out[15]~43 0xc0 1.27713e+06 0.5; - out[15]~44 0xc0 1.1486e+06 0.499992; - out[16] 0xc0 7.68002e+06 0.5; - out[16]~45 0xc0 1.27715e+06 0.5; - out[16]~46 0xc0 1.14856e+06 0.500004; - out[17] 0xc0 7.68002e+06 0.5; - out[17]~47 0xc0 1.27714e+06 0.5; - out[17]~48 0xc0 1.14858e+06 0.499998; - out[18] 0xc0 7.68002e+06 0.5; - out[18]~49 0xc0 1.27715e+06 0.5; - out[18]~50 0xc0 1.14857e+06 0.500001; - out[19] 0xc0 7.68002e+06 0.5; - out[19]~51 0xc0 1.27715e+06 0.5; - out[19]~52 0xc0 1.14858e+06 0.5; - out[20] 0xc0 7.68002e+06 0.5; - out[20]~53 0xc0 1.27715e+06 0.5; - out[20]~54 0xc0 1.14857e+06 0.5; - out[21] 0xc0 7.68002e+06 0.5; - out[21]~55 0xc0 1.27715e+06 0.5; - out[21]~56 0xc0 1.14857e+06 0.5; - out[22] 0xc0 7.68002e+06 0.5; - out[22]~57 0xc0 1.27715e+06 0.5; - out[22]~58 0xc0 1.14857e+06 0.5; - out[23] 0xc0 7.68002e+06 0.5; - out[23]~59 0xc0 1.72715e+06 0.5; - asj_altqmcpipe:ux000; - lpm_add_sub:acc; - add_sub_u4i:auto_generated; - pipeline_dffe[0] 0xc0 7.68002e+06 0.5; - pipeline_dffe[0]~22 0xc0 7.68002e+06 0.5; - pipeline_dffe[0]~23 0xc0 4.32001e+06 0.25; - pipeline_dffe[1] 0xc0 7.68002e+06 0.5; - pipeline_dffe[1]~24 0xc0 6.48002e+06 0.5; - pipeline_dffe[1]~25 0xc0 3.57751e+06 0.625; - pipeline_dffe[2] 0xc0 7.68002e+06 0.5; - pipeline_dffe[2]~26 0xc0 5.48439e+06 0.5; - pipeline_dffe[2]~27 0xc0 6.3722e+06 0.4375; - pipeline_dffe[3] 0xc0 7.68002e+06 0.5; - pipeline_dffe[3]~28 0xc0 5.98056e+06 0.5; - pipeline_dffe[3]~29 0xc0 4.88779e+06 0.53125; - pipeline_dffe[4] 0xc0 7.68002e+06 0.5; - pipeline_dffe[4]~30 0xc0 5.55883e+06 0.5; - pipeline_dffe[4]~31 0xc0 5.4588e+06 0.484375; - pipeline_dffe[5] 0xc0 7.68002e+06 0.5; - pipeline_dffe[5]~32 0xc0 5.68893e+06 0.5; - pipeline_dffe[5]~33 0xc0 5.11181e+06 0.507813; - pipeline_dffe[6] 0xc0 7.68002e+06 0.5; - pipeline_dffe[6]~34 0xc0 5.59902e+06 0.5; - pipeline_dffe[6]~35 0xc0 5.2676e+06 0.496094; - pipeline_dffe[7] 0xc0 7.68002e+06 0.5; - pipeline_dffe[7]~36 0xc0 5.63718e+06 0.5; - pipeline_dffe[7]~37 0xc0 5.18499e+06 0.501953; - pipeline_dffe[8] 0xc0 7.68002e+06 0.5; - pipeline_dffe[8]~38 0xc0 5.61632e+06 0.5; - pipeline_dffe[8]~39 0xc0 5.22508e+06 0.499023; - pipeline_dffe[9] 0xc0 7.68002e+06 0.5; - pipeline_dffe[9]~40 0xc0 5.6263e+06 0.5; - pipeline_dffe[9]~41 0xc0 5.20473e+06 0.500488; - pipeline_dffe[10] 0xc0 7.68002e+06 0.5; - pipeline_dffe[10]~42 0xc0 5.6212e+06 0.5; - pipeline_dffe[10]~43 0xc0 5.21483e+06 0.499756; - pipeline_dffe[11] 0xc0 7.68002e+06 0.5; - pipeline_dffe[11]~44 0xc0 5.62372e+06 0.5; - pipeline_dffe[11]~45 0xc0 5.20976e+06 0.500122; - pipeline_dffe[12] 0xc0 7.68002e+06 0.5; - pipeline_dffe[12]~46 0xc0 5.62245e+06 0.5; - pipeline_dffe[12]~47 0xc0 5.21229e+06 0.499939; - pipeline_dffe[13] 0xc0 7.68002e+06 0.5; - pipeline_dffe[13]~48 0xc0 5.62308e+06 0.5; - pipeline_dffe[13]~49 0xc0 5.21102e+06 0.500031; - pipeline_dffe[14] 0xc0 7.68002e+06 0.5; - pipeline_dffe[14]~50 0xc0 5.62277e+06 0.5; - pipeline_dffe[14]~51 0xc0 5.21165e+06 0.499985; - pipeline_dffe[15] 0xc0 7.68002e+06 0.5; - pipeline_dffe[15]~52 0xc0 5.62292e+06 0.5; - pipeline_dffe[15]~53 0xc0 5.21134e+06 0.500008; - pipeline_dffe[16] 0xc0 7.68002e+06 0.5; - pipeline_dffe[16]~54 0xc0 5.62285e+06 0.5; - pipeline_dffe[16]~55 0xc0 5.21149e+06 0.499996; - pipeline_dffe[17] 0xc0 7.68002e+06 0.5; - pipeline_dffe[17]~56 0xc0 5.62289e+06 0.5; - pipeline_dffe[17]~57 0xc0 5.21142e+06 0.500002; - pipeline_dffe[18] 0xc0 7.68002e+06 0.5; - pipeline_dffe[18]~58 0xc0 5.62286e+06 0.5; - pipeline_dffe[18]~59 0xc0 5.21146e+06 0.499999; - pipeline_dffe[19] 0xc0 7.68002e+06 0.5; - pipeline_dffe[19]~60 0xc0 5.62287e+06 0.5; - pipeline_dffe[19]~61 0xc0 5.21144e+06 0.5; - pipeline_dffe[20] 0xc0 7.68002e+06 0.5; - pipeline_dffe[20]~62 0xc0 5.62287e+06 0.5; - pipeline_dffe[20]~63 0xc0 5.21145e+06 0.5; - pipeline_dffe[21] 0xc0 7.68002e+06 0.5; - pipeline_dffe[21]~64 0xc0 5.62287e+06 0.5; - phi_int_arr_reg[0] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[1] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[2] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[3] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[4] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[5] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[6] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[7] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[8] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[9] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[10] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[11] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[12] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[13] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[14] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[15] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[16] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[17] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[18] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[19] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[20] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg[21] 0xc0 7.68002e+06 0.5; - phi_int_arr_reg~0 0xc0 4.32001e+06 0.75; - phi_int_arr_reg~1 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~2 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~3 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~4 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~5 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~6 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~7 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~8 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~9 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~10 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~11 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~12 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~13 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~14 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~15 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~16 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~17 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~18 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~19 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~20 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~21 0xc0 4.32001e+06 0.25; - phi_int_arr_reg~22 0xc0 4.32001e+06 0.25; - asj_gam_dp:ux008; - rom_add_cc_temp[0] 0xc0 7.68002e+06 0.5; - rom_add_cc_temp[1] 0xc0 7.68002e+06 0.5; - rom_add_cc_temp[2] 0xc0 7.68002e+06 0.5; - rom_add_cc_temp[3] 0xc0 7.68002e+06 0.5; - rom_add_cc_temp[4] 0xc0 7.68002e+06 0.5; - rom_add_cc_temp[5] 0xc0 7.68002e+06 0.5; - rom_add_cc_temp[6] 0xc0 7.68002e+06 0.5; - rom_add_cc_temp[7] 0xc0 7.68002e+06 0.5; - rom_add_cc_temp[8] 0xc0 7.68002e+06 0.5; - rom_add_cc_temp[9] 0xc0 7.68002e+06 0.5; - rom_add_cc_temp[9]~11 0xc0 7.68002e+06 0.5; - rom_add_cc_temp[9]~12 0xc0 7.68002e+06 0.5; - rom_add_cc_temp[10] 0xc0 7.68002e+06 0.5; - rom_add_cc_temp[10]~13 0xc0 7.68002e+06 0.5; - rom_add_cc_temp~2 0xc0 4.32001e+06 0.25; - rom_add_cc_temp~3 0xc0 4.32001e+06 0.25; - rom_add_cc_temp~4 0xc0 4.32001e+06 0.25; - rom_add_cc_temp~5 0xc0 4.32001e+06 0.25; - rom_add_cc_temp~6 0xc0 4.32001e+06 0.25; - rom_add_cc_temp~7 0xc0 4.32001e+06 0.25; - rom_add_cc_temp~8 0xc0 4.32001e+06 0.25; - rom_add_cc_temp~9 0xc0 4.32001e+06 0.25; - rom_add_cc_temp~10 0xc0 4.32001e+06 0.25; - rom_add_cs[9] 0xc0 7.68002e+06 0.5; - rom_add_cs[10] 0xc0 7.68002e+06 0.5; - rom_add_cs~0 0xc0 4.32001e+06 0.25; - rom_add_cs~1 0xc0 4.32001e+06 0.25; - rom_add_f[0] 0xc0 7.68002e+06 0.5; - rom_add_f[1] 0xc0 7.68002e+06 0.5; - rom_add_f[2] 0xc0 7.68002e+06 0.5; - rom_add_f[3] 0xc0 7.68002e+06 0.5; - rom_add_f[4] 0xc0 7.68002e+06 0.5; - rom_add_f[5] 0xc0 7.68002e+06 0.5; - rom_add_f[6] 0xc0 7.68002e+06 0.5; - rom_add_f[7] 0xc0 7.68002e+06 0.5; - rom_add_f[8] 0xc0 7.68002e+06 0.5; - rom_add_f[9] 0xc0 7.68002e+06 0.5; - rom_add_f[10] 0xc0 7.68002e+06 0.5; - rom_add_f~0 0xc0 4.32001e+06 0.25; - rom_add_f~1 0xc0 4.32001e+06 0.25; - rom_add_f~2 0xc0 4.32001e+06 0.25; - rom_add_f~3 0xc0 4.32001e+06 0.25; - rom_add_f~4 0xc0 4.32001e+06 0.25; - rom_add_f~5 0xc0 4.32001e+06 0.25; - rom_add_f~6 0xc0 4.32001e+06 0.25; - rom_add_f~7 0xc0 4.32001e+06 0.25; - rom_add_f~8 0xc0 4.32001e+06 0.25; - rom_add_f~9 0xc0 4.32001e+06 0.25; - rom_add_f~10 0xc0 4.32001e+06 0.25; - asj_nco_as_m_cen:ux0122; - altsyncram:altsyncram_component0; - altsyncram_fu91:auto_generated; - q_a[0] 0xc0 7.68002e+06 0.5; - q_a[1] 0xc0 7.68002e+06 0.5; - q_a[2] 0xc0 7.68002e+06 0.5; - q_a[3] 0xc0 7.68002e+06 0.5; - q_a[4] 0xc0 7.68002e+06 0.5; - q_a[5] 0xc0 7.68002e+06 0.5; - q_a[6] 0xc0 7.68002e+06 0.5; - q_a[7] 0xc0 7.68002e+06 0.5; - q_a[8] 0xc0 7.68002e+06 0.5; - q_a[9] 0xc0 7.68002e+06 0.5; - q_a[10] 0xc0 7.68002e+06 0.5; - q_a[11] 0xc0 7.68002e+06 0.5; - asj_nco_as_m_cen:ux0123; - altsyncram:altsyncram_component0; - altsyncram_au91:auto_generated; - q_a[0] 0xc0 7.68002e+06 0.5; - q_a[1] 0xc0 7.68002e+06 0.5; - q_a[2] 0xc0 7.68002e+06 0.5; - q_a[3] 0xc0 7.68002e+06 0.5; - q_a[4] 0xc0 7.68002e+06 0.5; - q_a[5] 0xc0 7.68002e+06 0.5; - q_a[6] 0xc0 7.68002e+06 0.5; - q_a[7] 0xc0 7.68002e+06 0.5; - q_a[8] 0xc0 7.68002e+06 0.5; - q_a[9] 0xc0 7.68002e+06 0.5; - q_a[10] 0xc0 7.68002e+06 0.5; - q_a[11] 0xc0 7.68002e+06 0.5; - asj_nco_as_m_dp_cen:ux0220; - altsyncram:altsyncram_component; - altsyncram_h982:auto_generated; - q_a[0] 0xc0 7.68002e+06 0.5; - q_a[1] 0xc0 7.68002e+06 0.5; - q_a[2] 0xc0 7.68002e+06 0.5; - q_a[3] 0xc0 7.68002e+06 0.5; - q_a[4] 0xc0 7.68002e+06 0.5; - q_a[5] 0xc0 7.68002e+06 0.5; - q_a[6] 0xc0 7.68002e+06 0.5; - q_a[7] 0xc0 7.68002e+06 0.5; - q_a[8] 0xc0 7.68002e+06 0.5; - q_a[9] 0xc0 7.68002e+06 0.5; - q_a[10] 0xc0 7.68002e+06 0.5; - q_a[11] 0xc0 7.68002e+06 0.5; - q_b[0] 0xc0 7.68002e+06 0.5; - q_b[1] 0xc0 7.68002e+06 0.5; - q_b[2] 0xc0 7.68002e+06 0.5; - q_b[3] 0xc0 7.68002e+06 0.5; - q_b[4] 0xc0 7.68002e+06 0.5; - q_b[5] 0xc0 7.68002e+06 0.5; - q_b[6] 0xc0 7.68002e+06 0.5; - q_b[7] 0xc0 7.68002e+06 0.5; - q_b[8] 0xc0 7.68002e+06 0.5; - q_b[9] 0xc0 7.68002e+06 0.5; - q_b[10] 0xc0 7.68002e+06 0.5; - q_b[11] 0xc0 7.68002e+06 0.5; - asj_nco_isdr:ux710isdr; - always0~0 0xc0 691877 0.0625; - data_ready 0xc0 7.68002e+06 0.5; - data_ready~0 0xc0 6.98873e+06 0.515625; - lpm_counter:lpm_counter_component; - cntr_asi:auto_generated; - counter_comb_bita0 0xc0 7.68002e+06 0.5; - counter_comb_bita0~COUT 0xc0 7.68002e+06 0.5; - counter_comb_bita1 0xc0 7.68002e+06 0.5; - counter_comb_bita1~COUT 0xc0 4.32001e+06 0.75; - counter_comb_bita2 0xc0 6.96002e+06 0.5; - counter_comb_bita2~COUT 0xc0 5.88002e+06 0.125; - counter_comb_bita3 0xc0 8.94002e+06 0.5; - counter_reg_bit[0] 0xc0 7.68002e+06 0.5; - counter_reg_bit[1] 0xc0 7.68002e+06 0.5; - counter_reg_bit[2] 0xc0 7.68002e+06 0.5; - counter_reg_bit[3] 0xc0 7.68002e+06 0.5; - STM32_CLK 0xc 5e+07 0.5; - STM32_CLK~input 0xc0 5e+07 0.5; - STM32_DATA_BUS[0]~result 0xc0 1 0.5; - STM32_DATA_BUS[0]~input 0xc0 1 0.5; - STM32_DATA_BUS[0]~output 0xc0 1.5625e+06 0.5; - STM32_DATA_BUS[1]~result 0x30 2e+07 0.5; - STM32_DATA_BUS[1]~input 0xc0 2e+07 0.5; - STM32_DATA_BUS[1]~output 0xc0 1.5625e+06 0.5; - STM32_DATA_BUS[2]~result 0x30 2e+07 0.5; - STM32_DATA_BUS[2]~input 0xc0 2e+07 0.5; - STM32_DATA_BUS[2]~output 0xc0 1.5625e+06 0.5; - STM32_DATA_BUS[3]~result 0x30 2e+07 0.5; - STM32_DATA_BUS[3]~input 0xc0 2e+07 0.5; - STM32_DATA_BUS[3]~output 0xc0 1.5625e+06 0.5; - STM32_DATA_BUS[4]~result 0x30 2e+07 0.5; - STM32_DATA_BUS[4]~input 0xc0 2e+07 0.5; - STM32_DATA_BUS[4]~output 0xc0 1.5625e+06 0.5; - STM32_DATA_BUS[5]~result 0x30 2e+07 0.5; - STM32_DATA_BUS[5]~input 0xc0 2e+07 0.5; - STM32_DATA_BUS[5]~output 0xc0 1.5625e+06 0.5; - STM32_DATA_BUS[6]~result 0x30 2e+07 0.5; - STM32_DATA_BUS[6]~input 0xc0 2e+07 0.5; - STM32_DATA_BUS[6]~output 0xc0 1.5625e+06 0.5; - STM32_DATA_BUS[7]~result 0x30 2e+07 0.5; - STM32_DATA_BUS[7]~input 0xc0 2e+07 0.5; - STM32_DATA_BUS[7]~output 0xc0 1.5625e+06 0.5; - stm32_interface:STM32_INTERFACE; - ADC_MAX[0] 0xc0 7.68002e+06 0.5; - ADC_MAX[0]~20 0xc0 4.32001e+06 0.25; - ADC_MAX[0]~21 0xc0 5.67001e+06 0.375; - ADC_MAX[1] 0xc0 7.68002e+06 0.5; - ADC_MAX[1]~22 0xc0 4.32001e+06 0.25; - ADC_MAX[1]~23 0xc0 3.72912e+06 0.4375; - ADC_MAX[2] 0xc0 7.68002e+06 0.5; - ADC_MAX[2]~24 0xc0 4.32001e+06 0.25; - ADC_MAX[2]~25 0xc0 2.49097e+06 0.65625; - ADC_MAX[3] 0xc0 7.68002e+06 0.5; - ADC_MAX[3]~26 0xc0 4.32001e+06 0.25; - ADC_MAX[3]~27 0xc0 2.01031e+06 0.296875; - ADC_MAX[4] 0xc0 7.68002e+06 0.5; - ADC_MAX[4]~28 0xc0 4.32001e+06 0.75; - ADC_MAX[4]~29 0xc0 3.4101e+06 0.476563; - ADC_MAX[5] 0xc0 7.68002e+06 0.5; - ADC_MAX[5]~30 0xc0 4.32001e+06 0.75; - ADC_MAX[5]~31 0xc0 4.51216e+06 0.636719; - ADC_MAX[6] 0xc0 7.68002e+06 0.5; - ADC_MAX[6]~32 0xc0 4.32001e+06 0.25; - ADC_MAX[6]~33 0xc0 4.17437e+06 0.556641; - ADC_MAX[7] 0xc0 7.68002e+06 0.5; - ADC_MAX[7]~34 0xc0 4.32001e+06 0.25; - ADC_MAX[7]~35 0xc0 2.60694e+06 0.34668; - ADC_MAX[8] 0xc0 7.68002e+06 0.5; - ADC_MAX[8]~40 0xc0 4.32001e+06 0.25; - ADC_MAX[8]~41 0xc0 2.04046e+06 0.70166; - ADC_MAX[9] 0xc0 7.68002e+06 0.5; - ADC_MAX[9]~42 0xc0 4.32001e+06 0.25; - ADC_MAX[9]~43 0xc0 2.88552e+06 0.27417; - ADC_MAX[10] 0xc0 7.68002e+06 0.5; - ADC_MAX[10]~44 0xc0 4.32001e+06 0.25; - ADC_MAX[10]~45 0xc0 2.02997e+06 0.737915; - ADC_MAX[11] 0xc0 7.68002e+06 0.5; - ADC_MAX[11]~46 0xc0 4.32001e+06 0.75; - ADC_MAX[11]~47 0xc0 2.38385e+06 0.256042; - ADC_MAX~12 0xc0 4.32001e+06 0.25; - ADC_MAX~13 0xc0 4.32001e+06 0.25; - ADC_MAX~14 0xc0 4.32001e+06 0.75; - ADC_MAX~15 0xc0 4.32001e+06 0.75; - ADC_MAX~16 0xc0 4.32001e+06 0.25; - ADC_MAX~17 0xc0 4.32001e+06 0.25; - ADC_MAX~18 0xc0 4.32001e+06 0.25; - ADC_MAX~19 0xc0 4.32001e+06 0.25; - ADC_MAX~36 0xc0 4.32001e+06 0.75; - ADC_MAX~37 0xc0 4.32001e+06 0.25; - ADC_MAX~38 0xc0 4.32001e+06 0.25; - ADC_MAX~39 0xc0 4.32001e+06 0.25; - ADC_MINMAX_RESET 0xc0 3.125e+06 0.5; - ADC_MINMAX_RESET~0 0xc0 1.38336e+06 0.500488; - ADC_MIN[0] 0xc0 7.68002e+06 0.5; - ADC_MIN[0]~20 0xc0 4.32001e+06 0.25; - ADC_MIN[0]~21 0xc0 1.83e+06 0.125; - ADC_MIN[1] 0xc0 7.68002e+06 0.5; - ADC_MIN[1]~22 0xc0 4.32001e+06 0.25; - ADC_MIN[1]~23 0xc0 1.89537e+06 0.8125; - ADC_MIN[2] 0xc0 7.68002e+06 0.5; - ADC_MIN[2]~24 0xc0 4.32001e+06 0.25; - ADC_MIN[2]~25 0xc0 1.82759e+06 0.21875; - ADC_MIN[3] 0xc0 7.68002e+06 0.5; - ADC_MIN[3]~26 0xc0 4.32001e+06 0.25; - ADC_MIN[3]~27 0xc0 1.79341e+06 0.765625; - ADC_MIN[4] 0xc0 7.68002e+06 0.5; - ADC_MIN[4]~28 0xc0 4.32001e+06 0.75; - ADC_MIN[4]~29 0xc0 3.82175e+06 0.492188; - ADC_MIN[5] 0xc0 7.68002e+06 0.5; - ADC_MIN[5]~30 0xc0 4.32001e+06 0.25; - ADC_MIN[5]~31 0xc0 4.5117e+06 0.628906; - ADC_MIN[6] 0xc0 7.68002e+06 0.5; - ADC_MIN[6]~32 0xc0 4.32001e+06 0.75; - ADC_MIN[6]~33 0xc0 4.15824e+06 0.560547; - ADC_MIN[7] 0xc0 7.68002e+06 0.5; - ADC_MIN[7]~34 0xc0 4.32001e+06 0.75; - ADC_MIN[7]~35 0xc0 2.5918e+06 0.344727; - ADC_MIN[8] 0xc0 7.68002e+06 0.5; - ADC_MIN[8]~40 0xc0 4.32001e+06 0.75; - ADC_MIN[8]~41 0xc0 2.03413e+06 0.702637; - ADC_MIN[9] 0xc0 7.68002e+06 0.5; - ADC_MIN[9]~42 0xc0 4.32001e+06 0.75; - ADC_MIN[9]~43 0xc0 2.8864e+06 0.273682; - ADC_MIN[10] 0xc0 7.68002e+06 0.5; - ADC_MIN[10]~44 0xc0 4.32001e+06 0.75; - ADC_MIN[10]~45 0xc0 2.02995e+06 0.738159; - ADC_MIN[11] 0xc0 7.68002e+06 0.5; - ADC_MIN[11]~46 0xc0 4.32001e+06 0.25; - ADC_MIN[11]~47 0xc0 2.38288e+06 0.25592; - ADC_MIN~12 0xc0 4.32001e+06 0.75; - ADC_MIN~13 0xc0 4.32001e+06 0.75; - ADC_MIN~14 0xc0 4.32001e+06 0.25; - ADC_MIN~15 0xc0 4.32001e+06 0.75; - ADC_MIN~16 0xc0 4.32001e+06 0.25; - ADC_MIN~17 0xc0 4.32001e+06 0.25; - ADC_MIN~18 0xc0 4.32001e+06 0.25; - ADC_MIN~19 0xc0 4.32001e+06 0.25; - ADC_MIN~36 0xc0 4.32001e+06 0.25; - ADC_MIN~37 0xc0 4.32001e+06 0.75; - ADC_MIN~38 0xc0 4.32001e+06 0.75; - ADC_MIN~39 0xc0 4.32001e+06 0.75; - ATT_1 0xc0 3.125e+06 0.5; - ATT_2 0xc0 3.125e+06 0.5; - ATT_4 0xc0 3.125e+06 0.5; - ATT_4~feeder 0xc0 2e+07 0.5; - ATT_05 0xc0 3.125e+06 0.5; - ATT_05~feeder 0xc0 2e+07 0.5; - ATT_8 0xc0 3.125e+06 0.5; - ATT_8~feeder 0xc0 2e+07 0.5; - ATT_16 0xc0 3.125e+06 0.5; - ATT_16~feeder 0xc0 2e+07 0.5; - BPF_A 0xc0 3.125e+06 0.5; - BPF_A~0 0xc0 2.12891e+06 0.125; - BPF_A~1 0xc0 1306.64 0.000488281; - BPF_B 0xc0 3.125e+06 0.5; - BPF_B~feeder 0xc0 2e+07 0.5; - BPF_OE1 0xc0 3.125e+06 0.5; - BPF_OE2 0xc0 3.125e+06 0.5; - BPF_OE2~feeder 0xc0 2e+07 0.5; - BUFFER_RX_I[0][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[0][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][6]~feeder 0xc0 1.63473e+06 0.204102; - BUFFER_RX_I[1][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][7]~feeder 0xc0 1.62892e+06 0.202209; - BUFFER_RX_I[1][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][11]~feeder 0xc0 1.609e+06 0.192406; - BUFFER_RX_I[1][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][12]~feeder 0xc0 1.61979e+06 0.190918; - BUFFER_RX_I[1][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[1][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[2][15]~feeder 0xc0 532322 0.166748; - BUFFER_RX_I[3][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[3][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[4][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][0]~feeder 0xc0 606799 0.165039; - BUFFER_RX_I[5][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][6]~feeder 0xc0 1.63473e+06 0.204102; - BUFFER_RX_I[5][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][10]~feeder 0xc0 1.61718e+06 0.194885; - BUFFER_RX_I[5][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[5][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][2]~feeder 0xc0 1.66256e+06 0.210449; - BUFFER_RX_I[6][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][5]~feeder 0xc0 1.62784e+06 0.20385; - BUFFER_RX_I[6][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][7]~feeder 0xc0 1.62892e+06 0.202209; - BUFFER_RX_I[6][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][8]~feeder 0xc0 1.62651e+06 0.200195; - BUFFER_RX_I[6][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][11]~feeder 0xc0 1.609e+06 0.192406; - BUFFER_RX_I[6][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][13]~feeder 0xc0 1.64325e+06 0.18985; - BUFFER_RX_I[6][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[6][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_I[7][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[0][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][3]~feeder 0xc0 1.63122e+06 0.206322; - BUFFER_RX_Q[1][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][4]~feeder 0xc0 1.6299e+06 0.205139; - BUFFER_RX_Q[1][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][9]~feeder 0xc0 1.61758e+06 0.197258; - BUFFER_RX_Q[1][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][10]~feeder 0xc0 1.61718e+06 0.194885; - BUFFER_RX_Q[1][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][11]~feeder 0xc0 1.609e+06 0.192406; - BUFFER_RX_Q[1][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][12]~feeder 0xc0 1.61979e+06 0.190918; - BUFFER_RX_Q[1][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][13]~feeder 0xc0 1.64325e+06 0.18985; - BUFFER_RX_Q[1][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[1][15]~feeder 0xc0 532322 0.166748; - BUFFER_RX_Q[2][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][3]~feeder 0xc0 1.63122e+06 0.206322; - BUFFER_RX_Q[2][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][10]~feeder 0xc0 1.61718e+06 0.194885; - BUFFER_RX_Q[2][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[2][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[3][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[4][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][1]~feeder 0xc0 1.67933e+06 0.211731; - BUFFER_RX_Q[5][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][10]~feeder 0xc0 1.61718e+06 0.194885; - BUFFER_RX_Q[5][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[5][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][6]~feeder 0xc0 1.63473e+06 0.204102; - BUFFER_RX_Q[6][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][11]~feeder 0xc0 1.609e+06 0.192406; - BUFFER_RX_Q[6][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[6][15]~feeder 0xc0 532322 0.166748; - BUFFER_RX_Q[7][0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_Q[7][15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[0] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[0]~16 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[0]~17 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[1] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[1]~18 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[1]~19 0xc0 4.32001e+06 0.75; - BUFFER_RX_head[2] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[2]~20 0xc0 6.96002e+06 0.5; - BUFFER_RX_head[2]~21 0xc0 5.88002e+06 0.125; - BUFFER_RX_head[3] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[3]~22 0xc0 8.94002e+06 0.5; - BUFFER_RX_head[3]~23 0xc0 1.95751e+06 0.9375; - BUFFER_RX_head[4] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[4]~24 0xc0 7.75877e+06 0.5; - BUFFER_RX_head[4]~25 0xc0 641720 0.03125; - BUFFER_RX_head[5] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[5]~26 0xc0 7.53588e+06 0.5; - BUFFER_RX_head[5]~27 0xc0 7.37545e+06 0.984375; - BUFFER_RX_head[6] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[6]~28 0xc0 1.11315e+07 0.5; - BUFFER_RX_head[6]~29 0xc0 2.3067e+06 0.0078125; - BUFFER_RX_head[7] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[7]~30 0xc0 8.71431e+06 0.5; - BUFFER_RX_head[7]~31 0xc0 721313 0.996094; - BUFFER_RX_head[8] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[8]~32 0xc0 7.98091e+06 0.5; - BUFFER_RX_head[8]~33 0xc0 225528 0.00195313; - BUFFER_RX_head[9] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[9]~34 0xc0 7.76284e+06 0.5; - BUFFER_RX_head[9]~35 0xc0 56440.5 0.999023; - BUFFER_RX_head[10] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[10]~36 0xc0 7.69325e+06 0.5; - BUFFER_RX_head[10]~37 0xc0 7.67914e+06 0.000488281; - BUFFER_RX_head[11] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[11]~38 0xc0 1.15121e+07 0.5; - BUFFER_RX_head[11]~39 0xc0 1.91979e+06 0.999756; - BUFFER_RX_head[12] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[12]~40 0xc0 8.63617e+06 0.5; - BUFFER_RX_head[12]~41 0xc0 8.15622e+06 0.00012207; - BUFFER_RX_head[13] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[13]~42 0xc0 1.17563e+07 0.5; - BUFFER_RX_head[13]~43 0xc0 2.03905e+06 0.999939; - BUFFER_RX_head[14] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[14]~44 0xc0 8.69861e+06 0.5; - BUFFER_RX_head[14]~45 0xc0 8.18885e+06 3.05176e-05; - BUFFER_RX_head[15] 0xc0 7.68002e+06 0.5; - BUFFER_RX_head[15]~46 0xc0 1.1774e+07 0.5; - BUFFER_RX_tail[0] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[0]~17 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[0]~18 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[1] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[1]~20 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[1]~21 0xc0 1.75781e+06 0.75; - BUFFER_RX_tail[2] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[2]~16 0xc0 3113.05 0.000976548; - BUFFER_RX_tail[2]~19 0xc0 1702.35 0.000486366; - BUFFER_RX_tail[2]~22 0xc0 2.83203e+06 0.5; - BUFFER_RX_tail[2]~23 0xc0 744629 0.125; - BUFFER_RX_tail[3] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[3]~24 0xc0 2.81372e+06 0.5; - BUFFER_RX_tail[3]~25 0xc0 2.62756e+06 0.9375; - BUFFER_RX_tail[4] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[4]~26 0xc0 4.07257e+06 0.5; - BUFFER_RX_tail[4]~27 0xc0 833321 0.03125; - BUFFER_RX_tail[5] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[5]~28 0xc0 3.35245e+06 0.5; - BUFFER_RX_tail[5]~29 0xc0 263464 0.984375; - BUFFER_RX_tail[6] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[6]~30 0xc0 3.1606e+06 0.5; - BUFFER_RX_tail[6]~31 0xc0 83095.6 0.0078125; - BUFFER_RX_tail[7] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[7]~32 0xc0 3.1181e+06 0.5; - BUFFER_RX_tail[7]~33 0xc0 3.09733e+06 0.996094; - BUFFER_RX_tail[8] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[8]~34 0xc0 4.64935e+06 0.5; - BUFFER_RX_tail[8]~35 0xc0 967963 0.00195313; - BUFFER_RX_tail[9] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[9]~36 0xc0 3.5968e+06 0.5; - BUFFER_RX_tail[9]~37 0xc0 302500 0.999023; - BUFFER_RX_tail[10] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[10]~38 0xc0 3.27015e+06 0.5; - BUFFER_RX_tail[10]~39 0xc0 94534.3 0.000488281; - BUFFER_RX_tail[11] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[11]~40 0xc0 3.16922e+06 0.5; - BUFFER_RX_tail[11]~41 0xc0 3.14558e+06 0.999756; - BUFFER_RX_tail[12] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[12]~42 0xc0 4.69627e+06 0.5; - BUFFER_RX_tail[12]~43 0xc0 982995 0.00012207; - BUFFER_RX_tail[13] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[13]~44 0xc0 3.61573e+06 0.5; - BUFFER_RX_tail[13]~45 0xc0 307186 0.999939; - BUFFER_RX_tail[14] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[14]~46 0xc0 3.27821e+06 0.5; - BUFFER_RX_tail[14]~47 0xc0 76796.5 3.05176e-05; - BUFFER_RX_tail[15] 0xc0 3.125e+06 0.5; - BUFFER_RX_tail[15]~48 0xc0 3.16321e+06 0.5; - CICFIR_GAIN[0] 0xc0 3.125e+06 0.5; - CICFIR_GAIN[0]~0 0xc0 971.469 0.000488281; - CICFIR_GAIN[1] 0xc0 3.125e+06 0.5; - CICFIR_GAIN[2] 0xc0 3.125e+06 0.5; - CICFIR_GAIN[3] 0xc0 3.125e+06 0.5; - CICFIR_GAIN[4] 0xc0 3.125e+06 0.5; - CICFIR_GAIN[5] 0xc0 3.125e+06 0.5; - CICFIR_GAIN[5]~1 0xc0 2e+07 0.5; - DAC_GAIN[0] 0xc0 3.125e+06 0.5; - DAC_GAIN[0]~0 0xc0 1306.64 0.000488281; - DAC_GAIN[1] 0xc0 3.125e+06 0.5; - DAC_GAIN[2] 0xc0 3.125e+06 0.5; - DAC_GAIN[3] 0xc0 3.125e+06 0.5; - DAC_GAIN[4] 0xc0 3.125e+06 0.5; - DAC_GAIN[5] 0xc0 3.125e+06 0.5; - DAC_GAIN[5]~1 0xc0 2e+07 0.5; - DAC_GAIN[6] 0xc0 3.125e+06 0.5; - DAC_GAIN[6]~feeder 0xc0 2e+07 0.5; - DAC_GAIN[7] 0xc0 3.125e+06 0.5; - DATA_BUS_OE 0xc0 3.125e+06 0.5; - DATA_BUS_OE~0 0xc0 6.67634e+06 0.500476; - DATA_BUS_OE~1 0xc0 6.99442e+06 0.500488; - DATA_BUS_OE~2 0xc0 8.60519e+06 0.0078125; - DATA_BUS_OUT[0] 0xc0 3.125e+06 0.5; - DATA_BUS_OUT[1] 0xc0 3.125e+06 0.5; - DATA_BUS_OUT[2] 0xc0 3.125e+06 0.5; - DATA_BUS_OUT[3] 0xc0 3.125e+06 0.5; - DATA_BUS_OUT[3]~54 0xc0 9.65487e+06 0.493658; - DATA_BUS_OUT[4] 0xc0 3.125e+06 0.5; - DATA_BUS_OUT[4]~3 0xc0 1.70143e+06 0.499998; - DATA_BUS_OUT[4]~12 0xc0 2.34375e+06 0.75; - DATA_BUS_OUT[4]~14 0xc0 16481.2 0.998047; - DATA_BUS_OUT[4]~21 0xc0 2.18129e+07 0.494141; - DATA_BUS_OUT[4]~23 0xc0 51126.7 0.995125; - DATA_BUS_OUT[4]~24 0xc0 2.15207e+07 0.490774; - DATA_BUS_OUT[5] 0xc0 3.125e+06 0.5; - DATA_BUS_OUT[5]~2 0xc0 457968 0.500365; - DATA_BUS_OUT[6] 0xc0 3.125e+06 0.5; - DATA_BUS_OUT[6]~1 0xc0 459697 0.500365; - DATA_BUS_OUT[7] 0xc0 3.125e+06 0.5; - DATA_BUS_OUT[7]~0 0xc0 1.70146e+06 0.499998; - DATA_BUS_OUT~13 0xc0 27278.5 0.992203; - DATA_BUS_OUT~15 0xc0 2.19727e+06 0.25; - DATA_BUS_OUT~16 0xc0 2191.19 0.00146436; - DATA_BUS_OUT~17 0xc0 2.99452e+06 0.500244; - DATA_BUS_OUT~18 0xc0 3.88802e+06 0.500732; - DATA_BUS_OUT~19 0xc0 2.05078e+06 0.25; - DATA_BUS_OUT~20 0xc0 2.72495e+06 0.499998; - DATA_BUS_OUT~22 0xc0 73278 0.996094; - DATA_BUS_OUT~25 0xc0 2.99452e+06 0.500244; - DATA_BUS_OUT~26 0xc0 3.89471e+06 0.500244; - DATA_BUS_OUT~27 0xc0 2.83203e+06 0.5; - DATA_BUS_OUT~28 0xc0 1.40021e+06 0.500365; - DATA_BUS_OUT~29 0xc0 734413 0.500365; - DATA_BUS_OUT~30 0xc0 2.99452e+06 0.500244; - DATA_BUS_OUT~31 0xc0 3.89471e+06 0.500244; - DATA_BUS_OUT~32 0xc0 2.17285e+06 0.5; - DATA_BUS_OUT~33 0xc0 1.39492e+06 0.500365; - DATA_BUS_OUT~34 0xc0 731641 0.500365; - DATA_BUS_OUT~35 0xc0 1.68457e+06 0.25; - DATA_BUS_OUT~36 0xc0 2013.36 0.00146436; - DATA_BUS_OUT~37 0xc0 2.99452e+06 0.500244; - DATA_BUS_OUT~38 0xc0 3.88802e+06 0.500732; - DATA_BUS_OUT~39 0xc0 2.05078e+06 0.25; - DATA_BUS_OUT~40 0xc0 2.72491e+06 0.499998; - DATA_BUS_OUT~41 0xc0 831.855 0.000488274; - DATA_BUS_OUT~42 0xc0 1.07422e+06 0.125; - DATA_BUS_OUT~43 0xc0 3.6717e+07 0.000976324; - DATA_BUS_OUT~44 0xc0 2.05078e+06 0.25; - DATA_BUS_OUT~45 0xc0 1.93606e+06 0.00292778; - DATA_BUS_OUT~46 0xc0 1.9125e+06 0.25; - DATA_BUS_OUT~47 0xc0 1274.69 0.000976563; - DATA_BUS_OUT~48 0xc0 2.9636e+06 0.00438786; - DATA_BUS_OUT~49 0xc0 5.90073e+07 0.00584556; - DATA_BUS_OUT~50 0xc0 2.99452e+06 0.500244; - DATA_BUS_OUT~51 0xc0 63528.8 0.990266; - DATA_BUS_OUT~52 0xc0 26518 0.987365; - DATA_BUS_OUT~53 0xc0 1.86852e+07 0.497127; - DATA_BUS_OUT~55 0xc0 831.855 0.000488274; - DATA_BUS_OUT~56 0xc0 1.9125e+06 0.25; - DATA_BUS_OUT~57 0xc0 37514.9 0.00292778; - DATA_BUS_OUT~58 0xc0 23929.3 0.00341463; - DATA_BUS_OUT~59 0xc0 1.9043e+06 0.25; - DATA_BUS_OUT~60 0xc0 2.27051e+06 0.34375; - DATA_BUS_OUT~61 0xc0 6.93554e+06 0.0018304; - DATA_BUS_OUT~62 0xc0 1.0581e+07 0.0057245; - DATA_BUS_OUT~63 0xc0 2.99452e+06 0.500244; - DATA_BUS_OUT~64 0xc0 5.73156e+06 0.497066; - DATA_BUS_OUT~65 0xc0 2.99452e+06 0.500244; - DATA_BUS_OUT~66 0xc0 1.53809e+06 0.25; - DATA_BUS_OUT~67 0xc0 2.47617e+07 0.00146437; - DATA_BUS_OUT~68 0xc0 1.2207e+06 0.125; - DATA_BUS_OUT~69 0xc0 266761 0.00244045; - DATA_BUS_OUT~70 0xc0 4.78156e+06 0.25; - DATA_BUS_OUT~71 0xc0 2125.68 0.00134277; - DATA_BUS_OUT~72 0xc0 1.02235e+06 0.00426638; - DATA_BUS_OUT~73 0xc0 9.50681e+07 0.00620999; - DATA_BUS_OUT~74 0xc0 1.5916e+07 0.496831; - DATA_BUS_OUT~75 0xc0 2.99452e+06 0.500244; - DATA_BUS_OUT~76 0xc0 5.27401e+06 0.25; - DATA_BUS_OUT~77 0xc0 1073.94 0.00134277; - DATA_BUS_OUT~78 0xc0 5660.04 0.000976324; - DATA_BUS_OUT~79 0xc0 1.53809e+06 0.25; - DATA_BUS_OUT~80 0xc0 7.24861e+06 0.00134277; - DATA_BUS_OUT~81 0xc0 1.11102e+07 0.00426638; - DATA_BUS_OUT~82 0xc0 6.9131e+06 0.00608897; - DATA_BUS_OUT~83 0xc0 1.93662e+06 0.49677; - DATA_BUS_OUT~84 0xc0 1.46713e+06 0.375; - DATA_BUS_OUT~85 0xc0 2.07138e+06 0.375; - DATA_BUS_OUT~86 0xc0 1.8384e+06 0.49344; - DATA_BUS_OUT~87 0xc0 1.8384e+06 0.49344; - Decoder0~0 0xc0 33.1019 6.10352e-05; - Decoder0~1 0xc0 3.2487 1.52588e-05; - Decoder0~2 0xc0 4.32001e+06 0.25; - Decoder0~3 0xc0 3.28793 1.52588e-05; - Decoder0~4 0xc0 33.1019 6.10352e-05; - Decoder0~5 0xc0 3.2487 1.52588e-05; - Decoder0~6 0xc0 3.28793 1.52588e-05; - Decoder0~7 0xc0 3.2487 1.52588e-05; - Decoder0~8 0xc0 3.2487 1.52588e-05; - Decoder0~9 0xc0 3.2487 1.52588e-05; - Decoder0~10 0xc0 3.2487 1.52588e-05; - Equal0~0 0xc0 1.5e+07 0.25; - Equal0~1 0xc0 4.92875e+06 0.03125; - Equal2~0 0xc0 4.30455e+06 0.00390625; - Equal4~0 0xc0 4.5e+06 0.125; - Equal8~0 0xc0 62441.8 0.015625; - Equal8~1 0xc0 2.34375e+06 0.25; - Equal9~0 0xc0 7401.78 0.00390625; - Equal12~0 0xc0 7401.78 0.00390625; - Equal13~0 0xc0 1.75781e+06 0.25; - Equal15~0 0xc0 1.75781e+06 0.25; - Equal17~0 0xc0 10328.7 0.00390625; - Equal20~0 0xc0 384522 0.0625; - Equal20~1 0xc0 6492.06 0.00390625; - Equal22~0 0xc0 681.686 0.000976563; - Equal24~0 0xc0 20848.2 0.0078125; - Equal24~1 0xc0 1.2207e+06 0.125; - Equal24~2 0xc0 4021.78 0.000976563; - Equal25~0 0xc0 16057.5 0.00390625; - Equal25~1 0xc0 1057.24 0.000976563; - Equal27~0 0xc0 1057.24 0.000976563; - Equal28~0 0xc0 1057.24 0.000976563; - Equal29~2 0xc0 11435.2 0.00390625; - Equal29~3 0xc0 457764 0.0625; - Equal29~4 0xc0 1041.59 0.000976563; - Equal30~0 0xc0 2.52001e+06 0.25; - Equal30~1 0xc0 2.52001e+06 0.25; - Equal30~2 0xc0 2.52001e+06 0.25; - Equal30~3 0xc0 2.52001e+06 0.25; - Equal30~4 0xc0 3958.88 0.00390625; - Equal30~5 0xc0 2.52001e+06 0.25; - Equal30~6 0xc0 2.52001e+06 0.25; - Equal30~7 0xc0 2.52001e+06 0.25; - Equal30~8 0xc0 2.52001e+06 0.25; - Equal30~9 0xc0 3958.88 0.00390625; - Equal30~10 0xc0 0.248361 1.52588e-05; - Equal33~2 0xc0 1041.59 0.000976563; - Equal34~0 0xc0 2.34375e+06 0.25; - Equal34~1 0xc0 384522 0.0625; - Equal34~2 0xc0 622559 0.0625; - Equal34~3 0xc0 10735 0.000976563; - Equal35~0 0xc0 457764 0.0625; - Equal35~1 0xc0 549316 0.0625; - Equal35~2 0xc0 2908.71 0.00195313; - Equal36~0 0xc0 1221.9 0.000976563; - FLASH_continue_read 0xc0 3.125e+06 0.5; - FLASH_continue_read~0 0xc0 377.763 0.000487804; - FLASH_continue_read~1 0xc0 2.97452e+06 0.499761; - FLASH_data_out[0] 0xc0 3.125e+06 0.5; - FLASH_data_out[1] 0xc0 3.125e+06 0.5; - FLASH_data_out[2] 0xc0 3.125e+06 0.5; - FLASH_data_out[3] 0xc0 3.125e+06 0.5; - FLASH_data_out[4] 0xc0 3.125e+06 0.5; - FLASH_data_out[5] 0xc0 3.125e+06 0.5; - FLASH_data_out[5]~feeder 0xc0 2e+07 0.5; - FLASH_data_out[6] 0xc0 3.125e+06 0.5; - FLASH_data_out[6]~feeder 0xc0 2e+07 0.5; - FLASH_data_out[7] 0xc0 3.125e+06 0.5; - FLASH_data_out[7]~0 0xc0 122.725 0.000487328; - FLASH_enable 0xc0 3.125e+06 0.5; - FLASH_enable~0 0xc0 6.5625e+06 0.75; - FLASH_enable~1 0xc0 1070.05 0.000488281; - FLASH_enable~2 0xc0 3.2375e+06 0.0625; - FLASH_enable~3 0xc0 7.85364e+06 0.499268; - FLASH_enable~feeder 0xc0 7.85364e+06 0.499268; - I_HOLD[0] 0xc0 3.125e+06 0.5; - I_HOLD[0]~5 0xc0 5203.95 0.000959003; - I_HOLD[0]~32 0xc0 1.5539e+06 0.5; - I_HOLD[0]~33 0xc0 775751 0.499992; - I_HOLD[1] 0xc0 3.125e+06 0.5; - I_HOLD[1]~28 0xc0 1.5539e+06 0.5; - I_HOLD[1]~29 0xc0 2.01698e+06 0.499992; - I_HOLD[2] 0xc0 3.125e+06 0.5; - I_HOLD[2]~24 0xc0 1.5539e+06 0.5; - I_HOLD[2]~25 0xc0 2.01698e+06 0.499992; - I_HOLD[3] 0xc0 3.125e+06 0.5; - I_HOLD[3]~18 0xc0 1.5539e+06 0.5; - I_HOLD[3]~19 0xc0 2.01698e+06 0.499992; - I_HOLD[4] 0xc0 3.125e+06 0.5; - I_HOLD[4]~16 0xc0 1.5539e+06 0.5; - I_HOLD[4]~17 0xc0 2.01698e+06 0.499992; - I_HOLD[5] 0xc0 3.125e+06 0.5; - I_HOLD[5]~12 0xc0 1.5539e+06 0.5; - I_HOLD[5]~13 0xc0 2.01698e+06 0.499992; - I_HOLD[6] 0xc0 3.125e+06 0.5; - I_HOLD[6]~8 0xc0 1.5539e+06 0.5; - I_HOLD[6]~9 0xc0 2.01698e+06 0.499992; - I_HOLD[7] 0xc0 3.125e+06 0.5; - I_HOLD[7]~3 0xc0 1.5539e+06 0.5; - I_HOLD[7]~4 0xc0 2.01698e+06 0.499992; - I_HOLD[8] 0xc0 3.125e+06 0.5; - I_HOLD[8]~2 0xc0 1406.25 0.000959003; - I_HOLD[8]~30 0xc0 1.5539e+06 0.5; - I_HOLD[8]~31 0xc0 775751 0.499992; - I_HOLD[9] 0xc0 3.125e+06 0.5; - I_HOLD[9]~26 0xc0 1.5539e+06 0.5; - I_HOLD[9]~27 0xc0 2.01698e+06 0.499992; - I_HOLD[10] 0xc0 3.125e+06 0.5; - I_HOLD[10]~22 0xc0 1.5539e+06 0.5; - I_HOLD[10]~23 0xc0 2.01698e+06 0.499992; - I_HOLD[11] 0xc0 3.125e+06 0.5; - I_HOLD[11]~20 0xc0 1.5539e+06 0.5; - I_HOLD[11]~21 0xc0 2.01698e+06 0.499992; - I_HOLD[12] 0xc0 3.125e+06 0.5; - I_HOLD[12]~14 0xc0 1.5539e+06 0.5; - I_HOLD[12]~15 0xc0 2.01698e+06 0.499992; - I_HOLD[13] 0xc0 3.125e+06 0.5; - I_HOLD[13]~10 0xc0 1.5539e+06 0.5; - I_HOLD[13]~11 0xc0 2.01698e+06 0.499992; - I_HOLD[14] 0xc0 3.125e+06 0.5; - I_HOLD[14]~6 0xc0 1.5539e+06 0.5; - I_HOLD[14]~7 0xc0 2.01698e+06 0.499992; - I_HOLD[15] 0xc0 3.125e+06 0.5; - I_HOLD[15]~0 0xc0 1.5539e+06 0.5; - I_HOLD[15]~1 0xc0 2.01698e+06 0.499992; - LPF_1 0xc0 3.125e+06 0.5; - LPF_2 0xc0 3.125e+06 0.5; - LPF_3 0xc0 3.125e+06 0.5; - LPF_3~feeder 0xc0 2e+07 0.5; - LessThan2~0 0xc0 691877 0.0625; - LessThan2~1 0xc0 945002 0.0625; - LessThan2~2 0xc0 945002 0.0625; - LessThan2~3 0xc0 131.378 0.000244141; - LessThan2~4 0xc0 5.15754e+06 0.499893; - LessThan3~0 0xc0 281525 0.0625; - LessThan3~1 0xc0 281525 0.0625; - LessThan3~2 0xc0 281525 0.0625; - LessThan3~3 0xc0 63048.9 0.0546875; - LessThan3~4 0xc0 2.24605e+06 0.499893; - LessThan4~0 0xc0 2.38385e+06 0.743958; - LessThan5~0 0xc0 2.38288e+06 0.74408; - Mux0~0 0xc0 2.66251e+06 0.5; - Mux0~1 0xc0 1.80502e+06 0.5; - Mux0~2 0xc0 2.66251e+06 0.5; - Mux0~3 0xc0 1.80502e+06 0.5; - Mux1~0 0xc0 2.66251e+06 0.5; - Mux1~1 0xc0 1.80502e+06 0.5; - Mux1~2 0xc0 2.66251e+06 0.5; - Mux1~3 0xc0 1.80502e+06 0.5; - Mux2~0 0xc0 2.66251e+06 0.5; - Mux2~1 0xc0 1.80502e+06 0.5; - Mux2~2 0xc0 2.66251e+06 0.5; - Mux2~3 0xc0 1.80502e+06 0.5; - Mux3~0 0xc0 2.66251e+06 0.5; - Mux3~1 0xc0 1.80502e+06 0.5; - Mux3~2 0xc0 2.66251e+06 0.5; - Mux3~3 0xc0 1.80502e+06 0.5; - Mux4~0 0xc0 2.66251e+06 0.5; - Mux4~1 0xc0 1.80502e+06 0.5; - Mux4~2 0xc0 2.66251e+06 0.5; - Mux4~3 0xc0 1.80502e+06 0.5; - Mux5~0 0xc0 2.66251e+06 0.5; - Mux5~1 0xc0 1.80502e+06 0.5; - Mux5~2 0xc0 2.66251e+06 0.5; - Mux5~3 0xc0 1.80502e+06 0.5; - Mux6~0 0xc0 2.66251e+06 0.5; - Mux6~1 0xc0 1.80502e+06 0.5; - Mux6~2 0xc0 2.66251e+06 0.5; - Mux6~3 0xc0 1.80502e+06 0.5; - Mux7~0 0xc0 2.66251e+06 0.5; - Mux7~1 0xc0 1.80502e+06 0.5; - Mux7~2 0xc0 2.66251e+06 0.5; - Mux7~3 0xc0 1.80502e+06 0.5; - Mux8~0 0xc0 2.66251e+06 0.5; - Mux8~1 0xc0 1.80502e+06 0.5; - Mux8~2 0xc0 2.66251e+06 0.5; - Mux8~3 0xc0 1.80502e+06 0.5; - Mux9~0 0xc0 2.66251e+06 0.5; - Mux9~1 0xc0 1.80502e+06 0.5; - Mux9~2 0xc0 2.66251e+06 0.5; - Mux9~3 0xc0 1.80502e+06 0.5; - Mux10~0 0xc0 2.66251e+06 0.5; - Mux10~1 0xc0 1.80502e+06 0.5; - Mux10~2 0xc0 2.66251e+06 0.5; - Mux10~3 0xc0 1.80502e+06 0.5; - Mux11~0 0xc0 2.66251e+06 0.5; - Mux11~1 0xc0 1.80502e+06 0.5; - Mux11~2 0xc0 2.66251e+06 0.5; - Mux11~3 0xc0 1.80502e+06 0.5; - Mux12~0 0xc0 2.66251e+06 0.5; - Mux12~1 0xc0 1.80502e+06 0.5; - Mux12~2 0xc0 2.66251e+06 0.5; - Mux12~3 0xc0 1.80502e+06 0.5; - Mux13~0 0xc0 2.66251e+06 0.5; - Mux13~1 0xc0 1.80502e+06 0.5; - Mux13~2 0xc0 2.66251e+06 0.5; - Mux13~3 0xc0 1.80502e+06 0.5; - Mux14~0 0xc0 2.66251e+06 0.5; - Mux14~1 0xc0 1.80502e+06 0.5; - Mux14~2 0xc0 2.66251e+06 0.5; - Mux14~3 0xc0 1.80502e+06 0.5; - Mux15~0 0xc0 2.66251e+06 0.5; - Mux15~1 0xc0 1.80502e+06 0.5; - Mux15~2 0xc0 2.66251e+06 0.5; - Mux15~3 0xc0 1.80502e+06 0.5; - Mux16~0 0xc0 2.66251e+06 0.5; - Mux16~1 0xc0 1.80502e+06 0.5; - Mux16~2 0xc0 2.66251e+06 0.5; - Mux16~3 0xc0 1.80502e+06 0.5; - Mux16~4 0xc0 1.5539e+06 0.5; - Mux17~0 0xc0 2.66251e+06 0.5; - Mux17~1 0xc0 1.80502e+06 0.5; - Mux17~2 0xc0 2.66251e+06 0.5; - Mux17~3 0xc0 1.80502e+06 0.5; - Mux17~4 0xc0 1.5539e+06 0.5; - Mux18~0 0xc0 2.66251e+06 0.5; - Mux18~1 0xc0 1.80502e+06 0.5; - Mux18~2 0xc0 2.66251e+06 0.5; - Mux18~3 0xc0 1.80502e+06 0.5; - Mux18~4 0xc0 1.5539e+06 0.5; - Mux19~0 0xc0 2.66251e+06 0.5; - Mux19~1 0xc0 1.80502e+06 0.5; - Mux19~2 0xc0 2.66251e+06 0.5; - Mux19~3 0xc0 1.80502e+06 0.5; - Mux19~4 0xc0 1.5539e+06 0.5; - Mux20~0 0xc0 2.66251e+06 0.5; - Mux20~1 0xc0 1.80502e+06 0.5; - Mux20~2 0xc0 2.66251e+06 0.5; - Mux20~3 0xc0 1.80502e+06 0.5; - Mux20~4 0xc0 1.5539e+06 0.5; - Mux21~0 0xc0 2.66251e+06 0.5; - Mux21~1 0xc0 1.80502e+06 0.5; - Mux21~2 0xc0 2.66251e+06 0.5; - Mux21~3 0xc0 1.80502e+06 0.5; - Mux21~4 0xc0 1.5539e+06 0.5; - Mux22~0 0xc0 2.66251e+06 0.5; - Mux22~1 0xc0 1.80502e+06 0.5; - Mux22~2 0xc0 2.66251e+06 0.5; - Mux22~3 0xc0 1.80502e+06 0.5; - Mux22~4 0xc0 1.5539e+06 0.5; - Mux23~0 0xc0 2.66251e+06 0.5; - Mux23~1 0xc0 1.80502e+06 0.5; - Mux23~2 0xc0 2.66251e+06 0.5; - Mux23~3 0xc0 1.80502e+06 0.5; - Mux23~4 0xc0 1.5539e+06 0.5; - Mux24~0 0xc0 2.66251e+06 0.5; - Mux24~1 0xc0 1.80502e+06 0.5; - Mux24~2 0xc0 2.66251e+06 0.5; - Mux24~3 0xc0 1.80502e+06 0.5; - Mux25~0 0xc0 2.66251e+06 0.5; - Mux25~1 0xc0 1.80502e+06 0.5; - Mux25~2 0xc0 2.66251e+06 0.5; - Mux25~3 0xc0 1.80502e+06 0.5; - Mux26~0 0xc0 2.66251e+06 0.5; - Mux26~1 0xc0 1.80502e+06 0.5; - Mux26~2 0xc0 2.66251e+06 0.5; - Mux26~3 0xc0 1.80502e+06 0.5; - Mux27~0 0xc0 2.66251e+06 0.5; - Mux27~1 0xc0 1.80502e+06 0.5; - Mux27~2 0xc0 2.66251e+06 0.5; - Mux27~3 0xc0 1.80502e+06 0.5; - Mux28~0 0xc0 2.66251e+06 0.5; - Mux28~1 0xc0 1.80502e+06 0.5; - Mux28~2 0xc0 2.66251e+06 0.5; - Mux28~3 0xc0 1.80502e+06 0.5; - Mux29~0 0xc0 2.66251e+06 0.5; - Mux29~1 0xc0 1.80502e+06 0.5; - Mux29~2 0xc0 2.66251e+06 0.5; - Mux29~3 0xc0 1.80502e+06 0.5; - Mux30~0 0xc0 2.66251e+06 0.5; - Mux30~1 0xc0 1.80502e+06 0.5; - Mux30~2 0xc0 2.66251e+06 0.5; - Mux30~3 0xc0 1.80502e+06 0.5; - Mux31~0 0xc0 2.66251e+06 0.5; - Mux31~1 0xc0 1.80502e+06 0.5; - Mux31~2 0xc0 2.66251e+06 0.5; - Mux31~3 0xc0 1.80502e+06 0.5; - NCO_freq[0] 0xc0 3.125e+06 0.5; - NCO_freq[0]~8 0xc0 1 0.5; - NCO_freq[1] 0xc0 3.125e+06 0.5; - NCO_freq[1]~7 0xc0 2e+07 0.5; - NCO_freq[2] 0xc0 3.125e+06 0.5; - NCO_freq[2]~feeder 0xc0 2e+07 0.5; - NCO_freq[3] 0xc0 3.125e+06 0.5; - NCO_freq[3]~6 0xc0 2e+07 0.5; - NCO_freq[4] 0xc0 3.125e+06 0.5; - NCO_freq[4]~feeder 0xc0 2e+07 0.5; - NCO_freq[5] 0xc0 3.125e+06 0.5; - NCO_freq[5]~5 0xc0 2e+07 0.5; - NCO_freq[6] 0xc0 3.125e+06 0.5; - NCO_freq[6]~feeder 0xc0 2e+07 0.5; - NCO_freq[7] 0xc0 3.125e+06 0.5; - NCO_freq[7]~1 0xc0 2077.36 0.000488281; - NCO_freq[7]~4 0xc0 2e+07 0.5; - NCO_freq[8] 0xc0 3.125e+06 0.5; - NCO_freq[8]~feeder 0xc0 1 0.5; - NCO_freq[9] 0xc0 3.125e+06 0.5; - NCO_freq[9]~0 0xc0 3.10087e+06 0.000488281; - NCO_freq[9]~3 0xc0 2e+07 0.5; - NCO_freq[10] 0xc0 3.125e+06 0.5; - NCO_freq[10]~feeder 0xc0 2e+07 0.5; - NCO_freq[11] 0xc0 3.125e+06 0.5; - NCO_freq[12] 0xc0 3.125e+06 0.5; - NCO_freq[12]~9 0xc0 2e+07 0.5; - NCO_freq[13] 0xc0 3.125e+06 0.5; - NCO_freq[13]~10 0xc0 2e+07 0.5; - NCO_freq[14] 0xc0 3.125e+06 0.5; - NCO_freq[14]~feeder 0xc0 2e+07 0.5; - NCO_freq[15] 0xc0 3.125e+06 0.5; - NCO_freq[15]~11 0xc0 2e+07 0.5; - NCO_freq[16] 0xc0 3.125e+06 0.5; - NCO_freq[16]~12 0xc0 1 0.5; - NCO_freq[17] 0xc0 3.125e+06 0.5; - NCO_freq[17]~2 0xc0 1.93822e+06 0.000488281; - NCO_freq[17]~13 0xc0 2e+07 0.5; - NCO_freq[18] 0xc0 3.125e+06 0.5; - NCO_freq[18]~feeder 0xc0 2e+07 0.5; - NCO_freq[19] 0xc0 3.125e+06 0.5; - NCO_freq[19]~feeder 0xc0 2e+07 0.5; - NCO_freq[20] 0xc0 3.125e+06 0.5; - NCO_freq[20]~feeder 0xc0 2e+07 0.5; - NCO_freq[21] 0xc0 3.125e+06 0.5; - NCO_freq[21]~feeder 0xc0 2e+07 0.5; - Q_HOLD[0] 0xc0 3.125e+06 0.5; - Q_HOLD[0]~2 0xc0 2.15659e+07 0.49125; - Q_HOLD[0]~5 0xc0 7292.45 0.00194836; - Q_HOLD[0]~6 0xc0 5171.73 0.00143593; - Q_HOLD[0]~19 0xc0 1.5539e+06 0.5; - Q_HOLD[0]~20 0xc0 541.193 0.499756; - Q_HOLD[1] 0xc0 3.125e+06 0.5; - Q_HOLD[1]~17 0xc0 1.5539e+06 0.5; - Q_HOLD[1]~18 0xc0 2.57205e+07 0.499756; - Q_HOLD[2] 0xc0 3.125e+06 0.5; - Q_HOLD[2]~15 0xc0 1.5539e+06 0.5; - Q_HOLD[2]~16 0xc0 2.57205e+07 0.499756; - Q_HOLD[3] 0xc0 3.125e+06 0.5; - Q_HOLD[3]~13 0xc0 1.5539e+06 0.5; - Q_HOLD[3]~14 0xc0 2.57689e+07 0.5; - Q_HOLD[4] 0xc0 3.125e+06 0.5; - Q_HOLD[4]~11 0xc0 1.5539e+06 0.5; - Q_HOLD[4]~12 0xc0 2.57689e+07 0.5; - Q_HOLD[5] 0xc0 3.125e+06 0.5; - Q_HOLD[5]~9 0xc0 1.5539e+06 0.5; - Q_HOLD[5]~10 0xc0 2.57205e+07 0.499756; - Q_HOLD[6] 0xc0 3.125e+06 0.5; - Q_HOLD[6]~7 0xc0 1.5539e+06 0.5; - Q_HOLD[6]~8 0xc0 2.57205e+07 0.499756; - Q_HOLD[7] 0xc0 3.125e+06 0.5; - Q_HOLD[7]~3 0xc0 1.5539e+06 0.5; - Q_HOLD[7]~4 0xc0 2.57205e+07 0.499756; - Q_HOLD[8] 0xc0 3.125e+06 0.5; - Q_HOLD[8]~21 0xc0 775751 0.499992; - Q_HOLD[8]~22 0xc0 42511.1 0.99221; - Q_HOLD[8]~23 0xc0 1289.84 0.000958532; - Q_HOLD[9] 0xc0 3.125e+06 0.5; - Q_HOLD[9]~24 0xc0 2.01698e+06 0.499992; - Q_HOLD[10] 0xc0 3.125e+06 0.5; - Q_HOLD[10]~25 0xc0 2.01698e+06 0.499992; - Q_HOLD[11] 0xc0 3.125e+06 0.5; - Q_HOLD[11]~26 0xc0 2.01698e+06 0.499992; - Q_HOLD[12] 0xc0 3.125e+06 0.5; - Q_HOLD[12]~27 0xc0 2.01698e+06 0.499992; - Q_HOLD[13] 0xc0 3.125e+06 0.5; - Q_HOLD[13]~28 0xc0 2.01698e+06 0.499992; - Q_HOLD[14] 0xc0 3.125e+06 0.5; - Q_HOLD[14]~29 0xc0 2.01698e+06 0.499992; - Q_HOLD[15] 0xc0 3.125e+06 0.5; - Q_HOLD[15]~30 0xc0 2.01698e+06 0.499992; - TX_CICFIR_GAIN[0] 0xc0 3.125e+06 0.5; - TX_CICFIR_GAIN[0]~0 0xc0 971.469 0.000488281; - TX_CICFIR_GAIN[0]~feeder 0xc0 1 0.5; - TX_CICFIR_GAIN[1] 0xc0 3.125e+06 0.5; - TX_CICFIR_GAIN[1]~feeder 0xc0 2e+07 0.5; - TX_CICFIR_GAIN[2] 0xc0 3.125e+06 0.5; - TX_CICFIR_GAIN[3] 0xc0 3.125e+06 0.5; - TX_CICFIR_GAIN[4] 0xc0 3.125e+06 0.5; - TX_I[0] 0xc0 3.125e+06 0.5; - TX_I[0]~feeder 0xc0 1 0.5; - TX_I[1] 0xc0 3.125e+06 0.5; - TX_I[1]~feeder 0xc0 2e+07 0.5; - TX_I[2] 0xc0 3.125e+06 0.5; - TX_I[3] 0xc0 3.125e+06 0.5; - TX_I[3]~feeder 0xc0 2e+07 0.5; - TX_I[4] 0xc0 3.125e+06 0.5; - TX_I[4]~feeder 0xc0 2e+07 0.5; - TX_I[5] 0xc0 3.125e+06 0.5; - TX_I[5]~feeder 0xc0 2e+07 0.5; - TX_I[6] 0xc0 3.125e+06 0.5; - TX_I[6]~feeder 0xc0 2e+07 0.5; - TX_I[7] 0xc0 3.125e+06 0.5; - TX_I[7]~feeder 0xc0 2e+07 0.5; - TX_I[8] 0xc0 3.125e+06 0.5; - TX_I[9] 0xc0 3.125e+06 0.5; - TX_I[9]~feeder 0xc0 3.125e+06 0.5; - TX_I[10] 0xc0 3.125e+06 0.5; - TX_I[11] 0xc0 3.125e+06 0.5; - TX_I[12] 0xc0 3.125e+06 0.5; - TX_I[13] 0xc0 3.125e+06 0.5; - TX_I[14] 0xc0 3.125e+06 0.5; - TX_I[15] 0xc0 3.125e+06 0.5; - TX_I[15]~feeder 0xc0 3.125e+06 0.5; - TX_NCO_freq[0] 0xc0 3.125e+06 0.5; - TX_NCO_freq[0]~8 0xc0 1 0.5; - TX_NCO_freq[1] 0xc0 3.125e+06 0.5; - TX_NCO_freq[1]~7 0xc0 2e+07 0.5; - TX_NCO_freq[2] 0xc0 3.125e+06 0.5; - TX_NCO_freq[3] 0xc0 3.125e+06 0.5; - TX_NCO_freq[3]~6 0xc0 2e+07 0.5; - TX_NCO_freq[4] 0xc0 3.125e+06 0.5; - TX_NCO_freq[5] 0xc0 3.125e+06 0.5; - TX_NCO_freq[5]~5 0xc0 2e+07 0.5; - TX_NCO_freq[6] 0xc0 3.125e+06 0.5; - TX_NCO_freq[6]~feeder 0xc0 2e+07 0.5; - TX_NCO_freq[7] 0xc0 3.125e+06 0.5; - TX_NCO_freq[7]~1 0xc0 465.501 0.000488281; - TX_NCO_freq[7]~4 0xc0 2e+07 0.5; - TX_NCO_freq[8] 0xc0 3.125e+06 0.5; - TX_NCO_freq[8]~feeder 0xc0 1 0.5; - TX_NCO_freq[9] 0xc0 3.125e+06 0.5; - TX_NCO_freq[9]~3 0xc0 2e+07 0.5; - TX_NCO_freq[10] 0xc0 3.125e+06 0.5; - TX_NCO_freq[10]~feeder 0xc0 2e+07 0.5; - TX_NCO_freq[11] 0xc0 3.125e+06 0.5; - TX_NCO_freq[11]~feeder 0xc0 2e+07 0.5; - TX_NCO_freq[12] 0xc0 3.125e+06 0.5; - TX_NCO_freq[12]~9 0xc0 2e+07 0.5; - TX_NCO_freq[13] 0xc0 3.125e+06 0.5; - TX_NCO_freq[13]~10 0xc0 2e+07 0.5; - TX_NCO_freq[14] 0xc0 3.125e+06 0.5; - TX_NCO_freq[14]~feeder 0xc0 2e+07 0.5; - TX_NCO_freq[15] 0xc0 3.125e+06 0.5; - TX_NCO_freq[15]~0 0xc0 465.501 0.000488281; - TX_NCO_freq[15]~11 0xc0 2e+07 0.5; - TX_NCO_freq[16] 0xc0 3.125e+06 0.5; - TX_NCO_freq[16]~12 0xc0 1 0.5; - TX_NCO_freq[17] 0xc0 3.125e+06 0.5; - TX_NCO_freq[17]~13 0xc0 2e+07 0.5; - TX_NCO_freq[18] 0xc0 3.125e+06 0.5; - TX_NCO_freq[19] 0xc0 3.125e+06 0.5; - TX_NCO_freq[19]~feeder 0xc0 2e+07 0.5; - TX_NCO_freq[20] 0xc0 3.125e+06 0.5; - TX_NCO_freq[21] 0xc0 3.125e+06 0.5; - TX_NCO_freq[21]~2 0xc0 739798 0.000488281; - TX_NCO_freq[21]~feeder 0xc0 2e+07 0.5; - TX_Q[0] 0xc0 3.125e+06 0.5; - TX_Q[0]~feeder 0xc0 3.125e+06 0.5; - TX_Q[1] 0xc0 3.125e+06 0.5; - TX_Q[2] 0xc0 3.125e+06 0.5; - TX_Q[2]~feeder 0xc0 3.125e+06 0.5; - TX_Q[3] 0xc0 3.125e+06 0.5; - TX_Q[3]~feeder 0xc0 3.125e+06 0.5; - TX_Q[4] 0xc0 3.125e+06 0.5; - TX_Q[4]~feeder 0xc0 3.125e+06 0.5; - TX_Q[5] 0xc0 3.125e+06 0.5; - TX_Q[5]~feeder 0xc0 3.125e+06 0.5; - TX_Q[6] 0xc0 3.125e+06 0.5; - TX_Q[6]~feeder 0xc0 3.125e+06 0.5; - TX_Q[7] 0xc0 3.125e+06 0.5; - TX_Q[8] 0xc0 3.125e+06 0.5; - TX_Q[8]~feeder 0xc0 3.125e+06 0.5; - TX_Q[9] 0xc0 3.125e+06 0.5; - TX_Q[9]~feeder 0xc0 3.125e+06 0.5; - TX_Q[10] 0xc0 3.125e+06 0.5; - TX_Q[10]~feeder 0xc0 3.125e+06 0.5; - TX_Q[11] 0xc0 3.125e+06 0.5; - TX_Q[12] 0xc0 3.125e+06 0.5; - TX_Q[13] 0xc0 3.125e+06 0.5; - TX_Q[13]~feeder 0xc0 3.125e+06 0.5; - TX_Q[14] 0xc0 3.125e+06 0.5; - TX_Q[14]~feeder 0xc0 3.125e+06 0.5; - TX_Q[15] 0xc0 3.125e+06 0.5; - k[0] 0xc0 3.125e+06 0.5; - k[1] 0xc0 3.125e+06 0.5; - k[2] 0xc0 3.125e+06 0.5; - k[3] 0xc0 3.125e+06 0.5; - k[4] 0xc0 3.125e+06 0.5; - k[5] 0xc0 3.125e+06 0.5; - k[6] 0xc0 3.125e+06 0.5; - k[7] 0xc0 3.125e+06 0.5; - k[8] 0xc0 3.125e+06 0.5; - k[9] 0xc0 3.125e+06 0.5; - k~2 0xc0 1.1e+07 0.375; - k~3 0xc0 9.102e+06 0.251953; - k~4 0xc0 1.48558e+07 0.496105; - k~5 0xc0 6705.8 0.996094; - k~6 0xc0 56077.2 0.980575; - k~7 0xc0 2.02491e+07 0.442; - k~8 0xc0 2.99344e+06 0.487419; - k~9 0xc0 3.98902e+07 0.498535; - k~10 0xc0 1.1e+07 0.375; - k~11 0xc0 2.22444e+07 0.251953; - k~12 0xc0 4.94522e+07 0.557265; - k~13 0xc0 1.43127e+06 0.00292778; - k~14 0xc0 1.48745e+06 0.972934; - k~15 0xc0 8.71161e+06 0.997073; - k~16 0xc0 1.54868e+07 0.491963; - k~17 0xc0 5e+06 0.25; - k~18 0xc0 6.51864e+06 0.507813; - k~19 0xc0 2.13812e+07 0.498896; - k~20 0xc0 5519.15 0.998048; - k~21 0xc0 8.57709e+06 0.995135; - k~22 0xc0 2.52841e+07 0.496596; - k~23 0xc0 1.1e+07 0.375; - k~24 0xc0 2.22444e+07 0.251953; - k~25 0xc0 2.00959e+07 0.557812; - k~26 0xc0 3.85003e+07 0.254305; - k~27 0xc0 4.5218e+07 0.445055; - k~28 0xc0 8.01966e+07 0.506793; - k~29 0xc0 5e+06 0.25; - k~30 0xc0 6.8288e+06 0.246094; - k~31 0xc0 6.51417e+07 0.562958; - k~32 0xc0 3.96649e+07 0.255802; - k~33 0xc0 12845.4 0.996094; - k~34 0xc0 3.93789e+07 0.495134; - k~35 0xc0 5.8073e+07 0.444501; - k~36 0xc0 1.1e+07 0.375; - k~37 0xc0 8.27298e+06 0.248047; - k~38 0xc0 5.94569e+06 0.513533; - k~39 0xc0 1.70742e+07 0.497076; - k~40 0xc0 1.61507e+07 0.43906; - k~41 0xc0 171602 0.992188; - k~42 0xc0 1.82594e+07 0.244202; - k~43 0xc0 16832.2 0.0116882; - k~44 0xc0 1.35679e+07 0.498052; - k~45 0xc0 5061.26 0.00581375; - k~46 0xc0 1.38388e+07 0.494673; - k~47 0xc0 2.67746e+07 0.436198; - k~48 0xc0 1.61011e+07 0.244202; - k~49 0xc0 9.02679e+06 0.495157; - k~50 0xc0 2.87931e+07 0.563615; - k~51 0xc0 43277.2 0.975791; - preamp_enable 0xc0 3.125e+06 0.5; - preamp_enable~0 0xc0 2.12891e+06 0.875; - preamp_enable~1 0xc0 739798 0.000488281; - preamp_enable~feeder 0xc0 2e+07 0.5; - reset_n 0xc0 7.68002e+06 0.5; - reset_n~clkctrl 0xc0 7.68002e+06 0.5; - reset_n~feeder 0xc0 3.125e+06 0.5; - rx 0xc0 3.125e+06 0.5; - rx~0 0xc0 1 0.5; - sync_reset_n 0xc0 3.125e+06 0.5; - sync_reset_n~0 0xc0 4.03199e+07 0.496101; - sync_reset_n~1 0xc0 1.72182e+07 0.0078125; - sync_reset_n~2 0xc0 1.49186e+07 0.5; - sync_reset_n~feeder 0xc0 1.49186e+07 0.5; - tx 0xc0 3.125e+06 0.5; - tx_iq_valid 0xc0 3.125e+06 0.5; - tx_iq_valid~0 0xc0 698.231 0.000488281; - tx_iq_valid~1 0xc0 3.2375e+06 0.0625; - tx_iq_valid~2 0xc0 7.01132e+06 0.499268; - tx_iq_valid~feeder 0xc0 7.01132e+06 0.499268; - tx~0 0xc0 1 0.5; - tx~clkctrl 0xc0 3.125e+06 0.5; - STM32_SYNC 0x30 2e+07 0.5; - STM32_SYNC~input 0xc0 2e+07 0.5; - clock_buffer:SYSCLK_BUFFER; - clock_buffer_altclkctrl_0:altclkctrl_0; - clock_buffer_altclkctrl_0_sub:clock_buffer_altclkctrl_0_sub_component; - wire_clkctrl1_outclk 0xc0 1.2288e+08 0.5; - tx_cic:TX_CIC_I; - tx_cic_cic_ii_0:cic_ii_0; - alt_cic_core:core; - auk_dspip_avalon_streaming_controller:avalon_controller; - auk_dspip_avalon_streaming_small_fifo:ready_FIFO; - Equal2~0 0xc0 5.70036e+06 0.125; - fifo_array[0][0] 0xc0 1.92012e+07 0.5; - fifo_array[0][0]~7 0xc0 5.70036e+06 0.875; - fifo_array[0][0]~8 0xc0 1.13241e+07 0.5; - fifo_array[1][0] 0xc0 1.92012e+07 0.5; - fifo_array[1][0]~5 0xc0 5.70036e+06 0.125; - fifo_array[1][0]~6 0xc0 1.13241e+07 0.5; - fifo_array[2][0] 0xc0 1.92012e+07 0.5; - fifo_array[2][0]~3 0xc0 4.57529e+06 0.125; - fifo_array[2][0]~4 0xc0 1.09859e+07 0.5; - fifo_array[3][0] 0xc0 1.92012e+07 0.5; - fifo_array[3][0]~9 0xc0 1.09859e+07 0.5; - fifo_array[4][0] 0xc0 1.92012e+07 0.5; - fifo_array[4][0]~1 0xc0 5.70036e+06 0.125; - fifo_array[4][0]~2 0xc0 1.13241e+07 0.5; - fifo_array[5][0] 0xc0 1.92012e+07 0.5; - fifo_array[5][0]~0 0xc0 1.13241e+07 0.5; - fifo_usedw[0] 0xc0 1.92012e+07 0.5; - fifo_usedw[0]~3 0xc0 1.90623e+07 0.5; - fifo_usedw[1] 0xc0 1.92012e+07 0.5; - fifo_usedw[2] 0xc0 1.92012e+07 0.5; - fifo_usedw~0 0xc0 1.11681e+07 0.328125; - fifo_usedw~1 0xc0 1.18133e+07 0.28125; - fifo_usedw~2 0xc0 1.10735e+07 0.452759; - fifo_usedw~4 0xc0 1.24233e+07 0.5; - Mux0~0 0xc0 6.65668e+06 0.5; - Mux0~1 0xc0 9.14062e+06 0.5; - rd_addr_ptr[0] 0xc0 1.92012e+07 0.5; - rd_addr_ptr[0]~2 0xc0 1.92012e+07 0.5; - rd_addr_ptr[1] 0xc0 1.92012e+07 0.5; - rd_addr_ptr[2] 0xc0 1.92012e+07 0.5; - rd_addr_ptr~0 0xc0 1.05757e+07 0.375; - rd_addr_ptr~1 0xc0 1.6201e+07 0.375; - usedw_process~0 0xc0 1.79449e+07 0.4375; - usedw_process~1 0xc0 9.80688e+06 0.21875; - usedw_process~2 0xc0 1.37658e+07 0.423828; - wr_addr_ptr[0] 0xc0 1.92012e+07 0.5; - wr_addr_ptr[0]~4 0xc0 1.92012e+07 0.5; - wr_addr_ptr[1] 0xc0 1.92012e+07 0.5; - wr_addr_ptr[2] 0xc0 1.92012e+07 0.5; - wr_addr_ptr~0 0xc0 5.70036e+06 0.875; - wr_addr_ptr~1 0xc0 4.57529e+06 0.125; - wr_addr_ptr~2 0xc0 1.05757e+07 0.375; - wr_addr_ptr~3 0xc0 1.05757e+07 0.375; - sink_ready_ctrl~0 0xc0 7.02115e+06 0.234375; - sink_ready_ctrl~1 0xc0 1.20008e+07 0.5; - sink_ready_ctrl~2 0xc0 7.24792e+06 0.234375; - sink_ready_ctrl~3 0xc0 4.07081e+06 0.0997925; - stall_reg 0xc0 1.92012e+07 0.5; - stall_w~0 0xc0 1.08007e+07 0.75; - auk_dspip_avalon_streaming_sink:input_sink; - data_valid 0xc0 1.92012e+07 0.5; - scfifo:sink_FIFO; - scfifo_gf71:auto_generated; - dffe_nae 0xc0 1.92012e+07 0.5; - dffe_nae~0 0xc0 4.12526e+06 0.125; - dffe_nae~1 0xc0 1.74881e+07 0.509388; - a_dpfifo_1lv:dpfifo; - _~0 0xc0 1.54672e+07 0.162422; - _~1 0xc0 615567 0.03125; - _~2 0xc0 1.44087e+07 0.489897; - _~3 0xc0 2.82069e+07 0.559381; - _~4 0xc0 1.33579e+06 0.0593815; - _~5 0xc0 5.70036e+06 0.125; - _~6 0xc0 1.35951e+06 0.0054574; - _~7 0xc0 3.56498e+07 0.527477; - _~8 0xc0 9.11458e+06 0.0249481; - empty_dff 0xc0 1.92012e+07 0.5; - altsyncram_l7h1:FIFOram; - q_b[0] 0xc0 1.92012e+07 0.5; - q_b[1] 0xc0 1.92012e+07 0.5; - q_b[2] 0xc0 1.92012e+07 0.5; - q_b[3] 0xc0 1.92012e+07 0.5; - q_b[4] 0xc0 1.92012e+07 0.5; - q_b[5] 0xc0 1.92012e+07 0.5; - q_b[6] 0xc0 1.92012e+07 0.5; - q_b[7] 0xc0 1.92012e+07 0.5; - q_b[8] 0xc0 1.92012e+07 0.5; - q_b[9] 0xc0 1.92012e+07 0.5; - q_b[10] 0xc0 1.92012e+07 0.5; - q_b[11] 0xc0 1.92012e+07 0.5; - q_b[12] 0xc0 1.92012e+07 0.5; - q_b[13] 0xc0 1.92012e+07 0.5; - q_b[14] 0xc0 1.92012e+07 0.5; - q_b[15] 0xc0 1.92012e+07 0.5; - full_dff 0xc0 1.92012e+07 0.5; - low_addressa[0] 0xc0 1.92012e+07 0.5; - low_addressa[1] 0xc0 1.92012e+07 0.5; - low_addressa[2] 0xc0 1.92012e+07 0.5; - ram_read_address[0]~0 0xc0 1.31322e+07 0.5; - ram_read_address[1]~1 0xc0 1.31322e+07 0.5; - ram_read_address[2]~2 0xc0 1.31322e+07 0.5; - rd_ptr_lsb 0xc0 1.92012e+07 0.5; - rd_ptr_lsb~0 0xc0 1.92012e+07 0.5; - cntr_r9b:rd_ptr_msb; - counter_comb_bita0 0xc0 1.92012e+07 0.5; - counter_comb_bita0~COUT 0xc0 1.92012e+07 0.5; - counter_comb_bita1 0xc0 1.92012e+07 0.5; - counter_reg_bit[0] 0xc0 1.92012e+07 0.5; - counter_reg_bit[1] 0xc0 1.92012e+07 0.5; - cntr_8a7:usedw_counter; - counter_comb_bita0 0xc0 1.92012e+07 0.5; - counter_comb_bita0~COUT 0xc0 1.72886e+07 0.5; - counter_comb_bita1 0xc0 1.82449e+07 0.5; - counter_comb_bita1~COUT 0xc0 8.70392e+06 0.75; - counter_comb_bita2 0xc0 1.63527e+07 0.5; - counter_reg_bit[0] 0xc0 1.92012e+07 0.5; - counter_reg_bit[1] 0xc0 1.92012e+07 0.5; - counter_reg_bit[2] 0xc0 1.92012e+07 0.5; - usedw_is_0_dff 0xc0 1.92012e+07 0.5; - usedw_is_1_dff 0xc0 1.92012e+07 0.5; - usedw_will_be_1~0 0xc0 5.31027e+07 0.456286; - valid_rreq 0xc0 1.67691e+07 0.0498962; - valid_wreq 0xc0 4.57529e+06 0.125; - cntr_s9b:wr_ptr; - counter_comb_bita0 0xc0 1.92012e+07 0.5; - counter_comb_bita0~COUT 0xc0 1.92012e+07 0.5; - counter_comb_bita1 0xc0 1.92012e+07 0.5; - counter_comb_bita1~COUT 0xc0 1.08007e+07 0.75; - counter_comb_bita2 0xc0 1.74011e+07 0.5; - counter_reg_bit[0] 0xc0 1.92012e+07 0.5; - counter_reg_bit[1] 0xc0 1.92012e+07 0.5; - counter_reg_bit[2] 0xc0 1.92012e+07 0.5; - alt_cic_int_siso:int_one; - auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 1.92012e+07 0.5; - dout[0] 0xc0 1.92012e+07 0.5; - dout[0]~17 0xc0 1.92012e+07 0.5; - dout[0]~18 0xc0 1.08007e+07 0.75; - dout[0]~51 0xc0 1.44009e+07 0.25; - dout[1] 0xc0 1.92012e+07 0.5; - dout[1]~19 0xc0 1.6201e+07 0.5; - dout[1]~20 0xc0 8.94432e+06 0.375; - dout[2] 0xc0 1.92012e+07 0.5; - dout[2]~21 0xc0 1.37118e+07 0.5; - dout[2]~22 0xc0 1.05311e+07 0.5625; - dout[3] 0xc0 1.92012e+07 0.5; - dout[3]~23 0xc0 1.36022e+07 0.5; - dout[3]~24 0xc0 1.42453e+07 0.46875; - dout[4] 0xc0 1.92012e+07 0.5; - dout[4]~25 0xc0 1.44042e+07 0.5; - dout[4]~26 0xc0 1.25509e+07 0.515625; - dout[5] 0xc0 1.92012e+07 0.5; - dout[5]~27 0xc0 1.3949e+07 0.5; - dout[5]~28 0xc0 1.33182e+07 0.492188; - dout[6] 0xc0 1.92012e+07 0.5; - dout[6]~29 0xc0 1.41329e+07 0.5; - dout[6]~30 0xc0 1.28995e+07 0.503906; - dout[7] 0xc0 1.92012e+07 0.5; - dout[7]~31 0xc0 1.40262e+07 0.5; - dout[7]~32 0xc0 1.30982e+07 0.498047; - dout[8] 0xc0 1.92012e+07 0.5; - dout[8]~33 0xc0 1.40754e+07 0.5; - dout[8]~34 0xc0 1.2996e+07 0.500977; - dout[9] 0xc0 1.92012e+07 0.5; - dout[9]~35 0xc0 1.40497e+07 0.5; - dout[9]~36 0xc0 1.30464e+07 0.499512; - dout[10] 0xc0 1.92012e+07 0.5; - dout[10]~37 0xc0 1.40623e+07 0.5; - dout[10]~38 0xc0 1.3021e+07 0.500244; - dout[11] 0xc0 1.92012e+07 0.5; - dout[11]~39 0xc0 1.40559e+07 0.5; - dout[11]~40 0xc0 1.30336e+07 0.499878; - dout[12] 0xc0 1.92012e+07 0.5; - dout[12]~41 0xc0 1.40591e+07 0.5; - dout[12]~42 0xc0 1.30273e+07 0.500061; - dout[13] 0xc0 1.92012e+07 0.5; - dout[13]~43 0xc0 1.40575e+07 0.5; - dout[13]~44 0xc0 1.30305e+07 0.499969; - dout[14] 0xc0 1.92012e+07 0.5; - dout[14]~45 0xc0 1.40583e+07 0.5; - dout[14]~46 0xc0 1.30289e+07 0.500015; - dout[15] 0xc0 1.92012e+07 0.5; - dout[15]~47 0xc0 1.40579e+07 0.5; - dout[15]~48 0xc0 1.30297e+07 0.499992; - dout[16] 0xc0 1.92012e+07 0.5; - dout[16]~49 0xc0 1.40581e+07 0.5; - dout_valid 0xc0 1.92012e+07 0.5; - auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 1.92012e+07 0.5; - dout[0] 0xc0 1.92012e+07 0.5; - dout[0]~18 0xc0 1.92012e+07 0.5; - dout[0]~19 0xc0 1.08007e+07 0.75; - dout[0]~feeder 0xc0 1.92012e+07 0.5; - dout[1] 0xc0 1.92012e+07 0.5; - dout[1]~20 0xc0 1.6201e+07 0.5; - dout[1]~21 0xc0 8.94432e+06 0.375; - dout[2] 0xc0 1.92012e+07 0.5; - dout[2]~22 0xc0 1.37118e+07 0.5; - dout[2]~23 0xc0 1.05311e+07 0.5625; - dout[3] 0xc0 1.92012e+07 0.5; - dout[3]~24 0xc0 1.36022e+07 0.5; - dout[3]~25 0xc0 1.42453e+07 0.46875; - dout[4] 0xc0 1.92012e+07 0.5; - dout[4]~26 0xc0 1.44042e+07 0.5; - dout[4]~27 0xc0 1.25509e+07 0.515625; - dout[5] 0xc0 1.92012e+07 0.5; - dout[5]~28 0xc0 1.3949e+07 0.5; - dout[5]~29 0xc0 1.33182e+07 0.492188; - dout[6] 0xc0 1.92012e+07 0.5; - dout[6]~30 0xc0 1.41329e+07 0.5; - dout[6]~31 0xc0 1.28995e+07 0.503906; - dout[7] 0xc0 1.92012e+07 0.5; - dout[7]~32 0xc0 1.40262e+07 0.5; - dout[7]~33 0xc0 1.30982e+07 0.498047; - dout[8] 0xc0 1.92012e+07 0.5; - dout[8]~34 0xc0 1.40754e+07 0.5; - dout[8]~35 0xc0 1.2996e+07 0.500977; - dout[9] 0xc0 1.92012e+07 0.5; - dout[9]~36 0xc0 1.40497e+07 0.5; - dout[9]~37 0xc0 1.30464e+07 0.499512; - dout[10] 0xc0 1.92012e+07 0.5; - dout[10]~38 0xc0 1.40623e+07 0.5; - dout[10]~39 0xc0 1.3021e+07 0.500244; - dout[11] 0xc0 1.92012e+07 0.5; - dout[11]~40 0xc0 1.40559e+07 0.5; - dout[11]~41 0xc0 1.30336e+07 0.499878; - dout[12] 0xc0 1.92012e+07 0.5; - dout[12]~42 0xc0 1.40591e+07 0.5; - dout[12]~43 0xc0 1.30273e+07 0.500061; - dout[13] 0xc0 1.92012e+07 0.5; - dout[13]~44 0xc0 1.40575e+07 0.5; - dout[13]~45 0xc0 1.30305e+07 0.499969; - dout[14] 0xc0 1.92012e+07 0.5; - dout[14]~46 0xc0 1.40583e+07 0.5; - dout[14]~47 0xc0 1.30289e+07 0.500015; - dout[15] 0xc0 1.92012e+07 0.5; - dout[15]~48 0xc0 1.40579e+07 0.5; - dout[15]~49 0xc0 1.30297e+07 0.499992; - dout[16] 0xc0 1.92012e+07 0.5; - dout[16]~50 0xc0 1.40581e+07 0.5; - dout[16]~51 0xc0 1.30293e+07 0.500004; - dout[74] 0xc0 1.92012e+07 0.5; - dout[74]~52 0xc0 1.76582e+07 0.5; - dout[74]~54 0xc0 1.44009e+07 0.25; - dout_valid 0xc0 1.92012e+07 0.5; - auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][16] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74] 0xc0 1.92012e+07 0.5; - dout[0] 0xc0 1.92012e+07 0.5; - dout[0]~19 0xc0 1.92012e+07 0.5; - dout[0]~20 0xc0 1.08007e+07 0.75; - dout[1] 0xc0 1.92012e+07 0.5; - dout[1]~21 0xc0 1.6201e+07 0.5; - dout[1]~22 0xc0 8.94432e+06 0.375; - dout[2] 0xc0 1.92012e+07 0.5; - dout[2]~23 0xc0 1.37118e+07 0.5; - dout[2]~24 0xc0 1.05311e+07 0.5625; - dout[3] 0xc0 1.92012e+07 0.5; - dout[3]~25 0xc0 1.36022e+07 0.5; - dout[3]~26 0xc0 1.42453e+07 0.46875; - dout[4] 0xc0 1.92012e+07 0.5; - dout[4]~27 0xc0 1.44042e+07 0.5; - dout[4]~28 0xc0 1.25509e+07 0.515625; - dout[5] 0xc0 1.92012e+07 0.5; - dout[5]~29 0xc0 1.3949e+07 0.5; - dout[5]~30 0xc0 1.33182e+07 0.492188; - dout[6] 0xc0 1.92012e+07 0.5; - dout[6]~31 0xc0 1.41329e+07 0.5; - dout[6]~32 0xc0 1.28995e+07 0.503906; - dout[7] 0xc0 1.92012e+07 0.5; - dout[7]~33 0xc0 1.40262e+07 0.5; - dout[7]~34 0xc0 1.30982e+07 0.498047; - dout[8] 0xc0 1.92012e+07 0.5; - dout[8]~35 0xc0 1.40754e+07 0.5; - dout[8]~36 0xc0 1.2996e+07 0.500977; - dout[9] 0xc0 1.92012e+07 0.5; - dout[9]~37 0xc0 1.40497e+07 0.5; - dout[9]~38 0xc0 1.30464e+07 0.499512; - dout[10] 0xc0 1.92012e+07 0.5; - dout[10]~39 0xc0 1.40623e+07 0.5; - dout[10]~40 0xc0 1.3021e+07 0.500244; - dout[11] 0xc0 1.92012e+07 0.5; - dout[11]~41 0xc0 1.40559e+07 0.5; - dout[11]~42 0xc0 1.30336e+07 0.499878; - dout[12] 0xc0 1.92012e+07 0.5; - dout[12]~43 0xc0 1.40591e+07 0.5; - dout[12]~44 0xc0 1.30273e+07 0.500061; - dout[13] 0xc0 1.92012e+07 0.5; - dout[13]~45 0xc0 1.40575e+07 0.5; - dout[13]~46 0xc0 1.30305e+07 0.499969; - dout[14] 0xc0 1.92012e+07 0.5; - dout[14]~47 0xc0 1.40583e+07 0.5; - dout[14]~48 0xc0 1.30289e+07 0.500015; - dout[15] 0xc0 1.92012e+07 0.5; - dout[15]~49 0xc0 1.40579e+07 0.5; - dout[15]~50 0xc0 1.30297e+07 0.499992; - dout[16] 0xc0 1.92012e+07 0.5; - dout[16]~51 0xc0 1.40581e+07 0.5; - dout[16]~52 0xc0 1.30293e+07 0.500004; - dout[17] 0xc0 1.92012e+07 0.5; - dout[17]~53 0xc0 1.4058e+07 0.5; - dout[17]~54 0xc0 1.30295e+07 0.499998; - dout[74] 0xc0 1.92012e+07 0.5; - dout[74]~55 0xc0 1.40581e+07 0.5; - dout[74]~57 0xc0 1.44009e+07 0.25; - dout_valid 0xc0 1.92012e+07 0.5; - auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][16] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][16]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][17] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][17]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 1.92012e+07 0.5; - dout[0] 0xc0 1.92012e+07 0.5; - dout[0]~20 0xc0 1.92012e+07 0.5; - dout[0]~21 0xc0 1.08007e+07 0.75; - dout[1] 0xc0 1.92012e+07 0.5; - dout[1]~22 0xc0 1.6201e+07 0.5; - dout[1]~23 0xc0 8.94432e+06 0.375; - dout[2] 0xc0 1.92012e+07 0.5; - dout[2]~24 0xc0 1.37118e+07 0.5; - dout[2]~25 0xc0 1.05311e+07 0.5625; - dout[3] 0xc0 1.92012e+07 0.5; - dout[3]~26 0xc0 1.36022e+07 0.5; - dout[3]~27 0xc0 1.42453e+07 0.46875; - dout[4] 0xc0 1.92012e+07 0.5; - dout[4]~28 0xc0 1.44042e+07 0.5; - dout[4]~29 0xc0 1.25509e+07 0.515625; - dout[5] 0xc0 1.92012e+07 0.5; - dout[5]~30 0xc0 1.3949e+07 0.5; - dout[5]~31 0xc0 1.33182e+07 0.492188; - dout[6] 0xc0 1.92012e+07 0.5; - dout[6]~32 0xc0 1.41329e+07 0.5; - dout[6]~33 0xc0 1.28995e+07 0.503906; - dout[7] 0xc0 1.92012e+07 0.5; - dout[7]~34 0xc0 1.40262e+07 0.5; - dout[7]~35 0xc0 1.30982e+07 0.498047; - dout[8] 0xc0 1.92012e+07 0.5; - dout[8]~36 0xc0 1.40754e+07 0.5; - dout[8]~37 0xc0 1.2996e+07 0.500977; - dout[9] 0xc0 1.92012e+07 0.5; - dout[9]~38 0xc0 1.40497e+07 0.5; - dout[9]~39 0xc0 1.30464e+07 0.499512; - dout[10] 0xc0 1.92012e+07 0.5; - dout[10]~40 0xc0 1.40623e+07 0.5; - dout[10]~41 0xc0 1.3021e+07 0.500244; - dout[11] 0xc0 1.92012e+07 0.5; - dout[11]~42 0xc0 1.40559e+07 0.5; - dout[11]~43 0xc0 1.30336e+07 0.499878; - dout[12] 0xc0 1.92012e+07 0.5; - dout[12]~44 0xc0 1.40591e+07 0.5; - dout[12]~45 0xc0 1.30273e+07 0.500061; - dout[13] 0xc0 1.92012e+07 0.5; - dout[13]~46 0xc0 1.40575e+07 0.5; - dout[13]~47 0xc0 1.30305e+07 0.499969; - dout[14] 0xc0 1.92012e+07 0.5; - dout[14]~48 0xc0 1.40583e+07 0.5; - dout[14]~49 0xc0 1.30289e+07 0.500015; - dout[15] 0xc0 1.92012e+07 0.5; - dout[15]~50 0xc0 1.40579e+07 0.5; - dout[15]~51 0xc0 1.30297e+07 0.499992; - dout[16] 0xc0 1.92012e+07 0.5; - dout[16]~52 0xc0 1.40581e+07 0.5; - dout[16]~53 0xc0 1.30293e+07 0.500004; - dout[17] 0xc0 1.92012e+07 0.5; - dout[17]~54 0xc0 1.4058e+07 0.5; - dout[17]~55 0xc0 1.30295e+07 0.499998; - dout[18] 0xc0 1.92012e+07 0.5; - dout[18]~56 0xc0 1.40581e+07 0.5; - dout[18]~57 0xc0 1.30294e+07 0.500001; - dout[19] 0xc0 1.92012e+07 0.5; - dout[19]~58 0xc0 1.4058e+07 0.5; - dout[74]~60 0xc0 1.44009e+07 0.25; - dout_valid 0xc0 1.92012e+07 0.5; - auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][16] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][16]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][17] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][17]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][18] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][18]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][19] 0xc0 1.92012e+07 0.5; - dout[0] 0xc0 1.92012e+07 0.5; - dout[0]~21 0xc0 1.92012e+07 0.5; - dout[0]~22 0xc0 1.08007e+07 0.75; - dout[1] 0xc0 1.92012e+07 0.5; - dout[1]~23 0xc0 1.6201e+07 0.5; - dout[1]~24 0xc0 8.94432e+06 0.375; - dout[2] 0xc0 1.92012e+07 0.5; - dout[2]~25 0xc0 1.37118e+07 0.5; - dout[2]~26 0xc0 1.05311e+07 0.5625; - dout[3] 0xc0 1.92012e+07 0.5; - dout[3]~27 0xc0 1.36022e+07 0.5; - dout[3]~28 0xc0 1.42453e+07 0.46875; - dout[4] 0xc0 1.92012e+07 0.5; - dout[4]~29 0xc0 1.44042e+07 0.5; - dout[4]~30 0xc0 1.25509e+07 0.515625; - dout[5] 0xc0 1.92012e+07 0.5; - dout[5]~31 0xc0 1.3949e+07 0.5; - dout[5]~32 0xc0 1.33182e+07 0.492188; - dout[6] 0xc0 1.92012e+07 0.5; - dout[6]~33 0xc0 1.41329e+07 0.5; - dout[6]~34 0xc0 1.28995e+07 0.503906; - dout[7] 0xc0 1.92012e+07 0.5; - dout[7]~35 0xc0 1.40262e+07 0.5; - dout[7]~36 0xc0 1.30982e+07 0.498047; - dout[8] 0xc0 1.92012e+07 0.5; - dout[8]~37 0xc0 1.40754e+07 0.5; - dout[8]~38 0xc0 1.2996e+07 0.500977; - dout[9] 0xc0 1.92012e+07 0.5; - dout[9]~39 0xc0 1.40497e+07 0.5; - dout[9]~40 0xc0 1.30464e+07 0.499512; - dout[10] 0xc0 1.92012e+07 0.5; - dout[10]~41 0xc0 1.40623e+07 0.5; - dout[10]~42 0xc0 1.3021e+07 0.500244; - dout[11] 0xc0 1.92012e+07 0.5; - dout[11]~43 0xc0 1.40559e+07 0.5; - dout[11]~44 0xc0 1.30336e+07 0.499878; - dout[12] 0xc0 1.92012e+07 0.5; - dout[12]~45 0xc0 1.40591e+07 0.5; - dout[12]~46 0xc0 1.30273e+07 0.500061; - dout[13] 0xc0 1.92012e+07 0.5; - dout[13]~47 0xc0 1.40575e+07 0.5; - dout[13]~48 0xc0 1.30305e+07 0.499969; - dout[14] 0xc0 1.92012e+07 0.5; - dout[14]~49 0xc0 1.40583e+07 0.5; - dout[14]~50 0xc0 1.30289e+07 0.500015; - dout[15] 0xc0 1.92012e+07 0.5; - dout[15]~51 0xc0 1.40579e+07 0.5; - dout[15]~52 0xc0 1.30297e+07 0.499992; - dout[16] 0xc0 1.92012e+07 0.5; - dout[16]~53 0xc0 1.40581e+07 0.5; - dout[16]~54 0xc0 1.30293e+07 0.500004; - dout[17] 0xc0 1.92012e+07 0.5; - dout[17]~55 0xc0 1.4058e+07 0.5; - dout[17]~56 0xc0 1.30295e+07 0.499998; - dout[18] 0xc0 1.92012e+07 0.5; - dout[18]~57 0xc0 1.40581e+07 0.5; - dout[18]~58 0xc0 1.30294e+07 0.500001; - dout[19] 0xc0 1.92012e+07 0.5; - dout[19]~59 0xc0 1.4058e+07 0.5; - dout[19]~60 0xc0 1.30294e+07 0.5; - dout[74] 0xc0 1.92012e+07 0.5; - dout[74]~61 0xc0 1.4058e+07 0.5; - dout[74]~63 0xc0 1.44009e+07 0.25; - dout_valid 0xc0 1.92012e+07 0.5; - auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][16] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][16]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][17] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][17]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][18] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][18]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][19] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74] 0xc0 1.92012e+07 0.5; - dout[0] 0xc0 1.92012e+07 0.5; - dout[0]~22 0xc0 1.92012e+07 0.5; - dout[0]~23 0xc0 1.08007e+07 0.75; - dout[1] 0xc0 1.92012e+07 0.5; - dout[1]~24 0xc0 1.6201e+07 0.5; - dout[1]~25 0xc0 8.94432e+06 0.375; - dout[1]~feeder 0xc0 1.6201e+07 0.5; - dout[2] 0xc0 1.92012e+07 0.5; - dout[2]~26 0xc0 1.37118e+07 0.5; - dout[2]~27 0xc0 1.05311e+07 0.5625; - dout[3] 0xc0 1.92012e+07 0.5; - dout[3]~28 0xc0 1.36022e+07 0.5; - dout[3]~29 0xc0 1.42453e+07 0.46875; - dout[4] 0xc0 1.92012e+07 0.5; - dout[4]~30 0xc0 1.44042e+07 0.5; - dout[4]~31 0xc0 1.25509e+07 0.515625; - dout[5] 0xc0 1.92012e+07 0.5; - dout[5]~32 0xc0 1.3949e+07 0.5; - dout[5]~33 0xc0 1.33182e+07 0.492188; - dout[6] 0xc0 1.92012e+07 0.5; - dout[6]~34 0xc0 1.41329e+07 0.5; - dout[6]~35 0xc0 1.28995e+07 0.503906; - dout[7] 0xc0 1.92012e+07 0.5; - dout[7]~36 0xc0 1.40262e+07 0.5; - dout[7]~37 0xc0 1.30982e+07 0.498047; - dout[8] 0xc0 1.92012e+07 0.5; - dout[8]~38 0xc0 1.40754e+07 0.5; - dout[8]~39 0xc0 1.2996e+07 0.500977; - dout[9] 0xc0 1.92012e+07 0.5; - dout[9]~40 0xc0 1.40497e+07 0.5; - dout[9]~41 0xc0 1.30464e+07 0.499512; - dout[10] 0xc0 1.92012e+07 0.5; - dout[10]~42 0xc0 1.40623e+07 0.5; - dout[10]~43 0xc0 1.3021e+07 0.500244; - dout[11] 0xc0 1.92012e+07 0.5; - dout[11]~44 0xc0 1.40559e+07 0.5; - dout[11]~45 0xc0 1.30336e+07 0.499878; - dout[12] 0xc0 1.92012e+07 0.5; - dout[12]~46 0xc0 1.40591e+07 0.5; - dout[12]~47 0xc0 1.30273e+07 0.500061; - dout[13] 0xc0 1.92012e+07 0.5; - dout[13]~48 0xc0 1.40575e+07 0.5; - dout[13]~49 0xc0 1.30305e+07 0.499969; - dout[14] 0xc0 1.92012e+07 0.5; - dout[14]~50 0xc0 1.40583e+07 0.5; - dout[14]~51 0xc0 1.30289e+07 0.500015; - dout[15] 0xc0 1.92012e+07 0.5; - dout[15]~52 0xc0 1.40579e+07 0.5; - dout[15]~53 0xc0 1.30297e+07 0.499992; - dout[16] 0xc0 1.92012e+07 0.5; - dout[16]~54 0xc0 1.40581e+07 0.5; - dout[16]~55 0xc0 1.30293e+07 0.500004; - dout[17] 0xc0 1.92012e+07 0.5; - dout[17]~56 0xc0 1.4058e+07 0.5; - dout[17]~57 0xc0 1.30295e+07 0.499998; - dout[18] 0xc0 1.92012e+07 0.5; - dout[18]~58 0xc0 1.40581e+07 0.5; - dout[18]~59 0xc0 1.30294e+07 0.500001; - dout[19] 0xc0 1.92012e+07 0.5; - dout[19]~60 0xc0 1.4058e+07 0.5; - dout[19]~61 0xc0 1.30294e+07 0.5; - dout[20] 0xc0 1.92012e+07 0.5; - dout[20]~62 0xc0 1.4058e+07 0.5; - dout[20]~63 0xc0 1.30294e+07 0.5; - dout[74] 0xc0 1.92012e+07 0.5; - dout[74]~64 0xc0 1.76583e+07 0.5; - dout[74]~66 0xc0 1.44009e+07 0.25; - dout_valid 0xc0 1.92012e+07 0.5; - dout_valid~feeder 0xc0 1.92012e+07 0.5; - Equal0~0 0xc0 5.70036e+06 0.125; - Equal0~1 0xc0 2.36265e+06 0.0625; - Equal0~2 0xc0 2.36265e+06 0.0625; - Equal0~3 0xc0 674.035 0.000244141; - counter_module:counter_fs_inst; - Add0~0 0xc0 1.92012e+07 0.5; - Add0~1 0xc0 1.92012e+07 0.5; - Add0~2 0xc0 1.92012e+07 0.5; - Add0~3 0xc0 1.08007e+07 0.75; - Add0~4 0xc0 1.74011e+07 0.5; - Add0~5 0xc0 1.47009e+07 0.125; - Add0~6 0xc0 2.23514e+07 0.5; - Add0~7 0xc0 4.27527e+06 0.9375; - Add0~8 0xc0 1.90887e+07 0.5; - Add0~9 0xc0 1.80199e+07 0.03125; - Add0~10 0xc0 2.70486e+07 0.5; - Add0~11 0xc0 4.54248e+06 0.984375; - Add0~12 0xc0 2.08818e+07 0.5; - Add0~13 0xc0 1.97462e+07 0.0078125; - Add0~14 0xc0 2.87766e+07 0.5; - Add0~15 0xc0 4.93889e+06 0.996094; - Add0~16 0xc0 2.15213e+07 0.5; - Add0~17 0xc0 2.02865e+07 0.00195313; - Add0~18 0xc0 2.92696e+07 0.5; - Add0~19 0xc0 5.07178e+06 0.999023; - Add0~20 0xc0 2.16997e+07 0.5; - Add0~21 0xc0 2.04317e+07 0.000488281; - Add0~22 0xc0 2.93983e+07 0.5; - Equal0~0 0xc0 1.7298e+06 0.0625; - Equal0~1 0xc0 1.7298e+06 0.0625; - Equal0~2 0xc0 445.47 0.000244141; - count[0] 0xc0 1.92012e+07 0.5; - count[1] 0xc0 1.92012e+07 0.5; - count[2] 0xc0 1.92012e+07 0.5; - count[3] 0xc0 1.92012e+07 0.5; - count[4] 0xc0 1.92012e+07 0.5; - count[5] 0xc0 1.92012e+07 0.5; - count[6] 0xc0 1.92012e+07 0.5; - count[7] 0xc0 1.92012e+07 0.5; - count[8] 0xc0 1.92012e+07 0.5; - count[9] 0xc0 1.92012e+07 0.5; - count[10] 0xc0 1.92012e+07 0.5; - count[11] 0xc0 1.92012e+07 0.5; - count~0 0xc0 2.87628e+07 0.499878; - count~1 0xc0 4.33782e+07 0.499878; - count~2 0xc0 5.87681e+07 0.499878; - auk_dspip_upsample:first_upsample; - dout[0]~21 0xc0 1.44009e+07 0.25; - dout[1]~20 0xc0 1.44009e+07 0.25; - dout[2]~19 0xc0 1.44009e+07 0.25; - dout[3]~18 0xc0 1.44009e+07 0.25; - dout[4]~17 0xc0 1.44009e+07 0.25; - dout[5]~16 0xc0 1.44009e+07 0.25; - dout[6]~15 0xc0 1.44009e+07 0.25; - dout[7]~14 0xc0 1.44009e+07 0.25; - dout[8]~13 0xc0 1.44009e+07 0.25; - dout[9]~12 0xc0 1.44009e+07 0.25; - dout[10]~11 0xc0 1.44009e+07 0.25; - dout[11]~10 0xc0 1.44009e+07 0.25; - dout[12]~9 0xc0 1.44009e+07 0.25; - dout[13]~8 0xc0 1.44009e+07 0.25; - dout[14]~7 0xc0 1.44009e+07 0.25; - dout[15]~6 0xc0 1.44009e+07 0.25; - dout[16]~5 0xc0 1.44009e+07 0.25; - dout[17]~4 0xc0 1.44009e+07 0.25; - dout[18]~3 0xc0 1.44009e+07 0.25; - dout[19]~2 0xc0 1.44009e+07 0.25; - dout[20]~1 0xc0 1.44009e+07 0.25; - dout[59]~0 0xc0 1.44009e+07 0.25; - auk_dspip_integrator:integrator_loop[0].auK_integrator; - auk_dspip_delay:\glogic:integrator_pipeline_0_generate:u1; - \register_fifo:fifo_data[0][0] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][0]~1 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][0]~2 0xc0 8.40054e+06 0.125; - \register_fifo:fifo_data[0][1] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1]~1 0xc0 1.90325e+07 0.5; - \register_fifo:fifo_data[0][1]~2 0xc0 6.53948e+06 0.8125; - \register_fifo:fifo_data[0][2] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2]~1 0xc0 2.37387e+07 0.5; - \register_fifo:fifo_data[0][2]~2 0xc0 3.58146e+07 0.21875; - \register_fifo:fifo_data[0][3] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3]~1 0xc0 3.17293e+07 0.5; - \register_fifo:fifo_data[0][3]~2 0xc0 1.22879e+07 0.765625; - \register_fifo:fifo_data[0][4] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4]~1 0xc0 2.07664e+07 0.5; - \register_fifo:fifo_data[0][4]~2 0xc0 1.57317e+07 0.242188; - \register_fifo:fifo_data[0][5] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5]~1 0xc0 2.16267e+07 0.5; - \register_fifo:fifo_data[0][5]~2 0xc0 1.01482e+07 0.753906; - \register_fifo:fifo_data[0][6] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6]~1 0xc0 2.27954e+07 0.5; - \register_fifo:fifo_data[0][6]~2 0xc0 3.65065e+07 0.248047; - \register_fifo:fifo_data[0][7] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7]~1 0xc0 2.79611e+07 0.5; - \register_fifo:fifo_data[0][7]~2 0xc0 1.54433e+07 0.750977; - \register_fifo:fifo_data[0][8] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8]~1 0xc0 2.43578e+07 0.5; - \register_fifo:fifo_data[0][8]~2 0xc0 3.71321e+07 0.249512; - \register_fifo:fifo_data[0][9] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9]~1 0xc0 3.11203e+07 0.5; - \register_fifo:fifo_data[0][9]~2 0xc0 1.28459e+07 0.750244; - \register_fifo:fifo_data[0][10] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10]~1 0xc0 2.35232e+07 0.5; - \register_fifo:fifo_data[0][10]~2 0xc0 3.66761e+07 0.249878; - \register_fifo:fifo_data[0][11] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11]~1 0xc0 3.09663e+07 0.5; - \register_fifo:fifo_data[0][11]~2 0xc0 1.27795e+07 0.750061; - \register_fifo:fifo_data[0][12] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12]~1 0xc0 1.71207e+07 0.5; - \register_fifo:fifo_data[0][12]~2 0xc0 3.66532e+07 0.249969; - \register_fifo:fifo_data[0][13] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13]~1 0xc0 3.09563e+07 0.5; - \register_fifo:fifo_data[0][13]~2 0xc0 1.27771e+07 0.750015; - \register_fifo:fifo_data[0][14] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14]~1 0xc0 1.7119e+07 0.5; - \register_fifo:fifo_data[0][14]~2 0xc0 1.85355e+07 0.249992; - \register_fifo:fifo_data[0][15] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15]~1 0xc0 2.22936e+07 0.5; - \register_fifo:fifo_data[0][15]~2 0xc0 1.26467e+07 0.750004; - \register_fifo:fifo_data[0][16] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][16]~1 0xc0 1.7078e+07 0.5; - \register_fifo:fifo_data[0][16]~2 0xc0 3.66285e+07 0.249998; - \register_fifo:fifo_data[0][17] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][17]~1 0xc0 2.79475e+07 0.5; - \register_fifo:fifo_data[0][17]~2 0xc0 1.54738e+07 0.750001; - \register_fifo:fifo_data[0][18] 0xc0 1.92012e+07 0.5; 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- \register_fifo:fifo_data[0][61] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][61]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][61]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][62] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][62]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][62]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][63] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][63]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][63]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][64] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][64]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][64]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][65] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][65]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][65]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][66] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][66]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][66]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][67] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][67]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][67]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][68] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][68]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][68]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][69] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][69]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][69]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][70] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][70]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][70]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][71] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][71]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][71]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][72] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][72]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][72]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][73] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][73]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][73]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][74] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74]~1 0xc0 1.76583e+07 0.5; - sample_valid 0xc0 1.92012e+07 0.5; - auk_dspip_avalon_streaming_source:output_source_0; - scfifo:source_FIFO; - scfifo_ci71:auto_generated; - dffe_af 0xc0 1.92012e+07 0.5; - dffe_af~0 0xc0 2.01107e+06 0.0625; - dffe_af~1 0xc0 5.48473e+06 0.25; - dffe_af~2 0xc0 2.16354e+07 0.5; - a_dpfifo_9qv:dpfifo; - _~0 0xc0 3.37522e+06 0.0625; - _~1 0xc0 6.60042e+06 0.125; - _~2 0xc0 1.20409e+07 0.314941; - _~3 0xc0 1.32585e+07 0.578125; - _~4 0xc0 1.76172e+07 0.509035; - _~5 0xc0 3.83931e+06 0.1875; - _~6 0xc0 7.93879e+06 0.4375; - empty_dff 0xc0 1.92012e+07 0.5; - altsyncram_hah1:FIFOram; - q_b[0] 0xc0 1.92012e+07 0.5; - q_b[1] 0xc0 1.92012e+07 0.5; - q_b[2] 0xc0 1.92012e+07 0.5; - q_b[3] 0xc0 1.92012e+07 0.5; - q_b[4] 0xc0 1.92012e+07 0.5; - q_b[5] 0xc0 1.92012e+07 0.5; - q_b[6] 0xc0 1.92012e+07 0.5; - q_b[7] 0xc0 1.92012e+07 0.5; - q_b[8] 0xc0 1.92012e+07 0.5; - q_b[9] 0xc0 1.92012e+07 0.5; - q_b[10] 0xc0 1.92012e+07 0.5; - q_b[11] 0xc0 1.92012e+07 0.5; - q_b[12] 0xc0 1.92012e+07 0.5; - q_b[13] 0xc0 1.92012e+07 0.5; - q_b[14] 0xc0 1.92012e+07 0.5; - q_b[15] 0xc0 1.92012e+07 0.5; - full_dff 0xc0 1.92012e+07 0.5; - low_addressa[0] 0xc0 1.92012e+07 0.5; - low_addressa[1] 0xc0 1.92012e+07 0.5; - low_addressa[2] 0xc0 1.92012e+07 0.5; - low_addressa[3] 0xc0 1.92012e+07 0.5; - low_addressa[4] 0xc0 1.92012e+07 0.5; - ram_read_address[0]~0 0xc0 1.05382e+07 0.5; - ram_read_address[1]~1 0xc0 8.97714e+06 0.5; - ram_read_address[2]~2 0xc0 8.97714e+06 0.5; - ram_read_address[3]~3 0xc0 8.00149e+06 0.5; - ram_read_address[4]~4 0xc0 8.97714e+06 0.5; - rd_ptr_lsb 0xc0 1.92012e+07 0.5; - rd_ptr_lsb~0 0xc0 1.92012e+07 0.5; - cntr_t9b:rd_ptr_msb; - counter_comb_bita0 0xc0 1.92012e+07 0.5; - counter_comb_bita0~COUT 0xc0 1.92012e+07 0.5; - counter_comb_bita1 0xc0 1.92012e+07 0.5; - counter_comb_bita1~COUT 0xc0 1.08007e+07 0.75; - counter_comb_bita2 0xc0 1.74011e+07 0.5; - counter_comb_bita2~COUT 0xc0 1.47009e+07 0.125; - counter_comb_bita3 0xc0 2.23514e+07 0.5; - counter_reg_bit[0] 0xc0 1.92012e+07 0.5; - counter_reg_bit[1] 0xc0 1.92012e+07 0.5; - counter_reg_bit[2] 0xc0 1.92012e+07 0.5; - counter_reg_bit[3] 0xc0 1.92012e+07 0.5; - cntr_aa7:usedw_counter; - counter_comb_bita0 0xc0 1.92012e+07 0.5; - counter_comb_bita0~COUT 0xc0 1.92012e+07 0.5; - counter_comb_bita1 0xc0 1.92012e+07 0.5; - counter_comb_bita1~COUT 0xc0 1.42509e+07 0.75; - counter_comb_bita2 0xc0 1.91262e+07 0.5; - counter_comb_bita2~COUT 0xc0 2.09779e+07 0.125; - counter_comb_bita3 0xc0 2.54899e+07 0.5; - counter_comb_bita3~COUT 0xc0 4.06535e+06 0.9375; - counter_comb_bita4 0xc0 1.89838e+07 0.5; - counter_reg_bit[0] 0xc0 1.92012e+07 0.5; - counter_reg_bit[1] 0xc0 1.92012e+07 0.5; - counter_reg_bit[2] 0xc0 1.92012e+07 0.5; - counter_reg_bit[3] 0xc0 1.92012e+07 0.5; - counter_reg_bit[4] 0xc0 1.92012e+07 0.5; - usedw_is_0_dff 0xc0 1.92012e+07 0.5; - usedw_is_1_dff 0xc0 1.92012e+07 0.5; - usedw_will_be_1~0 0xc0 1.7298e+06 0.0625; - usedw_will_be_1~1 0xc0 8.32634e+06 0.324219; - usedw_will_be_1~2 0xc0 1.64359e+07 0.478027; - valid_wreq 0xc0 1.44009e+07 0.75; - cntr_u9b:wr_ptr; - counter_comb_bita0 0xc0 1.92012e+07 0.5; - counter_comb_bita0~COUT 0xc0 1.92012e+07 0.5; - counter_comb_bita1 0xc0 1.92012e+07 0.5; - counter_comb_bita1~COUT 0xc0 1.08007e+07 0.75; - counter_comb_bita2 0xc0 1.74011e+07 0.5; - counter_comb_bita2~COUT 0xc0 1.47009e+07 0.125; - counter_comb_bita3 0xc0 2.23514e+07 0.5; - counter_comb_bita3~COUT 0xc0 4.27527e+06 0.9375; - counter_comb_bita4 0xc0 1.90887e+07 0.5; - counter_reg_bit[0] 0xc0 1.92012e+07 0.5; - counter_reg_bit[1] 0xc0 1.92012e+07 0.5; - counter_reg_bit[2] 0xc0 1.92012e+07 0.5; - counter_reg_bit[3] 0xc0 1.92012e+07 0.5; - counter_reg_bit[4] 0xc0 1.92012e+07 0.5; - source_valid_s 0xc0 1.92012e+07 0.5; - source_valid_s_process~0 0xc0 8.32553e+06 0.375; - source_valid_s_process~1 0xc0 8.32553e+06 0.625; - tx_cic:TX_CIC_Q; - tx_cic_cic_ii_0:cic_ii_0; - alt_cic_core:core; - auk_dspip_avalon_streaming_controller:avalon_controller; - auk_dspip_avalon_streaming_small_fifo:ready_FIFO; - Equal2~0 0xc0 5.70036e+06 0.125; - fifo_array[0][0] 0xc0 1.92012e+07 0.5; - fifo_array[0][0]~4 0xc0 5.70036e+06 0.875; - fifo_array[0][0]~5 0xc0 1.23258e+07 0.5; - fifo_array[1][0] 0xc0 1.92012e+07 0.5; - fifo_array[1][0]~2 0xc0 4.57529e+06 0.125; - fifo_array[1][0]~3 0xc0 1.19837e+07 0.5; - fifo_array[2][0] 0xc0 1.92012e+07 0.5; - fifo_array[2][0]~0 0xc0 4.57529e+06 0.125; - fifo_array[2][0]~1 0xc0 1.19837e+07 0.5; - fifo_array[3][0] 0xc0 1.92012e+07 0.5; - fifo_array[3][0]~6 0xc0 1.19837e+07 0.5; - fifo_array[4][0] 0xc0 1.92012e+07 0.5; - fifo_array[4][0]~8 0xc0 5.70036e+06 0.125; - fifo_array[4][0]~9 0xc0 1.23258e+07 0.5; - fifo_array[5][0] 0xc0 1.92012e+07 0.5; - fifo_array[5][0]~7 0xc0 1.1346e+07 0.5; - fifo_usedw[0] 0xc0 1.92012e+07 0.5; - fifo_usedw[0]~3 0xc0 1.48893e+07 0.5; - fifo_usedw[1] 0xc0 1.92012e+07 0.5; - fifo_usedw[2] 0xc0 1.92012e+07 0.5; - fifo_usedw~0 0xc0 1.5526e+07 0.328125; - fifo_usedw~1 0xc0 1.45697e+07 0.28125; - fifo_usedw~2 0xc0 1.15498e+07 0.452759; - fifo_usedw~4 0xc0 1.28297e+07 0.5; - Mux0~0 0xc0 8.62555e+06 0.5; - Mux0~1 0xc0 8.07181e+06 0.5; - rd_addr_ptr[0] 0xc0 1.92012e+07 0.5; - rd_addr_ptr[0]~2 0xc0 1.92012e+07 0.5; - rd_addr_ptr[1] 0xc0 1.92012e+07 0.5; - rd_addr_ptr[2] 0xc0 1.92012e+07 0.5; - rd_addr_ptr~0 0xc0 1.05757e+07 0.375; - rd_addr_ptr~1 0xc0 1.35009e+07 0.375; - usedw_process~0 0xc0 1.79449e+07 0.4375; - usedw_process~1 0xc0 9.09316e+06 0.21875; - usedw_process~2 0xc0 1.48371e+07 0.423828; - wr_addr_ptr[0] 0xc0 1.92012e+07 0.5; - wr_addr_ptr[0]~4 0xc0 1.92012e+07 0.5; - wr_addr_ptr[1] 0xc0 1.92012e+07 0.5; - wr_addr_ptr[2] 0xc0 1.92012e+07 0.5; - wr_addr_ptr~0 0xc0 4.57529e+06 0.125; - wr_addr_ptr~1 0xc0 5.70036e+06 0.875; - wr_addr_ptr~2 0xc0 1.35009e+07 0.375; - wr_addr_ptr~3 0xc0 1.05757e+07 0.375; - sink_ready_ctrl~0 0xc0 7.02115e+06 0.234375; - sink_ready_ctrl~1 0xc0 6.1879e+06 0.25; - sink_ready_ctrl~2 0xc0 2.06782e+07 0.191406; - sink_ready_ctrl~3 0xc0 3.98882e+06 0.200729; - stall_reg 0xc0 1.92012e+07 0.5; - stall_w~0 0xc0 1.08007e+07 0.75; - auk_dspip_avalon_streaming_sink:input_sink; - data_valid 0xc0 1.92012e+07 0.5; - scfifo:sink_FIFO; - scfifo_gf71:auto_generated; - dffe_nae 0xc0 1.92012e+07 0.5; - dffe_nae~0 0xc0 4.6878e+06 0.125; - dffe_nae~1 0xc0 1.45889e+07 0.503079; - a_dpfifo_1lv:dpfifo; - _~0 0xc0 7.6405e+06 0.200274; - _~1 0xc0 813333 0.03125; - _~2 0xc0 9.91621e+06 0.463874; - _~3 0xc0 1.7037e+07 0.556227; - _~4 0xc0 1.55731e+07 0.399863; - _~5 0xc0 1.7298e+06 0.0625; - _~6 0xc0 8.34675e+06 0.525621; - _~7 0xc0 7.58433e+06 0.0501823; - empty_dff 0xc0 1.92012e+07 0.5; - altsyncram_l7h1:FIFOram; - q_b[0] 0xc0 1.92012e+07 0.5; - q_b[1] 0xc0 1.92012e+07 0.5; - q_b[2] 0xc0 1.92012e+07 0.5; - q_b[3] 0xc0 1.92012e+07 0.5; - q_b[4] 0xc0 1.92012e+07 0.5; - q_b[5] 0xc0 1.92012e+07 0.5; - q_b[6] 0xc0 1.92012e+07 0.5; - q_b[7] 0xc0 1.92012e+07 0.5; - q_b[8] 0xc0 1.92012e+07 0.5; - q_b[9] 0xc0 1.92012e+07 0.5; - q_b[10] 0xc0 1.92012e+07 0.5; - q_b[11] 0xc0 1.92012e+07 0.5; - q_b[12] 0xc0 1.92012e+07 0.5; - q_b[13] 0xc0 1.92012e+07 0.5; - q_b[14] 0xc0 1.92012e+07 0.5; - q_b[15] 0xc0 1.92012e+07 0.5; - full_dff 0xc0 1.92012e+07 0.5; - low_addressa[0] 0xc0 1.92012e+07 0.5; - low_addressa[1] 0xc0 1.92012e+07 0.5; - low_addressa[2] 0xc0 1.92012e+07 0.5; - ram_read_address[0]~0 0xc0 1.09632e+07 0.5; - ram_read_address[1]~1 0xc0 7.96446e+06 0.5; - ram_read_address[2]~2 0xc0 7.96446e+06 0.5; - rd_ptr_lsb 0xc0 1.92012e+07 0.5; - rd_ptr_lsb~0 0xc0 1.92012e+07 0.5; - cntr_r9b:rd_ptr_msb; - counter_comb_bita0 0xc0 1.92012e+07 0.5; - counter_comb_bita0~COUT 0xc0 1.92012e+07 0.5; - counter_comb_bita1 0xc0 1.92012e+07 0.5; - counter_reg_bit[0] 0xc0 1.92012e+07 0.5; - counter_reg_bit[1] 0xc0 1.92012e+07 0.5; - cntr_8a7:usedw_counter; - counter_comb_bita0 0xc0 1.92012e+07 0.5; - counter_comb_bita0~COUT 0xc0 1.72886e+07 0.5; - counter_comb_bita1 0xc0 1.82449e+07 0.5; - counter_comb_bita1~COUT 0xc0 1.17208e+07 0.75; - counter_comb_bita2 0xc0 1.78612e+07 0.5; - counter_reg_bit[0] 0xc0 1.92012e+07 0.5; - counter_reg_bit[1] 0xc0 1.92012e+07 0.5; - counter_reg_bit[2] 0xc0 1.92012e+07 0.5; - usedw_is_0_dff 0xc0 1.92012e+07 0.5; - usedw_is_1_dff 0xc0 1.92012e+07 0.5; - usedw_will_be_1~0 0xc0 3.70961e+06 0.109375; - usedw_will_be_1~1 0xc0 1.64012e+07 0.440195; - valid_rreq 0xc0 1.40373e+07 0.100365; - valid_wreq 0xc0 4.57529e+06 0.125; - cntr_s9b:wr_ptr; - counter_comb_bita0 0xc0 1.92012e+07 0.5; - counter_comb_bita0~COUT 0xc0 1.92012e+07 0.5; - counter_comb_bita1 0xc0 1.92012e+07 0.5; - counter_comb_bita1~COUT 0xc0 1.08007e+07 0.75; - counter_comb_bita2 0xc0 1.74011e+07 0.5; - counter_reg_bit[0] 0xc0 1.92012e+07 0.5; - counter_reg_bit[1] 0xc0 1.92012e+07 0.5; - counter_reg_bit[2] 0xc0 1.92012e+07 0.5; - alt_cic_int_siso:int_one; - auk_dspip_differentiator:COMB_LOOP[0].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 1.92012e+07 0.5; - dout[0] 0xc0 1.92012e+07 0.5; - dout[0]~17 0xc0 1.92012e+07 0.5; - dout[0]~18 0xc0 1.08007e+07 0.75; - dout[0]~51 0xc0 1.44009e+07 0.25; - dout[0]~feeder 0xc0 1.92012e+07 0.5; - dout[1] 0xc0 1.92012e+07 0.5; - dout[1]~19 0xc0 1.6201e+07 0.5; - dout[1]~20 0xc0 8.94432e+06 0.375; - dout[2] 0xc0 1.92012e+07 0.5; - dout[2]~21 0xc0 1.37118e+07 0.5; - dout[2]~22 0xc0 1.05311e+07 0.5625; - dout[3] 0xc0 1.92012e+07 0.5; - dout[3]~23 0xc0 1.36022e+07 0.5; - dout[3]~24 0xc0 1.42453e+07 0.46875; - dout[4] 0xc0 1.92012e+07 0.5; - dout[4]~25 0xc0 1.44042e+07 0.5; - dout[4]~26 0xc0 1.25509e+07 0.515625; - dout[5] 0xc0 1.92012e+07 0.5; - dout[5]~27 0xc0 1.3949e+07 0.5; - dout[5]~28 0xc0 1.33182e+07 0.492188; - dout[6] 0xc0 1.92012e+07 0.5; - dout[6]~29 0xc0 1.41329e+07 0.5; - dout[6]~30 0xc0 1.28995e+07 0.503906; - dout[7] 0xc0 1.92012e+07 0.5; - dout[7]~31 0xc0 1.40262e+07 0.5; - dout[7]~32 0xc0 1.30982e+07 0.498047; - dout[8] 0xc0 1.92012e+07 0.5; - dout[8]~33 0xc0 1.40754e+07 0.5; - dout[8]~34 0xc0 1.2996e+07 0.500977; - dout[9] 0xc0 1.92012e+07 0.5; - dout[9]~35 0xc0 1.40497e+07 0.5; - dout[9]~36 0xc0 1.30464e+07 0.499512; - dout[10] 0xc0 1.92012e+07 0.5; - dout[10]~37 0xc0 1.40623e+07 0.5; - dout[10]~38 0xc0 1.3021e+07 0.500244; - dout[11] 0xc0 1.92012e+07 0.5; - dout[11]~39 0xc0 1.40559e+07 0.5; - dout[11]~40 0xc0 1.30336e+07 0.499878; - dout[12] 0xc0 1.92012e+07 0.5; - dout[12]~41 0xc0 1.40591e+07 0.5; - dout[12]~42 0xc0 1.30273e+07 0.500061; - dout[13] 0xc0 1.92012e+07 0.5; - dout[13]~43 0xc0 1.40575e+07 0.5; - dout[13]~44 0xc0 1.30305e+07 0.499969; - dout[14] 0xc0 1.92012e+07 0.5; - dout[14]~45 0xc0 1.40583e+07 0.5; - dout[14]~46 0xc0 1.30289e+07 0.500015; - dout[15] 0xc0 1.92012e+07 0.5; - dout[15]~47 0xc0 1.40579e+07 0.5; - dout[15]~48 0xc0 1.30297e+07 0.499992; - dout[16] 0xc0 1.92012e+07 0.5; - dout[16]~49 0xc0 1.40581e+07 0.5; - dout_valid 0xc0 1.92012e+07 0.5; - auk_dspip_differentiator:COMB_LOOP[1].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 1.92012e+07 0.5; - dout[0] 0xc0 1.92012e+07 0.5; - dout[0]~18 0xc0 1.92012e+07 0.5; - dout[0]~19 0xc0 1.08007e+07 0.75; - dout[0]~feeder 0xc0 1.92012e+07 0.5; - dout[1] 0xc0 1.92012e+07 0.5; - dout[1]~20 0xc0 1.6201e+07 0.5; - dout[1]~21 0xc0 8.94432e+06 0.375; - dout[2] 0xc0 1.92012e+07 0.5; - dout[2]~22 0xc0 1.37118e+07 0.5; - dout[2]~23 0xc0 1.05311e+07 0.5625; - dout[3] 0xc0 1.92012e+07 0.5; - dout[3]~24 0xc0 1.36022e+07 0.5; - dout[3]~25 0xc0 1.42453e+07 0.46875; - dout[4] 0xc0 1.92012e+07 0.5; - dout[4]~26 0xc0 1.44042e+07 0.5; - dout[4]~27 0xc0 1.25509e+07 0.515625; - dout[5] 0xc0 1.92012e+07 0.5; - dout[5]~28 0xc0 1.3949e+07 0.5; - dout[5]~29 0xc0 1.33182e+07 0.492188; - dout[6] 0xc0 1.92012e+07 0.5; - dout[6]~30 0xc0 1.41329e+07 0.5; - dout[6]~31 0xc0 1.28995e+07 0.503906; - dout[7] 0xc0 1.92012e+07 0.5; - dout[7]~32 0xc0 1.40262e+07 0.5; - dout[7]~33 0xc0 1.30982e+07 0.498047; - dout[8] 0xc0 1.92012e+07 0.5; - dout[8]~34 0xc0 1.40754e+07 0.5; - dout[8]~35 0xc0 1.2996e+07 0.500977; - dout[9] 0xc0 1.92012e+07 0.5; - dout[9]~36 0xc0 1.40497e+07 0.5; - dout[9]~37 0xc0 1.30464e+07 0.499512; - dout[10] 0xc0 1.92012e+07 0.5; - dout[10]~38 0xc0 1.40623e+07 0.5; - dout[10]~39 0xc0 1.3021e+07 0.500244; - dout[11] 0xc0 1.92012e+07 0.5; - dout[11]~40 0xc0 1.40559e+07 0.5; - dout[11]~41 0xc0 1.30336e+07 0.499878; - dout[12] 0xc0 1.92012e+07 0.5; - dout[12]~42 0xc0 1.40591e+07 0.5; - dout[12]~43 0xc0 1.30273e+07 0.500061; - dout[13] 0xc0 1.92012e+07 0.5; - dout[13]~44 0xc0 1.40575e+07 0.5; - dout[13]~45 0xc0 1.30305e+07 0.499969; - dout[14] 0xc0 1.92012e+07 0.5; - dout[14]~46 0xc0 1.40583e+07 0.5; - dout[14]~47 0xc0 1.30289e+07 0.500015; - dout[15] 0xc0 1.92012e+07 0.5; - dout[15]~48 0xc0 1.40579e+07 0.5; - dout[15]~49 0xc0 1.30297e+07 0.499992; - dout[16] 0xc0 1.92012e+07 0.5; - dout[16]~50 0xc0 1.40581e+07 0.5; - dout[16]~51 0xc0 1.30293e+07 0.500004; - dout[74] 0xc0 1.92012e+07 0.5; - dout[74]~52 0xc0 1.76582e+07 0.5; - dout[74]~54 0xc0 1.44009e+07 0.25; - dout_valid 0xc0 1.92012e+07 0.5; - auk_dspip_differentiator:COMB_LOOP[2].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][16] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74] 0xc0 1.92012e+07 0.5; - dout[0] 0xc0 1.92012e+07 0.5; - dout[0]~19 0xc0 1.92012e+07 0.5; - dout[0]~20 0xc0 1.08007e+07 0.75; - dout[0]~feeder 0xc0 1.92012e+07 0.5; - dout[1] 0xc0 1.92012e+07 0.5; - dout[1]~21 0xc0 1.6201e+07 0.5; - dout[1]~22 0xc0 8.94432e+06 0.375; - dout[2] 0xc0 1.92012e+07 0.5; - dout[2]~23 0xc0 1.37118e+07 0.5; - dout[2]~24 0xc0 1.05311e+07 0.5625; - dout[3] 0xc0 1.92012e+07 0.5; - dout[3]~25 0xc0 1.36022e+07 0.5; - dout[3]~26 0xc0 1.42453e+07 0.46875; - dout[4] 0xc0 1.92012e+07 0.5; - dout[4]~27 0xc0 1.44042e+07 0.5; - dout[4]~28 0xc0 1.25509e+07 0.515625; - dout[5] 0xc0 1.92012e+07 0.5; - dout[5]~29 0xc0 1.3949e+07 0.5; - dout[5]~30 0xc0 1.33182e+07 0.492188; - dout[6] 0xc0 1.92012e+07 0.5; - dout[6]~31 0xc0 1.41329e+07 0.5; - dout[6]~32 0xc0 1.28995e+07 0.503906; - dout[7] 0xc0 1.92012e+07 0.5; - dout[7]~33 0xc0 1.40262e+07 0.5; - dout[7]~34 0xc0 1.30982e+07 0.498047; - dout[8] 0xc0 1.92012e+07 0.5; - dout[8]~35 0xc0 1.40754e+07 0.5; - dout[8]~36 0xc0 1.2996e+07 0.500977; - dout[9] 0xc0 1.92012e+07 0.5; - dout[9]~37 0xc0 1.40497e+07 0.5; - dout[9]~38 0xc0 1.30464e+07 0.499512; - dout[10] 0xc0 1.92012e+07 0.5; - dout[10]~39 0xc0 1.40623e+07 0.5; - dout[10]~40 0xc0 1.3021e+07 0.500244; - dout[11] 0xc0 1.92012e+07 0.5; - dout[11]~41 0xc0 1.40559e+07 0.5; - dout[11]~42 0xc0 1.30336e+07 0.499878; - dout[12] 0xc0 1.92012e+07 0.5; - dout[12]~43 0xc0 1.40591e+07 0.5; - dout[12]~44 0xc0 1.30273e+07 0.500061; - dout[13] 0xc0 1.92012e+07 0.5; - dout[13]~45 0xc0 1.40575e+07 0.5; - dout[13]~46 0xc0 1.30305e+07 0.499969; - dout[14] 0xc0 1.92012e+07 0.5; - dout[14]~47 0xc0 1.40583e+07 0.5; - dout[14]~48 0xc0 1.30289e+07 0.500015; - dout[15] 0xc0 1.92012e+07 0.5; - dout[15]~49 0xc0 1.40579e+07 0.5; - dout[15]~50 0xc0 1.30297e+07 0.499992; - dout[16] 0xc0 1.92012e+07 0.5; - dout[16]~51 0xc0 1.40581e+07 0.5; - dout[16]~52 0xc0 1.30293e+07 0.500004; - dout[17] 0xc0 1.92012e+07 0.5; - dout[17]~53 0xc0 1.4058e+07 0.5; - dout[17]~54 0xc0 1.30295e+07 0.499998; - dout[74] 0xc0 1.92012e+07 0.5; - dout[74]~55 0xc0 1.76583e+07 0.5; - dout[74]~57 0xc0 1.44009e+07 0.25; - dout_valid 0xc0 1.92012e+07 0.5; - auk_dspip_differentiator:COMB_LOOP[3].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][16] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][17] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][17]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 1.92012e+07 0.5; - dout[0] 0xc0 1.92012e+07 0.5; - dout[0]~20 0xc0 1.92012e+07 0.5; - dout[0]~21 0xc0 1.08007e+07 0.75; - dout[1] 0xc0 1.92012e+07 0.5; - dout[1]~22 0xc0 1.6201e+07 0.5; - dout[1]~23 0xc0 8.94432e+06 0.375; - dout[2] 0xc0 1.92012e+07 0.5; - dout[2]~24 0xc0 1.37118e+07 0.5; - dout[2]~25 0xc0 1.05311e+07 0.5625; - dout[3] 0xc0 1.92012e+07 0.5; - dout[3]~26 0xc0 1.36022e+07 0.5; - dout[3]~27 0xc0 1.42453e+07 0.46875; - dout[4] 0xc0 1.92012e+07 0.5; - dout[4]~28 0xc0 1.44042e+07 0.5; - dout[4]~29 0xc0 1.25509e+07 0.515625; - dout[5] 0xc0 1.92012e+07 0.5; - dout[5]~30 0xc0 1.3949e+07 0.5; - dout[5]~31 0xc0 1.33182e+07 0.492188; - dout[6] 0xc0 1.92012e+07 0.5; - dout[6]~32 0xc0 1.41329e+07 0.5; - dout[6]~33 0xc0 1.28995e+07 0.503906; - dout[7] 0xc0 1.92012e+07 0.5; - dout[7]~34 0xc0 1.40262e+07 0.5; - dout[7]~35 0xc0 1.30982e+07 0.498047; - dout[8] 0xc0 1.92012e+07 0.5; - dout[8]~36 0xc0 1.40754e+07 0.5; - dout[8]~37 0xc0 1.2996e+07 0.500977; - dout[9] 0xc0 1.92012e+07 0.5; - dout[9]~38 0xc0 1.40497e+07 0.5; - dout[9]~39 0xc0 1.30464e+07 0.499512; - dout[10] 0xc0 1.92012e+07 0.5; - dout[10]~40 0xc0 1.40623e+07 0.5; - dout[10]~41 0xc0 1.3021e+07 0.500244; - dout[11] 0xc0 1.92012e+07 0.5; - dout[11]~42 0xc0 1.40559e+07 0.5; - dout[11]~43 0xc0 1.30336e+07 0.499878; - dout[12] 0xc0 1.92012e+07 0.5; - dout[12]~44 0xc0 1.40591e+07 0.5; - dout[12]~45 0xc0 1.30273e+07 0.500061; - dout[13] 0xc0 1.92012e+07 0.5; - dout[13]~46 0xc0 1.40575e+07 0.5; - dout[13]~47 0xc0 1.30305e+07 0.499969; - dout[14] 0xc0 1.92012e+07 0.5; - dout[14]~48 0xc0 1.40583e+07 0.5; - dout[14]~49 0xc0 1.30289e+07 0.500015; - dout[15] 0xc0 1.92012e+07 0.5; - dout[15]~50 0xc0 1.40579e+07 0.5; - dout[15]~51 0xc0 1.30297e+07 0.499992; - dout[16] 0xc0 1.92012e+07 0.5; - dout[16]~52 0xc0 1.40581e+07 0.5; - dout[16]~53 0xc0 1.30293e+07 0.500004; - dout[17] 0xc0 1.92012e+07 0.5; - dout[17]~54 0xc0 1.4058e+07 0.5; - dout[17]~55 0xc0 1.30295e+07 0.499998; - dout[18] 0xc0 1.92012e+07 0.5; - dout[18]~56 0xc0 1.40581e+07 0.5; - dout[18]~57 0xc0 1.30294e+07 0.500001; - dout[19] 0xc0 1.92012e+07 0.5; - dout[19]~58 0xc0 1.76583e+07 0.5; - dout[74]~60 0xc0 1.44009e+07 0.25; - dout_valid 0xc0 1.92012e+07 0.5; - auk_dspip_differentiator:COMB_LOOP[4].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][0]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][16] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][16]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][17] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][17]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][18] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][18]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][19] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][19]~feeder 0xc0 1.92012e+07 0.5; - dout[0] 0xc0 1.92012e+07 0.5; - dout[0]~21 0xc0 1.92012e+07 0.5; - dout[0]~22 0xc0 1.08007e+07 0.75; - dout[0]~feeder 0xc0 1.92012e+07 0.5; - dout[1] 0xc0 1.92012e+07 0.5; - dout[1]~23 0xc0 1.6201e+07 0.5; - dout[1]~24 0xc0 8.94432e+06 0.375; - dout[2] 0xc0 1.92012e+07 0.5; - dout[2]~25 0xc0 1.37118e+07 0.5; - dout[2]~26 0xc0 1.05311e+07 0.5625; - dout[3] 0xc0 1.92012e+07 0.5; - dout[3]~27 0xc0 1.36022e+07 0.5; - dout[3]~28 0xc0 1.42453e+07 0.46875; - dout[4] 0xc0 1.92012e+07 0.5; - dout[4]~29 0xc0 1.44042e+07 0.5; - dout[4]~30 0xc0 1.25509e+07 0.515625; - dout[5] 0xc0 1.92012e+07 0.5; - dout[5]~31 0xc0 1.3949e+07 0.5; - dout[5]~32 0xc0 1.33182e+07 0.492188; - dout[6] 0xc0 1.92012e+07 0.5; - dout[6]~33 0xc0 1.41329e+07 0.5; - dout[6]~34 0xc0 1.28995e+07 0.503906; - dout[7] 0xc0 1.92012e+07 0.5; - dout[7]~35 0xc0 1.40262e+07 0.5; - dout[7]~36 0xc0 1.30982e+07 0.498047; - dout[8] 0xc0 1.92012e+07 0.5; - dout[8]~37 0xc0 1.40754e+07 0.5; - dout[8]~38 0xc0 1.2996e+07 0.500977; - dout[9] 0xc0 1.92012e+07 0.5; - dout[9]~39 0xc0 1.40497e+07 0.5; - dout[9]~40 0xc0 1.30464e+07 0.499512; - dout[10] 0xc0 1.92012e+07 0.5; - dout[10]~41 0xc0 1.40623e+07 0.5; - dout[10]~42 0xc0 1.3021e+07 0.500244; - dout[11] 0xc0 1.92012e+07 0.5; - dout[11]~43 0xc0 1.40559e+07 0.5; - dout[11]~44 0xc0 1.30336e+07 0.499878; - dout[12] 0xc0 1.92012e+07 0.5; - dout[12]~45 0xc0 1.40591e+07 0.5; - dout[12]~46 0xc0 1.30273e+07 0.500061; - dout[13] 0xc0 1.92012e+07 0.5; - dout[13]~47 0xc0 1.40575e+07 0.5; - dout[13]~48 0xc0 1.30305e+07 0.499969; - dout[14] 0xc0 1.92012e+07 0.5; - dout[14]~49 0xc0 1.40583e+07 0.5; - dout[14]~50 0xc0 1.30289e+07 0.500015; - dout[15] 0xc0 1.92012e+07 0.5; - dout[15]~51 0xc0 1.40579e+07 0.5; - dout[15]~52 0xc0 1.30297e+07 0.499992; - dout[16] 0xc0 1.92012e+07 0.5; - dout[16]~53 0xc0 1.40581e+07 0.5; - dout[16]~54 0xc0 1.30293e+07 0.500004; - dout[17] 0xc0 1.92012e+07 0.5; - dout[17]~55 0xc0 1.4058e+07 0.5; - dout[17]~56 0xc0 1.30295e+07 0.499998; - dout[18] 0xc0 1.92012e+07 0.5; - dout[18]~57 0xc0 1.40581e+07 0.5; - dout[18]~58 0xc0 1.30294e+07 0.500001; - dout[19] 0xc0 1.92012e+07 0.5; - dout[19]~59 0xc0 1.4058e+07 0.5; - dout[19]~60 0xc0 1.30294e+07 0.5; - dout[74] 0xc0 1.92012e+07 0.5; - dout[74]~61 0xc0 1.4058e+07 0.5; - dout[74]~63 0xc0 1.44009e+07 0.25; - dout_valid 0xc0 1.92012e+07 0.5; - auk_dspip_differentiator:COMB_LOOP[5].auk_dsp_diff; - auk_dspip_delay:\glogic:u0; - \register_fifo:fifo_data[0][0] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][1] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][2] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][3] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][4] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][5]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][6]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][7]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][8] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][9]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][10] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][11] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][12] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][13] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][14]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][15] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][16] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][17] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][18] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][19] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][19]~feeder 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74]~feeder 0xc0 1.92012e+07 0.5; - dout[0] 0xc0 1.92012e+07 0.5; - dout[0]~22 0xc0 1.92012e+07 0.5; - dout[0]~23 0xc0 1.08007e+07 0.75; - dout[1] 0xc0 1.92012e+07 0.5; - dout[1]~24 0xc0 1.6201e+07 0.5; - dout[1]~25 0xc0 8.94432e+06 0.375; - dout[2] 0xc0 1.92012e+07 0.5; - dout[2]~26 0xc0 1.37118e+07 0.5; - dout[2]~27 0xc0 1.05311e+07 0.5625; - dout[3] 0xc0 1.92012e+07 0.5; - dout[3]~28 0xc0 1.36022e+07 0.5; - dout[3]~29 0xc0 1.42453e+07 0.46875; - dout[4] 0xc0 1.92012e+07 0.5; - dout[4]~30 0xc0 1.44042e+07 0.5; - dout[4]~31 0xc0 1.25509e+07 0.515625; - dout[5] 0xc0 1.92012e+07 0.5; - dout[5]~32 0xc0 1.3949e+07 0.5; - dout[5]~33 0xc0 1.33182e+07 0.492188; - dout[6] 0xc0 1.92012e+07 0.5; - dout[6]~34 0xc0 1.41329e+07 0.5; - dout[6]~35 0xc0 1.28995e+07 0.503906; - dout[7] 0xc0 1.92012e+07 0.5; - dout[7]~36 0xc0 1.40262e+07 0.5; - dout[7]~37 0xc0 1.30982e+07 0.498047; - dout[8] 0xc0 1.92012e+07 0.5; - dout[8]~38 0xc0 1.40754e+07 0.5; - dout[8]~39 0xc0 1.2996e+07 0.500977; - dout[9] 0xc0 1.92012e+07 0.5; - dout[9]~40 0xc0 1.40497e+07 0.5; - dout[9]~41 0xc0 1.30464e+07 0.499512; - dout[10] 0xc0 1.92012e+07 0.5; - dout[10]~42 0xc0 1.40623e+07 0.5; - dout[10]~43 0xc0 1.3021e+07 0.500244; - dout[11] 0xc0 1.92012e+07 0.5; - dout[11]~44 0xc0 1.40559e+07 0.5; - dout[11]~45 0xc0 1.30336e+07 0.499878; - dout[12] 0xc0 1.92012e+07 0.5; - dout[12]~46 0xc0 1.40591e+07 0.5; - dout[12]~47 0xc0 1.30273e+07 0.500061; - dout[13] 0xc0 1.92012e+07 0.5; - dout[13]~48 0xc0 1.40575e+07 0.5; - dout[13]~49 0xc0 1.30305e+07 0.499969; - dout[14] 0xc0 1.92012e+07 0.5; - dout[14]~50 0xc0 1.40583e+07 0.5; - dout[14]~51 0xc0 1.30289e+07 0.500015; - dout[15] 0xc0 1.92012e+07 0.5; - dout[15]~52 0xc0 1.40579e+07 0.5; - dout[15]~53 0xc0 1.30297e+07 0.499992; - dout[16] 0xc0 1.92012e+07 0.5; - dout[16]~54 0xc0 1.40581e+07 0.5; - dout[16]~55 0xc0 1.30293e+07 0.500004; - dout[17] 0xc0 1.92012e+07 0.5; - dout[17]~56 0xc0 1.4058e+07 0.5; - dout[17]~57 0xc0 1.30295e+07 0.499998; - dout[18] 0xc0 1.92012e+07 0.5; - dout[18]~58 0xc0 1.40581e+07 0.5; - dout[18]~59 0xc0 1.30294e+07 0.500001; - dout[19] 0xc0 1.92012e+07 0.5; - dout[19]~60 0xc0 1.4058e+07 0.5; - dout[19]~61 0xc0 1.30294e+07 0.5; - dout[20] 0xc0 1.92012e+07 0.5; - dout[20]~62 0xc0 1.4058e+07 0.5; - dout[20]~63 0xc0 1.30294e+07 0.5; - dout[74] 0xc0 1.92012e+07 0.5; - dout[74]~64 0xc0 1.76583e+07 0.5; - dout[74]~66 0xc0 1.44009e+07 0.25; - dout_valid 0xc0 1.92012e+07 0.5; - Equal0~0 0xc0 5.70036e+06 0.125; - Equal0~1 0xc0 2.36265e+06 0.0625; - Equal0~2 0xc0 2.36265e+06 0.0625; - Equal0~3 0xc0 422.989 0.000244141; - counter_module:counter_fs_inst; - Add0~0 0xc0 1.92012e+07 0.5; - Add0~1 0xc0 1.92012e+07 0.5; - Add0~2 0xc0 1.92012e+07 0.5; - Add0~3 0xc0 1.08007e+07 0.75; - Add0~4 0xc0 1.74011e+07 0.5; - Add0~5 0xc0 1.47009e+07 0.125; - Add0~6 0xc0 2.23514e+07 0.5; - Add0~7 0xc0 4.27527e+06 0.9375; - Add0~8 0xc0 1.90887e+07 0.5; - Add0~9 0xc0 1.80199e+07 0.03125; - Add0~10 0xc0 2.70486e+07 0.5; - Add0~11 0xc0 4.54248e+06 0.984375; - Add0~12 0xc0 2.08818e+07 0.5; - Add0~13 0xc0 1.97462e+07 0.0078125; - Add0~14 0xc0 2.87766e+07 0.5; - Add0~15 0xc0 4.93889e+06 0.996094; - Add0~16 0xc0 2.15213e+07 0.5; - Add0~17 0xc0 2.02865e+07 0.00195313; - Add0~18 0xc0 2.92696e+07 0.5; - Add0~19 0xc0 5.07178e+06 0.999023; - Add0~20 0xc0 2.16997e+07 0.5; - Add0~21 0xc0 2.04317e+07 0.000488281; - Add0~22 0xc0 2.93983e+07 0.5; - Equal0~0 0xc0 1.7298e+06 0.0625; - Equal0~1 0xc0 1.7298e+06 0.0625; - Equal0~2 0xc0 445.47 0.000244141; - count[0] 0xc0 1.92012e+07 0.5; - count[1] 0xc0 1.92012e+07 0.5; - count[2] 0xc0 1.92012e+07 0.5; - count[3] 0xc0 1.92012e+07 0.5; - count[4] 0xc0 1.92012e+07 0.5; - count[5] 0xc0 1.92012e+07 0.5; - count[6] 0xc0 1.92012e+07 0.5; - count[7] 0xc0 1.92012e+07 0.5; - count[8] 0xc0 1.92012e+07 0.5; - count[9] 0xc0 1.92012e+07 0.5; - count[10] 0xc0 1.92012e+07 0.5; - count[11] 0xc0 1.92012e+07 0.5; - count~0 0xc0 2.87628e+07 0.499878; - count~1 0xc0 2.16893e+07 0.499878; - count~2 0xc0 2.93842e+07 0.499878; - auk_dspip_upsample:first_upsample; - dout[0]~21 0xc0 1.44009e+07 0.25; - dout[1]~20 0xc0 1.44009e+07 0.25; - dout[2]~19 0xc0 1.44009e+07 0.25; - dout[3]~18 0xc0 1.44009e+07 0.25; - dout[4]~17 0xc0 1.44009e+07 0.25; - dout[5]~16 0xc0 1.44009e+07 0.25; - dout[6]~15 0xc0 1.44009e+07 0.25; - dout[7]~14 0xc0 1.44009e+07 0.25; - dout[8]~13 0xc0 1.44009e+07 0.25; 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- \register_fifo:fifo_data[0][39] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][39]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][39]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][40] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][40]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][40]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][41] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][41]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][41]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][42] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][42]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][42]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][43] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][43]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][43]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][44] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][44]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][44]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][45] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][45]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][45]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][46] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][46]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][46]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][47] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][47]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][47]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][48] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][48]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][48]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][49] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][49]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][49]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][50] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][50]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][50]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][51] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][51]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][51]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][52] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][52]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][52]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][53] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][53]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][53]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][54] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][54]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][54]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][55] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][55]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][55]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][56] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][56]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][56]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][57] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][57]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][57]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][58] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][58]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][58]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][59] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][59]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][59]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][60] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][60]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][60]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][61] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][61]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][61]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][62] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][62]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][62]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][63] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][63]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][63]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][64] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][64]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][64]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][65] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][65]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][65]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][66] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][66]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][66]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][67] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][67]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][67]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][68] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][68]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][68]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][69] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][69]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][69]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][70] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][70]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][70]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][71] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][71]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][71]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][72] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][72]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][72]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][73] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][73]~1 0xc0 1.4058e+07 0.5; - \register_fifo:fifo_data[0][73]~2 0xc0 1.30294e+07 0.5; - \register_fifo:fifo_data[0][74] 0xc0 1.92012e+07 0.5; - \register_fifo:fifo_data[0][74]~1 0xc0 1.76583e+07 0.5; - sample_valid 0xc0 1.92012e+07 0.5; - auk_dspip_avalon_streaming_source:output_source_0; - scfifo:source_FIFO; - scfifo_ci71:auto_generated; - dffe_af 0xc0 1.92012e+07 0.5; - dffe_af~0 0xc0 2.36265e+06 0.0625; - dffe_af~1 0xc0 5.48473e+06 0.25; - dffe_af~2 0xc0 2.17151e+07 0.5; - a_dpfifo_9qv:dpfifo; - _~0 0xc0 3.37522e+06 0.0625; - _~1 0xc0 4.57529e+06 0.125; - _~2 0xc0 7.42271e+06 0.314941; - _~3 0xc0 1.23711e+07 0.578125; - _~4 0xc0 1.18035e+07 0.509035; - _~5 0xc0 3.83931e+06 0.1875; - _~6 0xc0 7.93879e+06 0.4375; - empty_dff 0xc0 1.92012e+07 0.5; - altsyncram_hah1:FIFOram; - q_b[0] 0xc0 1.92012e+07 0.5; - q_b[1] 0xc0 1.92012e+07 0.5; - q_b[2] 0xc0 1.92012e+07 0.5; - q_b[3] 0xc0 1.92012e+07 0.5; - q_b[4] 0xc0 1.92012e+07 0.5; - q_b[5] 0xc0 1.92012e+07 0.5; - q_b[6] 0xc0 1.92012e+07 0.5; - q_b[7] 0xc0 1.92012e+07 0.5; - q_b[8] 0xc0 1.92012e+07 0.5; - q_b[9] 0xc0 1.92012e+07 0.5; - q_b[10] 0xc0 1.92012e+07 0.5; - q_b[11] 0xc0 1.92012e+07 0.5; - q_b[12] 0xc0 1.92012e+07 0.5; - q_b[13] 0xc0 1.92012e+07 0.5; - q_b[14] 0xc0 1.92012e+07 0.5; - q_b[15] 0xc0 1.92012e+07 0.5; - full_dff 0xc0 1.92012e+07 0.5; - low_addressa[0] 0xc0 1.92012e+07 0.5; - low_addressa[1] 0xc0 1.92012e+07 0.5; - low_addressa[2] 0xc0 1.92012e+07 0.5; - low_addressa[3] 0xc0 1.92012e+07 0.5; - low_addressa[4] 0xc0 1.92012e+07 0.5; - ram_read_address[0]~0 0xc0 8.00149e+06 0.5; - ram_read_address[1]~1 0xc0 8.00149e+06 0.5; - ram_read_address[2]~2 0xc0 8.00149e+06 0.5; - ram_read_address[3]~3 0xc0 8.00149e+06 0.5; - ram_read_address[4]~4 0xc0 8.00149e+06 0.5; - rd_ptr_lsb 0xc0 1.92012e+07 0.5; - rd_ptr_lsb~0 0xc0 1.92012e+07 0.5; - cntr_t9b:rd_ptr_msb; - counter_comb_bita0 0xc0 1.92012e+07 0.5; - counter_comb_bita0~COUT 0xc0 1.92012e+07 0.5; - counter_comb_bita1 0xc0 1.92012e+07 0.5; - counter_comb_bita1~COUT 0xc0 1.08007e+07 0.75; - counter_comb_bita2 0xc0 1.74011e+07 0.5; - counter_comb_bita2~COUT 0xc0 1.47009e+07 0.125; - counter_comb_bita3 0xc0 2.23514e+07 0.5; - counter_reg_bit[0] 0xc0 1.92012e+07 0.5; - counter_reg_bit[1] 0xc0 1.92012e+07 0.5; - counter_reg_bit[2] 0xc0 1.92012e+07 0.5; - counter_reg_bit[3] 0xc0 1.92012e+07 0.5; - cntr_aa7:usedw_counter; - counter_comb_bita0 0xc0 1.92012e+07 0.5; - counter_comb_bita0~COUT 0xc0 1.92012e+07 0.5; - counter_comb_bita1 0xc0 1.92012e+07 0.5; - counter_comb_bita1~COUT 0xc0 1.21508e+07 0.75; - counter_comb_bita2 0xc0 1.80762e+07 0.5; - counter_comb_bita2~COUT 0xc0 1.04186e+07 0.125; - counter_comb_bita3 0xc0 2.02103e+07 0.5; - counter_comb_bita3~COUT 0xc0 2.60382e+06 0.9375; - counter_comb_bita4 0xc0 1.8253e+07 0.5; - counter_reg_bit[0] 0xc0 1.92012e+07 0.5; - counter_reg_bit[1] 0xc0 1.92012e+07 0.5; - counter_reg_bit[2] 0xc0 1.92012e+07 0.5; - counter_reg_bit[3] 0xc0 1.92012e+07 0.5; - counter_reg_bit[4] 0xc0 1.92012e+07 0.5; - usedw_is_0_dff 0xc0 1.92012e+07 0.5; - usedw_is_1_dff 0xc0 1.92012e+07 0.5; - usedw_will_be_1~0 0xc0 1.7298e+06 0.0625; - usedw_will_be_1~1 0xc0 5.69918e+06 0.324219; - usedw_will_be_1~2 0xc0 1.41813e+07 0.478027; - valid_rreq~0 0xc0 8.32553e+06 0.375; - valid_wreq 0xc0 1.44009e+07 0.75; - cntr_u9b:wr_ptr; - counter_comb_bita0 0xc0 1.92012e+07 0.5; - counter_comb_bita0~COUT 0xc0 1.92012e+07 0.5; - counter_comb_bita1 0xc0 1.92012e+07 0.5; - counter_comb_bita1~COUT 0xc0 1.08007e+07 0.75; - counter_comb_bita2 0xc0 1.74011e+07 0.5; - counter_comb_bita2~COUT 0xc0 1.47009e+07 0.125; - counter_comb_bita3 0xc0 2.23514e+07 0.5; - counter_comb_bita3~COUT 0xc0 4.27527e+06 0.9375; - counter_comb_bita4 0xc0 1.90887e+07 0.5; - counter_reg_bit[0] 0xc0 1.92012e+07 0.5; - counter_reg_bit[1] 0xc0 1.92012e+07 0.5; - counter_reg_bit[2] 0xc0 1.92012e+07 0.5; - counter_reg_bit[3] 0xc0 1.92012e+07 0.5; - counter_reg_bit[4] 0xc0 1.92012e+07 0.5; - source_valid_s 0xc0 1.92012e+07 0.5; - source_valid_s_process~0 0xc0 8.32553e+06 0.625; - data_shifter:TX_CICCOMP_GAINER; - Mux0~0 0xc0 3.99805e+06 0.5; - Mux0~1 0xc0 9.75062e+06 0.5; - Mux0~2 0xc0 4.58687e+06 0.375; - Mux0~3 0xc0 2.55659e+06 0.46875; - Mux0~4 0xc0 3.99296e+06 0.46875; - Mux0~5 0xc0 2.13985e+06 0.484375; - Mux1~0 0xc0 3.99805e+06 0.5; - Mux1~1 0xc0 6.65668e+06 0.5; - Mux1~2 0xc0 4.51283e+06 0.5; - Mux1~3 0xc0 2.13405e+06 0.5; - Mux1~4 0xc0 4.45198e+06 0.4375; - Mux1~5 0xc0 2.21539e+06 0.46875; - Mux2~0 0xc0 3.99805e+06 0.5; - Mux2~1 0xc0 6.65668e+06 0.5; - Mux2~2 0xc0 4.51283e+06 0.5; - Mux2~3 0xc0 2.13405e+06 0.5; - Mux2~4 0xc0 5.48473e+06 0.25; - Mux2~5 0xc0 4.50852e+06 0.4375; - Mux2~6 0xc0 2.22233e+06 0.46875; - Mux3~0 0xc0 3.99805e+06 0.5; - Mux3~1 0xc0 6.65668e+06 0.5; - Mux3~2 0xc0 4.51283e+06 0.5; - Mux3~3 0xc0 2.13405e+06 0.5; - Mux3~4 0xc0 4.57529e+06 0.125; - Mux3~5 0xc0 5.33314e+06 0.40625; - Mux3~6 0xc0 2.35554e+06 0.453125; - Mux4~0 0xc0 6.65668e+06 0.5; - Mux4~1 0xc0 4.51283e+06 0.5; - Mux4~2 0xc0 3.99805e+06 0.5; - Mux4~3 0xc0 2.13405e+06 0.5; - Mux4~4 0xc0 4.57529e+06 0.125; - Mux4~5 0xc0 5.55782e+06 0.375; - Mux4~6 0xc0 2.42803e+06 0.4375; - Mux5~0 0xc0 6.65668e+06 0.5; - Mux5~1 0xc0 4.51283e+06 0.5; - Mux5~2 0xc0 3.99805e+06 0.5; - Mux5~3 0xc0 2.13405e+06 0.5; - Mux5~4 0xc0 4.57529e+06 0.125; - Mux5~5 0xc0 6.39882e+06 0.34375; - Mux5~6 0xc0 2.58894e+06 0.421875; - Mux6~0 0xc0 6.65668e+06 0.5; - Mux6~1 0xc0 4.51283e+06 0.5; - Mux6~2 0xc0 3.99805e+06 0.5; - Mux6~3 0xc0 2.13405e+06 0.5; - Mux6~4 0xc0 4.57529e+06 0.125; - Mux6~5 0xc0 7.79698e+06 0.3125; - Mux6~6 0xc0 2.83099e+06 0.40625; - Mux7~0 0xc0 6.65668e+06 0.5; - Mux7~1 0xc0 4.51283e+06 0.5; - Mux7~2 0xc0 3.99805e+06 0.5; - Mux7~3 0xc0 2.13405e+06 0.5; - Mux8~0 0xc0 6.65668e+06 0.5; - Mux8~1 0xc0 4.51283e+06 0.5; - Mux8~2 0xc0 3.99805e+06 0.5; - Mux8~3 0xc0 2.13405e+06 0.5; - Mux9~0 0xc0 6.65668e+06 0.5; - Mux9~1 0xc0 4.51283e+06 0.5; - Mux9~2 0xc0 3.99805e+06 0.5; - Mux9~3 0xc0 2.13405e+06 0.5; - Mux10~0 0xc0 6.65668e+06 0.5; - Mux10~1 0xc0 4.51283e+06 0.5; - Mux10~2 0xc0 3.99805e+06 0.5; - Mux10~3 0xc0 2.13405e+06 0.5; - Mux11~0 0xc0 6.65668e+06 0.5; - Mux11~1 0xc0 4.51283e+06 0.5; - Mux11~2 0xc0 3.99805e+06 0.5; - Mux11~3 0xc0 2.13405e+06 0.5; - Mux12~0 0xc0 6.65668e+06 0.5; - Mux12~1 0xc0 4.51283e+06 0.5; - Mux12~2 0xc0 6.65668e+06 0.5; - Mux12~3 0xc0 4.51283e+06 0.5; - Mux12~4 0xc0 6.65668e+06 0.5; - Mux12~5 0xc0 4.51283e+06 0.5; - Mux12~6 0xc0 9.75062e+06 0.5; - Mux12~7 0xc0 4.58687e+06 0.375; - Mux12~8 0xc0 6.65668e+06 0.5; - Mux12~9 0xc0 4.51283e+06 0.5; - Mux12~10 0xc0 3.99805e+06 0.5; - Mux12~11 0xc0 2.13405e+06 0.5; - Mux13~0 0xc0 6.65668e+06 0.5; - Mux13~1 0xc0 4.51283e+06 0.5; - Mux13~2 0xc0 6.65668e+06 0.5; - Mux13~3 0xc0 4.51283e+06 0.5; - Mux13~4 0xc0 6.65668e+06 0.5; - Mux13~5 0xc0 4.51283e+06 0.5; - Mux13~6 0xc0 4.78156e+06 0.25; - Mux13~7 0xc0 6.65668e+06 0.5; - Mux13~8 0xc0 4.51283e+06 0.5; - Mux13~9 0xc0 3.99805e+06 0.5; - Mux13~10 0xc0 2.13405e+06 0.5; - Mux14~0 0xc0 6.65668e+06 0.5; - Mux14~1 0xc0 4.51283e+06 0.5; - Mux14~2 0xc0 6.65668e+06 0.5; - Mux14~3 0xc0 4.51283e+06 0.5; - Mux14~4 0xc0 6.65668e+06 0.5; - Mux14~5 0xc0 4.51283e+06 0.5; - Mux14~6 0xc0 6.65668e+06 0.5; - Mux14~7 0xc0 4.51283e+06 0.5; - Mux14~8 0xc0 4.57529e+06 0.125; - Mux14~9 0xc0 3.99805e+06 0.5; - Mux14~10 0xc0 2.13405e+06 0.5; - Mux15~0 0xc0 6.65668e+06 0.5; - Mux15~1 0xc0 4.51283e+06 0.5; - Mux15~2 0xc0 6.65668e+06 0.5; - Mux15~3 0xc0 4.51283e+06 0.5; - Mux15~4 0xc0 6.65668e+06 0.5; - Mux15~5 0xc0 4.51283e+06 0.5; - Mux15~6 0xc0 6.65668e+06 0.5; - Mux15~7 0xc0 4.51283e+06 0.5; - Mux15~8 0xc0 3.99805e+06 0.5; - Mux15~9 0xc0 2.13405e+06 0.5; - Mux16~0 0xc0 3.99805e+06 0.5; - Mux16~1 0xc0 9.75062e+06 0.5; - Mux16~2 0xc0 4.58687e+06 0.375; - Mux16~3 0xc0 2.55659e+06 0.46875; - Mux16~4 0xc0 3.99296e+06 0.46875; - Mux16~5 0xc0 2.13985e+06 0.484375; - Mux17~0 0xc0 3.99805e+06 0.5; - Mux17~1 0xc0 6.65668e+06 0.5; - Mux17~2 0xc0 4.51283e+06 0.5; - Mux17~3 0xc0 2.13405e+06 0.5; - Mux17~4 0xc0 4.45198e+06 0.4375; - Mux17~5 0xc0 2.21539e+06 0.46875; - Mux18~0 0xc0 3.99805e+06 0.5; - Mux18~1 0xc0 6.65668e+06 0.5; - Mux18~2 0xc0 4.51283e+06 0.5; - Mux18~3 0xc0 2.13405e+06 0.5; - Mux18~4 0xc0 5.48473e+06 0.25; - Mux18~5 0xc0 4.50852e+06 0.4375; - Mux18~6 0xc0 2.22233e+06 0.46875; - Mux19~0 0xc0 3.99805e+06 0.5; - Mux19~1 0xc0 6.65668e+06 0.5; - Mux19~2 0xc0 4.51283e+06 0.5; - Mux19~3 0xc0 2.13405e+06 0.5; - Mux19~4 0xc0 4.57529e+06 0.125; - Mux19~5 0xc0 5.33314e+06 0.40625; - Mux19~6 0xc0 2.35554e+06 0.453125; - Mux20~0 0xc0 6.65668e+06 0.5; - Mux20~1 0xc0 4.51283e+06 0.5; - Mux20~2 0xc0 3.99805e+06 0.5; - Mux20~3 0xc0 2.13405e+06 0.5; - Mux20~4 0xc0 4.57529e+06 0.125; - Mux20~5 0xc0 5.33314e+06 0.40625; - Mux20~6 0xc0 2.06169e+06 0.416016; - Mux21~0 0xc0 6.65668e+06 0.5; - Mux21~1 0xc0 4.51283e+06 0.5; - Mux21~2 0xc0 3.99805e+06 0.5; - Mux21~3 0xc0 2.13405e+06 0.5; - Mux21~4 0xc0 4.57529e+06 0.125; - Mux21~5 0xc0 5.33314e+06 0.40625; - Mux21~6 0xc0 2.0299e+06 0.378906; - Mux22~0 0xc0 6.65668e+06 0.5; - Mux22~1 0xc0 4.51283e+06 0.5; - Mux22~2 0xc0 3.99805e+06 0.5; - Mux22~3 0xc0 2.13405e+06 0.5; - Mux22~4 0xc0 4.57529e+06 0.125; - Mux22~5 0xc0 5.33314e+06 0.40625; - Mux22~6 0xc0 2.22206e+06 0.341797; - Mux23~0 0xc0 6.65668e+06 0.5; - Mux23~1 0xc0 4.51283e+06 0.5; - Mux23~2 0xc0 3.99805e+06 0.5; - Mux23~3 0xc0 2.13405e+06 0.5; - Mux24~0 0xc0 6.65668e+06 0.5; - Mux24~1 0xc0 4.51283e+06 0.5; - Mux24~2 0xc0 3.99805e+06 0.5; - Mux24~3 0xc0 2.13405e+06 0.5; - Mux25~0 0xc0 6.65668e+06 0.5; - Mux25~1 0xc0 4.51283e+06 0.5; - Mux25~2 0xc0 3.99805e+06 0.5; - Mux25~3 0xc0 2.13405e+06 0.5; - Mux26~0 0xc0 6.65668e+06 0.5; - Mux26~1 0xc0 4.51283e+06 0.5; - Mux26~2 0xc0 3.99805e+06 0.5; - Mux26~3 0xc0 2.13405e+06 0.5; - Mux27~0 0xc0 6.65668e+06 0.5; - Mux27~1 0xc0 4.51283e+06 0.5; - Mux27~2 0xc0 3.99805e+06 0.5; - Mux27~3 0xc0 2.13405e+06 0.5; - Mux28~0 0xc0 6.65668e+06 0.5; - Mux28~1 0xc0 4.51283e+06 0.5; - Mux28~2 0xc0 6.65668e+06 0.5; - Mux28~3 0xc0 4.51283e+06 0.5; - Mux28~4 0xc0 6.65668e+06 0.5; - Mux28~5 0xc0 4.51283e+06 0.5; - Mux28~6 0xc0 9.75062e+06 0.5; - Mux28~7 0xc0 4.58687e+06 0.375; - Mux28~8 0xc0 6.65668e+06 0.5; - Mux28~9 0xc0 4.51283e+06 0.5; - Mux28~10 0xc0 3.99805e+06 0.5; - Mux28~11 0xc0 2.13405e+06 0.5; - Mux29~0 0xc0 6.65668e+06 0.5; - Mux29~1 0xc0 4.51283e+06 0.5; - Mux29~2 0xc0 6.65668e+06 0.5; - Mux29~3 0xc0 4.51283e+06 0.5; - Mux29~4 0xc0 6.65668e+06 0.5; - Mux29~5 0xc0 4.51283e+06 0.5; - Mux29~6 0xc0 4.78156e+06 0.25; - Mux29~7 0xc0 6.65668e+06 0.5; - Mux29~8 0xc0 4.51283e+06 0.5; - Mux29~9 0xc0 3.99805e+06 0.5; - Mux29~10 0xc0 2.13405e+06 0.5; - Mux30~0 0xc0 6.65668e+06 0.5; - Mux30~1 0xc0 4.51283e+06 0.5; - Mux30~2 0xc0 6.65668e+06 0.5; - Mux30~3 0xc0 4.51283e+06 0.5; - Mux30~4 0xc0 6.65668e+06 0.5; - Mux30~5 0xc0 4.51283e+06 0.5; - Mux30~6 0xc0 6.65668e+06 0.5; - Mux30~7 0xc0 4.51283e+06 0.5; - Mux30~8 0xc0 4.57529e+06 0.125; - Mux30~9 0xc0 3.99805e+06 0.5; - Mux30~10 0xc0 2.13405e+06 0.5; - Mux31~0 0xc0 6.65668e+06 0.5; - Mux31~1 0xc0 4.51283e+06 0.5; - Mux31~2 0xc0 6.65668e+06 0.5; - Mux31~3 0xc0 4.51283e+06 0.5; - Mux31~4 0xc0 6.65668e+06 0.5; - Mux31~5 0xc0 4.51283e+06 0.5; - Mux31~6 0xc0 6.65668e+06 0.5; - Mux31~7 0xc0 4.51283e+06 0.5; - Mux31~8 0xc0 3.99805e+06 0.5; - Mux31~9 0xc0 2.13405e+06 0.5; - data_out_I[0]~29 0xc0 300385 0.015625; - data_out_I[0]~30 0xc0 2.84553e+06 0.130859; - data_out_I[1]~26 0xc0 1.7298e+06 0.0625; - data_out_I[1]~27 0xc0 336909 0.0302734; - data_out_I[1]~28 0xc0 2.76953e+06 0.136353; - data_out_I[2]~23 0xc0 1.7298e+06 0.0625; - data_out_I[2]~24 0xc0 407646 0.0449219; - data_out_I[2]~25 0xc0 2.70035e+06 0.141846; - data_out_I[3]~20 0xc0 1.7298e+06 0.0625; - data_out_I[3]~21 0xc0 655978 0.0595703; - data_out_I[3]~22 0xc0 2.65022e+06 0.147339; - data_out_I[4]~17 0xc0 1.7298e+06 0.0625; - data_out_I[4]~18 0xc0 1.02056e+06 0.0742188; - data_out_I[4]~19 0xc0 2.6139e+06 0.152832; - data_out_I[5]~14 0xc0 2.17587e+06 0.121094; - data_out_I[5]~15 0xc0 2.76586e+06 0.185547; - data_out_I[5]~16 0xc0 2.30462e+06 0.171387; - data_out_I[6]~11 0xc0 2.36063e+06 0.179688; - data_out_I[6]~12 0xc0 2.58544e+06 0.214844; - data_out_I[6]~13 0xc0 2.22758e+06 0.178711; - data_out_I[7]~8 0xc0 2.85588e+06 0.238281; - data_out_I[7]~9 0xc0 2.50522e+06 0.244141; - data_out_I[7]~10 0xc0 2.17194e+06 0.186035; - data_out_I[8]~7 0xc0 3.74696e+06 0.296875; - data_out_I[8]~31 0xc0 2.53487e+06 0.273438; - data_out_I[8]~32 0xc0 2.13829e+06 0.193359; - data_out_I[9]~6 0xc0 2.18727e+06 0.226563; - data_out_I[10]~5 0xc0 2.19676e+06 0.230469; - data_out_I[11]~4 0xc0 2.21555e+06 0.234375; - data_out_I[12]~3 0xc0 2.24409e+06 0.238281; - data_out_I[13]~2 0xc0 2.27327e+06 0.242188; - data_out_I[14]~1 0xc0 2.27285e+06 0.242188; - data_out_I[15]~0 0xc0 2.24285e+06 0.238281; - data_out_Q[0]~7 0xc0 1.2207e+06 0.125; - data_out_Q[0]~33 0xc0 300385 0.015625; - data_out_Q[0]~34 0xc0 2.84553e+06 0.130859; - data_out_Q[1]~30 0xc0 1.7298e+06 0.0625; - data_out_Q[1]~31 0xc0 336909 0.0302734; - data_out_Q[1]~32 0xc0 2.76953e+06 0.136353; - data_out_Q[2]~27 0xc0 1.7298e+06 0.0625; - data_out_Q[2]~28 0xc0 407646 0.0449219; - data_out_Q[2]~29 0xc0 2.70035e+06 0.141846; - data_out_Q[3]~24 0xc0 1.7298e+06 0.0625; - data_out_Q[3]~25 0xc0 655978 0.0595703; - data_out_Q[3]~26 0xc0 2.65022e+06 0.147339; - data_out_Q[4]~20 0xc0 1.3916e+06 0.25; - data_out_Q[4]~21 0xc0 1.7298e+06 0.0625; - data_out_Q[4]~22 0xc0 1.02056e+06 0.0742188; - data_out_Q[4]~23 0xc0 2.6139e+06 0.152832; - data_out_Q[5]~17 0xc0 2.17587e+06 0.121094; - data_out_Q[5]~18 0xc0 2.76586e+06 0.185547; - data_out_Q[5]~19 0xc0 2.30462e+06 0.171387; - data_out_Q[6]~14 0xc0 2.36063e+06 0.179688; - data_out_Q[6]~15 0xc0 2.58544e+06 0.214844; - data_out_Q[6]~16 0xc0 2.22758e+06 0.178711; - data_out_Q[7]~11 0xc0 2.85588e+06 0.238281; - data_out_Q[7]~12 0xc0 2.50522e+06 0.244141; - data_out_Q[7]~13 0xc0 2.17194e+06 0.186035; - data_out_Q[8]~8 0xc0 3.74696e+06 0.296875; - data_out_Q[8]~9 0xc0 2.53487e+06 0.273438; - data_out_Q[8]~10 0xc0 2.13829e+06 0.193359; - data_out_Q[9]~6 0xc0 2.09586e+06 0.210449; - data_out_Q[10]~5 0xc0 2.1063e+06 0.219727; - data_out_Q[11]~4 0xc0 2.15493e+06 0.229004; - data_out_Q[12]~3 0xc0 2.24409e+06 0.238281; - data_out_Q[13]~2 0xc0 2.27327e+06 0.242188; - data_out_Q[14]~1 0xc0 2.27285e+06 0.242188; - data_out_Q[15]~0 0xc0 2.24285e+06 0.238281; - data_valid_out_Q~0 0xc0 1.08007e+07 0.25; - tx_ciccomp:TX_CICCOMP_I; - tx_ciccomp_0002:tx_ciccomp_inst; - tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst; - tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[0] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[0]~1 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[0]~2 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[1] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[1]~1 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[1]~2 0xc0 1.08007e+07 0.25; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[2] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[2]~1 0xc0 1.74011e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[2]~2 0xc0 5.10033e+06 0.875; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[3] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[3]~1 0xc0 1.75511e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[3]~2 0xc0 1.6276e+07 0.0625; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[4] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[4]~1 0xc0 2.50891e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[4]~2 0xc0 4.21902e+06 0.96875; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[5] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[5]~1 0xc0 2.01482e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[5]~2 0xc0 1.90934e+07 0.015625; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[6] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[6]~1 0xc0 2.81573e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[6]~2 0xc0 4.78273e+06 0.992188; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[7] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[7]~1 0xc0 2.12949e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[7]~2 0xc0 2.00992e+07 0.00390625; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_aseq_clkproc:u0_m0_wo0_aseq_c[8]~1 0xc0 2.91014e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[0] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[0]~1 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[0]~2 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[0]~_wirecell 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[1] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[1]~1 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[1]~2 0xc0 1.08007e+07 0.25; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[2] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[2]~1 0xc0 1.74011e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[2]~2 0xc0 5.10033e+06 0.875; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[3] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[3]~1 0xc0 1.75511e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[3]~2 0xc0 1.6276e+07 0.0625; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[4] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[4]~1 0xc0 2.50891e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[4]~2 0xc0 4.21902e+06 0.96875; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[5] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[5]~1 0xc0 2.01482e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[5]~2 0xc0 1.90934e+07 0.015625; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[6] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[6]~1 0xc0 2.81573e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[6]~2 0xc0 4.78273e+06 0.992188; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[7] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[7]~1 0xc0 2.12949e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[7]~2 0xc0 2.00992e+07 0.00390625; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[8] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_oseq_clkproc:u0_m0_wo0_oseq_c[8]~1 0xc0 2.91014e+07 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[0] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[1] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[2] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[3] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[4] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[5] 0xc0 1.92012e+07 0.5; - \u0_m0_wo0_run_clkproc:u0_m0_wo0_run_enable_c[6] 0xc0 1.92012e+07 0.5; - Add0~0 0xc0 1.92012e+07 0.5; - Add0~1 0xc0 1.92012e+07 0.5; - Add0~2 0xc0 1.92012e+07 0.5; - Add0~3 0xc0 1.08007e+07 0.25; - Add0~4 0xc0 1.74011e+07 0.5; - Add0~5 0xc0 5.10033e+06 0.875; - Add0~6 0xc0 1.75511e+07 0.5; - Add0~7 0xc0 1.6276e+07 0.0625; - Add0~8 0xc0 2.50891e+07 0.5; - Add0~9 0xc0 4.21902e+06 0.96875; - Add0~10 0xc0 2.01482e+07 0.5; - Add0~11 0xc0 1.90934e+07 0.015625; - Add0~12 0xc0 2.81573e+07 0.5; - Add1~0 0xc0 1.92012e+07 0.5; - Add1~1 0xc0 1.92012e+07 0.5; - Add1~2 0xc0 1.92012e+07 0.5; - Add1~3 0xc0 1.08007e+07 0.25; - Add1~4 0xc0 1.74011e+07 0.5; - Add1~5 0xc0 5.10033e+06 0.875; - Add1~6 0xc0 1.75511e+07 0.5; - Add1~7 0xc0 1.6276e+07 0.0625; - Add1~8 0xc0 2.50891e+07 0.5; - Add1~9 0xc0 4.21902e+06 0.96875; - Add1~10 0xc0 2.01482e+07 0.5; - Add1~11 0xc0 1.90934e+07 0.015625; - Add1~12 0xc0 2.81573e+07 0.5; - Add1~14 0xc0 2.4398e+07 0.5; - Add1~15 0xc0 1.99114e+07 0.5; - Add1~16 0xc0 2.36171e+07 0.5; - Add1~17 0xc0 1.79636e+07 0.5; - Add1~18 0xc0 1.49365e+07 0.5; - Add1~19 0xc0 1.5601e+07 0.5; - Add1~20 0xc0 9.75062e+06 0.5; - Add2~0 0xc0 7.07858e+06 0.5; - Add3~0 0xc0 1.92012e+07 0.5; - Add3~1 0xc0 1.92012e+07 0.5; - Add3~2 0xc0 1.92012e+07 0.5; - Add3~3 0xc0 1.08007e+07 0.25; - Add3~4 0xc0 1.74011e+07 0.5; - Add3~5 0xc0 5.10033e+06 0.875; - Add3~6 0xc0 1.75511e+07 0.5; - Add3~7 0xc0 1.6276e+07 0.0625; - Add3~8 0xc0 2.50891e+07 0.5; - Add3~9 0xc0 4.21902e+06 0.96875; - Add3~10 0xc0 2.01482e+07 0.5; - Add3~11 0xc0 1.90934e+07 0.015625; - Add3~12 0xc0 2.81573e+07 0.5; - Add3~13 0xc0 2.33839e+07 0.492188; - Add3~14 0xc0 2.12949e+07 0.5; - Add3~15 0xc0 1.51489e+07 0.753906; - Add3~16 0xc0 1.96508e+07 0.5; - Add6~0 0xc0 1.92012e+07 0.5; - Add6~1 0xc0 1.92012e+07 0.5; - Add6~2 0xc0 1.92012e+07 0.5; - Add6~2_wirecell 0xc0 1.92012e+07 0.5; - Add6~3 0xc0 1.08007e+07 0.25; - Add6~4 0xc0 1.74011e+07 0.5; - Add6~4_wirecell 0xc0 1.74011e+07 0.5; - Add6~5 0xc0 5.10033e+06 0.875; - Add6~6 0xc0 1.75511e+07 0.5; - Add6~6_wirecell 0xc0 1.75511e+07 0.5; - Add6~7 0xc0 1.6276e+07 0.0625; - Add6~8 0xc0 2.50891e+07 0.5; - Add6~8_wirecell 0xc0 2.50891e+07 0.5; - Add6~9 0xc0 4.21902e+06 0.96875; - Add6~10 0xc0 2.01482e+07 0.5; - Add6~10_wirecell 0xc0 2.01482e+07 0.5; - Add6~11 0xc0 1.90934e+07 0.015625; - Add6~12 0xc0 2.81573e+07 0.5; - Add14~1 0xc0 1.92012e+07 0.5; - Add14~2 0xc0 1.92012e+07 0.5; - Add14~2_wirecell 0xc0 1.92012e+07 0.5; - Add14~3 0xc0 1.08007e+07 0.25; - Add14~4 0xc0 1.74011e+07 0.5; - Add14~4_wirecell 0xc0 1.74011e+07 0.5; - Add14~5 0xc0 5.10033e+06 0.875; - Add14~6 0xc0 1.75511e+07 0.5; - Add14~6_wirecell 0xc0 1.75511e+07 0.5; - Add14~7 0xc0 1.6276e+07 0.0625; - Add14~8 0xc0 2.50891e+07 0.5; - Add14~8_wirecell 0xc0 2.50891e+07 0.5; - Add14~9 0xc0 4.21902e+06 0.96875; - Add14~10 0xc0 2.01482e+07 0.5; - Add14~10_wirecell 0xc0 2.01482e+07 0.5; - Add14~11 0xc0 1.90934e+07 0.015625; - Add14~12 0xc0 2.81573e+07 0.5; - Add14~13 0xc0 2.33839e+07 0.492188; - Add14~14 0xc0 2.12949e+07 0.5; - Add14~15 0xc0 1.51489e+07 0.753906; - Add14~16 0xc0 1.96508e+07 0.5; - dspba_delay:d_in0_m0_wi0_wo0_assign_id1_q_13; - delay_signals[0][0] 0xc0 1.92012e+07 0.5; - delay_signals[0][0]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][0] 0xc0 1.92012e+07 0.5; - delay_signals[1][0]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[2][0] 0xc0 1.92012e+07 0.5; - delay_signals[2][0]~feeder 0xc0 3.125e+06 0.5; - dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17; - delay_signals[0][0] 0xc0 1.92012e+07 0.5; - delay_signals[0][0]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][1] 0xc0 1.92012e+07 0.5; - delay_signals[0][1]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][2] 0xc0 1.92012e+07 0.5; - delay_signals[0][2]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][3] 0xc0 1.92012e+07 0.5; - delay_signals[0][3]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][4] 0xc0 1.92012e+07 0.5; - delay_signals[0][5] 0xc0 1.92012e+07 0.5; - delay_signals[0][5]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][6] 0xc0 1.92012e+07 0.5; - delay_signals[0][6]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][7] 0xc0 1.92012e+07 0.5; - delay_signals[0][8] 0xc0 1.92012e+07 0.5; - delay_signals[0][8]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][9] 0xc0 1.92012e+07 0.5; - delay_signals[0][9]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][10] 0xc0 1.92012e+07 0.5; - delay_signals[0][11] 0xc0 1.92012e+07 0.5; - delay_signals[0][11]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][12] 0xc0 1.92012e+07 0.5; - delay_signals[0][12]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][13] 0xc0 1.92012e+07 0.5; - delay_signals[0][13]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][14] 0xc0 1.92012e+07 0.5; - delay_signals[0][14]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][15] 0xc0 1.92012e+07 0.5; - delay_signals[0][16] 0xc0 1.92012e+07 0.5; - delay_signals[0][16]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][17] 0xc0 1.92012e+07 0.5; - delay_signals[0][17]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][18] 0xc0 1.92012e+07 0.5; - delay_signals[0][18]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][19] 0xc0 1.92012e+07 0.5; - delay_signals[0][19]~feeder 0xc0 1.92012e+07 0.5; - dspba_delay:d_u0_m0_wo0_aseq_q_16; - delay_signals[0][0] 0xc0 1.92012e+07 0.5; - delay_signals[0][0]~feeder 0xc0 1.92012e+07 0.5; - dspba_delay:d_u0_m0_wo0_compute_q_14; - delay_signals[0][0] 0xc0 1.92012e+07 0.5; - delay_signals[0][0]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][0] 0xc0 1.92012e+07 0.5; - delay_signals[1][0]~feeder 0xc0 1.92012e+07 0.5; - dspba_delay:d_u0_m0_wo0_compute_q_15; - delay_signals[0][0] 0xc0 1.92012e+07 0.5; - delay_signals[0][0]~feeder 0xc0 1.92012e+07 0.5; - dspba_delay:d_u0_m0_wo0_compute_q_16; - delay_signals[0][0] 0xc0 1.92012e+07 0.5; - delay_signals[0][0]~feeder 0xc0 1.92012e+07 0.5; - dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16; - delay_signals[0][20] 0xc0 1.92012e+07 0.5; - delay_signals[0][20]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][21] 0xc0 1.92012e+07 0.5; - delay_signals[0][21]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][22] 0xc0 1.92012e+07 0.5; - delay_signals[0][22]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][23] 0xc0 1.92012e+07 0.5; - delay_signals[0][23]~feeder 0xc0 1.92012e+07 0.5; - dspba_delay:d_xIn_0_13; - delay_signals[0][0] 0xc0 1.92012e+07 0.5; - delay_signals[0][0]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][1] 0xc0 1.92012e+07 0.5; - delay_signals[0][2] 0xc0 1.92012e+07 0.5; - delay_signals[0][2]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][3] 0xc0 1.92012e+07 0.5; - delay_signals[0][4] 0xc0 1.92012e+07 0.5; - delay_signals[0][5] 0xc0 1.92012e+07 0.5; - delay_signals[0][5]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][6] 0xc0 1.92012e+07 0.5; - delay_signals[0][7] 0xc0 1.92012e+07 0.5; - delay_signals[0][8] 0xc0 1.92012e+07 0.5; - delay_signals[0][8]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][9] 0xc0 1.92012e+07 0.5; - delay_signals[0][9]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][10] 0xc0 1.92012e+07 0.5; - delay_signals[0][10]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][11] 0xc0 1.92012e+07 0.5; - delay_signals[0][11]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][12] 0xc0 1.92012e+07 0.5; - delay_signals[0][12]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][13] 0xc0 1.92012e+07 0.5; - delay_signals[0][13]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][14] 0xc0 1.92012e+07 0.5; - delay_signals[0][14]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][15] 0xc0 1.92012e+07 0.5; - delay_signals[0][15]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][0] 0xc0 1.92012e+07 0.5; - delay_signals[1][0]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][1] 0xc0 1.92012e+07 0.5; - delay_signals[1][1]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][2] 0xc0 1.92012e+07 0.5; - delay_signals[1][3] 0xc0 1.92012e+07 0.5; - delay_signals[1][3]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][4] 0xc0 1.92012e+07 0.5; - delay_signals[1][4]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][5] 0xc0 1.92012e+07 0.5; - delay_signals[1][5]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][6] 0xc0 1.92012e+07 0.5; - delay_signals[1][6]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][7] 0xc0 1.92012e+07 0.5; - delay_signals[1][8] 0xc0 1.92012e+07 0.5; - delay_signals[1][9] 0xc0 1.92012e+07 0.5; - delay_signals[1][9]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][10] 0xc0 1.92012e+07 0.5; - delay_signals[1][10]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][11] 0xc0 1.92012e+07 0.5; - delay_signals[1][12] 0xc0 1.92012e+07 0.5; - delay_signals[1][13] 0xc0 1.92012e+07 0.5; - delay_signals[1][14] 0xc0 1.92012e+07 0.5; - delay_signals[1][15] 0xc0 1.92012e+07 0.5; - delay_signals[1][15]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[2][0] 0xc0 1.92012e+07 0.5; - delay_signals[2][0]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][1] 0xc0 1.92012e+07 0.5; - delay_signals[2][1]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][2] 0xc0 1.92012e+07 0.5; - delay_signals[2][3] 0xc0 1.92012e+07 0.5; - delay_signals[2][3]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][4] 0xc0 1.92012e+07 0.5; - delay_signals[2][4]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][5] 0xc0 1.92012e+07 0.5; - delay_signals[2][5]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][6] 0xc0 1.92012e+07 0.5; - delay_signals[2][6]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][7] 0xc0 1.92012e+07 0.5; - delay_signals[2][7]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][8] 0xc0 1.92012e+07 0.5; - delay_signals[2][8]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][9] 0xc0 1.92012e+07 0.5; - delay_signals[2][10] 0xc0 1.92012e+07 0.5; - delay_signals[2][10]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][11] 0xc0 1.92012e+07 0.5; - delay_signals[2][11]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][12] 0xc0 1.92012e+07 0.5; - delay_signals[2][13] 0xc0 1.92012e+07 0.5; - delay_signals[2][13]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][14] 0xc0 1.92012e+07 0.5; - delay_signals[2][14]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][15] 0xc0 1.92012e+07 0.5; - delay_signals[2][15]~feeder 0xc0 3.125e+06 0.5; - Equal1~0 0xc0 1.7298e+06 0.0625; - Equal1~1 0xc0 1.7298e+06 0.0625; - Equal1~2 0xc0 167472 0.00195313; - Mux2~0 0xc0 1.58102e+07 0.125; - Mux2~1 0xc0 1.77964e+07 0.28125; - Mux3~0 0xc0 8.50836e+06 0.4375; - Mux3~1 0xc0 9.78813e+06 0.4375; - Mux3~2 0xc0 2.0106e+07 0.40625; - Mux3~3 0xc0 1.05232e+07 0.382813; - Mux4~0 0xc0 8.70993e+06 0.5; - Mux4~1 0xc0 7.24734e+06 0.5; - Mux4~2 0xc0 1.72152e+07 0.390625; - Mux4~3 0xc0 1.33307e+07 0.359863; - Mux5~0 0xc0 1.01256e+07 0.5625; - Mux5~1 0xc0 7.21452e+06 0.5625; - Mux5~2 0xc0 1.7926e+07 0.375; - Mux5~3 0xc0 1.0107e+07 0.335938; - Mux6~0 0xc0 7.05983e+06 0.375; - Mux6~1 0xc0 1.05757e+07 0.625; - Mux6~2 0xc0 1.62636e+07 0.421875; - Mux6~3 0xc0 2.3022e+07 0.404785; - Mux7~0 0xc0 8.81775e+06 0.4375; - Mux7~1 0xc0 1.01256e+07 0.5625; - Mux7~2 0xc0 1.92294e+07 0.375; - Mux7~3 0xc0 1.18404e+07 0.335938; - Mux8~0 0xc0 9.61937e+06 0.4375; - Mux8~1 0xc0 1.09132e+07 0.5625; - Mux8~2 0xc0 1.22711e+07 0.390625; - Mux8~3 0xc0 1.49378e+07 0.353027; - Mux9~0 0xc0 5.23158e+06 0.25; - Mux9~1 0xc0 5.23158e+06 0.75; - Mux9~2 0xc0 1.7298e+06 0.0625; - Mux9~3 0xc0 1.84137e+07 0.328125; - Mux9~4 0xc0 1.7298e+06 0.0625; - Mux9~5 0xc0 8.47888e+06 0.258301; - Mux9~6 0xc0 4.57529e+06 0.125; - Mux9~7 0xc0 5.70036e+06 0.125; - u0_m0_wo0_accum_p1_of_2_o[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[0]~21 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[0]~22 0xc0 1.08007e+07 0.25; - u0_m0_wo0_accum_p1_of_2_o[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[1]~23 0xc0 1.6201e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[1]~24 0xc0 8.94432e+06 0.625; - u0_m0_wo0_accum_p1_of_2_o[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[2]~25 0xc0 1.37118e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[2]~26 0xc0 1.59315e+07 0.4375; - u0_m0_wo0_accum_p1_of_2_o[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[3]~27 0xc0 1.49523e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[3]~28 0xc0 1.22202e+07 0.53125; - u0_m0_wo0_accum_p1_of_2_o[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[4]~29 0xc0 1.38979e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[4]~30 0xc0 1.36478e+07 0.484375; - u0_m0_wo0_accum_p1_of_2_o[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[5]~31 0xc0 1.42232e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[5]~32 0xc0 1.27803e+07 0.507813; - u0_m0_wo0_accum_p1_of_2_o[6] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[6]~33 0xc0 1.39984e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[6]~34 0xc0 1.31698e+07 0.496094; - u0_m0_wo0_accum_p1_of_2_o[7] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[7]~35 0xc0 1.40938e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[7]~36 0xc0 1.29633e+07 0.501953; - u0_m0_wo0_accum_p1_of_2_o[8] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[8]~37 0xc0 1.40417e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[8]~38 0xc0 1.30635e+07 0.499023; - u0_m0_wo0_accum_p1_of_2_o[9] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[9]~39 0xc0 1.40666e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[9]~40 0xc0 1.30126e+07 0.500488; - u0_m0_wo0_accum_p1_of_2_o[10] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[10]~41 0xc0 1.40539e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[10]~42 0xc0 1.30379e+07 0.499756; - u0_m0_wo0_accum_p1_of_2_o[11] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[11]~43 0xc0 1.40602e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[11]~44 0xc0 1.30252e+07 0.500122; - u0_m0_wo0_accum_p1_of_2_o[12] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[12]~45 0xc0 1.4057e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[12]~46 0xc0 1.30315e+07 0.499939; - u0_m0_wo0_accum_p1_of_2_o[13] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[13]~47 0xc0 1.40586e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[13]~48 0xc0 1.30284e+07 0.500031; - u0_m0_wo0_accum_p1_of_2_o[14] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[14]~49 0xc0 1.40578e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[14]~50 0xc0 1.30299e+07 0.499985; - u0_m0_wo0_accum_p1_of_2_o[15] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[15]~51 0xc0 1.40582e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[15]~52 0xc0 1.30291e+07 0.500008; - u0_m0_wo0_accum_p1_of_2_o[16] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[16]~53 0xc0 1.4058e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[16]~54 0xc0 1.30295e+07 0.499996; - u0_m0_wo0_accum_p1_of_2_o[17] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[17]~55 0xc0 1.40581e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[17]~56 0xc0 1.30293e+07 0.500002; - u0_m0_wo0_accum_p1_of_2_o[18] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[18]~57 0xc0 1.4058e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[18]~58 0xc0 1.30294e+07 0.499999; - u0_m0_wo0_accum_p1_of_2_o[19] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[19]~59 0xc0 1.40581e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[19]~60 0xc0 1.30294e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[20] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[20]~61 0xc0 1.30294e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[1]~11 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[1]~12 0xc0 1.5601e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[1]~13 0xc0 9.3006e+06 0.5; - u0_m0_wo0_accum_p2_of_2_o[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[2]~14 0xc0 1.31258e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[2]~15 0xc0 1.25633e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[3]~16 0xc0 1.39415e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[3]~17 0xc0 1.29711e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[4]~18 0xc0 1.76437e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[4]~19 0xc0 1.84225e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[5]~20 0xc0 1.90065e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[5]~21 0xc0 1.91039e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[6] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[6]~22 0xc0 1.91769e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[6]~23 0xc0 1.91891e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[7] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[7]~24 0xc0 1.91982e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[7]~25 0xc0 1.91997e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[8] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[8]~26 0xc0 1.92008e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[8]~27 0xc0 1.9201e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[9] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[9]~28 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[9]~29 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[10] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[10]~30 0xc0 1.92012e+07 0.5; - u0_m0_wo0_aseq_eq 0xc0 1.92012e+07 0.5; - u0_m0_wo0_aseq_eq~0 0xc0 4.27527e+06 0.0625; - u0_m0_wo0_aseq_eq~1 0xc0 2.36265e+06 0.0625; - u0_m0_wo0_aseq_eq~2 0xc0 632853 0.015625; - u0_m0_wo0_aseq_eq~3 0xc0 9.57628e+06 0.250732; - u0_m0_wo0_ca0_i[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[0]~15 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[1]~5 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[1]~6 0xc0 1.08007e+07 0.25; - u0_m0_wo0_ca0_i[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[2]~7 0xc0 1.74011e+07 0.5; - u0_m0_wo0_ca0_i[2]~8 0xc0 4.57529e+06 0.875; - u0_m0_wo0_ca0_i[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[3]~9 0xc0 1.72886e+07 0.5; - u0_m0_wo0_ca0_i[3]~10 0xc0 1.61448e+07 0.0625; - u0_m0_wo0_ca0_i[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[4]~11 0xc0 2.50235e+07 0.5; - u0_m0_wo0_ca0_i[4]~12 0xc0 4.18621e+06 0.96875; - u0_m0_wo0_ca0_i[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[5]~13 0xc0 2.01318e+07 0.5; - u0_m0_wo0_cm0_q[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_cm0_q[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_cm0_q[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_cm0_q[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_cm0_q[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_cm0_q[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_cm0_q[6] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_cm0_q[7] 0xc0 1.92012e+07 0.5; - dspba_delay:u0_m0_wo0_compute; - delay_signals[0][0] 0xc0 1.92012e+07 0.5; - delay_signals[0][0]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][0] 0xc0 1.92012e+07 0.5; - dspba_delay:u0_m0_wo0_memread; - delay_signals[0][0] 0xc0 1.92012e+07 0.5; - lpm_mult:u0_m0_wo0_mtree_mult1_0_component; - mult_ncu:auto_generated; - mac_mult1 0xc0 7.68049e+07 0.5; - mac_mult1~12 0xc0 0 0; - mac_mult1~13 0xc0 0 0; - mac_mult1~14 0xc0 0 0; - mac_mult1~15 0xc0 0 0; - mac_mult1~16 0xc0 0 0; - mac_mult1~17 0xc0 0 0; - mac_mult1~18 0xc0 0 0; - mac_mult1~19 0xc0 0 0; - mac_mult1~20 0xc0 0 0; - mac_mult1~21 0xc0 0 0; - mac_mult1~22 0xc0 0 0; - mac_mult1~23 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT2 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT3 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT4 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT5 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT6 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT7 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT8 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT9 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT10 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT11 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT12 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT13 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT14 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT15 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT16 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT17 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT18 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT19 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT20 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT21 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT22 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT23 0xc0 7.68049e+07 0.5; - result[0] 0xc0 1.92012e+07 0.5; - result[1] 0xc0 1.92012e+07 0.5; - result[2] 0xc0 1.92012e+07 0.5; - result[3] 0xc0 1.92012e+07 0.5; - result[4] 0xc0 1.92012e+07 0.5; - result[5] 0xc0 1.92012e+07 0.5; - result[6] 0xc0 1.92012e+07 0.5; - result[7] 0xc0 1.92012e+07 0.5; - result[8] 0xc0 1.92012e+07 0.5; - result[9] 0xc0 1.92012e+07 0.5; - result[10] 0xc0 1.92012e+07 0.5; - result[11] 0xc0 1.92012e+07 0.5; - result[12] 0xc0 1.92012e+07 0.5; - result[13] 0xc0 1.92012e+07 0.5; - result[14] 0xc0 1.92012e+07 0.5; - result[15] 0xc0 1.92012e+07 0.5; - result[16] 0xc0 1.92012e+07 0.5; - result[17] 0xc0 1.92012e+07 0.5; - result[18] 0xc0 1.92012e+07 0.5; - result[19] 0xc0 1.92012e+07 0.5; - result[20] 0xc0 1.92012e+07 0.5; - result[21] 0xc0 1.92012e+07 0.5; - result[22] 0xc0 1.92012e+07 0.5; - result[23] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_oseq_eq 0xc0 1.92012e+07 0.5; - u0_m0_wo0_oseq_gated_q[0] 0xc0 1.44009e+07 0.25; - u0_m0_wo0_oseq_gated_reg_q[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_run_count[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_run_count[0]~0 0xc0 9.01933e+06 0.5; - u0_m0_wo0_run_count[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_run_enableQ[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_run_enableQ~0 0xc0 9.25978e+06 0.25; - u0_m0_wo0_run_q[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_run_q[0]~feeder 0xc0 1.92012e+07 0.5; - altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem; - altsyncram_0mn3:auto_generated; - q_b[0] 0xc0 1.92012e+07 0.5; - q_b[1] 0xc0 1.92012e+07 0.5; - q_b[2] 0xc0 1.92012e+07 0.5; - q_b[3] 0xc0 1.92012e+07 0.5; - q_b[4] 0xc0 1.92012e+07 0.5; - q_b[5] 0xc0 1.92012e+07 0.5; - q_b[6] 0xc0 1.92012e+07 0.5; - q_b[7] 0xc0 1.92012e+07 0.5; - q_b[8] 0xc0 1.92012e+07 0.5; - q_b[9] 0xc0 1.92012e+07 0.5; - q_b[10] 0xc0 1.92012e+07 0.5; - q_b[11] 0xc0 1.92012e+07 0.5; - q_b[12] 0xc0 1.92012e+07 0.5; - q_b[13] 0xc0 1.92012e+07 0.5; - q_b[14] 0xc0 1.92012e+07 0.5; - q_b[15] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0]~6 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0]~7 0xc0 1.08007e+07 0.25; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1]~8 0xc0 1.6201e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1]~9 0xc0 8.94432e+06 0.625; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2]~10 0xc0 1.37118e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2]~11 0xc0 1.59315e+07 0.4375; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3]~12 0xc0 1.49523e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3]~13 0xc0 1.22202e+07 0.53125; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4]~14 0xc0 1.38979e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4]~15 0xc0 1.36478e+07 0.484375; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[5]~16 0xc0 1.78269e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_clkproc~0 0xc0 1.44009e+07 0.25; - u0_m0_wo0_wi0_r0_ra0_count0_i[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[0]~5 0xc0 1.5601e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[1]~6 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[1]~7 0xc0 1.08007e+07 0.25; - u0_m0_wo0_wi0_r0_ra0_count0_i[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[2]~8 0xc0 1.74011e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[2]~9 0xc0 4.57529e+06 0.875; - u0_m0_wo0_wi0_r0_ra0_count0_i[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[3]~10 0xc0 1.72886e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[3]~11 0xc0 1.61448e+07 0.0625; - u0_m0_wo0_wi0_r0_ra0_count0_i[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[4]~12 0xc0 2.50235e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[4]~13 0xc0 4.18621e+06 0.96875; - u0_m0_wo0_wi0_r0_ra0_count0_i[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[5]~14 0xc0 2.01318e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0]~7 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0]~8 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1]~9 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1]~10 0xc0 1.08007e+07 0.25; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2]~11 0xc0 1.74011e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2]~12 0xc0 5.10033e+06 0.875; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3]~13 0xc0 1.75511e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3]~14 0xc0 1.6276e+07 0.0625; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4]~15 0xc0 2.50891e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4]~16 0xc0 4.21902e+06 0.96875; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5]~17 0xc0 2.01482e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5]~18 0xc0 1.90934e+07 0.015625; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6]~19 0xc0 2.81573e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[0]~15 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[1]~5 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[1]~6 0xc0 1.08007e+07 0.25; - u0_m0_wo0_wi0_r0_ra0_count1_i[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[2]~7 0xc0 1.74011e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[2]~8 0xc0 4.57529e+06 0.875; - u0_m0_wo0_wi0_r0_ra0_count1_i[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[3]~9 0xc0 1.72886e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[3]~10 0xc0 1.61448e+07 0.0625; - u0_m0_wo0_wi0_r0_ra0_count1_i[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[4]~11 0xc0 2.50235e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[4]~12 0xc0 4.18621e+06 0.96875; - u0_m0_wo0_wi0_r0_ra0_count1_i[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[5]~13 0xc0 2.01318e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[0]~15 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[0]~_wirecell 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[1]~5 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[1]~6 0xc0 1.08007e+07 0.25; - u0_m0_wo0_wi0_r0_wa0_i[1]~_wirecell 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[2]~7 0xc0 1.74011e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[2]~8 0xc0 4.57529e+06 0.875; - u0_m0_wo0_wi0_r0_wa0_i[2]~_wirecell 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[3]~9 0xc0 1.72886e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[3]~10 0xc0 1.61448e+07 0.0625; - u0_m0_wo0_wi0_r0_wa0_i[3]~_wirecell 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[4]~11 0xc0 2.50235e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[4]~12 0xc0 4.18621e+06 0.96875; - u0_m0_wo0_wi0_r0_wa0_i[4]~_wirecell 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[5]~13 0xc0 2.01318e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[5]~_wirecell 0xc0 1.92012e+07 0.5; - auk_dspip_avalon_streaming_sink_hpfir:sink; - auk_dspip_avalon_streaming_source_hpfir:source; - data_out[0] 0xc0 1.92012e+07 0.5; - data_out[1] 0xc0 1.92012e+07 0.5; - data_out[2] 0xc0 1.92012e+07 0.5; - data_out[3] 0xc0 1.92012e+07 0.5; - data_out[4] 0xc0 1.92012e+07 0.5; - data_out[4]~feeder 0xc0 1.92012e+07 0.5; - data_out[5] 0xc0 1.92012e+07 0.5; - data_out[6] 0xc0 1.92012e+07 0.5; - data_out[7] 0xc0 1.92012e+07 0.5; - data_out[8] 0xc0 1.92012e+07 0.5; - data_out[9] 0xc0 1.92012e+07 0.5; - data_out[10] 0xc0 1.92012e+07 0.5; - data_out[11] 0xc0 1.92012e+07 0.5; - data_out[12] 0xc0 1.92012e+07 0.5; - data_out[13] 0xc0 1.92012e+07 0.5; - data_out[14] 0xc0 1.92012e+07 0.5; - data_out[15] 0xc0 1.92012e+07 0.5; - data_out[16] 0xc0 1.92012e+07 0.5; - data_out[17] 0xc0 1.92012e+07 0.5; - data_out[18] 0xc0 1.92012e+07 0.5; - data_out[19] 0xc0 1.92012e+07 0.5; - data_out[20] 0xc0 1.92012e+07 0.5; - data_out[21] 0xc0 1.92012e+07 0.5; - data_out[22] 0xc0 1.92012e+07 0.5; - data_out[23] 0xc0 1.92012e+07 0.5; - data_out[24] 0xc0 1.92012e+07 0.5; - data_out[25] 0xc0 1.92012e+07 0.5; - data_out[26] 0xc0 1.92012e+07 0.5; - data_out[27] 0xc0 1.92012e+07 0.5; - data_out[27]~feeder 0xc0 1.92012e+07 0.5; - data_out[28] 0xc0 1.92012e+07 0.5; - data_out[28]~feeder 0xc0 1.92012e+07 0.5; - data_out[29] 0xc0 1.92012e+07 0.5; - data_valid 0xc0 1.92012e+07 0.5; - tx_ciccomp:TX_CICCOMP_Q; - tx_ciccomp_0002:tx_ciccomp_inst; - tx_ciccomp_0002_ast:tx_ciccomp_0002_ast_inst; - tx_ciccomp_0002_rtl_core:\real_passthrough:hpfircore_core; - Add6~0 0xc0 1.92012e+07 0.5; - Add6~1 0xc0 1.92012e+07 0.5; - Add6~2 0xc0 1.92012e+07 0.5; - Add6~2_wirecell 0xc0 1.92012e+07 0.5; - Add6~3 0xc0 1.08007e+07 0.25; - Add6~4 0xc0 1.74011e+07 0.5; - Add6~4_wirecell 0xc0 1.74011e+07 0.5; - Add6~5 0xc0 5.10033e+06 0.875; - Add6~6 0xc0 1.75511e+07 0.5; - Add6~6_wirecell 0xc0 1.75511e+07 0.5; - Add6~7 0xc0 1.6276e+07 0.0625; - Add6~8 0xc0 2.50891e+07 0.5; - Add6~8_wirecell 0xc0 2.50891e+07 0.5; - Add6~9 0xc0 4.21902e+06 0.96875; - Add6~10 0xc0 2.01482e+07 0.5; - Add6~10_wirecell 0xc0 2.01482e+07 0.5; - Add6~11 0xc0 1.90934e+07 0.015625; - Add6~12 0xc0 2.81573e+07 0.5; - dspba_delay:d_u0_m0_wo0_accum_p1_of_2_q_17; - delay_signals[0][0] 0xc0 1.92012e+07 0.5; - delay_signals[0][0]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][1] 0xc0 1.92012e+07 0.5; - delay_signals[0][2] 0xc0 1.92012e+07 0.5; - delay_signals[0][3] 0xc0 1.92012e+07 0.5; - delay_signals[0][4] 0xc0 1.92012e+07 0.5; - delay_signals[0][4]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][5] 0xc0 1.92012e+07 0.5; - delay_signals[0][5]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][6] 0xc0 1.92012e+07 0.5; - delay_signals[0][6]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][7] 0xc0 1.92012e+07 0.5; - delay_signals[0][7]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][8] 0xc0 1.92012e+07 0.5; - delay_signals[0][8]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][9] 0xc0 1.92012e+07 0.5; - delay_signals[0][9]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][10] 0xc0 1.92012e+07 0.5; - delay_signals[0][11] 0xc0 1.92012e+07 0.5; - delay_signals[0][12] 0xc0 1.92012e+07 0.5; - delay_signals[0][12]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][13] 0xc0 1.92012e+07 0.5; - delay_signals[0][14] 0xc0 1.92012e+07 0.5; - delay_signals[0][14]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][15] 0xc0 1.92012e+07 0.5; - delay_signals[0][15]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][16] 0xc0 1.92012e+07 0.5; - delay_signals[0][16]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][17] 0xc0 1.92012e+07 0.5; - delay_signals[0][17]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][18] 0xc0 1.92012e+07 0.5; - delay_signals[0][19] 0xc0 1.92012e+07 0.5; - delay_signals[0][19]~feeder 0xc0 1.92012e+07 0.5; - dspba_delay:d_u0_m0_wo0_mtree_mult1_0_q_16; - delay_signals[0][20] 0xc0 1.92012e+07 0.5; - delay_signals[0][21] 0xc0 1.92012e+07 0.5; - delay_signals[0][21]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][22] 0xc0 1.92012e+07 0.5; - delay_signals[0][23] 0xc0 1.92012e+07 0.5; - delay_signals[0][23]~feeder 0xc0 1.92012e+07 0.5; - dspba_delay:d_xIn_0_13; - delay_signals[0][0] 0xc0 1.92012e+07 0.5; - delay_signals[0][1] 0xc0 1.92012e+07 0.5; - delay_signals[0][1]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][2] 0xc0 1.92012e+07 0.5; - delay_signals[0][3] 0xc0 1.92012e+07 0.5; - delay_signals[0][3]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][4] 0xc0 1.92012e+07 0.5; - delay_signals[0][5] 0xc0 1.92012e+07 0.5; - delay_signals[0][5]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][6] 0xc0 1.92012e+07 0.5; - delay_signals[0][6]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][7] 0xc0 1.92012e+07 0.5; - delay_signals[0][7]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][8] 0xc0 1.92012e+07 0.5; - delay_signals[0][8]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][9] 0xc0 1.92012e+07 0.5; - delay_signals[0][9]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][10] 0xc0 1.92012e+07 0.5; - delay_signals[0][11] 0xc0 1.92012e+07 0.5; - delay_signals[0][11]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][12] 0xc0 1.92012e+07 0.5; - delay_signals[0][12]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][13] 0xc0 1.92012e+07 0.5; - delay_signals[0][13]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[0][14] 0xc0 1.92012e+07 0.5; - delay_signals[0][15] 0xc0 1.92012e+07 0.5; - delay_signals[0][15]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][0] 0xc0 1.92012e+07 0.5; - delay_signals[1][1] 0xc0 1.92012e+07 0.5; - delay_signals[1][2] 0xc0 1.92012e+07 0.5; - delay_signals[1][2]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][3] 0xc0 1.92012e+07 0.5; - delay_signals[1][3]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][4] 0xc0 1.92012e+07 0.5; - delay_signals[1][4]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][5] 0xc0 1.92012e+07 0.5; - delay_signals[1][6] 0xc0 1.92012e+07 0.5; - delay_signals[1][6]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][7] 0xc0 1.92012e+07 0.5; - delay_signals[1][8] 0xc0 1.92012e+07 0.5; - delay_signals[1][8]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][9] 0xc0 1.92012e+07 0.5; - delay_signals[1][9]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][10] 0xc0 1.92012e+07 0.5; - delay_signals[1][11] 0xc0 1.92012e+07 0.5; - delay_signals[1][11]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][12] 0xc0 1.92012e+07 0.5; - delay_signals[1][12]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][13] 0xc0 1.92012e+07 0.5; - delay_signals[1][13]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][14] 0xc0 1.92012e+07 0.5; - delay_signals[1][14]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[1][15] 0xc0 1.92012e+07 0.5; - delay_signals[1][15]~feeder 0xc0 1.92012e+07 0.5; - delay_signals[2][0] 0xc0 1.92012e+07 0.5; - delay_signals[2][0]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][1] 0xc0 1.92012e+07 0.5; - delay_signals[2][1]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][2] 0xc0 1.92012e+07 0.5; - delay_signals[2][3] 0xc0 1.92012e+07 0.5; - delay_signals[2][3]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][4] 0xc0 1.92012e+07 0.5; - delay_signals[2][5] 0xc0 1.92012e+07 0.5; - delay_signals[2][5]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][6] 0xc0 1.92012e+07 0.5; - delay_signals[2][6]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][7] 0xc0 1.92012e+07 0.5; - delay_signals[2][7]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][8] 0xc0 1.92012e+07 0.5; - delay_signals[2][8]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][9] 0xc0 1.92012e+07 0.5; - delay_signals[2][9]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][10] 0xc0 1.92012e+07 0.5; - delay_signals[2][10]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][11] 0xc0 1.92012e+07 0.5; - delay_signals[2][12] 0xc0 1.92012e+07 0.5; - delay_signals[2][12]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][13] 0xc0 1.92012e+07 0.5; - delay_signals[2][13]~feeder 0xc0 3.125e+06 0.5; - delay_signals[2][14] 0xc0 1.92012e+07 0.5; - delay_signals[2][15] 0xc0 1.92012e+07 0.5; - delay_signals[2][15]~feeder 0xc0 3.125e+06 0.5; - Mux2~0 0xc0 1.48603e+07 0.125; - Mux2~1 0xc0 2.4707e+07 0.28125; - Mux3~0 0xc0 7.21452e+06 0.4375; - Mux3~1 0xc0 7.21452e+06 0.4375; - Mux3~2 0xc0 1.51198e+07 0.40625; - Mux3~3 0xc0 2.76864e+07 0.382813; - Mux4~0 0xc0 1.08757e+07 0.5; - Mux4~1 0xc0 7.24734e+06 0.5; - Mux4~2 0xc0 1.50393e+07 0.390625; - Mux4~3 0xc0 1.99845e+07 0.359863; - Mux5~0 0xc0 8.94432e+06 0.5625; - Mux5~1 0xc0 7.21452e+06 0.5625; - Mux5~2 0xc0 1.68556e+07 0.375; - Mux5~3 0xc0 1.99276e+07 0.335938; - Mux6~0 0xc0 8.52242e+06 0.375; - Mux6~1 0xc0 8.52242e+06 0.625; - Mux6~2 0xc0 1.91842e+07 0.421875; - Mux6~3 0xc0 1.47046e+07 0.404785; - Mux7~0 0xc0 7.97395e+06 0.4375; - Mux7~1 0xc0 1.01256e+07 0.5625; - Mux7~2 0xc0 1.8159e+07 0.375; - Mux7~3 0xc0 3.39019e+07 0.335938; - Mux8~0 0xc0 8.38179e+06 0.4375; - Mux8~1 0xc0 7.63643e+06 0.5625; - Mux8~2 0xc0 2.75113e+07 0.390625; - Mux8~3 0xc0 1.21151e+07 0.353027; - Mux9~0 0xc0 5.23158e+06 0.25; - Mux9~1 0xc0 7.763e+06 0.75; - Mux9~2 0xc0 1.7298e+06 0.0625; - Mux9~3 0xc0 1.02013e+07 0.328125; - Mux9~4 0xc0 2.36265e+06 0.0625; - Mux9~5 0xc0 1.33417e+07 0.258301; - Mux9~6 0xc0 4.57529e+06 0.125; - Mux9~7 0xc0 5.70036e+06 0.125; - u0_m0_wo0_accum_p1_of_2_o[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[0]~21 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[0]~22 0xc0 1.08007e+07 0.25; - u0_m0_wo0_accum_p1_of_2_o[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[1]~23 0xc0 1.6201e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[1]~24 0xc0 8.94432e+06 0.625; - u0_m0_wo0_accum_p1_of_2_o[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[2]~25 0xc0 1.37118e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[2]~26 0xc0 1.59315e+07 0.4375; - u0_m0_wo0_accum_p1_of_2_o[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[3]~27 0xc0 1.49523e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[3]~28 0xc0 1.22202e+07 0.53125; - u0_m0_wo0_accum_p1_of_2_o[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[4]~29 0xc0 1.38979e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[4]~30 0xc0 1.36478e+07 0.484375; - u0_m0_wo0_accum_p1_of_2_o[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[5]~31 0xc0 1.42232e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[5]~32 0xc0 1.27803e+07 0.507813; - u0_m0_wo0_accum_p1_of_2_o[6] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[6]~33 0xc0 1.39984e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[6]~34 0xc0 1.31698e+07 0.496094; - u0_m0_wo0_accum_p1_of_2_o[7] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[7]~35 0xc0 1.40938e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[7]~36 0xc0 1.29633e+07 0.501953; - u0_m0_wo0_accum_p1_of_2_o[8] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[8]~37 0xc0 1.40417e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[8]~38 0xc0 1.30635e+07 0.499023; - u0_m0_wo0_accum_p1_of_2_o[9] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[9]~39 0xc0 1.40666e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[9]~40 0xc0 1.30126e+07 0.500488; - u0_m0_wo0_accum_p1_of_2_o[10] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[10]~41 0xc0 1.40539e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[10]~42 0xc0 1.30379e+07 0.499756; - u0_m0_wo0_accum_p1_of_2_o[11] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[11]~43 0xc0 1.40602e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[11]~44 0xc0 1.30252e+07 0.500122; - u0_m0_wo0_accum_p1_of_2_o[12] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[12]~45 0xc0 1.4057e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[12]~46 0xc0 1.30315e+07 0.499939; - u0_m0_wo0_accum_p1_of_2_o[13] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[13]~47 0xc0 1.40586e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[13]~48 0xc0 1.30284e+07 0.500031; - u0_m0_wo0_accum_p1_of_2_o[14] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[14]~49 0xc0 1.40578e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[14]~50 0xc0 1.30299e+07 0.499985; - u0_m0_wo0_accum_p1_of_2_o[15] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[15]~51 0xc0 1.40582e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[15]~52 0xc0 1.30291e+07 0.500008; - u0_m0_wo0_accum_p1_of_2_o[16] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[16]~53 0xc0 1.4058e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[16]~54 0xc0 1.30295e+07 0.499996; - u0_m0_wo0_accum_p1_of_2_o[17] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[17]~55 0xc0 1.40581e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[17]~56 0xc0 1.30293e+07 0.500002; - u0_m0_wo0_accum_p1_of_2_o[18] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[18]~57 0xc0 1.4058e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[18]~58 0xc0 1.30294e+07 0.499999; - u0_m0_wo0_accum_p1_of_2_o[19] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[19]~59 0xc0 1.40581e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[19]~60 0xc0 1.30294e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[20] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p1_of_2_o[20]~61 0xc0 1.30294e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[1]~11 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[1]~12 0xc0 1.5601e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[1]~13 0xc0 9.3006e+06 0.5; - u0_m0_wo0_accum_p2_of_2_o[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[2]~14 0xc0 1.31258e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[2]~15 0xc0 1.25633e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[3]~16 0xc0 1.39415e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[3]~17 0xc0 1.29711e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[4]~18 0xc0 1.76437e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[4]~19 0xc0 1.84225e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[5]~20 0xc0 1.90065e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[5]~21 0xc0 1.91039e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[6] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[6]~22 0xc0 1.91769e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[6]~23 0xc0 1.91891e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[7] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[7]~24 0xc0 1.91982e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[7]~25 0xc0 1.91997e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[8] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[8]~26 0xc0 1.92008e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[8]~27 0xc0 1.9201e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[9] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[9]~28 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[9]~29 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[10] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_accum_p2_of_2_o[10]~30 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[0]~15 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[1]~5 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[1]~6 0xc0 1.08007e+07 0.25; - u0_m0_wo0_ca0_i[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[2]~7 0xc0 1.74011e+07 0.5; - u0_m0_wo0_ca0_i[2]~8 0xc0 4.57529e+06 0.875; - u0_m0_wo0_ca0_i[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[3]~9 0xc0 1.72886e+07 0.5; - u0_m0_wo0_ca0_i[3]~10 0xc0 1.61448e+07 0.0625; - u0_m0_wo0_ca0_i[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[4]~11 0xc0 2.50235e+07 0.5; - u0_m0_wo0_ca0_i[4]~12 0xc0 4.18621e+06 0.96875; - u0_m0_wo0_ca0_i[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_ca0_i[5]~13 0xc0 2.01318e+07 0.5; - u0_m0_wo0_cm0_q[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_cm0_q[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_cm0_q[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_cm0_q[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_cm0_q[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_cm0_q[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_cm0_q[6] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_cm0_q[7] 0xc0 1.92012e+07 0.5; - lpm_mult:u0_m0_wo0_mtree_mult1_0_component; - mult_ncu:auto_generated; - mac_mult1 0xc0 7.68049e+07 0.5; - mac_mult1~12 0xc0 0 0; - mac_mult1~13 0xc0 0 0; - mac_mult1~14 0xc0 0 0; - mac_mult1~15 0xc0 0 0; - mac_mult1~16 0xc0 0 0; - mac_mult1~17 0xc0 0 0; - mac_mult1~18 0xc0 0 0; - mac_mult1~19 0xc0 0 0; - mac_mult1~20 0xc0 0 0; - mac_mult1~21 0xc0 0 0; - mac_mult1~22 0xc0 0 0; - mac_mult1~23 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT2 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT3 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT4 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT5 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT6 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT7 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT8 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT9 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT10 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT11 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT12 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT13 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT14 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT15 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT16 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT17 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT18 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT19 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT20 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT21 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT22 0xc0 7.68049e+07 0.5; - mac_mult1~DATAOUT23 0xc0 7.68049e+07 0.5; - result[0] 0xc0 1.92012e+07 0.5; - result[1] 0xc0 1.92012e+07 0.5; - result[2] 0xc0 1.92012e+07 0.5; - result[3] 0xc0 1.92012e+07 0.5; - result[4] 0xc0 1.92012e+07 0.5; - result[5] 0xc0 1.92012e+07 0.5; - result[6] 0xc0 1.92012e+07 0.5; - result[7] 0xc0 1.92012e+07 0.5; - result[8] 0xc0 1.92012e+07 0.5; - result[9] 0xc0 1.92012e+07 0.5; - result[10] 0xc0 1.92012e+07 0.5; - result[11] 0xc0 1.92012e+07 0.5; - result[12] 0xc0 1.92012e+07 0.5; - result[13] 0xc0 1.92012e+07 0.5; - result[14] 0xc0 1.92012e+07 0.5; - result[15] 0xc0 1.92012e+07 0.5; - result[16] 0xc0 1.92012e+07 0.5; - result[17] 0xc0 1.92012e+07 0.5; - result[18] 0xc0 1.92012e+07 0.5; - result[19] 0xc0 1.92012e+07 0.5; - result[20] 0xc0 1.92012e+07 0.5; - result[21] 0xc0 1.92012e+07 0.5; - result[22] 0xc0 1.92012e+07 0.5; - result[23] 0xc0 1.92012e+07 0.5; - altsyncram:u0_m0_wo0_wi0_r0_memr0_dmem; - altsyncram_0mn3:auto_generated; - q_b[0] 0xc0 1.92012e+07 0.5; - q_b[1] 0xc0 1.92012e+07 0.5; - q_b[2] 0xc0 1.92012e+07 0.5; - q_b[3] 0xc0 1.92012e+07 0.5; - q_b[4] 0xc0 1.92012e+07 0.5; - q_b[5] 0xc0 1.92012e+07 0.5; - q_b[6] 0xc0 1.92012e+07 0.5; - q_b[7] 0xc0 1.92012e+07 0.5; - q_b[8] 0xc0 1.92012e+07 0.5; - q_b[9] 0xc0 1.92012e+07 0.5; - q_b[10] 0xc0 1.92012e+07 0.5; - q_b[11] 0xc0 1.92012e+07 0.5; - q_b[12] 0xc0 1.92012e+07 0.5; - q_b[13] 0xc0 1.92012e+07 0.5; - q_b[14] 0xc0 1.92012e+07 0.5; - q_b[15] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0]~6 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[0]~7 0xc0 1.08007e+07 0.25; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1]~8 0xc0 1.6201e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[1]~9 0xc0 8.94432e+06 0.625; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2]~10 0xc0 1.37118e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[2]~11 0xc0 1.59315e+07 0.4375; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3]~12 0xc0 1.49523e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[3]~13 0xc0 1.22202e+07 0.53125; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4]~14 0xc0 1.38979e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[4]~15 0xc0 1.36478e+07 0.484375; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_add_0_0_o[5]~16 0xc0 1.42232e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_clkproc~0 0xc0 1.44009e+07 0.25; - u0_m0_wo0_wi0_r0_ra0_count0_i[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[0]~5 0xc0 1.74011e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[1]~6 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[1]~7 0xc0 1.08007e+07 0.25; - u0_m0_wo0_wi0_r0_ra0_count0_i[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[2]~8 0xc0 1.74011e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[2]~9 0xc0 4.57529e+06 0.875; - u0_m0_wo0_wi0_r0_ra0_count0_i[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[3]~10 0xc0 1.72886e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[3]~11 0xc0 1.61448e+07 0.0625; - u0_m0_wo0_wi0_r0_ra0_count0_i[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[4]~12 0xc0 2.50235e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[4]~13 0xc0 4.18621e+06 0.96875; - u0_m0_wo0_wi0_r0_ra0_count0_i[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_i[5]~14 0xc0 2.01318e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0]~7 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[0]~8 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1]~9 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[1]~10 0xc0 1.08007e+07 0.25; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2]~11 0xc0 1.74011e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[2]~12 0xc0 5.10033e+06 0.875; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3]~13 0xc0 1.75511e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[3]~14 0xc0 1.6276e+07 0.0625; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4]~15 0xc0 2.50891e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[4]~16 0xc0 4.21902e+06 0.96875; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5]~17 0xc0 2.01482e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[5]~18 0xc0 1.90934e+07 0.015625; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count0_inner_i[6]~19 0xc0 2.81573e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[0]~15 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[1]~5 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[1]~6 0xc0 1.08007e+07 0.25; - u0_m0_wo0_wi0_r0_ra0_count1_i[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[2]~7 0xc0 1.74011e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[2]~8 0xc0 4.57529e+06 0.875; - u0_m0_wo0_wi0_r0_ra0_count1_i[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[3]~9 0xc0 1.72886e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[3]~10 0xc0 1.61448e+07 0.0625; - u0_m0_wo0_wi0_r0_ra0_count1_i[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[4]~11 0xc0 2.50235e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[4]~12 0xc0 4.18621e+06 0.96875; - u0_m0_wo0_wi0_r0_ra0_count1_i[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_ra0_count1_i[5]~13 0xc0 2.01318e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[0] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[0]~15 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[0]~_wirecell 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[1] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[1]~5 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[1]~6 0xc0 1.08007e+07 0.25; - u0_m0_wo0_wi0_r0_wa0_i[1]~_wirecell 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[2] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[2]~7 0xc0 1.74011e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[2]~8 0xc0 4.57529e+06 0.875; - u0_m0_wo0_wi0_r0_wa0_i[2]~_wirecell 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[3] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[3]~9 0xc0 1.72886e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[3]~10 0xc0 1.61448e+07 0.0625; - u0_m0_wo0_wi0_r0_wa0_i[3]~_wirecell 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[4] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[4]~11 0xc0 2.50235e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[4]~12 0xc0 4.18621e+06 0.96875; - u0_m0_wo0_wi0_r0_wa0_i[4]~_wirecell 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[5] 0xc0 1.92012e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[5]~13 0xc0 2.01318e+07 0.5; - u0_m0_wo0_wi0_r0_wa0_i[5]~_wirecell 0xc0 1.92012e+07 0.5; - auk_dspip_avalon_streaming_sink_hpfir:sink; - auk_dspip_avalon_streaming_source_hpfir:source; - data_out[0] 0xc0 1.92012e+07 0.5; - data_out[1] 0xc0 1.92012e+07 0.5; - data_out[2] 0xc0 1.92012e+07 0.5; - data_out[3] 0xc0 1.92012e+07 0.5; - data_out[4] 0xc0 1.92012e+07 0.5; - data_out[5] 0xc0 1.92012e+07 0.5; - data_out[6] 0xc0 1.92012e+07 0.5; - data_out[7] 0xc0 1.92012e+07 0.5; - data_out[8] 0xc0 1.92012e+07 0.5; - data_out[9] 0xc0 1.92012e+07 0.5; - data_out[10] 0xc0 1.92012e+07 0.5; - data_out[11] 0xc0 1.92012e+07 0.5; - data_out[12] 0xc0 1.92012e+07 0.5; - data_out[12]~feeder 0xc0 1.92012e+07 0.5; - data_out[13] 0xc0 1.92012e+07 0.5; - data_out[14] 0xc0 1.92012e+07 0.5; - data_out[15] 0xc0 1.92012e+07 0.5; - data_out[16] 0xc0 1.92012e+07 0.5; - data_out[17] 0xc0 1.92012e+07 0.5; - data_out[18] 0xc0 1.92012e+07 0.5; - data_out[19] 0xc0 1.92012e+07 0.5; - data_out[20] 0xc0 1.92012e+07 0.5; - data_out[21] 0xc0 1.92012e+07 0.5; - data_out[22] 0xc0 1.92012e+07 0.5; - data_out[23] 0xc0 1.92012e+07 0.5; - data_out[24] 0xc0 1.92012e+07 0.5; - data_out[24]~feeder 0xc0 1.92012e+07 0.5; - data_out[25] 0xc0 1.92012e+07 0.5; - data_out[25]~feeder 0xc0 1.92012e+07 0.5; - data_out[26] 0xc0 1.92012e+07 0.5; - data_out[26]~feeder 0xc0 1.92012e+07 0.5; - data_out[27] 0xc0 1.92012e+07 0.5; - data_out[27]~feeder 0xc0 1.92012e+07 0.5; - data_out[28] 0xc0 1.92012e+07 0.5; - data_out[29] 0xc0 1.92012e+07 0.5; - tx_mixer:TX_MIXER_I; - lpm_mult:lpm_mult_component; - mult_abt:auto_generated; - mac_mult1 0xc0 3.84025e+07 0.5; - mac_mult1~0 0xc0 0 0; - mac_mult1~1 0xc0 0 0; - mac_mult1~2 0xc0 0 0; - mac_mult1~3 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT2 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT3 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT4 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT5 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT6 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT7 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT8 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT9 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT10 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT11 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT12 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT13 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT14 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT15 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT16 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT17 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT18 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT19 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT20 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT21 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT22 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT23 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT24 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT25 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT26 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT27 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT28 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT29 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT30 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT31 0xc0 3.84025e+07 0.5; - result[0] 0xc0 1.92012e+07 0.5; - result[1] 0xc0 1.92012e+07 0.5; - result[2] 0xc0 1.92012e+07 0.5; - result[3] 0xc0 1.92012e+07 0.5; - result[4] 0xc0 1.92012e+07 0.5; - result[5] 0xc0 1.92012e+07 0.5; - result[6] 0xc0 1.92012e+07 0.5; - result[7] 0xc0 1.92012e+07 0.5; - result[8] 0xc0 1.92012e+07 0.5; - result[9] 0xc0 1.92012e+07 0.5; - result[10] 0xc0 1.92012e+07 0.5; - result[11] 0xc0 1.92012e+07 0.5; - result[12] 0xc0 1.92012e+07 0.5; - result[13] 0xc0 1.92012e+07 0.5; - result[14] 0xc0 1.92012e+07 0.5; - result[15] 0xc0 1.92012e+07 0.5; - result[16] 0xc0 1.92012e+07 0.5; - result[17] 0xc0 1.92012e+07 0.5; - result[18] 0xc0 1.92012e+07 0.5; - result[19] 0xc0 1.92012e+07 0.5; - result[20] 0xc0 1.92012e+07 0.5; - result[21] 0xc0 1.92012e+07 0.5; - result[22] 0xc0 1.92012e+07 0.5; - result[23] 0xc0 1.92012e+07 0.5; - result[24] 0xc0 1.92012e+07 0.5; - result[25] 0xc0 1.92012e+07 0.5; - result[26] 0xc0 1.92012e+07 0.5; - result[27] 0xc0 1.92012e+07 0.5; - result[28] 0xc0 1.92012e+07 0.5; - result[29] 0xc0 1.92012e+07 0.5; - result[30] 0xc0 1.92012e+07 0.5; - result[31] 0xc0 1.92012e+07 0.5; - tx_mixer:TX_MIXER_Q; - lpm_mult:lpm_mult_component; - mult_abt:auto_generated; - mac_mult1 0xc0 3.84025e+07 0.5; - mac_mult1~0 0xc0 0 0; - mac_mult1~1 0xc0 0 0; - mac_mult1~2 0xc0 0 0; - mac_mult1~3 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT2 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT3 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT4 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT5 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT6 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT7 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT8 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT9 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT10 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT11 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT12 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT13 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT14 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT15 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT16 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT17 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT18 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT19 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT20 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT21 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT22 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT23 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT24 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT25 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT26 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT27 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT28 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT29 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT30 0xc0 3.84025e+07 0.5; - mac_mult1~DATAOUT31 0xc0 3.84025e+07 0.5; - result[0] 0xc0 1.92012e+07 0.5; - result[1] 0xc0 1.92012e+07 0.5; - result[2] 0xc0 1.92012e+07 0.5; - result[3] 0xc0 1.92012e+07 0.5; - result[4] 0xc0 1.92012e+07 0.5; - result[5] 0xc0 1.92012e+07 0.5; - result[6] 0xc0 1.92012e+07 0.5; - result[7] 0xc0 1.92012e+07 0.5; - result[8] 0xc0 1.92012e+07 0.5; - result[9] 0xc0 1.92012e+07 0.5; - result[10] 0xc0 1.92012e+07 0.5; - result[11] 0xc0 1.92012e+07 0.5; - result[12] 0xc0 1.92012e+07 0.5; - result[13] 0xc0 1.92012e+07 0.5; - result[14] 0xc0 1.92012e+07 0.5; - result[15] 0xc0 1.92012e+07 0.5; - result[16] 0xc0 1.92012e+07 0.5; - result[17] 0xc0 1.92012e+07 0.5; - result[18] 0xc0 1.92012e+07 0.5; - result[19] 0xc0 1.92012e+07 0.5; - result[20] 0xc0 1.92012e+07 0.5; - result[21] 0xc0 1.92012e+07 0.5; - result[22] 0xc0 1.92012e+07 0.5; - result[23] 0xc0 1.92012e+07 0.5; - result[24] 0xc0 1.92012e+07 0.5; - result[25] 0xc0 1.92012e+07 0.5; - result[26] 0xc0 1.92012e+07 0.5; - result[27] 0xc0 1.92012e+07 0.5; - result[28] 0xc0 1.92012e+07 0.5; - result[29] 0xc0 1.92012e+07 0.5; - result[30] 0xc0 1.92012e+07 0.5; - result[31] 0xc0 1.92012e+07 0.5; - tx_nco:TX_NCO; - tx_nco_nco_ii_0:nco_ii_0; - asj_nco_mob_w:blk0; - Equal0~0 0xc0 2.36265e+06 0.0625; - Equal0~1 0xc0 1.08007e+07 0.25; - Equal0~2 0xc0 42808.2 0.00390625; - Equal0~3 0xc0 2.36265e+06 0.0625; - Equal0~4 0xc0 2.36265e+06 0.0625; - Equal0~5 0xc0 16681.7 0.999992; - add_one 0xc0 1.44009e+07 0.25; - data_tmp[0] 0xc0 1.92012e+07 0.5; - data_tmp[1] 0xc0 1.92012e+07 0.5; - data_tmp[2] 0xc0 1.92012e+07 0.5; - data_tmp[3] 0xc0 1.92012e+07 0.5; - data_tmp[4] 0xc0 1.92012e+07 0.5; - data_tmp[5] 0xc0 1.92012e+07 0.5; - data_tmp[6] 0xc0 1.92012e+07 0.5; - data_tmp[7] 0xc0 1.92012e+07 0.5; - data_tmp[8] 0xc0 1.92012e+07 0.5; - data_tmp[9] 0xc0 1.92012e+07 0.5; - data_tmp[10] 0xc0 1.92012e+07 0.5; - data_tmp[11] 0xc0 1.92012e+07 0.5; - data_tmp[12] 0xc0 1.92012e+07 0.5; - data_tmp[13] 0xc0 1.92012e+07 0.5; - data_tmp[14] 0xc0 1.92012e+07 0.5; - data_tmp[15] 0xc0 1.92012e+07 0.5; - is_zero 0xc0 1.92012e+07 0.5; - lpm_add_sub:lpm_add_sub_component; - add_sub_jpk:auto_generated; - pipeline_dffe[0]~16 0xc0 1.92012e+07 0.5; - pipeline_dffe[0]~17 0xc0 8.40054e+06 0.125; - pipeline_dffe[1]~18 0xc0 1.92012e+07 0.5; - pipeline_dffe[1]~19 0xc0 2.92519e+06 0.9375; - pipeline_dffe[2]~20 0xc0 1.84137e+07 0.5; - pipeline_dffe[2]~21 0xc0 1.76824e+07 0.03125; - pipeline_dffe[3]~22 0xc0 2.68798e+07 0.5; - pipeline_dffe[3]~23 0xc0 4.4581e+06 0.984375; - pipeline_dffe[4]~24 0xc0 2.08396e+07 0.5; - pipeline_dffe[4]~25 0xc0 1.97251e+07 0.0078125; - pipeline_dffe[5]~26 0xc0 2.87661e+07 0.5; - pipeline_dffe[5]~27 0xc0 4.93362e+06 0.996094; - pipeline_dffe[6]~28 0xc0 2.15186e+07 0.5; - pipeline_dffe[6]~29 0xc0 2.02852e+07 0.00195313; - pipeline_dffe[7]~30 0xc0 2.9269e+07 0.5; - pipeline_dffe[7]~31 0xc0 5.07145e+06 0.999023; - pipeline_dffe[8]~32 0xc0 2.16995e+07 0.5; - pipeline_dffe[8]~33 0xc0 2.04316e+07 0.000488281; - pipeline_dffe[9]~34 0xc0 2.93983e+07 0.5; - pipeline_dffe[9]~35 0xc0 5.10792e+06 0.999756; - pipeline_dffe[10]~36 0xc0 2.17458e+07 0.5; - pipeline_dffe[10]~37 0xc0 2.04688e+07 0.00012207; - pipeline_dffe[11]~38 0xc0 2.9431e+07 0.5; - pipeline_dffe[11]~39 0xc0 5.11721e+06 0.999939; - pipeline_dffe[12]~40 0xc0 2.17575e+07 0.5; - pipeline_dffe[12]~41 0xc0 2.04782e+07 3.05176e-05; - pipeline_dffe[13]~42 0xc0 2.94392e+07 0.5; - pipeline_dffe[13]~43 0xc0 5.11955e+06 0.999985; - pipeline_dffe[14]~44 0xc0 2.17604e+07 0.5; - pipeline_dffe[14]~45 0xc0 2.04805e+07 7.62939e-06; - pipeline_dffe[15]~46 0xc0 2.94412e+07 0.5; - asj_nco_mob_w:blk1; - Equal0~0 0xc0 2.36265e+06 0.0625; - Equal0~1 0xc0 1.08007e+07 0.25; - Equal0~2 0xc0 46159.3 0.00390625; - Equal0~3 0xc0 2.36265e+06 0.0625; - Equal0~4 0xc0 2.36265e+06 0.0625; - Equal0~5 0xc0 3.36133 0.999992; - add_one 0xc0 1.44009e+07 0.25; - data_tmp[0] 0xc0 1.92012e+07 0.5; - data_tmp[1] 0xc0 1.92012e+07 0.5; - data_tmp[2] 0xc0 1.92012e+07 0.5; - data_tmp[3] 0xc0 1.92012e+07 0.5; - data_tmp[4] 0xc0 1.92012e+07 0.5; - data_tmp[5] 0xc0 1.92012e+07 0.5; - data_tmp[6] 0xc0 1.92012e+07 0.5; - data_tmp[7] 0xc0 1.92012e+07 0.5; - data_tmp[8] 0xc0 1.92012e+07 0.5; - data_tmp[9] 0xc0 1.92012e+07 0.5; - data_tmp[10] 0xc0 1.92012e+07 0.5; - data_tmp[11] 0xc0 1.92012e+07 0.5; - data_tmp[12] 0xc0 1.92012e+07 0.5; - data_tmp[13] 0xc0 1.92012e+07 0.5; - data_tmp[14] 0xc0 1.92012e+07 0.5; - data_tmp[15] 0xc0 1.92012e+07 0.5; - is_zero 0xc0 1.92012e+07 0.5; - lpm_add_sub:lpm_add_sub_component; - add_sub_jpk:auto_generated; - pipeline_dffe[0]~16 0xc0 1.92012e+07 0.5; - pipeline_dffe[0]~17 0xc0 8.40054e+06 0.125; - pipeline_dffe[1]~18 0xc0 1.92012e+07 0.5; - pipeline_dffe[1]~19 0xc0 2.92519e+06 0.9375; - pipeline_dffe[2]~20 0xc0 1.84137e+07 0.5; - pipeline_dffe[2]~21 0xc0 1.76824e+07 0.03125; - pipeline_dffe[3]~22 0xc0 2.68798e+07 0.5; - pipeline_dffe[3]~23 0xc0 4.4581e+06 0.984375; - pipeline_dffe[4]~24 0xc0 2.08396e+07 0.5; - pipeline_dffe[4]~25 0xc0 1.97251e+07 0.0078125; - pipeline_dffe[5]~26 0xc0 2.87661e+07 0.5; - pipeline_dffe[5]~27 0xc0 4.93362e+06 0.996094; - pipeline_dffe[6]~28 0xc0 2.15186e+07 0.5; - pipeline_dffe[6]~29 0xc0 2.02852e+07 0.00195313; - pipeline_dffe[7]~30 0xc0 2.9269e+07 0.5; - pipeline_dffe[7]~31 0xc0 5.07145e+06 0.999023; - pipeline_dffe[8]~32 0xc0 2.16995e+07 0.5; - pipeline_dffe[8]~33 0xc0 2.04316e+07 0.000488281; - pipeline_dffe[9]~34 0xc0 2.93983e+07 0.5; - pipeline_dffe[9]~35 0xc0 5.10792e+06 0.999756; - pipeline_dffe[10]~36 0xc0 2.17458e+07 0.5; - pipeline_dffe[10]~37 0xc0 2.04688e+07 0.00012207; - pipeline_dffe[11]~38 0xc0 2.9431e+07 0.5; - pipeline_dffe[11]~39 0xc0 5.11721e+06 0.999939; - pipeline_dffe[12]~40 0xc0 2.17575e+07 0.5; - pipeline_dffe[12]~41 0xc0 2.04782e+07 3.05176e-05; - pipeline_dffe[13]~42 0xc0 2.94392e+07 0.5; - pipeline_dffe[13]~43 0xc0 5.11955e+06 0.999985; - pipeline_dffe[14]~44 0xc0 2.17604e+07 0.5; - pipeline_dffe[14]~45 0xc0 2.04805e+07 7.62939e-06; - pipeline_dffe[15]~46 0xc0 2.94412e+07 0.5; - asj_nco_mady_cen:m0; - lpm_mult:Mult0; - mult_36t:auto_generated; - mac_mult1 0xc0 4.80031e+06 0.5; - mac_mult1~0 0xc0 0 0; - mac_mult1~1 0xc0 0 0; - mac_mult1~2 0xc0 0 0; - mac_mult1~3 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT2 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT3 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT4 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT5 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT6 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT7 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT8 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT9 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT10 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT11 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT12 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT13 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT14 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT15 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT16 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT17 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT18 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT19 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT20 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT21 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT22 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT23 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT24 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT25 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT26 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT27 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT28 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT29 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT30 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT31 0xc0 4.80031e+06 0.5; - mac_out2 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT1 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT2 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT3 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT4 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT5 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT6 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT7 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT8 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT9 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT10 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT11 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT12 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT13 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT14 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT15 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT16 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT17 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT18 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT19 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT20 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT21 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT22 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT23 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT24 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT25 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT26 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT27 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT28 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT29 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT30 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT31 0xc0 4.80031e+06 0.5; - lpm_mult:Mult1; - mult_36t:auto_generated; - mac_mult1 0xc0 4.80031e+06 0.5; - mac_mult1~0 0xc0 0 0; - mac_mult1~1 0xc0 0 0; - mac_mult1~2 0xc0 0 0; - mac_mult1~3 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT2 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT3 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT4 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT5 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT6 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT7 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT8 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT9 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT10 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT11 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT12 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT13 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT14 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT15 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT16 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT17 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT18 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT19 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT20 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT21 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT22 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT23 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT24 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT25 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT26 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT27 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT28 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT29 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT30 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT31 0xc0 4.80031e+06 0.5; - mac_out2 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT1 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT2 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT3 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT4 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT5 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT6 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT7 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT8 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT9 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT10 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT11 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT12 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT13 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT14 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT15 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT16 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT17 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT18 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT19 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT20 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT21 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT22 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT23 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT24 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT25 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT26 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT27 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT28 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT29 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT30 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT31 0xc0 4.80031e+06 0.5; - out[15] 0xc0 1.92012e+07 0.5; - out[15]~18 0xc0 2.47516e+06 0.25; - out[15]~20 0xc0 1.89746e+06 0.625; - out[15]~22 0xc0 3.52567e+06 0.4375; - out[15]~24 0xc0 2.68324e+06 0.53125; - out[15]~26 0xc0 3.01258e+06 0.484375; - out[15]~28 0xc0 2.81434e+06 0.507813; - out[15]~30 0xc0 2.90374e+06 0.496094; - out[15]~32 0xc0 2.85644e+06 0.501953; - out[15]~34 0xc0 2.87942e+06 0.499023; - out[15]~36 0xc0 2.86776e+06 0.500488; - out[15]~38 0xc0 2.87355e+06 0.499756; - out[15]~40 0xc0 2.87065e+06 0.500122; - out[15]~42 0xc0 2.8721e+06 0.499939; - out[15]~44 0xc0 2.87137e+06 0.500031; - out[15]~46 0xc0 2.87173e+06 0.499985; - out[15]~47 0xc0 3.19309e+06 0.5; - out[15]~48 0xc0 2.87155e+06 0.500008; - out[16] 0xc0 1.92012e+07 0.5; - out[16]~49 0xc0 3.19305e+06 0.5; - out[16]~50 0xc0 2.87164e+06 0.499996; - out[17] 0xc0 1.92012e+07 0.5; - out[17]~51 0xc0 3.19307e+06 0.5; - out[17]~52 0xc0 2.8716e+06 0.500002; - out[18] 0xc0 1.92012e+07 0.5; - out[18]~53 0xc0 3.19306e+06 0.5; - out[18]~54 0xc0 2.87162e+06 0.499999; - out[19] 0xc0 1.92012e+07 0.5; - out[19]~55 0xc0 3.19306e+06 0.5; - out[19]~56 0xc0 2.87161e+06 0.5; - out[20] 0xc0 1.92012e+07 0.5; - out[20]~57 0xc0 3.19306e+06 0.5; - out[20]~58 0xc0 2.87161e+06 0.5; - out[21] 0xc0 1.92012e+07 0.5; - out[21]~59 0xc0 3.19306e+06 0.5; - out[21]~60 0xc0 2.87161e+06 0.5; - out[22] 0xc0 1.92012e+07 0.5; - out[22]~61 0xc0 3.19306e+06 0.5; - out[22]~62 0xc0 2.87161e+06 0.5; - out[23] 0xc0 1.92012e+07 0.5; - out[23]~63 0xc0 3.19306e+06 0.5; - out[23]~64 0xc0 2.87161e+06 0.5; - out[24] 0xc0 1.92012e+07 0.5; - out[24]~65 0xc0 3.19306e+06 0.5; - out[24]~66 0xc0 2.87161e+06 0.5; - out[25] 0xc0 1.92012e+07 0.5; - out[25]~67 0xc0 3.19306e+06 0.5; - out[25]~68 0xc0 2.87161e+06 0.5; - out[26] 0xc0 1.92012e+07 0.5; - out[26]~69 0xc0 3.19306e+06 0.5; - out[26]~70 0xc0 2.87161e+06 0.5; - out[27] 0xc0 1.92012e+07 0.5; - out[27]~71 0xc0 3.19306e+06 0.5; - out[27]~72 0xc0 2.87161e+06 0.5; - out[28] 0xc0 1.92012e+07 0.5; - out[28]~73 0xc0 3.19306e+06 0.5; - out[28]~74 0xc0 2.87161e+06 0.5; - out[29] 0xc0 1.92012e+07 0.5; - out[29]~75 0xc0 3.19306e+06 0.5; - out[29]~76 0xc0 2.87161e+06 0.5; - out[30] 0xc0 1.92012e+07 0.5; - out[30]~77 0xc0 3.19306e+06 0.5; - out[30]~78 0xc0 2.87161e+06 0.5; - out[31] 0xc0 1.92012e+07 0.5; - out[31]~79 0xc0 4.31813e+06 0.5; - asj_nco_madx_cen:m1; - lpm_mult:Mult0; - mult_36t:auto_generated; - mac_mult1 0xc0 4.80031e+06 0.5; - mac_mult1~0 0xc0 0 0; - mac_mult1~1 0xc0 0 0; - mac_mult1~2 0xc0 0 0; - mac_mult1~3 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT2 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT3 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT4 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT5 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT6 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT7 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT8 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT9 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT10 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT11 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT12 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT13 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT14 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT15 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT16 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT17 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT18 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT19 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT20 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT21 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT22 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT23 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT24 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT25 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT26 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT27 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT28 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT29 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT30 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT31 0xc0 4.80031e+06 0.5; - mac_out2 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT1 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT2 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT3 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT4 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT5 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT6 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT7 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT8 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT9 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT10 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT11 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT12 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT13 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT14 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT15 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT16 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT17 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT18 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT19 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT20 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT21 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT22 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT23 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT24 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT25 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT26 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT27 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT28 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT29 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT30 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT31 0xc0 4.80031e+06 0.5; - lpm_mult:Mult1; - mult_36t:auto_generated; - mac_mult1 0xc0 4.80031e+06 0.5; - mac_mult1~0 0xc0 0 0; - mac_mult1~1 0xc0 0 0; - mac_mult1~2 0xc0 0 0; - mac_mult1~3 0xc0 0 0; - mac_mult1~DATAOUT1 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT2 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT3 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT4 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT5 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT6 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT7 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT8 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT9 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT10 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT11 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT12 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT13 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT14 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT15 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT16 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT17 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT18 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT19 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT20 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT21 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT22 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT23 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT24 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT25 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT26 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT27 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT28 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT29 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT30 0xc0 4.80031e+06 0.5; - mac_mult1~DATAOUT31 0xc0 4.80031e+06 0.5; - mac_out2 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT1 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT2 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT3 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT4 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT5 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT6 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT7 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT8 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT9 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT10 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT11 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT12 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT13 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT14 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT15 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT16 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT17 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT18 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT19 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT20 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT21 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT22 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT23 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT24 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT25 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT26 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT27 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT28 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT29 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT30 0xc0 4.80031e+06 0.5; - mac_out2~DATAOUT31 0xc0 4.80031e+06 0.5; - out[15] 0xc0 1.92012e+07 0.5; - out[15]~18 0xc0 2.47516e+06 0.75; - out[15]~20 0xc0 1.89746e+06 0.375; - out[15]~22 0xc0 2.2881e+06 0.5625; - out[15]~24 0xc0 3.14733e+06 0.46875; - out[15]~26 0xc0 2.76119e+06 0.515625; - out[15]~28 0xc0 2.93761e+06 0.492188; - out[15]~30 0xc0 2.8418e+06 0.503906; - out[15]~32 0xc0 2.88738e+06 0.498047; - out[15]~34 0xc0 2.86395e+06 0.500977; - out[15]~36 0xc0 2.8755e+06 0.499512; - out[15]~38 0xc0 2.86968e+06 0.500244; - out[15]~40 0xc0 2.87258e+06 0.499878; - out[15]~42 0xc0 2.87113e+06 0.500061; - out[15]~44 0xc0 2.87185e+06 0.499969; - out[15]~46 0xc0 2.87149e+06 0.500015; - out[15]~47 0xc0 3.19303e+06 0.5; - out[15]~48 0xc0 2.87167e+06 0.499992; - out[16] 0xc0 1.92012e+07 0.5; - out[16]~49 0xc0 3.19308e+06 0.5; - out[16]~50 0xc0 2.87158e+06 0.500004; - out[17] 0xc0 1.92012e+07 0.5; - out[17]~51 0xc0 3.19305e+06 0.5; - out[17]~52 0xc0 2.87163e+06 0.499998; - out[18] 0xc0 1.92012e+07 0.5; - out[18]~53 0xc0 3.19307e+06 0.5; - out[18]~54 0xc0 2.8716e+06 0.500001; - out[19] 0xc0 1.92012e+07 0.5; - out[19]~55 0xc0 3.19306e+06 0.5; - out[19]~56 0xc0 2.87162e+06 0.5; - out[20] 0xc0 1.92012e+07 0.5; - out[20]~57 0xc0 3.19306e+06 0.5; - out[20]~58 0xc0 2.87161e+06 0.5; - out[21] 0xc0 1.92012e+07 0.5; - out[21]~59 0xc0 3.19306e+06 0.5; - out[21]~60 0xc0 2.87161e+06 0.5; - out[22] 0xc0 1.92012e+07 0.5; - out[22]~61 0xc0 3.19306e+06 0.5; - out[22]~62 0xc0 2.87161e+06 0.5; - out[23] 0xc0 1.92012e+07 0.5; - out[23]~63 0xc0 3.19306e+06 0.5; - out[23]~64 0xc0 2.87161e+06 0.5; - out[24] 0xc0 1.92012e+07 0.5; - out[24]~65 0xc0 3.19306e+06 0.5; - out[24]~66 0xc0 2.87161e+06 0.5; - out[25] 0xc0 1.92012e+07 0.5; - out[25]~67 0xc0 3.19306e+06 0.5; - out[25]~68 0xc0 2.87161e+06 0.5; - out[26] 0xc0 1.92012e+07 0.5; - out[26]~69 0xc0 3.19306e+06 0.5; - out[26]~70 0xc0 2.87161e+06 0.5; - out[27] 0xc0 1.92012e+07 0.5; - out[27]~71 0xc0 3.19306e+06 0.5; - out[27]~72 0xc0 2.87161e+06 0.5; - out[28] 0xc0 1.92012e+07 0.5; - out[28]~73 0xc0 3.19306e+06 0.5; - out[28]~74 0xc0 2.87161e+06 0.5; - out[29] 0xc0 1.92012e+07 0.5; - out[29]~75 0xc0 3.19306e+06 0.5; - out[29]~76 0xc0 2.87161e+06 0.5; - out[30] 0xc0 1.92012e+07 0.5; - out[30]~77 0xc0 3.19306e+06 0.5; - out[30]~78 0xc0 2.87161e+06 0.5; - out[31] 0xc0 1.92012e+07 0.5; - out[31]~79 0xc0 4.31813e+06 0.5; - asj_altqmcpipe:ux000; - lpm_add_sub:acc; - add_sub_u4i:auto_generated; - pipeline_dffe[0] 0xc0 1.92012e+07 0.5; - pipeline_dffe[0]~22 0xc0 1.92012e+07 0.5; - pipeline_dffe[0]~23 0xc0 1.08007e+07 0.25; - pipeline_dffe[1] 0xc0 1.92012e+07 0.5; - pipeline_dffe[1]~24 0xc0 1.6201e+07 0.5; - pipeline_dffe[1]~25 0xc0 8.94432e+06 0.625; - pipeline_dffe[2] 0xc0 1.92012e+07 0.5; - pipeline_dffe[2]~26 0xc0 1.37118e+07 0.5; - pipeline_dffe[2]~27 0xc0 1.59315e+07 0.4375; - pipeline_dffe[3] 0xc0 1.92012e+07 0.5; - pipeline_dffe[3]~28 0xc0 1.49523e+07 0.5; - pipeline_dffe[3]~29 0xc0 1.22202e+07 0.53125; - pipeline_dffe[4] 0xc0 1.92012e+07 0.5; - pipeline_dffe[4]~30 0xc0 1.38979e+07 0.5; - pipeline_dffe[4]~31 0xc0 1.36478e+07 0.484375; - pipeline_dffe[5] 0xc0 1.92012e+07 0.5; - pipeline_dffe[5]~32 0xc0 1.42232e+07 0.5; - pipeline_dffe[5]~33 0xc0 1.27803e+07 0.507813; - pipeline_dffe[6] 0xc0 1.92012e+07 0.5; - pipeline_dffe[6]~34 0xc0 1.39984e+07 0.5; - pipeline_dffe[6]~35 0xc0 1.31698e+07 0.496094; - pipeline_dffe[7] 0xc0 1.92012e+07 0.5; - pipeline_dffe[7]~36 0xc0 1.40938e+07 0.5; - pipeline_dffe[7]~37 0xc0 1.29633e+07 0.501953; - pipeline_dffe[8] 0xc0 1.92012e+07 0.5; - pipeline_dffe[8]~38 0xc0 1.40417e+07 0.5; - pipeline_dffe[8]~39 0xc0 1.30635e+07 0.499023; - pipeline_dffe[9] 0xc0 1.92012e+07 0.5; - pipeline_dffe[9]~40 0xc0 1.40666e+07 0.5; - pipeline_dffe[9]~41 0xc0 1.30126e+07 0.500488; - pipeline_dffe[10] 0xc0 1.92012e+07 0.5; - pipeline_dffe[10]~42 0xc0 1.40539e+07 0.5; - pipeline_dffe[10]~43 0xc0 1.30379e+07 0.499756; - pipeline_dffe[11] 0xc0 1.92012e+07 0.5; - pipeline_dffe[11]~44 0xc0 1.40602e+07 0.5; - pipeline_dffe[11]~45 0xc0 1.30252e+07 0.500122; - pipeline_dffe[12] 0xc0 1.92012e+07 0.5; - pipeline_dffe[12]~46 0xc0 1.4057e+07 0.5; - pipeline_dffe[12]~47 0xc0 1.30315e+07 0.499939; - pipeline_dffe[13] 0xc0 1.92012e+07 0.5; - pipeline_dffe[13]~48 0xc0 1.40586e+07 0.5; - pipeline_dffe[13]~49 0xc0 1.30284e+07 0.500031; - pipeline_dffe[14] 0xc0 1.92012e+07 0.5; - pipeline_dffe[14]~50 0xc0 1.40578e+07 0.5; - pipeline_dffe[14]~51 0xc0 1.30299e+07 0.499985; - pipeline_dffe[15] 0xc0 1.92012e+07 0.5; - pipeline_dffe[15]~52 0xc0 1.40582e+07 0.5; - pipeline_dffe[15]~53 0xc0 1.30291e+07 0.500008; - pipeline_dffe[16] 0xc0 1.92012e+07 0.5; - pipeline_dffe[16]~54 0xc0 1.4058e+07 0.5; - pipeline_dffe[16]~55 0xc0 1.30295e+07 0.499996; - pipeline_dffe[17] 0xc0 1.92012e+07 0.5; - pipeline_dffe[17]~56 0xc0 1.40581e+07 0.5; - pipeline_dffe[17]~57 0xc0 1.30293e+07 0.500002; - pipeline_dffe[18] 0xc0 1.92012e+07 0.5; - pipeline_dffe[18]~58 0xc0 1.4058e+07 0.5; - pipeline_dffe[18]~59 0xc0 1.30294e+07 0.499999; - pipeline_dffe[19] 0xc0 1.92012e+07 0.5; - pipeline_dffe[19]~60 0xc0 1.40581e+07 0.5; - pipeline_dffe[19]~61 0xc0 1.30294e+07 0.5; - pipeline_dffe[20] 0xc0 1.92012e+07 0.5; - pipeline_dffe[20]~62 0xc0 1.4058e+07 0.5; - pipeline_dffe[20]~63 0xc0 1.30294e+07 0.5; - pipeline_dffe[21] 0xc0 1.92012e+07 0.5; - pipeline_dffe[21]~64 0xc0 1.76583e+07 0.5; - phi_int_arr_reg[0] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[0]~5 0xc0 3.125e+06 0.5; - phi_int_arr_reg[1] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[1]~4 0xc0 3.125e+06 0.5; - phi_int_arr_reg[2] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[2]~feeder 0xc0 3.125e+06 0.5; - phi_int_arr_reg[3] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[3]~3 0xc0 3.125e+06 0.5; - phi_int_arr_reg[4] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[4]~feeder 0xc0 3.125e+06 0.5; - phi_int_arr_reg[5] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[5]~2 0xc0 3.125e+06 0.5; - phi_int_arr_reg[6] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[6]~feeder 0xc0 3.125e+06 0.5; - phi_int_arr_reg[7] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[7]~1 0xc0 3.125e+06 0.5; - phi_int_arr_reg[8] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[9] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[9]~0 0xc0 3.125e+06 0.5; - phi_int_arr_reg[10] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[11] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[12] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[12]~6 0xc0 3.125e+06 0.5; - phi_int_arr_reg[12]~feeder 0xc0 3.125e+06 0.5; - phi_int_arr_reg[13] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[13]~7 0xc0 3.125e+06 0.5; - phi_int_arr_reg[14] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[14]~feeder 0xc0 3.125e+06 0.5; - phi_int_arr_reg[15] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[15]~8 0xc0 3.125e+06 0.5; - phi_int_arr_reg[16] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[16]~9 0xc0 3.125e+06 0.5; - phi_int_arr_reg[17] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[17]~10 0xc0 3.125e+06 0.5; - phi_int_arr_reg[18] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[18]~feeder 0xc0 3.125e+06 0.5; - phi_int_arr_reg[19] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[19]~feeder 0xc0 3.125e+06 0.5; - phi_int_arr_reg[20] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[20]~feeder 0xc0 3.125e+06 0.5; - phi_int_arr_reg[21] 0xc0 1.92012e+07 0.5; - phi_int_arr_reg[21]~feeder 0xc0 3.125e+06 0.5; - asj_gam_dp:ux008; - Add0~0 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[0] 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[1] 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[1]~feeder 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[2] 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[3] 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[4] 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[4]~feeder 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[5] 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[5]~feeder 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[6] 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[6]~feeder 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[7] 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[7]~feeder 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[8] 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[9] 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[9]~0 0xc0 1.92012e+07 0.5; - rom_add_cc_temp[10] 0xc0 1.92012e+07 0.5; - rom_add_cs[9] 0xc0 1.92012e+07 0.5; - rom_add_cs[9]~feeder 0xc0 1.92012e+07 0.5; - rom_add_cs[10] 0xc0 1.92012e+07 0.5; - rom_add_cs[10]~feeder 0xc0 1.92012e+07 0.5; - rom_add_f[0] 0xc0 1.92012e+07 0.5; - rom_add_f[0]~feeder 0xc0 1.92012e+07 0.5; - rom_add_f[1] 0xc0 1.92012e+07 0.5; - rom_add_f[1]~feeder 0xc0 1.92012e+07 0.5; - rom_add_f[2] 0xc0 1.92012e+07 0.5; - rom_add_f[2]~feeder 0xc0 1.92012e+07 0.5; - rom_add_f[3] 0xc0 1.92012e+07 0.5; - rom_add_f[4] 0xc0 1.92012e+07 0.5; - rom_add_f[4]~feeder 0xc0 1.92012e+07 0.5; - rom_add_f[5] 0xc0 1.92012e+07 0.5; - rom_add_f[5]~feeder 0xc0 1.92012e+07 0.5; - rom_add_f[6] 0xc0 1.92012e+07 0.5; - rom_add_f[6]~feeder 0xc0 1.92012e+07 0.5; - rom_add_f[7] 0xc0 1.92012e+07 0.5; - rom_add_f[7]~feeder 0xc0 1.92012e+07 0.5; - rom_add_f[8] 0xc0 1.92012e+07 0.5; - rom_add_f[9] 0xc0 1.92012e+07 0.5; - rom_add_f[9]~feeder 0xc0 1.92012e+07 0.5; - rom_add_f[10] 0xc0 1.92012e+07 0.5; - rom_add_f[10]~feeder 0xc0 1.92012e+07 0.5; - asj_nco_as_m_cen:ux0122; - altsyncram:altsyncram_component0; - altsyncram_u8a1:auto_generated; - q_a[0] 0xc0 1.92012e+07 0.5; - q_a[1] 0xc0 1.92012e+07 0.5; - q_a[2] 0xc0 1.92012e+07 0.5; - q_a[3] 0xc0 1.92012e+07 0.5; - q_a[4] 0xc0 1.92012e+07 0.5; - q_a[5] 0xc0 1.92012e+07 0.5; - q_a[6] 0xc0 1.92012e+07 0.5; - q_a[7] 0xc0 1.92012e+07 0.5; - q_a[8] 0xc0 1.92012e+07 0.5; - q_a[9] 0xc0 1.92012e+07 0.5; - q_a[10] 0xc0 1.92012e+07 0.5; - q_a[11] 0xc0 1.92012e+07 0.5; - q_a[12] 0xc0 1.92012e+07 0.5; - q_a[13] 0xc0 1.92012e+07 0.5; - q_a[14] 0xc0 1.92012e+07 0.5; - q_a[15] 0xc0 1.92012e+07 0.5; - asj_nco_as_m_cen:ux0123; - altsyncram:altsyncram_component0; - altsyncram_p8a1:auto_generated; - q_a[0] 0xc0 1.92012e+07 0.5; - q_a[1] 0xc0 1.92012e+07 0.5; - q_a[2] 0xc0 1.92012e+07 0.5; - q_a[3] 0xc0 1.92012e+07 0.5; - q_a[4] 0xc0 1.92012e+07 0.5; - q_a[5] 0xc0 1.92012e+07 0.5; - q_a[6] 0xc0 1.92012e+07 0.5; - q_a[7] 0xc0 1.92012e+07 0.5; - q_a[8] 0xc0 1.92012e+07 0.5; - q_a[9] 0xc0 1.92012e+07 0.5; - q_a[10] 0xc0 1.92012e+07 0.5; - q_a[11] 0xc0 1.92012e+07 0.5; - q_a[12] 0xc0 1.92012e+07 0.5; - q_a[13] 0xc0 1.92012e+07 0.5; - q_a[14] 0xc0 1.92012e+07 0.5; - q_a[15] 0xc0 1.92012e+07 0.5; - asj_nco_as_m_dp_cen:ux0220; - altsyncram:altsyncram_component; - altsyncram_4k82:auto_generated; - q_a[0] 0xc0 1.92012e+07 0.5; - q_a[1] 0xc0 1.92012e+07 0.5; - q_a[2] 0xc0 1.92012e+07 0.5; - q_a[3] 0xc0 1.92012e+07 0.5; - q_a[4] 0xc0 1.92012e+07 0.5; - q_a[5] 0xc0 1.92012e+07 0.5; - q_a[6] 0xc0 1.92012e+07 0.5; - q_a[7] 0xc0 1.92012e+07 0.5; - q_a[8] 0xc0 1.92012e+07 0.5; - q_a[9] 0xc0 1.92012e+07 0.5; - q_a[10] 0xc0 1.92012e+07 0.5; - q_a[11] 0xc0 1.92012e+07 0.5; - q_a[12] 0xc0 1.92012e+07 0.5; - q_a[13] 0xc0 1.92012e+07 0.5; - q_a[14] 0xc0 1.92012e+07 0.5; - q_a[15] 0xc0 1.92012e+07 0.5; - q_b[0] 0xc0 1.92012e+07 0.5; - q_b[1] 0xc0 1.92012e+07 0.5; - q_b[2] 0xc0 1.92012e+07 0.5; - q_b[3] 0xc0 1.92012e+07 0.5; - q_b[4] 0xc0 1.92012e+07 0.5; - q_b[5] 0xc0 1.92012e+07 0.5; - q_b[6] 0xc0 1.92012e+07 0.5; - q_b[7] 0xc0 1.92012e+07 0.5; - q_b[8] 0xc0 1.92012e+07 0.5; - q_b[9] 0xc0 1.92012e+07 0.5; - q_b[10] 0xc0 1.92012e+07 0.5; - q_b[11] 0xc0 1.92012e+07 0.5; - q_b[12] 0xc0 1.92012e+07 0.5; - q_b[13] 0xc0 1.92012e+07 0.5; - q_b[14] 0xc0 1.92012e+07 0.5; - q_b[15] 0xc0 1.92012e+07 0.5; - asj_nco_isdr:ux710isdr; - lpm_counter:lpm_counter_component; - tx_pll:TX_PLL; - altpll:altpll_component; - tx_pll_altpll:auto_generated; - wire_pll1_clk[0] 0xc 3.0722e+08 0.5; - wire_pll1_clk[0]~clkctrl 0xc0 3.0722e+08 0.5; - wire_pll1_fbout 0xc0 0 0; - tx_summator:TX_SUMMATOR; - lpm_add_sub:LPM_ADD_SUB_component; - add_sub_1vk:auto_generated; - overflow_dffe[0] 0xc0 1.92012e+07 0.5; - overflow_dffe[0]~0 0xc0 8.71127e+06 0.25; - pipeline_dffe[0] 0xc0 1.92012e+07 0.5; - pipeline_dffe[1] 0xc0 1.92012e+07 0.5; - pipeline_dffe[2] 0xc0 1.92012e+07 0.5; - pipeline_dffe[3] 0xc0 1.92012e+07 0.5; - pipeline_dffe[4] 0xc0 1.92012e+07 0.5; - pipeline_dffe[5] 0xc0 1.92012e+07 0.5; - pipeline_dffe[6] 0xc0 1.92012e+07 0.5; - pipeline_dffe[7] 0xc0 1.92012e+07 0.5; - pipeline_dffe[8] 0xc0 1.92012e+07 0.5; - pipeline_dffe[9] 0xc0 1.92012e+07 0.5; - pipeline_dffe[10] 0xc0 1.92012e+07 0.5; - pipeline_dffe[11] 0xc0 1.92012e+07 0.5; - pipeline_dffe[12] 0xc0 1.92012e+07 0.5; - pipeline_dffe[13] 0xc0 1.92012e+07 0.5; - pipeline_dffe[14] 0xc0 1.92012e+07 0.5; - pipeline_dffe[15] 0xc0 1.92012e+07 0.5; - pipeline_dffe[16] 0xc0 1.92012e+07 0.5; - pipeline_dffe[17] 0xc0 1.92012e+07 0.5; - pipeline_dffe[18] 0xc0 1.92012e+07 0.5; - pipeline_dffe[19] 0xc0 1.92012e+07 0.5; - pipeline_dffe[20] 0xc0 1.92012e+07 0.5; - pipeline_dffe[21] 0xc0 1.92012e+07 0.5; - pipeline_dffe[22] 0xc0 1.92012e+07 0.5; - pipeline_dffe[23] 0xc0 1.92012e+07 0.5; - pipeline_dffe[24] 0xc0 1.92012e+07 0.5; - pipeline_dffe[25] 0xc0 1.92012e+07 0.5; - pipeline_dffe[26] 0xc0 1.92012e+07 0.5; - pipeline_dffe[27] 0xc0 1.92012e+07 0.5; - pipeline_dffe[28] 0xc0 1.92012e+07 0.5; - pipeline_dffe[29] 0xc0 1.92012e+07 0.5; - pipeline_dffe[30] 0xc0 1.92012e+07 0.5; - pipeline_dffe[31] 0xc0 1.92012e+07 0.5; - pipeline_dffe[31]~_wirecell 0xc0 1.92012e+07 0.5; - result_int[0]~0 0xc0 1.92012e+07 0.5; - result_int[0]~1 0xc0 1.08007e+07 0.25; - result_int[1]~2 0xc0 1.6201e+07 0.5; - result_int[1]~3 0xc0 8.94432e+06 0.625; - result_int[2]~4 0xc0 1.37118e+07 0.5; - result_int[2]~5 0xc0 1.59315e+07 0.4375; - result_int[3]~6 0xc0 1.49523e+07 0.5; - result_int[3]~7 0xc0 1.22202e+07 0.53125; - result_int[4]~8 0xc0 1.38979e+07 0.5; - result_int[4]~9 0xc0 1.36478e+07 0.484375; - result_int[5]~10 0xc0 1.42232e+07 0.5; - result_int[5]~11 0xc0 1.27803e+07 0.507813; - result_int[6]~12 0xc0 1.39984e+07 0.5; - result_int[6]~13 0xc0 1.31698e+07 0.496094; - result_int[7]~14 0xc0 1.40938e+07 0.5; - result_int[7]~15 0xc0 1.29633e+07 0.501953; - result_int[8]~16 0xc0 1.40417e+07 0.5; - result_int[8]~17 0xc0 1.30635e+07 0.499023; - result_int[9]~18 0xc0 1.40666e+07 0.5; - result_int[9]~19 0xc0 1.30126e+07 0.500488; - result_int[10]~20 0xc0 1.40539e+07 0.5; - result_int[10]~21 0xc0 1.30379e+07 0.499756; - result_int[11]~22 0xc0 1.40602e+07 0.5; - result_int[11]~23 0xc0 1.30252e+07 0.500122; - result_int[12]~24 0xc0 1.4057e+07 0.5; - result_int[12]~25 0xc0 1.30315e+07 0.499939; - result_int[13]~26 0xc0 1.40586e+07 0.5; - result_int[13]~27 0xc0 1.30284e+07 0.500031; - result_int[14]~28 0xc0 1.40578e+07 0.5; - result_int[14]~29 0xc0 1.30299e+07 0.499985; - result_int[15]~30 0xc0 1.40582e+07 0.5; - result_int[15]~31 0xc0 1.30291e+07 0.500008; - result_int[16]~32 0xc0 1.4058e+07 0.5; - result_int[16]~33 0xc0 1.30295e+07 0.499996; - result_int[17]~34 0xc0 1.40581e+07 0.5; - result_int[17]~35 0xc0 1.30293e+07 0.500002; - result_int[18]~36 0xc0 1.4058e+07 0.5; - result_int[18]~37 0xc0 1.30294e+07 0.499999; - result_int[19]~38 0xc0 1.40581e+07 0.5; - result_int[19]~39 0xc0 1.30294e+07 0.5; - result_int[20]~40 0xc0 1.4058e+07 0.5; - result_int[20]~41 0xc0 1.30294e+07 0.5; - result_int[21]~42 0xc0 1.4058e+07 0.5; - result_int[21]~43 0xc0 1.30294e+07 0.5; - result_int[22]~44 0xc0 1.4058e+07 0.5; - result_int[22]~45 0xc0 1.30294e+07 0.5; - result_int[23]~46 0xc0 1.4058e+07 0.5; - result_int[23]~47 0xc0 1.30294e+07 0.5; - result_int[24]~48 0xc0 1.4058e+07 0.5; - result_int[24]~49 0xc0 1.30294e+07 0.5; - result_int[25]~50 0xc0 1.4058e+07 0.5; - result_int[25]~51 0xc0 1.30294e+07 0.5; - result_int[26]~52 0xc0 1.4058e+07 0.5; - result_int[26]~53 0xc0 1.30294e+07 0.5; - result_int[27]~54 0xc0 1.4058e+07 0.5; - result_int[27]~55 0xc0 1.30294e+07 0.5; - result_int[28]~56 0xc0 1.4058e+07 0.5; - result_int[28]~57 0xc0 1.30294e+07 0.5; - result_int[29]~58 0xc0 1.4058e+07 0.5; - result_int[29]~59 0xc0 1.30294e+07 0.5; - result_int[30]~60 0xc0 1.4058e+07 0.5; - result_int[30]~61 0xc0 1.30294e+07 0.5; - result_int[31]~62 0xc0 1.76583e+07 0.5; - TXRX_OUT 0xc0 3.125e+06 0.5; - TXRX_OUT~output 0xc0 3.125e+06 0.5; - ~GND 0xc0 0 0; - ~QIC_CREATED_GND~I 0xc0 0 0; - -END_OUTPUT_SIGNAL_INFO; - diff --git a/FPGA_61.440/rx_cic.sopcinfo b/FPGA_61.440/rx_cic.sopcinfo index 78dfe0a..f285934 100644 --- a/FPGA_61.440/rx_cic.sopcinfo +++ b/FPGA_61.440/rx_cic.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1617214524 + 1644138350 false true false diff --git a/FPGA_61.440/stm32_interface.bsf b/FPGA_61.440/stm32_interface.bsf index 4ab76e1..3837466 100644 --- a/FPGA_61.440/stm32_interface.bsf +++ b/FPGA_61.440/stm32_interface.bsf @@ -310,6 +310,13 @@ refer to the applicable agreement for further details. (text "LPF_3" (rect 239 507 267 519)(font "Arial" )) (line (pt 288 512)(pt 272 512)(line_width 1)) ) + (port + (pt 288 528) + (output) + (text "VCXO_correction[15..0]" (rect 0 0 96 12)(font "Arial" )) + (text "VCXO_correction[15..0]" (rect 171 523 267 535)(font "Arial" )) + (line (pt 288 528)(pt 272 528)(line_width 3)) + ) (port (pt 288 32) (bidir) diff --git a/FPGA_61.440/stm32_interface.v b/FPGA_61.440/stm32_interface.v index 8dd9ca7..21467fc 100644 --- a/FPGA_61.440/stm32_interface.v +++ b/FPGA_61.440/stm32_interface.v @@ -41,7 +41,8 @@ BPF_OE1, BPF_OE2, LPF_1, LPF_2, -LPF_3 +LPF_3, +VCXO_correction ); input clk_in; @@ -86,6 +87,7 @@ output reg BPF_OE2 = 0; output reg LPF_1 = 0; output reg LPF_2 = 0; output reg LPF_3 = 0; +output reg unsigned [15:0] VCXO_correction = 32767; inout [7:0] DATA_BUS; reg [7:0] DATA_BUS_OUT; @@ -237,8 +239,18 @@ begin LPF_1 = DATA_BUS[4:4]; LPF_2 = DATA_BUS[5:5]; LPF_3 = DATA_BUS[6:6]; - k = 999; + k = 112; end + else if (k == 112) + begin + VCXO_correction[15:8] = DATA_BUS[7:0]; + k = 113; + end + else if (k == 113) + begin + VCXO_correction[7:0] = DATA_BUS[7:0]; + k = 999; + end else if (k == 200) //SEND PARAMS begin DATA_BUS_OUT[0:0] = ADC_OTR; diff --git a/FPGA_61.440/tx_cic.sopcinfo b/FPGA_61.440/tx_cic.sopcinfo index f7334af..6fb49ef 100644 --- a/FPGA_61.440/tx_cic.sopcinfo +++ b/FPGA_61.440/tx_cic.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1617214539 + 1644138363 false true false diff --git a/FPGA_61.440/tx_nco.sopcinfo b/FPGA_61.440/tx_nco.sopcinfo index 2ee3aaf..981b955 100644 --- a/FPGA_61.440/tx_nco.sopcinfo +++ b/FPGA_61.440/tx_nco.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1617214553 + 1644138376 false true false diff --git a/FPGA_61.440/vcxo_controller.bsf b/FPGA_61.440/vcxo_controller.bsf index 32810d0..e027db3 100644 --- a/FPGA_61.440/vcxo_controller.bsf +++ b/FPGA_61.440/vcxo_controller.bsf @@ -20,63 +20,31 @@ refer to the applicable agreement for further details. */ (header "symbol" (version "1.1")) (symbol - (rect 16 16 280 128) + (rect 16 16 240 96) (text "vcxo_controller" (rect 5 0 66 12)(font "Arial" )) - (text "inst" (rect 8 96 20 108)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) (port (pt 0 32) (input) - (text "vcxo_clk_in" (rect 0 0 48 12)(font "Arial" )) - (text "vcxo_clk_in" (rect 21 27 69 39)(font "Arial" )) + (text "pwm_clk_in" (rect 0 0 47 12)(font "Arial" )) + (text "pwm_clk_in" (rect 21 27 68 39)(font "Arial" )) (line (pt 0 32)(pt 16 32)(line_width 1)) ) (port (pt 0 48) (input) - (text "tcxo_clk_in" (rect 0 0 44 12)(font "Arial" )) - (text "tcxo_clk_in" (rect 21 43 65 55)(font "Arial" )) - (line (pt 0 48)(pt 16 48)(line_width 1)) + (text "VCXO_correction[15..0]" (rect 0 0 96 12)(font "Arial" )) + (text "VCXO_correction[15..0]" (rect 21 43 117 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) ) (port - (pt 0 64) - (input) - (text "VCXO_correction[7..0]" (rect 0 0 93 12)(font "Arial" )) - (text "VCXO_correction[7..0]" (rect 21 59 114 71)(font "Arial" )) - (line (pt 0 64)(pt 16 64)(line_width 3)) - ) - (port - (pt 264 32) - (output) - (text "freq_error[23..0]" (rect 0 0 67 12)(font "Arial" )) - (text "freq_error[23..0]" (rect 176 27 243 39)(font "Arial" )) - (line (pt 264 32)(pt 248 32)(line_width 3)) - ) - (port - (pt 264 48) + (pt 224 32) (output) (text "pump" (rect 0 0 22 12)(font "Arial" )) - (text "pump" (rect 221 43 243 55)(font "Arial" )) - (line (pt 264 48)(pt 248 48)(line_width 1)) + (text "pump" (rect 181 27 203 39)(font "Arial" )) + (line (pt 224 32)(pt 208 32)(line_width 1)) ) - (port - (pt 264 64) - (output) - (text "PWM[23..0]" (rect 0 0 49 12)(font "Arial" )) - (text "PWM[23..0]" (rect 194 59 243 71)(font "Arial" )) - (line (pt 264 64)(pt 248 64)(line_width 3)) - ) - (parameter - "VCXO_freq_khz" - "122880" - "" - (type "PARAMETER_SIGNED_DEC") ) - (parameter - "TCXO_freq_khz" - "49152" - "" - (type "PARAMETER_SIGNED_DEC") ) (drawing - (rectangle (rect 16 16 248 96)(line_width 1)) + (rectangle (rect 16 16 208 64)(line_width 1)) ) - (annotation_block (parameter)(rect 280 -64 380 16)) ) diff --git a/FPGA_61.440/vcxo_controller.v b/FPGA_61.440/vcxo_controller.v index bf1345d..e5b6325 100644 --- a/FPGA_61.440/vcxo_controller.v +++ b/FPGA_61.440/vcxo_controller.v @@ -1,114 +1,32 @@ module vcxo_controller( -vcxo_clk_in, -tcxo_clk_in, +pwm_clk_in, VCXO_correction, -freq_error, -pump, -PWM +pump ); -parameter VCXO_freq_khz = 1228800; //x100hz -parameter TCXO_freq_khz = 122880; //x100hz +input pwm_clk_in; +input unsigned [15:0] VCXO_correction; -input vcxo_clk_in; -input tcxo_clk_in; -input signed [7:0] VCXO_correction; - -output reg signed [23:0] freq_error = 0; output reg pump = 0; -output reg signed [23:0] PWM = 500; -reg [23:0] PWM_max = 1000; -reg signed [23:0] freq_error_now = 0; -reg signed [23:0] freq_error_prev = 0; -reg signed [23:0] freq_error_diff = 0; -reg signed [31:0] VCXO_counter = 0; -reg signed [31:0] TCXO_counter = 0; -reg [31:0] PWM_counter = 0; -reg counter_reset = 0; -reg counter_resetted = 0; -reg [7:0] state = 0; +reg unsigned [15:0] PWM_counter_MAX = 65500; +reg unsigned [15:0] PWM_counter = 0; -always @ (posedge vcxo_clk_in) +always @ (posedge pwm_clk_in) begin - if(state != 2 && state != 3) - begin - if(counter_reset) - begin - VCXO_counter <= 0; - counter_resetted <= 1; - end - else - begin - VCXO_counter <= VCXO_counter + 1; - counter_resetted <= 0; - end - end -end - -always @ (posedge tcxo_clk_in) -begin - //do PWM - PWM_counter = PWM_counter + 1; - if(PWM_counter >= PWM_max) + //count PWM + if(PWM_counter > PWM_counter_MAX) PWM_counter = 0; + else + PWM_counter = PWM_counter + 1; - if(PWM > PWM_counter) + //do PWM + if(PWM_counter <= VCXO_correction) pump = 1; else pump = 0; - - if(counter_reset && !counter_resetted) - begin - //wait VCXO reset - end - else - begin - if(state == 0) - begin - TCXO_counter = 0; - counter_reset = 0; - state = 1; - end - else if(state == 1) - begin - TCXO_counter = TCXO_counter + 1; - - if(TCXO_counter >= TCXO_freq_khz) - state = 2; - end - else if(state == 2) - begin - freq_error_now = VCXO_counter - VCXO_freq_khz + VCXO_correction; - freq_error_diff = freq_error_prev - freq_error_now; - - if(freq_error_diff > -50 && freq_error_diff < 50) //measure errors - if(freq_error_now > -1000 && freq_error_now < 1000) //measure errors - begin - //save - freq_error = freq_error_now; - - //tune - if(freq_error_now < 0) - PWM = PWM + 1; - else if(freq_error_now > 0) - PWM = PWM - 1; - end - - state = 3; - end - else if(state == 3) - begin - freq_error_prev = freq_error_now; - if(PWM > PWM_max) - PWM = PWM_max; - if(PWM < 0) - PWM = 0; - counter_reset = 1; - state = 0; - end - end end + endmodule diff --git a/STM32/Core/Src/fpga.c b/STM32/Core/Src/fpga.c index 414960c..f2dec6a 100644 --- a/STM32/Core/Src/fpga.c +++ b/STM32/Core/Src/fpga.c @@ -335,6 +335,17 @@ static inline void FPGA_fpgadata_sendparam(void) FPGA_writePacket(FPGA_fpgadata_out_tmp8); FPGA_clockRise(); FPGA_clockFall(); + + //OUT VCXO_CORRECTION + uint16_t FPGA_fpgadata_out_tmp16 = CALIBRATE.vcxo_calibration; // 32767 - center (50% cycle) + FPGA_writePacket(((FPGA_fpgadata_out_tmp16 & (0XFF << 8)) >> 8)); + FPGA_clockRise(); + FPGA_clockFall(); + + //OUT TX-FREQ + FPGA_writePacket(FPGA_fpgadata_out_tmp16 & 0XFF); + FPGA_clockRise(); + FPGA_clockFall(); } // get parameters diff --git a/STM32/Core/Src/settings.c b/STM32/Core/Src/settings.c index e49717b..496802f 100644 --- a/STM32/Core/Src/settings.c +++ b/STM32/Core/Src/settings.c @@ -293,8 +293,6 @@ void LoadCalibration(bool clear) CALIBRATE.rf_out_power_12m = 22; //12m CALIBRATE.rf_out_power_10m = 22; //10m - CALIBRATE.VCXO_CALIBR = 0; - CALIBRATE.VCXO_CALIBRT = 0; CALIBRATE.freq_correctur_160 = 0; CALIBRATE.freq_correctur_80 = 0; CALIBRATE.freq_correctur_40 = 0; @@ -314,6 +312,7 @@ void LoadCalibration(bool clear) CALIBRATE.smeter_calibration = -10; // S-Meter calibration, set when calibrating the transceiver to S9 CALIBRATE.swr_trans_rate = 11.0f; // SWR Transormator rate CALIBRATE.volt_cal_rate = 11.0f; // VOLTAGE + CALIBRATE.vcxo_calibration = 32767; // VCXO PWM CALIBRATE.ENDBit = 100; sendToDebug_strln("[OK] Loaded default calibrate settings"); diff --git a/STM32/Core/Src/settings.h b/STM32/Core/Src/settings.h index c215e89..22263e7 100644 --- a/STM32/Core/Src/settings.h +++ b/STM32/Core/Src/settings.h @@ -8,9 +8,7 @@ #include "bands.h" #define SETT_VERSION 101 // Settings config version -#define CALIB_VERSION 100 // Calibration config version -//#define ADC_CLOCK (int32_t)(64320000 + (CALIBRATE.VCXO_CALIBR * 10)) // ADC generator frequency калибровка частоты генератора -//#define DAC_CLOCK (int32_t)(160800000 + (CALIBRATE.VCXO_CALIBRT * 10)) // DAC generator frequency +#define CALIB_VERSION 101 // Calibration config version #define ADC_CLOCK 61440000 // ADC generator frequency калибровка частоты генератора #define DAC_CLOCK 153600000 // DAC generator frequency #define MAX_RX_FREQ_HZ 750000000 // Maximum receive frequency (from the ADC datasheet) @@ -205,8 +203,6 @@ extern struct TRX_CALIBRATE { uint8_t flash_id; //eeprom check - int16_t VCXO_CALIBR; - int16_t VCXO_CALIBRT; bool ENCODER_INVERT; bool ENCODER2_INVERT; uint8_t ENCODER_DEBOUNCE; @@ -248,6 +244,8 @@ extern struct TRX_CALIBRATE uint8_t rf_out_power_12m; uint8_t rf_out_power_10m; + uint16_t vcxo_calibration; + uint8_t csum; //check sum uint8_t ENDBit; //end bit } CALIBRATE; diff --git a/STM32/Core/Src/system_menu.c b/STM32/Core/Src/system_menu.c index 5a56a04..9d2c382 100644 --- a/STM32/Core/Src/system_menu.c +++ b/STM32/Core/Src/system_menu.c @@ -135,7 +135,6 @@ static void SYSMENU_HANDL_CALIB_FREQUENCY_10M(int8_t direction); static void SYSMENU_HANDL_CALIB_FREQUENCY_SIBI(int8_t direction); static void SYSMENU_HANDL_CALIB_FREQUENCY_52(int8_t direction); static void SYSMENU_HANDL_VCXO_CALIBR(int8_t direction); -static void SYSMENU_HANDL_VCXO_CALIBRT(int8_t direction); static void SYSMENU_HANDL_TRXMENU(int8_t direction); static void SYSMENU_HANDL_AUDIOMENU(int8_t direction); @@ -275,8 +274,7 @@ static const struct sysmenu_item_handler sysmenu_calibration_handlers[] = {"S METER", SYSMENU_INT16, (uint32_t *)&CALIBRATE.smeter_calibration, SYSMENU_HANDL_CALIB_S_METER}, {"SWR TRANS RATE", SYSMENU_FLOAT32, (uint32_t *)&CALIBRATE.swr_trans_rate, SYSMENU_HANDL_CALIB_SWR_TRANS_RATE}, {"VOLT CALIBR", SYSMENU_FLOAT32, (uint32_t *)&CALIBRATE.volt_cal_rate, SYSMENU_HANDL_CALIB_VOLT}, -// {"VCXO Cor-RX", SYSMENU_INT16, (uint32_t *)&CALIBRATE.VCXO_CALIBR, SYSMENU_HANDL_VCXO_CALIBR}, -// {"VCXO Cor-TX", SYSMENU_INT16, (uint32_t *)&CALIBRATE.VCXO_CALIBRT, SYSMENU_HANDL_VCXO_CALIBRT}, + {"VCXO CALIBR", SYSMENU_UINT16, (uint32_t *)&CALIBRATE.vcxo_calibration, SYSMENU_HANDL_VCXO_CALIBR}, {"F-correctur 160m", SYSMENU_INT16, (uint32_t *)&CALIBRATE.freq_correctur_160, SYSMENU_HANDL_CALIB_FREQUENCY_160M}, {"F-correctur 80m", SYSMENU_INT16, (uint32_t *)&CALIBRATE.freq_correctur_80, SYSMENU_HANDL_CALIB_FREQUENCY_80M}, {"F-correctur 40m", SYSMENU_INT16, (uint32_t *)&CALIBRATE.freq_correctur_40, SYSMENU_HANDL_CALIB_FREQUENCY_40M}, @@ -2031,25 +2029,14 @@ static void SYSMENU_HANDL_CALIB_VOLT(int8_t direction) //########################################################################################################### static void SYSMENU_HANDL_VCXO_CALIBR(int8_t direction) { - CALIBRATE.VCXO_CALIBR += direction; - if (CALIBRATE.VCXO_CALIBR < -1000) - CALIBRATE.VCXO_CALIBR = -1000; - if (CALIBRATE.VCXO_CALIBR > 1000) - CALIBRATE.VCXO_CALIBR = 1000; - TRX_setFrequency(CurrentVFO()->Freq, CurrentVFO()); + CALIBRATE.vcxo_calibration += direction; + if (CALIBRATE.vcxo_calibration < 1) + CALIBRATE.vcxo_calibration = 1; + if (CALIBRATE.vcxo_calibration > 65500) + CALIBRATE.vcxo_calibration = 65500; + FPGA_NeedSendParams = true; } -static void SYSMENU_HANDL_VCXO_CALIBRT(int8_t direction) -{ - CALIBRATE.VCXO_CALIBRT += direction; - if (CALIBRATE.VCXO_CALIBRT < -1000) - CALIBRATE.VCXO_CALIBRT = -1000; - if (CALIBRATE.VCXO_CALIBRT > 1000) - CALIBRATE.VCXO_CALIBRT = 1000; - TRX_setFrequency(CurrentVFO()->Freq, CurrentVFO()); -} - - //160M static void SYSMENU_HANDL_CALIB_FREQUENCY_160M(int8_t direction) { diff --git a/STM32/MDK-ARM/WOLF-Lite.uvoptx b/STM32/MDK-ARM/WOLF-Lite.uvoptx index 78bb6c1..399edb6 100644 --- a/STM32/MDK-ARM/WOLF-Lite.uvoptx +++ b/STM32/MDK-ARM/WOLF-Lite.uvoptx @@ -3701,6 +3701,1254 @@ + + 222 + 0 + 481 + 1 +
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