kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
VCXO PWM
XGudron
rodzic
c136dee7cf
commit
5c147109ea
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@ -2,6 +2,10 @@ FPGA/db/*
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FPGA/output_files/*
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FPGA/greybox_tmp/*
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FPGA/incremental_db/*
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FPGA_61.440/db/*
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FPGA_61.440/output_files/*
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FPGA_61.440/greybox_tmp/*
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FPGA_61.440/incremental_db/*
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STM32/MDK-ARM/WOLF-Lite/*.htm
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STM32/MDK-ARM/WOLF-Lite/*.hex
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STM32/Debug/*
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@ -1,11 +1,11 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="DEBUG" kind="DEBUG" version="1.0" fabric="QSYS">
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<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
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<!-- 2021.03.31.22:16:32 -->
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<!-- 2022.02.06.13:06:43 -->
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<!-- A collection of modules and connections -->
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<parameter name="AUTO_GENERATION_ID">
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<type>java.lang.Integer</type>
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<value>1617214592</value>
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<value>1644138403</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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@ -1,11 +1,11 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="DEBUG2" kind="DEBUG2" version="1.0" fabric="QSYS">
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<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
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<!-- 2021.03.31.22:16:46 -->
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<!-- 2022.02.06.13:06:55 -->
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<!-- A collection of modules and connections -->
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<parameter name="AUTO_GENERATION_ID">
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<type>java.lang.Integer</type>
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<value>1617214606</value>
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<value>1644138415</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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@ -512,6 +512,22 @@ refer to the applicable agreement for further details.
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)
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(annotation_block (location)(rect 3688 48 3744 72))
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)
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(pin
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(output)
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(rect 3416 1168 3592 1184)
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(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
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(text "VCXO_PWM" (rect 90 0 151 12)(font "Arial" ))
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(pt 0 8)
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(drawing
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(line (pt 0 8)(pt 52 8))
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(line (pt 52 4)(pt 78 4))
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(line (pt 52 12)(pt 78 12))
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||||
(line (pt 52 12)(pt 52 4))
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(line (pt 78 4)(pt 82 8))
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(line (pt 82 8)(pt 78 12))
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(line (pt 78 12)(pt 82 8))
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)
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)
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(pin
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(bidir)
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(rect 3456 168 3632 184)
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@ -1620,314 +1636,6 @@ refer to the applicable agreement for further details.
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(circle (rect 72 56 104 88))
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)
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)
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(symbol
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(rect 3088 144 3376 704)
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(text "stm32_interface" (rect 5 0 85 12)(font "Arial" ))
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(text "STM32_INTERFACE" (rect 8 544 109 556)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "clk_in" (rect 0 0 28 12)(font "Arial" ))
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(text "clk_in" (rect 21 27 49 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32))
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)
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(port
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(pt 0 48)
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(input)
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(text "RX_I[15..0]" (rect 0 0 55 12)(font "Arial" ))
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(text "RX_I[15..0]" (rect 21 43 76 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 3))
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)
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(port
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(pt 0 64)
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(input)
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(text "RX_Q[15..0]" (rect 0 0 60 12)(font "Arial" ))
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(text "RX_Q[15..0]" (rect 21 59 81 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64)(line_width 3))
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)
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(port
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(pt 0 80)
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(input)
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(text "DATA_SYNC" (rect 0 0 66 12)(font "Arial" ))
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(text "DATA_SYNC" (rect 21 75 87 87)(font "Arial" ))
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(line (pt 0 80)(pt 16 80))
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)
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(port
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(pt 0 96)
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(input)
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(text "ADC_OTR" (rect 0 0 51 12)(font "Arial" ))
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(text "ADC_OTR" (rect 21 91 72 103)(font "Arial" ))
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(line (pt 0 96)(pt 16 96))
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)
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(port
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(pt 0 112)
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(input)
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(text "DAC_OTR" (rect 0 0 51 12)(font "Arial" ))
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(text "DAC_OTR" (rect 21 107 72 119)(font "Arial" ))
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(line (pt 0 112)(pt 16 112))
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)
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(port
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(pt 0 128)
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(input)
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(text "ADC_IN[11..0]" (rect 0 0 73 12)(font "Arial" ))
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(text "ADC_IN[11..0]" (rect 21 123 94 135)(font "Arial" ))
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(line (pt 0 128)(pt 16 128)(line_width 3))
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)
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(port
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(pt 0 144)
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(input)
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(text "adcclk_in" (rect 0 0 46 12)(font "Arial" ))
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(text "adcclk_in" (rect 21 139 67 151)(font "Arial" ))
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(line (pt 0 144)(pt 16 144))
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)
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(port
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(pt 0 160)
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(input)
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(text "FLASH_data_in[7..0]" (rect 0 0 102 12)(font "Arial" ))
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(text "FLASH_data_in[7..0]" (rect 21 155 123 167)(font "Arial" ))
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(line (pt 0 160)(pt 16 160)(line_width 3))
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)
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(port
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(pt 0 176)
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(input)
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(text "FLASH_busy" (rect 0 0 66 12)(font "Arial" ))
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(text "FLASH_busy" (rect 21 171 87 183)(font "Arial" ))
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(line (pt 0 176)(pt 16 176))
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)
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(port
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(pt 0 192)
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(input)
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(text "IQ_valid" (rect 0 0 41 12)(font "Arial" ))
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(text "IQ_valid" (rect 21 187 62 199)(font "Arial" ))
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(line (pt 0 192)(pt 16 192))
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)
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(port
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(pt 288 48)
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(output)
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(text "NCO_freq[21..0]" (rect 0 0 82 12)(font "Arial" ))
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(text "NCO_freq[21..0]" (rect 198 43 280 55)(font "Arial" ))
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(line (pt 288 48)(pt 272 48)(line_width 3))
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)
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(port
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(pt 288 64)
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(output)
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(text "preamp_enable" (rect 0 0 74 12)(font "Arial" ))
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(text "preamp_enable" (rect 205 59 279 71)(font "Arial" ))
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(line (pt 288 64)(pt 272 64))
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)
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(port
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(pt 288 80)
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(output)
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(text "rx" (rect 0 0 9 12)(font "Arial" ))
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(text "rx" (rect 260 75 269 87)(font "Arial" ))
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(line (pt 288 80)(pt 272 80))
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)
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(port
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(pt 288 96)
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(output)
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(text "tx" (rect 0 0 9 12)(font "Arial" ))
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(text "tx" (rect 260 91 269 103)(font "Arial" ))
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(line (pt 288 96)(pt 272 96))
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)
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(port
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(pt 288 112)
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(output)
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(text "TX_I[15..0]" (rect 0 0 53 12)(font "Arial" ))
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(text "TX_I[15..0]" (rect 223 107 276 119)(font "Arial" ))
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(line (pt 288 112)(pt 272 112)(line_width 3))
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)
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(port
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(pt 288 128)
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(output)
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(text "TX_Q[15..0]" (rect 0 0 57 12)(font "Arial" ))
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(text "TX_Q[15..0]" (rect 219 123 276 135)(font "Arial" ))
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(line (pt 288 128)(pt 272 128)(line_width 3))
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)
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(port
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(pt 288 144)
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(output)
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(text "reset_n" (rect 0 0 36 12)(font "Arial" ))
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(text "reset_n" (rect 237 139 273 151)(font "Arial" ))
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(line (pt 288 144)(pt 272 144))
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)
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(port
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(pt 288 160)
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(output)
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(text "stage_debug[15..0]" (rect 0 0 94 12)(font "Arial" ))
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(text "stage_debug[15..0]" (rect 188 155 282 167)(font "Arial" ))
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(line (pt 288 160)(pt 272 160)(line_width 3))
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)
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(port
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(pt 288 176)
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(output)
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(text "FLASH_data_out[7..0]" (rect 0 0 109 12)(font "Arial" ))
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(text "FLASH_data_out[7..0]" (rect 175 171 284 183)(font "Arial" ))
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(line (pt 288 176)(pt 272 176)(line_width 3))
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)
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(port
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(pt 288 192)
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(output)
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(text "FLASH_enable" (rect 0 0 73 12)(font "Arial" ))
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(text "FLASH_enable" (rect 206 187 279 199)(font "Arial" ))
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(line (pt 288 192)(pt 272 192))
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)
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(port
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(pt 288 208)
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||||
(output)
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(text "FLASH_continue_read" (rect 0 0 109 12)(font "Arial" ))
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(text "FLASH_continue_read" (rect 175 203 284 215)(font "Arial" ))
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(line (pt 288 208)(pt 272 208))
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)
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(port
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(pt 288 224)
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(output)
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(text "CIC_GAIN[7..0]" (rect 0 0 79 12)(font "Arial" ))
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(text "CIC_GAIN[7..0]" (rect 201 219 280 231)(font "Arial" ))
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(line (pt 288 224)(pt 272 224)(line_width 3))
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)
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(port
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(pt 288 240)
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(output)
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(text "CICFIR_GAIN[7..0]" (rect 0 0 97 12)(font "Arial" ))
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(text "CICFIR_GAIN[7..0]" (rect 185 235 282 247)(font "Arial" ))
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||||
(line (pt 288 240)(pt 272 240)(line_width 3))
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||||
)
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(port
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(pt 288 256)
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||||
(output)
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(text "TX_CICFIR_GAIN[7..0]" (rect 0 0 115 12)(font "Arial" ))
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(text "TX_CICFIR_GAIN[7..0]" (rect 170 251 285 263)(font "Arial" ))
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||||
(line (pt 288 256)(pt 272 256)(line_width 3))
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||||
)
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||||
(port
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||||
(pt 288 272)
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||||
(output)
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||||
(text "DAC_GAIN[7..0]" (rect 0 0 82 12)(font "Arial" ))
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||||
(text "DAC_GAIN[7..0]" (rect 198 267 280 279)(font "Arial" ))
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||||
(line (pt 288 272)(pt 272 272)(line_width 3))
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||||
)
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||||
(port
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||||
(pt 288 288)
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||||
(output)
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||||
(text "tx_iq_valid" (rect 0 0 53 12)(font "Arial" ))
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||||
(text "tx_iq_valid" (rect 223 283 276 295)(font "Arial" ))
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||||
(line (pt 288 288)(pt 272 288))
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||||
)
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||||
(port
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||||
(pt 288 304)
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||||
(output)
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||||
(text "TX_NCO_freq[21..0]" (rect 0 0 100 12)(font "Arial" ))
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||||
(text "TX_NCO_freq[21..0]" (rect 183 299 283 311)(font "Arial" ))
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||||
(line (pt 288 304)(pt 272 304)(line_width 3))
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||||
)
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||||
(port
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||||
(pt 288 320)
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||||
(output)
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||||
(text "ATT_05" (rect 0 0 36 12)(font "Arial" ))
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||||
(text "ATT_05" (rect 237 315 273 327)(font "Arial" ))
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||||
(line (pt 288 320)(pt 272 320))
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||||
)
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||||
(port
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||||
(pt 288 336)
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||||
(output)
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||||
(text "ATT_1" (rect 0 0 30 12)(font "Arial" ))
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(text "ATT_1" (rect 242 331 272 343)(font "Arial" ))
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(line (pt 288 336)(pt 272 336))
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||||
)
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||||
(port
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||||
(pt 288 352)
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||||
(output)
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||||
(text "ATT_2" (rect 0 0 30 12)(font "Arial" ))
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||||
(text "ATT_2" (rect 242 347 272 359)(font "Arial" ))
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||||
(line (pt 288 352)(pt 272 352))
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||||
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||||
(port
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||||
(pt 288 368)
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||||
(output)
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||||
(text "ATT_4" (rect 0 0 30 12)(font "Arial" ))
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||||
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||||
(line (pt 288 368)(pt 272 368))
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||||
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||||
(port
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||||
(pt 288 384)
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||||
(output)
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||||
(text "ATT_8" (rect 0 0 30 12)(font "Arial" ))
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(text "ATT_8" (rect 242 379 272 391)(font "Arial" ))
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||||
(line (pt 288 384)(pt 272 384))
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||||
)
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||||
(port
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||||
(pt 288 400)
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||||
(output)
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||||
(text "ATT_16" (rect 0 0 36 12)(font "Arial" ))
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(text "ATT_16" (rect 237 395 273 407)(font "Arial" ))
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(line (pt 288 400)(pt 272 400))
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)
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(port
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(pt 288 416)
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(output)
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(text "BPF_A" (rect 0 0 35 12)(font "Arial" ))
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(text "BPF_A" (rect 238 411 273 423)(font "Arial" ))
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(line (pt 288 416)(pt 272 416))
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)
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(port
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(pt 288 432)
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(output)
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(text "BPF_B" (rect 0 0 34 12)(font "Arial" ))
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(text "BPF_B" (rect 239 427 273 439)(font "Arial" ))
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(line (pt 288 432)(pt 272 432))
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)
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(port
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(pt 288 448)
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||||
(output)
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||||
(text "BPF_OE1" (rect 0 0 48 12)(font "Arial" ))
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(text "BPF_OE1" (rect 227 443 275 455)(font "Arial" ))
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(line (pt 288 448)(pt 272 448))
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)
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||||
(port
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(pt 288 464)
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||||
(output)
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||||
(text "BPF_OE2" (rect 0 0 48 12)(font "Arial" ))
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||||
(text "BPF_OE2" (rect 227 459 275 471)(font "Arial" ))
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||||
(line (pt 288 464)(pt 272 464))
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||||
)
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||||
(port
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||||
(pt 288 480)
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||||
(output)
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||||
(text "LPF_1" (rect 0 0 31 12)(font "Arial" ))
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||||
(text "LPF_1" (rect 241 475 272 487)(font "Arial" ))
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||||
(line (pt 288 480)(pt 272 480))
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||||
)
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||||
(port
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||||
(pt 288 496)
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||||
(output)
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||||
(text "LPF_2" (rect 0 0 31 12)(font "Arial" ))
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||||
(text "LPF_2" (rect 241 491 272 503)(font "Arial" ))
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||||
(line (pt 288 496)(pt 272 496))
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||||
)
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||||
(port
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||||
(pt 288 512)
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||||
(output)
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||||
(text "LPF_3" (rect 0 0 31 12)(font "Arial" ))
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||||
(text "LPF_3" (rect 241 507 272 519)(font "Arial" ))
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||||
(line (pt 288 512)(pt 272 512))
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||||
)
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||||
(port
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||||
(pt 288 32)
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||||
(bidir)
|
||||
(text "DATA_BUS[7..0]" (rect 0 0 82 12)(font "Arial" ))
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||||
(text "DATA_BUS[7..0]" (rect 193 27 275 39)(font "Arial" ))
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||||
(line (pt 288 32)(pt 272 32)(line_width 3))
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||||
)
|
||||
(parameter
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||||
"rx_buffer_length"
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||||
"7"
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||||
""
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||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(drawing
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||||
(rectangle (rect 16 16 272 544))
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||||
)
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||||
(annotation_block (parameter)(rect 3088 96 3296 136))
|
||||
)
|
||||
(symbol
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||||
(rect 4464 224 4768 368)
|
||||
(text "data_shifter" (rect 5 0 64 12)(font "Arial" ))
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||||
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@ -2443,21 +2151,21 @@ refer to the applicable agreement for further details.
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|||
(pt 384 72)
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||||
(output)
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||||
(text "ast_source_data[45..0]" (rect 0 0 132 14)(font "Arial" (font_size 8)))
|
||||
(text "ast_source_data[45..0]" (rect 268 61 379 75)(font "Arial" (font_size 8)))
|
||||
(text "ast_source_data[45..0]" (rect 268 61 400 75)(font "Arial" (font_size 8)))
|
||||
(line (pt 384 72)(pt 224 72)(line_width 3))
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||||
)
|
||||
(port
|
||||
(pt 384 88)
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||||
(output)
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||||
(text "ast_source_valid" (rect 0 0 97 14)(font "Arial" (font_size 8)))
|
||||
(text "ast_source_valid" (rect 297 77 379 91)(font "Arial" (font_size 8)))
|
||||
(text "ast_source_valid" (rect 297 77 394 91)(font "Arial" (font_size 8)))
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||||
(line (pt 384 88)(pt 224 88))
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||||
)
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||||
(port
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||||
(pt 384 104)
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||||
(output)
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||||
(text "ast_source_error[1..0]" (rect 0 0 128 14)(font "Arial" (font_size 8)))
|
||||
(text "ast_source_error[1..0]" (rect 273 93 381 107)(font "Arial" (font_size 8)))
|
||||
(text "ast_source_error[1..0]" (rect 273 93 401 107)(font "Arial" (font_size 8)))
|
||||
(line (pt 384 104)(pt 224 104)(line_width 3))
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||||
)
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||||
(drawing
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||||
|
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@ -2535,21 +2243,21 @@ refer to the applicable agreement for further details.
|
|||
(pt 384 72)
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||||
(output)
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||||
(text "ast_source_data[45..0]" (rect 0 0 132 14)(font "Arial" (font_size 8)))
|
||||
(text "ast_source_data[45..0]" (rect 268 61 379 75)(font "Arial" (font_size 8)))
|
||||
(text "ast_source_data[45..0]" (rect 268 61 400 75)(font "Arial" (font_size 8)))
|
||||
(line (pt 384 72)(pt 224 72)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 384 88)
|
||||
(output)
|
||||
(text "ast_source_valid" (rect 0 0 97 14)(font "Arial" (font_size 8)))
|
||||
(text "ast_source_valid" (rect 297 77 379 91)(font "Arial" (font_size 8)))
|
||||
(text "ast_source_valid" (rect 297 77 394 91)(font "Arial" (font_size 8)))
|
||||
(line (pt 384 88)(pt 224 88))
|
||||
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|
||||
(port
|
||||
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|
||||
(output)
|
||||
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|
||||
(text "ast_source_error[1..0]" (rect 273 93 381 107)(font "Arial" (font_size 8)))
|
||||
(text "ast_source_error[1..0]" (rect 273 93 401 107)(font "Arial" (font_size 8)))
|
||||
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|
||||
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|
||||
(drawing
|
||||
|
|
@ -2736,21 +2444,21 @@ refer to the applicable agreement for further details.
|
|||
(pt 384 72)
|
||||
(output)
|
||||
(text "ast_source_data[29..0]" (rect 0 0 132 14)(font "Arial" (font_size 8)))
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|
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||||
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|
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|
||||
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|
||||
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|
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|
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|
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||||
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|
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||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
(drawing
|
||||
|
|
@ -2828,21 +2536,21 @@ refer to the applicable agreement for further details.
|
|||
(pt 384 72)
|
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(output)
|
||||
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|
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|
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|
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||||
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
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||||
|
|
@ -2877,6 +2585,350 @@ refer to the applicable agreement for further details.
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
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(port
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(output)
|
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|
||||
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|
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|
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(port
|
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
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|
||||
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|
||||
(port
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|
||||
(output)
|
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|
||||
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|
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|
||||
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|
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(port
|
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|
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(output)
|
||||
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|
||||
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|
||||
(line (pt 288 528)(pt 272 528)(line_width 3))
|
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|
||||
(port
|
||||
(pt 288 32)
|
||||
(bidir)
|
||||
(text "DATA_BUS[7..0]" (rect 0 0 82 12)(font "Arial" ))
|
||||
(text "DATA_BUS[7..0]" (rect 193 27 275 39)(font "Arial" ))
|
||||
(line (pt 288 32)(pt 272 32)(line_width 3))
|
||||
)
|
||||
(parameter
|
||||
"rx_buffer_length"
|
||||
"7"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(drawing
|
||||
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|
||||
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|
||||
(annotation_block (parameter)(rect 3088 96 3296 136))
|
||||
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|
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(symbol
|
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(rect 3080 1144 3304 1224)
|
||||
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|
||||
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|
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(port
|
||||
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|
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(input)
|
||||
(text "pwm_clk_in" (rect 0 0 56 12)(font "Arial" ))
|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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(port
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|
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(output)
|
||||
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|
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|
||||
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|
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|
||||
(drawing
|
||||
(rectangle (rect 16 16 208 64))
|
||||
)
|
||||
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|
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|
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(pt 528 32)
|
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(pt 440 32)
|
||||
|
|
@ -4117,10 +4169,6 @@ refer to the applicable agreement for further details.
|
|||
(pt 3048 784)
|
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(pt 3048 904)
|
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)
|
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(connector
|
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|
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|
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|
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|
|
@ -4263,6 +4311,34 @@ refer to the applicable agreement for further details.
|
|||
(pt 1216 192)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 3080 1176)
|
||||
(pt 3048 1176)
|
||||
)
|
||||
(connector
|
||||
(pt 3048 904)
|
||||
(pt 3048 1008)
|
||||
)
|
||||
(connector
|
||||
(pt 3048 1008)
|
||||
(pt 3048 1176)
|
||||
)
|
||||
(connector
|
||||
(text "VCXO_correction[15..0]" (rect 2954 1176 3064 1193)(font "Intel Clear" ))
|
||||
(pt 3080 1192)
|
||||
(pt 2944 1192)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 3304 1176)
|
||||
(pt 3416 1176)
|
||||
)
|
||||
(connector
|
||||
(text "VCXO_correction[15..0]" (rect 3498 672 3608 689)(font "Intel Clear" ))
|
||||
(pt 3376 672)
|
||||
(pt 3536 672)
|
||||
(bus)
|
||||
)
|
||||
(junction (pt 376 120))
|
||||
(junction (pt 440 32))
|
||||
(junction (pt 440 448))
|
||||
|
|
@ -4289,4 +4365,5 @@ refer to the applicable agreement for further details.
|
|||
(junction (pt 3472 104))
|
||||
(junction (pt 3048 904))
|
||||
(junction (pt 440 -32))
|
||||
(junction (pt 3048 1008))
|
||||
(text "153.6mhz" (rect 3328 760 3388 779)(font "Intel Clear" (font_size 8)))
|
||||
|
|
|
|||
|
|
@ -321,4 +321,6 @@ set_global_assignment -name SIP_FILE tx_ciccomp.sip
|
|||
set_global_assignment -name QIP_FILE diffclock_buff.qip
|
||||
set_global_assignment -name QIP_FILE dcdc_pll.qip
|
||||
set_global_assignment -name QIP_FILE tx_pll.qip
|
||||
set_location_assignment PIN_143 -to VCXO_PWM
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VCXO_PWM
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
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|
|
@ -1,11 +1,11 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="clock_buffer" kind="clock_buffer" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
|
||||
<!-- 2021.03.31.22:15:10 -->
|
||||
<!-- 2022.02.06.13:05:37 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>1617214510</value>
|
||||
<value>1644138337</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
|
|
|
|||
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|
|
@ -1,96 +0,0 @@
|
|||
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=5 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" clk1_divide_by=1280 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=16276 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=MAIN_PLL" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
//VERSION_BEGIN 18.1 cbx_altclkbuf 2018:09:12:13:04:24:SJ cbx_altiobuf_bidir 2018:09:12:13:04:24:SJ cbx_altiobuf_in 2018:09:12:13:04:24:SJ cbx_altiobuf_out 2018:09:12:13:04:24:SJ cbx_altpll 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END
|
||||
//CBXI_INSTANCE_NAME="WOLF_LITE_MAIN_PLL_MAIN_PLL_altpll_altpll_component"
|
||||
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
|
||||
// altera message_off 10463
|
||||
|
||||
|
||||
|
||||
// Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
//synthesis_resources = cycloneive_pll 1
|
||||
//synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
//synopsys translate_on
|
||||
module MAIN_PLL_altpll
|
||||
(
|
||||
clk,
|
||||
inclk) /* synthesis synthesis_clearbox=1 */;
|
||||
output [4:0] clk;
|
||||
input [1:0] inclk;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 [1:0] inclk;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [4:0] wire_pll1_clk;
|
||||
wire wire_pll1_fbout;
|
||||
|
||||
cycloneive_pll pll1
|
||||
(
|
||||
.activeclock(),
|
||||
.clk(wire_pll1_clk),
|
||||
.clkbad(),
|
||||
.fbin(wire_pll1_fbout),
|
||||
.fbout(wire_pll1_fbout),
|
||||
.inclk(inclk),
|
||||
.locked(),
|
||||
.phasedone(),
|
||||
.scandataout(),
|
||||
.scandone(),
|
||||
.vcooverrange(),
|
||||
.vcounderrange()
|
||||
`ifndef FORMAL_VERIFICATION
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
,
|
||||
.areset(1'b0),
|
||||
.clkswitch(1'b0),
|
||||
.configupdate(1'b0),
|
||||
.pfdena(1'b1),
|
||||
.phasecounterselect({3{1'b0}}),
|
||||
.phasestep(1'b0),
|
||||
.phaseupdown(1'b0),
|
||||
.scanclk(1'b0),
|
||||
.scanclkena(1'b1),
|
||||
.scandata(1'b0)
|
||||
`ifndef FORMAL_VERIFICATION
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
);
|
||||
defparam
|
||||
pll1.bandwidth_type = "auto",
|
||||
pll1.clk0_divide_by = 5,
|
||||
pll1.clk0_duty_cycle = 50,
|
||||
pll1.clk0_multiply_by = 1,
|
||||
pll1.clk0_phase_shift = "0",
|
||||
pll1.clk1_divide_by = 1280,
|
||||
pll1.clk1_duty_cycle = 50,
|
||||
pll1.clk1_multiply_by = 1,
|
||||
pll1.clk1_phase_shift = "0",
|
||||
pll1.compensate_clock = "clk0",
|
||||
pll1.inclk0_input_frequency = 16276,
|
||||
pll1.operation_mode = "normal",
|
||||
pll1.pll_type = "auto",
|
||||
pll1.lpm_type = "cycloneive_pll";
|
||||
assign
|
||||
clk = {wire_pll1_clk[4:0]};
|
||||
endmodule //MAIN_PLL_altpll
|
||||
//VALID FILE
|
||||
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Some files were not shown because too many files have changed in this diff Show More
Ładowanie…
Reference in New Issue