kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
Encoder2
Encoder2 debounce это задержка для повторного срабатывание (дребезг) Encoder2 slow rate кол-во щелчков для срабатывания. Автор linoobmaster
Антон
rodzic
03482e7631
commit
4b5c0232a4
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@ -48,6 +48,7 @@ static void FRONTPANEL_ENC2SW_hold_handler(uint32_t parameter);
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static bool FRONTPanel_MCP3008_1_Enabled = true;
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static int32_t ENCODER_slowler = 0;
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static int32_t ENCODER2_slowler = 0;
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static uint32_t ENCODER_AValDeb = 0;
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static uint32_t ENCODER2_AValDeb = 0;
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//static uint8_t enc2_func_mode = 0;
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@ -239,22 +240,75 @@ void FRONTPANEL_ENCODER2_checkRotate(void)
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{
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uint8_t ENCODER2_DTVal = HAL_GPIO_ReadPin(ENC2_DT_GPIO_Port, ENC2_DT_Pin);
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uint8_t ENCODER2_CLKVal = HAL_GPIO_ReadPin(ENC2_CLK_GPIO_Port, ENC2_CLK_Pin);
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static uint32_t ENCstartMeasureTime = 0;
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static int16_t ENCticksInInterval = 0;
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static float32_t ENCAcceleration = 0;
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static uint8_t ENClastClkVal = 0;
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static bool ENCfirst = true;
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if (ENCfirst)
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{
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ENClastClkVal = ENCODER2_CLKVal;
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ENCfirst = false;
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}
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if (ENClastClkVal != ENCODER2_CLKVal)
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{
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if ((HAL_GetTick() - ENCODER2_AValDeb) < CALIBRATE.ENCODER2_DEBOUNCE)
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return;
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if (!CALIBRATE.ENCODER_ON_FALLING || ENCODER2_CLKVal == 0)
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{
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if (ENCODER2_DTVal != ENCODER2_CLKVal)
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{ // If pin A changed first - clockwise rotation
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FRONTPANEL_ENCODER2_Rotated(CALIBRATE.ENCODER2_INVERT ? 1 : -1);
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}
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else
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{ // otherwise B changed its state first - counterclockwise rotation
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FRONTPANEL_ENCODER2_Rotated(CALIBRATE.ENCODER2_INVERT ? -1 : 1);
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}
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{ // If pin A changed first - clockwise rotation
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ENCODER2_slowler--;
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if (ENCODER2_slowler <= -CALIBRATE.ENCODER2_SLOW_RATE)
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{
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//acceleration
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ENCticksInInterval++;
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if((HAL_GetTick() - ENCstartMeasureTime) > ENCODER_ACCELERATION)
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{
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ENCstartMeasureTime = HAL_GetTick();
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ENCAcceleration = (10.0f + ENCticksInInterval - 1.0f) / 10.0f;
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ENCticksInInterval = 0;
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}
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//do rotate
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FRONTPANEL_ENCODER2_Rotated(CALIBRATE.ENCODER2_INVERT ? ENCAcceleration : -ENCAcceleration);
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ENCODER2_slowler = 0;
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}
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}
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else
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{ // otherwise B changed its state first - counterclockwise rotation
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ENCODER2_slowler++;
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if (ENCODER2_slowler >= CALIBRATE.ENCODER2_SLOW_RATE)
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{
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//acceleration
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ENCticksInInterval++;
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if((HAL_GetTick() - ENCstartMeasureTime) > ENCODER_ACCELERATION)
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{
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ENCstartMeasureTime = HAL_GetTick();
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ENCAcceleration = (10.0f + ENCticksInInterval - 1.0f) / 10.0f;
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ENCticksInInterval = 0;
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}
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//do rotate
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FRONTPANEL_ENCODER2_Rotated(CALIBRATE.ENCODER2_INVERT ? -ENCAcceleration : ENCAcceleration);
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ENCODER2_slowler = 0;
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}
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}
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// if (ENCODER2_DTVal != ENCODER2_CLKVal)
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// { // If pin A changed first - clockwise rotation
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// FRONTPANEL_ENCODER2_Rotated(CALIBRATE.ENCODER2_INVERT ? 1 : -1);
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// }
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// else
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// { // otherwise B changed its state first - counterclockwise rotation
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// FRONTPANEL_ENCODER2_Rotated(CALIBRATE.ENCODER2_INVERT ? -1 : 1);
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// }
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}
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ENCODER2_AValDeb = HAL_GetTick();
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ENClastClkVal = ENCODER2_CLKVal;
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}
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}
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static void FRONTPANEL_ENCODER_Rotated(float32_t direction) // rotated encoder, handler here, direction -1 - left, 1 - right
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@ -336,24 +390,25 @@ static void FRONTPANEL_ENCODER2_Rotated(int8_t direction) // rotated encoder, ha
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float64_t step = 0;
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if (TRX.Fast)
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{
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step = (float32_t)TRX.FRQ_FAST_STEP * 2; // Fast
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step = (float32_t)TRX.FRQ_ENC_FAST_STEP; // Fast
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freq_round = roundf((float64_t)vfo->Freq / step) * step;
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newfreq = (uint32_t)((int32_t)freq_round + (int32_t)step * direction);
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// newfreq = (uint32_t)((int32_t)vfo->Freq + (int32_t)((float32_t)TRX.FRQ_FAST_STEP * direction));
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// if ((vfo->Freq % TRX.FRQ_FAST_STEP) > 0 && fabsf(direction) <= 1.0f)
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// newfreq = vfo->Freq / TRX.FRQ_FAST_STEP * TRX.FRQ_FAST_STEP;
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// step = (float32_t)TRX.FRQ_FAST_STEP * 2; // Fast
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// freq_round = roundf((float64_t)vfo->Freq / step) * step;
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// newfreq = (uint32_t)((int32_t)freq_round + (int32_t)step * direction);
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}
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else
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{
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step = (float32_t)TRX.FRQ_STEP * 2; // Regular
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step = (float32_t)TRX.FRQ_ENC_STEP; // Regular
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freq_round = roundf((float64_t)vfo->Freq / step) * step;
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newfreq = (uint32_t)((int32_t)freq_round + (int32_t)step * direction);
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// newfreq = (uint32_t)((int32_t)vfo->Freq + (int32_t)((float32_t)TRX.FRQ_STEP * direction));
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// if ((vfo->Freq % TRX.FRQ_STEP) > 0 && fabsf(direction) <= 1.0f)
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// newfreq = vfo->Freq / TRX.FRQ_STEP * TRX.FRQ_STEP;
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// step = (float32_t)TRX.FRQ_STEP * 2; // Regular
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// freq_round = roundf((float64_t)vfo->Freq / step) * step;
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// newfreq = (uint32_t)((int32_t)freq_round + (int32_t)step * direction);
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}
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TRX_setFrequency(newfreq, vfo);
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LCD_UpdateQuery.FreqInfo = true;
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@ -205,6 +205,8 @@ void LoadSettings(bool clear)
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TRX.DNR_MINIMAL = 99; // DNR averaging when searching for minimum magnitude
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TRX.FRQ_STEP = 10; // frequency tuning step by the main encoder
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TRX.FRQ_FAST_STEP = 100; // frequency tuning step by the main encoder in FAST mode
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TRX.FRQ_ENC_STEP = 2500; // frequency tuning step by main add. encoder
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TRX.FRQ_ENC_FAST_STEP = 5000; // frequency tuning step by main add. encoder in FAST mode
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TRX.AGC_GAIN_TARGET = -25; // Maximum (target) AGC gain
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TRX.TX_Compressor_speed_SSB = 3; // TX ñêîðîñòü êîìïðåññîðà SSB
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TRX.TX_Compressor_maxgain_SSB = 10; // TX ìàêñèìàëüíîå óñèëåíèå SSB
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@ -276,8 +278,9 @@ void LoadCalibration(bool clear)
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CALIBRATE.ENCODER_INVERT = false; // invert left-right rotation of the main encoder
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CALIBRATE.ENCODER2_INVERT = false; // invert left-right rotation of the optional encoder
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CALIBRATE.ENCODER_DEBOUNCE = 0; // time to eliminate contact bounce at the main encoder, ms
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CALIBRATE.ENCODER2_DEBOUNCE = 50; // time to eliminate contact bounce at the additional encoder, ms
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CALIBRATE.ENCODER2_DEBOUNCE = 30; // time to eliminate contact bounce at the additional encoder, ms
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CALIBRATE.ENCODER_SLOW_RATE = 25; // slow down the encoder for high resolutions
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CALIBRATE.ENCODER2_SLOW_RATE = 2; // slow down the encoder for high resolutions
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CALIBRATE.ENCODER_ON_FALLING = false; // encoder only triggers when level A falls
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CALIBRATE.CICFIR_GAINER_val = 35; // Offset from the output of the CIC compensator
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CALIBRATE.TXCICFIR_GAINER_val = 27; // Offset from the TX-CIC output of the compensator
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@ -9,10 +9,32 @@
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#define SETT_VERSION 101 // Settings config version
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#define CALIB_VERSION 101 // Calibration config version
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//#define ADC_CLOCK 64320000 // ADC generator frequency eaeea?iaea ?anoiou aaia?aoi?a
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//#define DAC_CLOCK 160800000 // DAC generator frequency
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#ifdef FRONT_R7KBI_61_440
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#define ADC_CLOCK 61440000 // ADC generator frequency êàëèáðîâêà ÷àñòîòû ãåíåðàòîðà
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#define DAC_CLOCK 153600000 // DAC generator frequency
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#define BUTTONS_R7KBI true //Author board buttons
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#endif
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#ifdef FRONT_R7KBI_64_320
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#define ADC_CLOCK 64320000 // ADC generator frequency eaeea?iaea ?anoiou aaia?aoi?a
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#define DAC_CLOCK 160800000 // DAC generator frequency
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#define BUTTONS_R7KBI true //Author board buttons
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#endif
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#ifdef FRONT_ALEX_61_440
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#define ADC_CLOCK 61440000 // ADC generator frequency êàëèáðîâêà ÷àñòîòû ãåíåðàòîðà
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#define DAC_CLOCK 153600000 // DAC generator frequency
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#define BUTTONS_R7KBI false //Author board buttons
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#endif
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#ifdef FRONT_ALEX_64_320
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#define ADC_CLOCK 64320000 // ADC generator frequency eaeea?iaea ?anoiou aaia?aoi?a
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#define DAC_CLOCK 160800000 // DAC generator frequency
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#define BUTTONS_R7KBI false //Author board buttons
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#endif
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//#define ADC_CLOCK 64320000 // ADC generator frequency eaeea?iaea ?anoiou aaia?aoi?a
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//#define DAC_CLOCK 160800000 // DAC generator frequency
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//#define ADC_CLOCK 61440000 // ADC generator frequency êàëèáðîâêà ÷àñòîòû ãåíåðàòîðà
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//#define DAC_CLOCK 153600000 // DAC generator frequency
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#define MAX_RX_FREQ_HZ 750000000 // Maximum receive frequency (from the ADC datasheet)
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#define MAX_TX_FREQ_HZ (DAC_CLOCK / 2) // Maximum transmission frequency
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#define TRX_SAMPLERATE 48000 // audio stream sampling rate during processing
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@ -34,7 +56,7 @@
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#define ENCODER_MIN_RATE_ACCELERATION 1.2f //encoder enable rounding if lower than value
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#define TRX_MAX_SWR 5 //maximum SWR to enable protect (NOT IN TUNE MODE!)
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#define BUTTONS_R7KBI true //Author board buttons
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//#define BUTTONS_R7KBI true //Author board buttons
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// select LCD, comment on others
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//#define LCD_ILI9481 true
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@ -123,6 +145,8 @@ extern struct TRX_SETTINGS
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bool TWO_SIGNAL_TUNE;
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uint16_t FRQ_STEP;
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uint16_t FRQ_FAST_STEP;
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uint16_t FRQ_ENC_STEP;
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uint16_t FRQ_ENC_FAST_STEP;
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bool Debug_Console;
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bool BandMapEnabled;
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bool InputType_MIC;
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@ -210,6 +234,7 @@ extern struct TRX_CALIBRATE
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uint8_t ENCODER_DEBOUNCE;
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uint8_t ENCODER2_DEBOUNCE;
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uint8_t ENCODER_SLOW_RATE;
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uint8_t ENCODER2_SLOW_RATE;
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bool ENCODER_ON_FALLING;
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uint8_t CICFIR_GAINER_val;
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uint8_t TXCICFIR_GAINER_val;
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@ -98,6 +98,7 @@ static void SYSMENU_HANDL_SETTIME(int8_t direction);
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static void SYSMENU_HANDL_Bootloader(int8_t direction);
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static void SYSMENU_HANDL_CALIB_ENCODER_SLOW_RATE(int8_t direction);
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static void SYSMENU_HANDL_CALIB_ENCODER2_SLOW_RATE(int8_t direction);
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static void SYSMENU_HANDL_CALIB_ENCODER_INVERT(int8_t direction);
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static void SYSMENU_HANDL_CALIB_ENCODER2_INVERT(int8_t direction);
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static void SYSMENU_HANDL_CALIB_ENCODER_DEBOUNCE(int8_t direction);
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@ -160,6 +161,8 @@ static const struct sysmenu_item_handler sysmenu_trx_handlers[] =
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{"Shift Interval", SYSMENU_UINT16, (uint32_t *)&TRX.SHIFT_INTERVAL, SYSMENU_HANDL_TRX_SHIFT_INTERVAL},
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{"Freq Step", SYSMENU_UINT16, (uint32_t *)&TRX.FRQ_STEP, SYSMENU_HANDL_TRX_FRQ_STEP},
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{"Freq Step FAST", SYSMENU_UINT16, (uint32_t *)&TRX.FRQ_FAST_STEP, SYSMENU_HANDL_TRX_FRQ_FAST_STEP},
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{"Freq Step ENC2", SYSMENU_UINT16, (uint32_t *)&TRX.FRQ_ENC_STEP, SYSMENU_HANDL_TRX_FRQ_ENC_STEP},
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{"Freq Step FAST ENC2", SYSMENU_UINT16, (uint32_t *)&TRX.FRQ_ENC_FAST_STEP, SYSMENU_HANDL_TRX_FRQ_ENC_FAST_STEP},
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{"Encoder Accelerate", SYSMENU_BOOLEAN, (uint32_t *)&TRX.Encoder_Accelerate, SYSMENU_HANDL_TRX_ENC_ACCELERATE},
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{"Encoder TX/OFF", SYSMENU_BOOLEAN, (uint32_t *)&TRX.Encoder_OFF, SYSMENU_HANDL_TXOFF_ENC},
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{"Att step, dB", SYSMENU_UINT8, (uint32_t *)&TRX.ATT_STEP, SYSMENU_HANDL_TRX_ATT_STEP},
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@ -252,6 +255,7 @@ static const struct sysmenu_item_handler sysmenu_calibration_handlers[] =
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{"Encoder debounce", SYSMENU_UINT8, (uint32_t *)&CALIBRATE.ENCODER_DEBOUNCE, SYSMENU_HANDL_CALIB_ENCODER_DEBOUNCE},
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{"Encoder2 debounce", SYSMENU_UINT8, (uint32_t *)&CALIBRATE.ENCODER2_DEBOUNCE, SYSMENU_HANDL_CALIB_ENCODER2_DEBOUNCE},
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{"Encoder slow rate", SYSMENU_UINT8, (uint32_t *)&CALIBRATE.ENCODER_SLOW_RATE, SYSMENU_HANDL_CALIB_ENCODER_SLOW_RATE},
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{"Encoder2 slow rate", SYSMENU_UINT8, (uint32_t *)&CALIBRATE.ENCODER2_SLOW_RATE, SYSMENU_HANDL_CALIB_ENCODER2_SLOW_RATE},
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{"Encoder on falling", SYSMENU_BOOLEAN, (uint32_t *)&CALIBRATE.ENCODER_ON_FALLING, SYSMENU_HANDL_CALIB_ENCODER_ON_FALLING},
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{"CICCOMP Shift", SYSMENU_UINT8, (uint32_t *)&CALIBRATE.CICFIR_GAINER_val, SYSMENU_HANDL_CALIB_CICCOMP_SHIFT},
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{"TX CICCOMP Shift", SYSMENU_UINT8, (uint32_t *)&CALIBRATE.TXCICFIR_GAINER_val, SYSMENU_HANDL_CALIB_TXCICCOMP_SHIFT},
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@ -496,6 +500,58 @@ static void SYSMENU_HANDL_TRX_FRQ_FAST_STEP(int8_t direction)
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TRX.FRQ_FAST_STEP = freq_steps[0];
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}
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static void SYSMENU_HANDL_TRX_FRQ_ENC_STEP(int8_t direction)
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{
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const uint16_t freq_steps[] = {1, 10, 25, 50, 100, 500, 1000, 5000};
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for (uint8_t i = 0; i < ARRLENTH(freq_steps); i++)
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if (TRX.FRQ_ENC_STEP == freq_steps[i])
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{
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if (direction < 0)
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{
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if (i > 0)
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TRX.FRQ_ENC_STEP = freq_steps[i - 1];
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else
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TRX.FRQ_ENC_STEP = freq_steps[0];
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return;
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}
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else
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{
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if (i < (ARRLENTH(freq_steps) - 1))
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TRX.FRQ_ENC_STEP = freq_steps[i + 1];
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else
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TRX.FRQ_ENC_STEP = freq_steps[ARRLENTH(freq_steps) - 1];
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return;
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}
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}
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TRX.FRQ_ENC_STEP = freq_steps[0];
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}
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static void SYSMENU_HANDL_TRX_FRQ_ENC_FAST_STEP(int8_t direction)
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{
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const uint16_t freq_steps[] = {1, 10, 25, 50, 100, 500, 1000, 5000};
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for (uint8_t i = 0; i < ARRLENTH(freq_steps); i++)
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if (TRX.FRQ_ENC_FAST_STEP == freq_steps[i])
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{
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if (direction < 0)
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{
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if (i > 0)
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TRX.FRQ_ENC_FAST_STEP = freq_steps[i - 1];
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else
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TRX.FRQ_ENC_FAST_STEP = freq_steps[0];
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return;
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}
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else
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{
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if (i < (ARRLENTH(freq_steps) - 1))
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TRX.FRQ_ENC_FAST_STEP = freq_steps[i + 1];
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else
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TRX.FRQ_ENC_FAST_STEP = freq_steps[ARRLENTH(freq_steps) - 1];
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return;
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}
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}
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TRX.FRQ_ENC_FAST_STEP = freq_steps[0];
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}
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static void SYSMENU_HANDL_TRX_ENC_ACCELERATE(int8_t direction)
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{
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if (direction > 0)
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@ -1773,6 +1829,15 @@ static void SYSMENU_HANDL_CALIB_ENCODER_SLOW_RATE(int8_t direction)
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CALIBRATE.ENCODER_SLOW_RATE = 100;
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}
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static void SYSMENU_HANDL_CALIB_ENCODER2_SLOW_RATE(int8_t direction)
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{
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CALIBRATE.ENCODER2_SLOW_RATE += direction;
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if (CALIBRATE.ENCODER2_SLOW_RATE < 1)
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CALIBRATE.ENCODER2_SLOW_RATE = 1;
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if (CALIBRATE.ENCODER2_SLOW_RATE > 100)
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CALIBRATE.ENCODER2_SLOW_RATE = 100;
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}
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static void SYSMENU_HANDL_CALIB_ENCODER_ON_FALLING(int8_t direction)
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{
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if (direction > 0)
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@ -0,0 +1,48 @@
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// File: STM32F405_415_407_417_427_437_429_439.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
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// refer to STM32F40x STM32F41x datasheets
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// refer to STM32F42x STM32F43x datasheets
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU configuration register (DBGMCU_CR)
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// <o.2> DBG_STANDBY <i> Debug Standby Mode
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// <o.1> DBG_STOP <i> Debug Stop Mode
|
||||
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
|
||||
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
|
||||
// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
|
||||
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
|
||||
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
|
||||
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
|
||||
// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
|
||||
// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
|
||||
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
|
||||
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
|
||||
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
|
||||
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
|
||||
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
|
||||
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
|
||||
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
|
||||
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
|
||||
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
|
||||
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
|
||||
// </h>
|
||||
DbgMCU_APB1_Fz = 0x00000000;
|
||||
|
||||
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
|
||||
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
|
||||
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
|
||||
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
|
||||
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
|
||||
// </h>
|
||||
DbgMCU_APB2_Fz = 0x00000000;
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
// File: STM32F405_415_407_417_427_437_429_439.dbgconf
|
||||
// Version: 1.0.0
|
||||
// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
|
||||
// refer to STM32F40x STM32F41x datasheets
|
||||
// refer to STM32F42x STM32F43x datasheets
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Debug MCU configuration register (DBGMCU_CR)
|
||||
// <o.2> DBG_STANDBY <i> Debug Standby Mode
|
||||
// <o.1> DBG_STOP <i> Debug Stop Mode
|
||||
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
|
||||
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
|
||||
// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
|
||||
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
|
||||
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
|
||||
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
|
||||
// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
|
||||
// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
|
||||
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
|
||||
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
|
||||
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
|
||||
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
|
||||
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
|
||||
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
|
||||
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
|
||||
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
|
||||
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
|
||||
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
|
||||
// </h>
|
||||
DbgMCU_APB1_Fz = 0x00000000;
|
||||
|
||||
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
|
||||
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
|
||||
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
|
||||
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
|
||||
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
|
||||
// </h>
|
||||
DbgMCU_APB2_Fz = 0x00000000;
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
// File: STM32F405_415_407_417_427_437_429_439.dbgconf
|
||||
// Version: 1.0.0
|
||||
// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
|
||||
// refer to STM32F40x STM32F41x datasheets
|
||||
// refer to STM32F42x STM32F43x datasheets
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Debug MCU configuration register (DBGMCU_CR)
|
||||
// <o.2> DBG_STANDBY <i> Debug Standby Mode
|
||||
// <o.1> DBG_STOP <i> Debug Stop Mode
|
||||
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
|
||||
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
|
||||
// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
|
||||
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
|
||||
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
|
||||
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
|
||||
// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
|
||||
// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
|
||||
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
|
||||
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
|
||||
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
|
||||
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
|
||||
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
|
||||
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
|
||||
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
|
||||
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
|
||||
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
|
||||
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
|
||||
// </h>
|
||||
DbgMCU_APB1_Fz = 0x00000000;
|
||||
|
||||
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
|
||||
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
|
||||
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
|
||||
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
|
||||
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
|
||||
// </h>
|
||||
DbgMCU_APB2_Fz = 0x00000000;
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
// File: STM32F405_415_407_417_427_437_429_439.dbgconf
|
||||
// Version: 1.0.0
|
||||
// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
|
||||
// refer to STM32F40x STM32F41x datasheets
|
||||
// refer to STM32F42x STM32F43x datasheets
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Debug MCU configuration register (DBGMCU_CR)
|
||||
// <o.2> DBG_STANDBY <i> Debug Standby Mode
|
||||
// <o.1> DBG_STOP <i> Debug Stop Mode
|
||||
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
|
||||
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
|
||||
// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
|
||||
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
|
||||
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
|
||||
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
|
||||
// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
|
||||
// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
|
||||
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
|
||||
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
|
||||
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
|
||||
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
|
||||
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
|
||||
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
|
||||
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
|
||||
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
|
||||
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
|
||||
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
|
||||
// </h>
|
||||
DbgMCU_APB1_Fz = 0x00000000;
|
||||
|
||||
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
|
||||
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
|
||||
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
|
||||
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
|
||||
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
|
||||
// </h>
|
||||
DbgMCU_APB2_Fz = 0x00000000;
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
|
|
@ -1,21 +1,21 @@
|
|||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'WOLF-Lite'
|
||||
* Target: 'WOLF-Lite'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "stm32f4xx.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'WOLF-Lite'
|
||||
* Target: 'WOLF-Lite'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "stm32f4xx.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'WOLF-Lite'
|
||||
* Target: 'WOLF-Lite_ALEX_61.440'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "stm32f4xx.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'WOLF-Lite'
|
||||
* Target: 'WOLF-Lite_ALEX_64.320'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "stm32f4xx.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'WOLF-Lite'
|
||||
* Target: 'WOLF-Lite_R7KBI_61.440'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "stm32f4xx.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'WOLF-Lite'
|
||||
* Target: 'WOLF-Lite_R7KBI_64.320'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "stm32f4xx.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
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Load Diff
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Ładowanie…
Reference in New Issue