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kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
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master
linoobs 2022-04-25 19:59:04 +02:00
rodzic 14dfc9bb75
commit 3c90e0a05e
3 zmienionych plików z 93 dodań i 5 usunięć
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91
STM32/Core/Src/fpga.c
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@ -238,6 +238,7 @@ static inline void FPGA_fpgadata_sendparam(void)
FPGA_clockRise();
FPGA_clockFall();
#if defined(FRONT_R7KBI_61_440) || defined(FRONT_ALEX_61_440)
//STAGE 16
//out BPF
FPGA_fpgadata_out_tmp8 = 0;
@ -336,7 +337,6 @@ static inline void FPGA_fpgadata_sendparam(void)
FPGA_clockRise();
FPGA_clockFall();
#if defined(FRONT_R7KBI_61_440) || defined(FRONT_ALEX_61_440)
//OUT VCXO_CORRECTION
uint16_t FPGA_fpgadata_out_tmp16 = 37280 + (CALIBRATE.vcxo_calibration * 14); // 32767 - center (50% cycle)
FPGA_writePacket(((FPGA_fpgadata_out_tmp16 & (0XFF << 8)) >> 8));
@ -348,6 +348,95 @@ static inline void FPGA_fpgadata_sendparam(void)
FPGA_clockRise();
FPGA_clockFall();
#endif
#if defined(FRONT_R7KBI_64_320) || defined(FRONT_ALEX_64_320)
//STAGE 16
//out BPF
FPGA_fpgadata_out_tmp8 = 0;
if(CurrentVFO()->Freq >= 1500000 && CurrentVFO()->Freq <= 2400000) //160m
{
bitWrite(FPGA_fpgadata_out_tmp8, 0, 0); //BPF_A
bitWrite(FPGA_fpgadata_out_tmp8, 1, 0); //BPF_B
bitWrite(FPGA_fpgadata_out_tmp8, 3, 1); //BPF_OE1
bitWrite(FPGA_fpgadata_out_tmp8, 2, 0); //BPF_OE2
bitWrite(FPGA_fpgadata_out_tmp8, 4, 0); //LPF1
bitWrite(FPGA_fpgadata_out_tmp8, 5, 0); //LPF2
bitWrite(FPGA_fpgadata_out_tmp8, 6, 0); //LPF3
}
else if(CurrentVFO()->Freq >= 2400000 && CurrentVFO()->Freq <= 4500000) //80m
{
bitWrite(FPGA_fpgadata_out_tmp8, 0, 1); //BPF_A
bitWrite(FPGA_fpgadata_out_tmp8, 1, 0); //BPF_B
bitWrite(FPGA_fpgadata_out_tmp8, 3, 1); //BPF_OE1
bitWrite(FPGA_fpgadata_out_tmp8, 2, 0); //BPF_OE2
bitWrite(FPGA_fpgadata_out_tmp8, 4, 1); //LPF1
bitWrite(FPGA_fpgadata_out_tmp8, 5, 0); //LPF2
bitWrite(FPGA_fpgadata_out_tmp8, 6, 0); //LPF3
}
else if(CurrentVFO()->Freq >= 4500000 && CurrentVFO()->Freq <= 7500000) //40m
{
bitWrite(FPGA_fpgadata_out_tmp8, 0, 0); //BPF_A
bitWrite(FPGA_fpgadata_out_tmp8, 1, 1); //BPF_B
bitWrite(FPGA_fpgadata_out_tmp8, 3, 1); //BPF_OE1
bitWrite(FPGA_fpgadata_out_tmp8, 2, 0); //BPF_OE2
bitWrite(FPGA_fpgadata_out_tmp8, 4, 0); //LPF1
bitWrite(FPGA_fpgadata_out_tmp8, 5, 1); //LPF2
bitWrite(FPGA_fpgadata_out_tmp8, 6, 0); //LPF3
}
else if(CurrentVFO()->Freq >= 7500000 && CurrentVFO()->Freq <= 12000000) //30m
{
bitWrite(FPGA_fpgadata_out_tmp8, 0, 1); //BPF_A
bitWrite(FPGA_fpgadata_out_tmp8, 1, 1); //BPF_B
bitWrite(FPGA_fpgadata_out_tmp8, 3, 1); //BPF_OE1
bitWrite(FPGA_fpgadata_out_tmp8, 2, 0); //BPF_OE2
bitWrite(FPGA_fpgadata_out_tmp8, 4, 1); //LPF1
bitWrite(FPGA_fpgadata_out_tmp8, 5, 1); //LPF2
bitWrite(FPGA_fpgadata_out_tmp8, 6, 0); //LPF3
}
else if(CurrentVFO()->Freq >= 12000000 && CurrentVFO()->Freq <= 14800000) //20m
{
bitWrite(FPGA_fpgadata_out_tmp8, 0, 0); //BPF_A
bitWrite(FPGA_fpgadata_out_tmp8, 1, 0); //BPF_B
bitWrite(FPGA_fpgadata_out_tmp8, 3, 0); //BPF_OE1
bitWrite(FPGA_fpgadata_out_tmp8, 2, 1); //BPF_OE2
bitWrite(FPGA_fpgadata_out_tmp8, 4, 0); //LPF1
bitWrite(FPGA_fpgadata_out_tmp8, 5, 0); //LPF2
bitWrite(FPGA_fpgadata_out_tmp8, 6, 1); //LPF3
}
else if(CurrentVFO()->Freq >= 14800000 && CurrentVFO()->Freq <= 22000000) //17,15m
{
bitWrite(FPGA_fpgadata_out_tmp8, 0, 1); //BPF_A
bitWrite(FPGA_fpgadata_out_tmp8, 1, 0); //BPF_B
bitWrite(FPGA_fpgadata_out_tmp8, 3, 0); //BPF_OE1
bitWrite(FPGA_fpgadata_out_tmp8, 2, 1); //BPF_OE2
bitWrite(FPGA_fpgadata_out_tmp8, 4, 1); //LPF1
bitWrite(FPGA_fpgadata_out_tmp8, 5, 0); //LPF2
bitWrite(FPGA_fpgadata_out_tmp8, 6, 1); //LPF3
}
else if(CurrentVFO()->Freq >= 22000000 && CurrentVFO()->Freq <= 32000000) //12,10m
{
bitWrite(FPGA_fpgadata_out_tmp8, 0, 0); //BPF_A
bitWrite(FPGA_fpgadata_out_tmp8, 1, 1); //BPF_B
bitWrite(FPGA_fpgadata_out_tmp8, 3, 0); //BPF_OE1
bitWrite(FPGA_fpgadata_out_tmp8, 2, 1); //BPF_OE2
bitWrite(FPGA_fpgadata_out_tmp8, 4, 0); //LPF1
bitWrite(FPGA_fpgadata_out_tmp8, 5, 1); //LPF2
bitWrite(FPGA_fpgadata_out_tmp8, 6, 1); //LPF3
}
else //if(CurrentVFO()->Freq >= 0 && CurrentVFO()->Freq <= 53000000) //6m
{
bitWrite(FPGA_fpgadata_out_tmp8, 0, 1); //BPF_A
bitWrite(FPGA_fpgadata_out_tmp8, 1, 1); //BPF_B
bitWrite(FPGA_fpgadata_out_tmp8, 3, 0); //BPF_OE1
bitWrite(FPGA_fpgadata_out_tmp8, 2, 1); //BPF_OE2
bitWrite(FPGA_fpgadata_out_tmp8, 4, 1); //LPF1
bitWrite(FPGA_fpgadata_out_tmp8, 5, 1); //LPF2
bitWrite(FPGA_fpgadata_out_tmp8, 6, 1); //LPF3
}
//bitWrite(FPGA_fpgadata_out_tmp8, 7, 0); //unused
FPGA_writePacket(FPGA_fpgadata_out_tmp8);
FPGA_clockRise();
FPGA_clockFall();
#endif
}
// get parameters

7
STM32/Core/Src/settings.h
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@ -80,8 +80,8 @@
#define ADC_INPUT_IMPEDANCE 200.0f //50ohm -> 1:4 trans
#define ADC_RANGE 1.0f
#define ADC_DRIVER_GAIN_DB 20.0f //on 14mhz
#define AUTOGAINER_TAGET (ADC_FULL_SCALE / 3)
#define AUTOGAINER_HYSTERESIS (ADC_FULL_SCALE / 10)
#define AUTOGAINER_TAGET (ADC_FULL_SCALE / 10)
#define AUTOGAINER_HYSTERESIS 200 //(ADC_FULL_SCALE / 10)
#define MAX_CALLSIGN_LENGTH 16
@ -229,6 +229,7 @@ extern struct TRX_CALIBRATE
{
uint8_t flash_id; //eeprom check
int16_t vcxo_calibration;
bool ENCODER_INVERT;
bool ENCODER2_INVERT;
uint8_t ENCODER_DEBOUNCE;
@ -271,8 +272,6 @@ extern struct TRX_CALIBRATE
uint8_t rf_out_power_12m;
uint8_t rf_out_power_10m;
int16_t vcxo_calibration;
uint8_t csum; //check sum
uint8_t ENDBit; //end bit
} CALIBRATE;

BIN
STM32/MDK-ARM/WOLF-Lite_R7KBI_61_440.bin
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