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TX fix

master
XGudron 2021-03-24 18:39:33 +03:00
rodzic 4bdd855c0f
commit 27641d3625
7 zmienionych plików z 130 dodań i 101 usunięć
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22
STM32/Core/Src/audio_processor.c
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@ -308,12 +308,21 @@ void processTxAudio(void)
}
else //AUDIO CODEC AUDIO
{
uint32_t dma_index = CODEC_AUDIO_BUFFER_SIZE - (uint16_t)__HAL_DMA_GET_COUNTER(hi2s3.hdmarx);
uint32_t dma_index = CODEC_AUDIO_BUFFER_SIZE - (uint16_t)__HAL_DMA_GET_COUNTER(hi2s3.hdmarx) / 2;
//uint32_t dma_index = (uint16_t)__HAL_DMA_GET_COUNTER(hi2s3.hdmarx);
if ((dma_index % 2) == 1)
dma_index--;
//sendToDebug_uint32(CODEC_AUDIO_BUFFER_SIZE, false);
readFromCircleBuffer32((uint32_t *)&CODEC_Audio_Buffer_TX[0], (uint32_t *)&Processor_AudioBuffer_A[0], dma_index, CODEC_AUDIO_BUFFER_SIZE, AUDIO_BUFFER_SIZE);
}
//sendToDebug_int32(convertToSPIBigEndian(CODEC_Audio_Buffer_TX[0]), false);
//sendToDebug_int32(convertToSPIBigEndian(CODEC_Audio_Buffer_TX[380]), false);
//sendToDebug_int32(convertToSPIBigEndian(CODEC_Audio_Buffer_TX[640]), false);
//sendToDebug_newline();
//sendToDebug_int32(convertToSPIBigEndian(Processor_AudioBuffer_A[0]), true);
//sendToDebug_str(" ");
//sendToDebug_int32(Processor_AudioBuffer_A[0], false);
//One-signal zero-tune generator
if (TRX_Tune && !TRX.TWO_SIGNAL_TUNE)
{
@ -376,10 +385,14 @@ void processTxAudio(void)
//Copy and convert buffer
for (uint_fast16_t i = 0; i < AUDIO_BUFFER_HALF_SIZE; i++)
{
FPGA_Audio_Buffer_TX_I_tmp[i] = (float32_t)Processor_AudioBuffer_A[i * 2] / 2147483648.0f;
FPGA_Audio_Buffer_TX_Q_tmp[i] = (float32_t)Processor_AudioBuffer_A[i * 2 + 1] / 2147483648.0f;
//FPGA_Audio_Buffer_TX_I_tmp[i] = (float32_t)Processor_AudioBuffer_A[i * 2] / 2147483648.0f;
//FPGA_Audio_Buffer_TX_Q_tmp[i] = (float32_t)Processor_AudioBuffer_A[i * 2 + 1] / 2147483648.0f;
FPGA_Audio_Buffer_TX_I_tmp[i] = (float32_t)convertToSPIBigEndian(Processor_AudioBuffer_A[i * 2]) / 2147483648.0f;
FPGA_Audio_Buffer_TX_Q_tmp[i] = (float32_t)convertToSPIBigEndian(Processor_AudioBuffer_A[i * 2 + 1]) / 2147483648.0f;
}
//sendToDebug_float32(FPGA_Audio_Buffer_TX_I_tmp[0],false);
if (TRX.InputType_MIC)
{
//Mic Gain
@ -599,6 +612,7 @@ void processTxAudio(void)
//
if (FPGA_Audio_Buffer_State) //Send to FPGA DMA
{
//sendToDebug_float32(FPGA_Audio_SendBuffer_I[0],false);
HAL_DMA_Start(&hdma_memtomem_dma2_stream1, (uint32_t)&FPGA_Audio_Buffer_TX_I_tmp[0], (uint32_t)&FPGA_Audio_SendBuffer_I[AUDIO_BUFFER_HALF_SIZE], AUDIO_BUFFER_HALF_SIZE);
HAL_DMA_PollForTransfer(&hdma_memtomem_dma2_stream1, HAL_DMA_FULL_TRANSFER, HAL_MAX_DELAY);
HAL_DMA_Start(&hdma_memtomem_dma2_stream1, (uint32_t)&FPGA_Audio_Buffer_TX_Q_tmp[0], (uint32_t)&FPGA_Audio_SendBuffer_Q[AUDIO_BUFFER_HALF_SIZE], AUDIO_BUFFER_HALF_SIZE);

2
STM32/Core/Src/front_unit.h
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@ -5,7 +5,7 @@
#include <stdbool.h>
#define MCP3008_THRESHOLD 100
#define BOTTOM_SCROLLBUTTONS_GROUPS_COUNT 7
#define BOTTOM_SCROLLBUTTONS_GROUPS_COUNT 6
typedef struct
{

39
STM32/Core/Src/trx_manager.c
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@ -52,7 +52,6 @@ uint32_t TRX_freq_phrase = 0;
uint32_t TRX_freq_phrase_tx = 0;
float32_t TRX_InVoltage = 12.0f;
static uint_fast8_t TRX_TXRXMode = 0; //0 - undef, 1 - rx, 2 - tx, 3 - txrx
static void TRX_Start_RX(void);
static void TRX_Start_TX(void);
static void TRX_Start_TXRX(void);
@ -66,7 +65,9 @@ bool TRX_on_TX(void)
void TRX_Init()
{
TRX_Start_RX();
TRX_Start_TXRX();
WM8731_TXRX_mode();
WM8731_start_i2s_and_dma();
uint_fast8_t saved_mode = CurrentVFO()->Mode;
TRX_setFrequency(CurrentVFO()->Freq, CurrentVFO());
TRX_setMode(saved_mode, CurrentVFO());
@ -87,33 +88,17 @@ void TRX_Restart_Mode()
LCD_UpdateQuery.TopButtons = true;
LCD_UpdateQuery.StatusInfoGUIRedraw = true;
}
//
if (TRX_on_TX())
{
if (mode == TRX_MODE_LOOPBACK || mode == TRX_MODE_CW_L || mode == TRX_MODE_CW_U)
TRX_Start_TXRX();
else
TRX_Start_TX();
}
else
{
TRX_Start_RX();
}
FFT_Reset();
}
static void TRX_Start_RX()
{
if (TRX_TXRXMode == 1)
return;
//sendToDebug_str("RX MODE\r\n");
sendToDebug_str("RX MODE\r\n");
WM8731_CleanBuffer();
Processor_NeedRXBuffer = false;
WM8731_Buffer_underrun = false;
WM8731_DMA_state = true;
WM8731_RX_mode();
WM8731_start_i2s_and_dma();
TRX_TXRXMode = 1;
//clean TX buffer
memset((void *)&FPGA_Audio_SendBuffer_Q[0], 0x00, sizeof(FPGA_Audio_SendBuffer_Q));
memset((void *)&FPGA_Audio_SendBuffer_I[0], 0x00, sizeof(FPGA_Audio_SendBuffer_I));
@ -121,25 +106,15 @@ static void TRX_Start_RX()
static void TRX_Start_TX()
{
if (TRX_TXRXMode == 2)
return;
//sendToDebug_str("TX MODE\r\n");
sendToDebug_str("TX MODE\r\n");
WM8731_CleanBuffer();
HAL_Delay(10); // delay before the RF signal is applied, so that the relay has time to trigger
WM8731_TX_mode();
WM8731_start_i2s_and_dma();
TRX_TXRXMode = 2;
}
static void TRX_Start_TXRX()
{
if (TRX_TXRXMode == 3)
return;
//sendToDebug_str("TXRX MODE\r\n");
sendToDebug_str("TXRX MODE\r\n");
WM8731_CleanBuffer();
WM8731_TXRX_mode();
WM8731_start_i2s_and_dma();
TRX_TXRXMode = 3;
}
void TRX_ptt_change(void)

162
STM32/Core/Src/wm8731.c
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@ -28,8 +28,7 @@ void WM8731_start_i2s_and_dma(void)
WM8731_CleanBuffer();
if (HAL_I2S_GetState(&hi2s3) == HAL_I2S_STATE_READY)
{
HAL_I2SEx_TransmitReceive_DMA(&hi2s3, (uint16_t*)&CODEC_Audio_Buffer_RX[0], (uint16_t*)&CODEC_Audio_Buffer_TX[0], CODEC_AUDIO_BUFFER_SIZE);
I2SEx_Fix(&hi2s3);
HAL_I2S_TXRX_DMA(&hi2s3, (uint16_t *)&CODEC_Audio_Buffer_RX[0], (uint16_t *)&CODEC_Audio_Buffer_TX[0], CODEC_AUDIO_BUFFER_SIZE * 2, CODEC_AUDIO_BUFFER_SIZE); // 32bit rx spi, 16bit tx spi
}
}
@ -62,40 +61,6 @@ static uint8_t WM8731_SendI2CCommand(uint8_t reg, uint8_t value)
return st;
}
// switch to TX mode (mute the speaker, etc.)
void WM8731_TX_mode(void)
{
WM8731_SendI2CCommand(B8(00000101), B8(10000000)); //R2 Left Headphone Out
WM8731_SendI2CCommand(B8(00000111), B8(10000000)); //R3 Right Headphone Out
WM8731_SendI2CCommand(B8(00001010), B8(00011110)); //R5 Digital Audio Path Control
if (TRX.InputType_LINE) //line
{
WM8731_SendI2CCommand(B8(00000000), B8(00010111)); //R0 Left Line In
WM8731_SendI2CCommand(B8(00000010), B8(00010111)); //R1 Right Line In
WM8731_SendI2CCommand(B8(00001000), B8(00000010)); //R4 Analogue Audio Path Control
WM8731_SendI2CCommand(B8(00001100), B8(01101010)); //R6 Power Down Control
}
if (TRX.InputType_MIC) //mic
{
WM8731_SendI2CCommand(B8(00000001), B8(10000000)); //R0 Left Line In
WM8731_SendI2CCommand(B8(00000011), B8(10000000)); //R1 Right Line In
WM8731_SendI2CCommand(B8(00001000), B8(00000101)); //R4 Analogue Audio Path Control
WM8731_SendI2CCommand(B8(00001100), B8(01101001)); //R6 Power Down Control
}
}
// switch to RX mode (mute the microphone, etc.)
void WM8731_RX_mode(void)
{
WM8731_SendI2CCommand(B8(00000000), B8(10000000)); //R0 Left Line In
WM8731_SendI2CCommand(B8(00000010), B8(10000000)); //R1 Right Line In
WM8731_SendI2CCommand(B8(00000101), B8(11111111)); //R2 Left Headphone Out
WM8731_SendI2CCommand(B8(00000111), B8(11111111)); //R3 Right Headphone Out
WM8731_SendI2CCommand(B8(00001000), B8(00010110)); //R4 Analogue Audio Path Control
WM8731_SendI2CCommand(B8(00001010), B8(00010000)); //R5 Digital Audio Path Control
WM8731_SendI2CCommand(B8(00001100), B8(01100111)); //R6 Power Down Control
}
// switch to mixed RX-TX mode (for LOOP)
void WM8731_TXRX_mode(void) //loopback
{
@ -162,14 +127,12 @@ void WM8731_Init(void)
}
// RX Buffer is fully sent to the codec
void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
{
if (hi2s->Instance == SPI3)
if (((I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent)->Instance == SPI3)
{
if (Processor_NeedRXBuffer) // if the audio codec did not provide data to the buffer, raise the error flag
{
WM8731_Buffer_underrun = true;
}
WM8731_DMA_state = true;
Processor_NeedRXBuffer = true;
if (CurrentVFO()->Mode == TRX_MODE_LOOPBACK)
@ -179,14 +142,12 @@ void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
}
// RX Buffer half sent to the codec
void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
if (hi2s->Instance == SPI3)
if (((I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent)->Instance == SPI3)
{
if (Processor_NeedRXBuffer) // if the audio codec did not provide data to the buffer, raise the error flag
{
WM8731_Buffer_underrun = true;
}
WM8731_DMA_state = false;
Processor_NeedRXBuffer = true;
if (CurrentVFO()->Mode == TRX_MODE_LOOPBACK)
@ -195,29 +156,110 @@ void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
}
}
static void UA3REO_I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma)
// TX Buffer is completely taken from the codec
static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
HAL_I2S_RxCpltCallback(hi2s);
}
static void UA3REO_I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma)
// TX Buffer half received from the codec
static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
HAL_I2SEx_TxRxCpltCallback(hi2s);
I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
HAL_I2S_RxHalfCpltCallback(hi2s);
}
static void UA3REO_I2SEx_DMAErr(DMA_HandleTypeDef *hdma)
// DMA I2S error
static void I2S_DMAError(DMA_HandleTypeDef *hdma)
{
sendToDebug_str("err");
I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
/* Disable Rx and Tx DMA Request */
CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
hi2s->TxXferCount = (uint16_t)0UL;
hi2s->RxXferCount = (uint16_t)0UL;
hi2s->State = HAL_I2S_STATE_READY;
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
/* Call user error callback */
HAL_I2S_ErrorCallback(hi2s);
}
static void I2SEx_Fix(I2S_HandleTypeDef *hi2s)
static HAL_StatusTypeDef HAL_I2S_TXRX_DMA(I2S_HandleTypeDef *hi2s, uint16_t *txData, uint16_t *rxData, uint16_t txSize, uint16_t rxSize)
{
hi2s->hdmarx->XferHalfCpltCallback = NULL;
hi2s->hdmatx->XferHalfCpltCallback = UA3REO_I2SEx_TxRxDMAHalfCplt;
hi2s->hdmarx->XferCpltCallback = NULL;
hi2s->hdmatx->XferCpltCallback = UA3REO_I2SEx_TxRxDMACplt;
hi2s->hdmarx->XferErrorCallback = NULL;
hi2s->hdmatx->XferErrorCallback = UA3REO_I2SEx_DMAErr;
}
if ((rxData == NULL) || (txData == NULL) || (rxSize == 0UL) || (txSize == 0UL))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2s);
if (hi2s->State != HAL_I2S_STATE_READY)
{
__HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
/* Set state and reset error code */
hi2s->pTxBuffPtr = txData;
hi2s->pRxBuffPtr = rxData;
hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->TxXferSize = txSize;
hi2s->TxXferCount = txSize;
hi2s->RxXferSize = (rxSize << 1U);
hi2s->RxXferCount = (rxSize << 1U);
hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
/* Enable the Rx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
{
// Update SPI error code
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize))
{
//Update SPI error code
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
/* Enable Rx DMA Request */
SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
/* Enable Tx DMA Request */
SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
/* Check if the I2S is already enabled */
if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2Sext(receiver) before enabling I2Sx peripheral */
__HAL_I2SEXT_ENABLE(hi2s);
/* Enable I2S peripheral after the I2Sext */
__HAL_I2S_ENABLE(hi2s);
}
__HAL_UNLOCK(hi2s);
return HAL_OK;
}

2
STM32/Core/Src/wm8731.h
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@ -23,8 +23,6 @@ extern bool WM8731_Muting; //Muting flag
extern void WM8731_Init(void); //I2C audio codec initialization
extern void WM8731_start_i2s_and_dma(void); //I2S bus start
extern void WM8731_CleanBuffer(void); //clear the audio codec and USB audio buffer
extern void WM8731_TX_mode(void); //switch to TX mode (mute the speaker, etc.)
extern void WM8731_RX_mode(void); //switching to RX mode (mute the microphone, etc.)
extern void WM8731_TXRX_mode(void); //switch to mixed mode RX-TX (for LOOP)
extern void WM8731_Mute(void); //mute audio out
extern void WM8731_UnMute(void); //disable audio mute

2
STM32/MDK-ARM/WOLF-Lite.uvoptx
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@ -223,7 +223,7 @@
<Group>
<GroupName>Application/User/Core</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>

2
STM32/MDK-ARM/WOLF-Lite.uvprojx
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@ -327,7 +327,7 @@
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<useXO>1</useXO>
<v6Lang>3</v6Lang>
<v6LangP>3</v6LangP>
<vShortEn>1</vShortEn>