diff --git a/FPGA/.qsys_edit/rx_cic_schematic.nlv b/FPGA/.qsys_edit/rx_cic_schematic.nlv
index b586029..a30582a 100644
--- a/FPGA/.qsys_edit/rx_cic_schematic.nlv
+++ b/FPGA/.qsys_edit/rx_cic_schematic.nlv
@@ -3,9 +3,8 @@
preplace inst rx_cic -pg 1 -lvl 1 -y 40 -regy -20
preplace inst rx_cic.cic_ii_0 -pg 1 -lvl 1 -y 30
preplace netloc EXPORTrx_cic(SLAVE)rx_cic.reset,(SLAVE)cic_ii_0.reset) 1 0 1 NJ
-preplace netloc EXPORTrx_cic(SLAVE)cic_ii_0.clock,(SLAVE)rx_cic.clock) 1 0 1 NJ
-preplace netloc EXPORTrx_cic(SLAVE)cic_ii_0.clken,(SLAVE)rx_cic.clken) 1 0 1 NJ
-preplace netloc EXPORTrx_cic(SLAVE)cic_ii_0.av_st_out,(SLAVE)rx_cic.av_st_out) 1 0 1 NJ
+preplace netloc EXPORTrx_cic(SLAVE)rx_cic.clock,(SLAVE)cic_ii_0.clock) 1 0 1 NJ
preplace netloc EXPORTrx_cic(SLAVE)rx_cic.av_st_in,(SLAVE)cic_ii_0.av_st_in) 1 0 1 NJ
+preplace netloc EXPORTrx_cic(SLAVE)rx_cic.av_st_out,(SLAVE)cic_ii_0.av_st_out) 1 0 1 NJ
levelinfo -pg 1 0 70 210
levelinfo -hier rx_cic 80 110 200
diff --git a/FPGA/DEBUG.sopcinfo b/FPGA/DEBUG.sopcinfo
index c9f55cc..4b53b7f 100644
--- a/FPGA/DEBUG.sopcinfo
+++ b/FPGA/DEBUG.sopcinfo
@@ -1,11 +1,11 @@
-
+
java.lang.Integer
- 1612209581
+ 1613135608
false
true
false
diff --git a/FPGA/DEBUG2.sopcinfo b/FPGA/DEBUG2.sopcinfo
index dcd9945..3e77056 100644
--- a/FPGA/DEBUG2.sopcinfo
+++ b/FPGA/DEBUG2.sopcinfo
@@ -1,11 +1,11 @@
-
+
java.lang.Integer
- 1612209592
+ 1613135620
false
true
false
diff --git a/FPGA/WOLF-LITE.bdf b/FPGA/WOLF-LITE.bdf
index aa3c9d2..cf6cd0e 100644
--- a/FPGA/WOLF-LITE.bdf
+++ b/FPGA/WOLF-LITE.bdf
@@ -89,7 +89,7 @@ refer to the applicable agreement for further details.
)
(pin
(input)
- (rect 136 -24 312 -8)
+ (rect -56 -56 120 -40)
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
(text "ADC_INPUT[11..0]" (rect 9 0 103 12)(font "Arial" ))
(pt 176 8)
@@ -102,7 +102,7 @@ refer to the applicable agreement for further details.
(line (pt 117 12)(pt 121 8))
)
(text "GND" (rect 136 7 157 17)(font "Arial" (font_size 6)))
- (annotation_block (location)(rect 80 -8 136 16))
+ (annotation_block (location)(rect -112 -40 -56 -16))
)
(pin
(input)
@@ -1928,95 +1928,6 @@ refer to the applicable agreement for further details.
)
(annotation_block (parameter)(rect 3088 96 3296 136))
)
-(symbol
- (rect 2248 160 2552 304)
- (text "data_shifter" (rect 5 0 64 12)(font "Arial" ))
- (text "RX_CICFIR_GAINER" (rect 8 128 115 140)(font "Arial" ))
- (port
- (pt 0 32)
- (input)
- (text "data_in_I[in_width-1..0]" (rect 0 0 113 12)(font "Arial" ))
- (text "data_in_I[in_width-1..0]" (rect 21 27 134 39)(font "Arial" ))
- (line (pt 0 32)(pt 16 32)(line_width 3))
- )
- (port
- (pt 0 48)
- (input)
- (text "data_valid_I" (rect 0 0 60 12)(font "Arial" ))
- (text "data_valid_I" (rect 21 43 81 55)(font "Arial" ))
- (line (pt 0 48)(pt 16 48))
- )
- (port
- (pt 0 64)
- (input)
- (text "data_in_Q[in_width-1..0]" (rect 0 0 118 12)(font "Arial" ))
- (text "data_in_Q[in_width-1..0]" (rect 21 59 139 71)(font "Arial" ))
- (line (pt 0 64)(pt 16 64)(line_width 3))
- )
- (port
- (pt 0 80)
- (input)
- (text "data_valid_Q" (rect 0 0 64 12)(font "Arial" ))
- (text "data_valid_Q" (rect 21 75 85 87)(font "Arial" ))
- (line (pt 0 80)(pt 16 80))
- )
- (port
- (pt 0 96)
- (input)
- (text "distance[7..0]" (rect 0 0 67 12)(font "Arial" ))
- (text "distance[7..0]" (rect 21 91 88 103)(font "Arial" ))
- (line (pt 0 96)(pt 16 96)(line_width 3))
- )
- (port
- (pt 0 112)
- (input)
- (text "enabled" (rect 0 0 37 12)(font "Arial" ))
- (text "enabled" (rect 21 107 58 119)(font "Arial" ))
- (line (pt 0 112)(pt 16 112))
- )
- (port
- (pt 304 32)
- (output)
- (text "data_out_I[out_width-1..0]" (rect 0 0 127 12)(font "Arial" ))
- (text "data_out_I[out_width-1..0]" (rect 176 27 303 39)(font "Arial" ))
- (line (pt 304 32)(pt 288 32)(line_width 3))
- )
- (port
- (pt 304 48)
- (output)
- (text "data_valid_out_I" (rect 0 0 81 12)(font "Arial" ))
- (text "data_valid_out_I" (rect 215 43 296 55)(font "Arial" ))
- (line (pt 304 48)(pt 288 48))
- )
- (port
- (pt 304 64)
- (output)
- (text "data_out_Q[out_width-1..0]" (rect 0 0 132 12)(font "Arial" ))
- (text "data_out_Q[out_width-1..0]" (rect 172 59 304 71)(font "Arial" ))
- (line (pt 304 64)(pt 288 64)(line_width 3))
- )
- (port
- (pt 304 80)
- (output)
- (text "data_valid_out_Q" (rect 0 0 86 12)(font "Arial" ))
- (text "data_valid_out_Q" (rect 211 75 297 87)(font "Arial" ))
- (line (pt 304 80)(pt 288 80))
- )
- (parameter
- "in_width"
- "30"
- ""
- (type "PARAMETER_SIGNED_DEC") )
- (parameter
- "out_width"
- "16"
- ""
- (type "PARAMETER_SIGNED_DEC") )
- (drawing
- (rectangle (rect 16 16 288 128))
- )
- (annotation_block (parameter)(rect 2288 96 2458 153))
-)
(symbol
(rect 3080 944 3320 1112)
(text "MAIN_PLL" (rect 89 0 162 16)(font "Arial" (font_size 10)))
@@ -2399,6 +2310,62 @@ refer to the applicable agreement for further details.
(line (pt 0 0)(pt 0 216))
)
)
+(symbol
+ (rect 160 -88 320 24)
+ (text "ADC_Latch" (rect 48 0 125 16)(font "Arial" (font_size 10)))
+ (text "ADC_Latch" (rect 8 96 61 113)(font "Intel Clear" ))
+ (port
+ (pt 0 40)
+ (input)
+ (text "dataa[11..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+ (text "dataa[11..0]" (rect 4 26 71 40)(font "Arial" (font_size 8)))
+ (line (pt 0 40)(pt 64 40)(line_width 3))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "datab[11..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+ (text "datab[11..0]" (rect 4 58 71 72)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 64 72)(line_width 3))
+ )
+ (port
+ (pt 0 96)
+ (input)
+ (text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+ (text "clken" (rect 4 82 33 96)(font "Arial" (font_size 8)))
+ (line (pt 0 96)(pt 80 96))
+ )
+ (port
+ (pt 0 56)
+ (input)
+ (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+ (text "clock" (rect 4 42 33 56)(font "Arial" (font_size 8)))
+ (line (pt 0 56)(pt 64 56))
+ )
+ (port
+ (pt 160 56)
+ (output)
+ (text "result[11..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+ (text "result[11..0]" (rect 101 42 168 56)(font "Arial" (font_size 8)))
+ (line (pt 160 56)(pt 96 56)(line_width 3))
+ )
+ (drawing
+ (text "A+B" (rect 75 51 99 65)(font "Arial" (font_size 8)))
+ (text "A" (rect 64 35 73 49)(font "Arial" (font_size 8)))
+ (text "B" (rect 65 67 73 81)(font "Arial" (font_size 8)))
+ (line (pt 64 32)(pt 64 80))
+ (line (pt 64 32)(pt 96 40))
+ (line (pt 64 80)(pt 96 72))
+ (line (pt 96 40)(pt 96 72))
+ (line (pt 80 76)(pt 80 96))
+ (line (pt 0 0)(pt 162 0))
+ (line (pt 162 0)(pt 162 114))
+ (line (pt 0 114)(pt 162 114))
+ (line (pt 0 0)(pt 0 114))
+ (line (pt 64 50)(pt 70 56))
+ (line (pt 70 56)(pt 64 62))
+ )
+)
(symbol
(rect 896 -8 1152 264)
(text "rx_cic" (rect 110 -1 151 15)(font "Arial" (font_size 10)))
@@ -2462,8 +2429,8 @@ refer to the applicable agreement for further details.
(port
(pt 256 72)
(output)
- (text "out_data[85..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
- (text "out_data[85..0]" (rect 181 61 252 75)(font "Arial" (font_size 8)))
+ (text "out_data[31..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
+ (text "out_data[31..0]" (rect 183 61 254 75)(font "Arial" (font_size 8)))
(line (pt 256 72)(pt 176 72)(line_width 3))
)
(port
@@ -2581,8 +2548,8 @@ refer to the applicable agreement for further details.
(port
(pt 256 72)
(output)
- (text "out_data[85..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
- (text "out_data[85..0]" (rect 181 61 252 75)(font "Arial" (font_size 8)))
+ (text "out_data[31..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
+ (text "out_data[31..0]" (rect 183 61 254 75)(font "Arial" (font_size 8)))
(line (pt 256 72)(pt 176 72)(line_width 3))
)
(port
@@ -2638,9 +2605,193 @@ refer to the applicable agreement for further details.
)
)
(symbol
- (rect 1296 208 1600 352)
+ (rect 1768 8 2152 224)
+ (text "rx_ciccomp" (rect 158 -1 237 15)(font "Arial" (font_size 10)))
+ (text "RX_CICCOMP_I" (rect 8 200 89 212)(font "Arial" ))
+ (port
+ (pt 0 72)
+ (input)
+ (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "clk" (rect 4 61 19 75)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 144 72))
+ )
+ (port
+ (pt 0 112)
+ (input)
+ (text "reset_n" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+ (text "reset_n" (rect 4 101 47 115)(font "Arial" (font_size 8)))
+ (line (pt 0 112)(pt 144 112))
+ )
+ (port
+ (pt 0 152)
+ (input)
+ (text "ast_sink_data[31..0]" (rect 0 0 114 14)(font "Arial" (font_size 8)))
+ (text "ast_sink_data[31..0]" (rect 4 141 118 155)(font "Arial" (font_size 8)))
+ (line (pt 0 152)(pt 144 152)(line_width 3))
+ )
+ (port
+ (pt 0 168)
+ (input)
+ (text "ast_sink_valid" (rect 0 0 80 14)(font "Arial" (font_size 8)))
+ (text "ast_sink_valid" (rect 4 157 84 171)(font "Arial" (font_size 8)))
+ (line (pt 0 168)(pt 144 168))
+ )
+ (port
+ (pt 0 184)
+ (input)
+ (text "ast_sink_error[1..0]" (rect 0 0 110 14)(font "Arial" (font_size 8)))
+ (text "ast_sink_error[1..0]" (rect 4 173 114 187)(font "Arial" (font_size 8)))
+ (line (pt 0 184)(pt 144 184)(line_width 3))
+ )
+ (port
+ (pt 384 72)
+ (output)
+ (text "ast_source_data[45..0]" (rect 0 0 132 14)(font "Arial" (font_size 8)))
+ (text "ast_source_data[45..0]" (rect 268 61 379 75)(font "Arial" (font_size 8)))
+ (line (pt 384 72)(pt 224 72)(line_width 3))
+ )
+ (port
+ (pt 384 88)
+ (output)
+ (text "ast_source_valid" (rect 0 0 97 14)(font "Arial" (font_size 8)))
+ (text "ast_source_valid" (rect 297 77 379 91)(font "Arial" (font_size 8)))
+ (line (pt 384 88)(pt 224 88))
+ )
+ (port
+ (pt 384 104)
+ (output)
+ (text "ast_source_error[1..0]" (rect 0 0 128 14)(font "Arial" (font_size 8)))
+ (text "ast_source_error[1..0]" (rect 273 93 381 107)(font "Arial" (font_size 8)))
+ (line (pt 384 104)(pt 224 104)(line_width 3))
+ )
+ (drawing
+ (text "clk" (rect 129 43 146 58)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "clk" (rect 149 67 163 79)(font "Arial" (color 0 0 0)))
+ (text "rst" (rect 129 83 145 98)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "reset_n" (rect 149 107 185 119)(font "Arial" (color 0 0 0)))
+ (text "avalon_streaming_sink" (rect 10 123 162 138)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "data" (rect 149 147 170 159)(font "Arial" (color 0 0 0)))
+ (text "valid" (rect 149 163 172 175)(font "Arial" (color 0 0 0)))
+ (text "error" (rect 149 179 171 191)(font "Arial" (color 0 0 0)))
+ (text "avalon_streaming_source" (rect 225 43 394 58)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "data" (rect 203 67 224 79)(font "Arial" (color 0 0 0)))
+ (text "valid" (rect 201 83 224 95)(font "Arial" (color 0 0 0)))
+ (text "error" (rect 199 99 221 111)(font "Arial" (color 0 0 0)))
+ (text " altera_fir_compiler_ii " (rect 289 200 397 212)(font "Arial" ))
+ (line (pt 144 32)(pt 224 32))
+ (line (pt 224 32)(pt 224 200))
+ (line (pt 144 200)(pt 224 200))
+ (line (pt 144 32)(pt 144 200))
+ (line (pt 145 52)(pt 145 76))
+ (line (pt 146 52)(pt 146 76))
+ (line (pt 145 92)(pt 145 116))
+ (line (pt 146 92)(pt 146 116))
+ (line (pt 145 132)(pt 145 188))
+ (line (pt 146 132)(pt 146 188))
+ (line (pt 223 52)(pt 223 108))
+ (line (pt 222 52)(pt 222 108))
+ (line (pt 0 0)(pt 384 0))
+ (line (pt 384 0)(pt 384 216))
+ (line (pt 0 216)(pt 384 216))
+ (line (pt 0 0)(pt 0 216))
+ )
+)
+(symbol
+ (rect 1768 240 2152 456)
+ (text "rx_ciccomp" (rect 158 -1 237 15)(font "Arial" (font_size 10)))
+ (text "RX_CICOMP_Q" (rect 8 200 85 212)(font "Arial" ))
+ (port
+ (pt 0 72)
+ (input)
+ (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "clk" (rect 4 61 19 75)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 144 72))
+ )
+ (port
+ (pt 0 112)
+ (input)
+ (text "reset_n" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+ (text "reset_n" (rect 4 101 47 115)(font "Arial" (font_size 8)))
+ (line (pt 0 112)(pt 144 112))
+ )
+ (port
+ (pt 0 152)
+ (input)
+ (text "ast_sink_data[31..0]" (rect 0 0 114 14)(font "Arial" (font_size 8)))
+ (text "ast_sink_data[31..0]" (rect 4 141 118 155)(font "Arial" (font_size 8)))
+ (line (pt 0 152)(pt 144 152)(line_width 3))
+ )
+ (port
+ (pt 0 168)
+ (input)
+ (text "ast_sink_valid" (rect 0 0 80 14)(font "Arial" (font_size 8)))
+ (text "ast_sink_valid" (rect 4 157 84 171)(font "Arial" (font_size 8)))
+ (line (pt 0 168)(pt 144 168))
+ )
+ (port
+ (pt 0 184)
+ (input)
+ (text "ast_sink_error[1..0]" (rect 0 0 110 14)(font "Arial" (font_size 8)))
+ (text "ast_sink_error[1..0]" (rect 4 173 114 187)(font "Arial" (font_size 8)))
+ (line (pt 0 184)(pt 144 184)(line_width 3))
+ )
+ (port
+ (pt 384 72)
+ (output)
+ (text "ast_source_data[45..0]" (rect 0 0 132 14)(font "Arial" (font_size 8)))
+ (text "ast_source_data[45..0]" (rect 268 61 379 75)(font "Arial" (font_size 8)))
+ (line (pt 384 72)(pt 224 72)(line_width 3))
+ )
+ (port
+ (pt 384 88)
+ (output)
+ (text "ast_source_valid" (rect 0 0 97 14)(font "Arial" (font_size 8)))
+ (text "ast_source_valid" (rect 297 77 379 91)(font "Arial" (font_size 8)))
+ (line (pt 384 88)(pt 224 88))
+ )
+ (port
+ (pt 384 104)
+ (output)
+ (text "ast_source_error[1..0]" (rect 0 0 128 14)(font "Arial" (font_size 8)))
+ (text "ast_source_error[1..0]" (rect 273 93 381 107)(font "Arial" (font_size 8)))
+ (line (pt 384 104)(pt 224 104)(line_width 3))
+ )
+ (drawing
+ (text "clk" (rect 129 43 146 58)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "clk" (rect 149 67 163 79)(font "Arial" (color 0 0 0)))
+ (text "rst" (rect 129 83 145 98)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "reset_n" (rect 149 107 185 119)(font "Arial" (color 0 0 0)))
+ (text "avalon_streaming_sink" (rect 10 123 162 138)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "data" (rect 149 147 170 159)(font "Arial" (color 0 0 0)))
+ (text "valid" (rect 149 163 172 175)(font "Arial" (color 0 0 0)))
+ (text "error" (rect 149 179 171 191)(font "Arial" (color 0 0 0)))
+ (text "avalon_streaming_source" (rect 225 43 394 58)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "data" (rect 203 67 224 79)(font "Arial" (color 0 0 0)))
+ (text "valid" (rect 201 83 224 95)(font "Arial" (color 0 0 0)))
+ (text "error" (rect 199 99 221 111)(font "Arial" (color 0 0 0)))
+ (text " altera_fir_compiler_ii " (rect 289 200 397 212)(font "Arial" ))
+ (line (pt 144 32)(pt 224 32))
+ (line (pt 224 32)(pt 224 200))
+ (line (pt 144 200)(pt 224 200))
+ (line (pt 144 32)(pt 144 200))
+ (line (pt 145 52)(pt 145 76))
+ (line (pt 146 52)(pt 146 76))
+ (line (pt 145 92)(pt 145 116))
+ (line (pt 146 92)(pt 146 116))
+ (line (pt 145 132)(pt 145 188))
+ (line (pt 146 132)(pt 146 188))
+ (line (pt 223 52)(pt 223 108))
+ (line (pt 222 52)(pt 222 108))
+ (line (pt 0 0)(pt 384 0))
+ (line (pt 384 0)(pt 384 216))
+ (line (pt 0 216)(pt 384 216))
+ (line (pt 0 0)(pt 0 216))
+ )
+)
+(symbol
+ (rect 2248 160 2552 304)
(text "data_shifter" (rect 5 0 64 12)(font "Arial" ))
- (text "CIC_GAINER" (rect 8 128 67 145)(font "Intel Clear" ))
+ (text "RX_CICFIR_GAINER" (rect 8 128 115 140)(font "Arial" ))
(port
(pt 0 32)
(input)
@@ -2713,7 +2864,7 @@ refer to the applicable agreement for further details.
)
(parameter
"in_width"
- "86"
+ "46"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
@@ -2724,191 +2875,7 @@ refer to the applicable agreement for further details.
(drawing
(rectangle (rect 16 16 288 128))
)
- (annotation_block (parameter)(rect 1352 72 1522 129))
-)
-(symbol
- (rect 1768 8 2152 224)
- (text "rx_ciccomp" (rect 158 -1 237 15)(font "Arial" (font_size 10)))
- (text "RX_CICCOMP_I" (rect 8 200 89 212)(font "Arial" ))
- (port
- (pt 0 72)
- (input)
- (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
- (text "clk" (rect 4 61 19 75)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72))
- )
- (port
- (pt 0 112)
- (input)
- (text "reset_n" (rect 0 0 43 14)(font "Arial" (font_size 8)))
- (text "reset_n" (rect 4 101 47 115)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112))
- )
- (port
- (pt 0 152)
- (input)
- (text "ast_sink_data[15..0]" (rect 0 0 114 14)(font "Arial" (font_size 8)))
- (text "ast_sink_data[15..0]" (rect 4 141 118 155)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "ast_sink_valid" (rect 0 0 80 14)(font "Arial" (font_size 8)))
- (text "ast_sink_valid" (rect 4 157 84 171)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168))
- )
- (port
- (pt 0 184)
- (input)
- (text "ast_sink_error[1..0]" (rect 0 0 110 14)(font "Arial" (font_size 8)))
- (text "ast_sink_error[1..0]" (rect 4 173 114 187)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 384 72)
- (output)
- (text "ast_source_data[29..0]" (rect 0 0 132 14)(font "Arial" (font_size 8)))
- (text "ast_source_data[29..0]" (rect 268 61 379 75)(font "Arial" (font_size 8)))
- (line (pt 384 72)(pt 224 72)(line_width 3))
- )
- (port
- (pt 384 88)
- (output)
- (text "ast_source_valid" (rect 0 0 97 14)(font "Arial" (font_size 8)))
- (text "ast_source_valid" (rect 297 77 379 91)(font "Arial" (font_size 8)))
- (line (pt 384 88)(pt 224 88))
- )
- (port
- (pt 384 104)
- (output)
- (text "ast_source_error[1..0]" (rect 0 0 128 14)(font "Arial" (font_size 8)))
- (text "ast_source_error[1..0]" (rect 273 93 381 107)(font "Arial" (font_size 8)))
- (line (pt 384 104)(pt 224 104)(line_width 3))
- )
- (drawing
- (text "clk" (rect 129 43 146 58)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 67 163 79)(font "Arial" (color 0 0 0)))
- (text "rst" (rect 129 83 145 98)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset_n" (rect 149 107 185 119)(font "Arial" (color 0 0 0)))
- (text "avalon_streaming_sink" (rect 10 123 162 138)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "data" (rect 149 147 170 159)(font "Arial" (color 0 0 0)))
- (text "valid" (rect 149 163 172 175)(font "Arial" (color 0 0 0)))
- (text "error" (rect 149 179 171 191)(font "Arial" (color 0 0 0)))
- (text "avalon_streaming_source" (rect 225 43 394 58)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "data" (rect 203 67 224 79)(font "Arial" (color 0 0 0)))
- (text "valid" (rect 201 83 224 95)(font "Arial" (color 0 0 0)))
- (text "error" (rect 199 99 221 111)(font "Arial" (color 0 0 0)))
- (text " altera_fir_compiler_ii " (rect 289 200 397 212)(font "Arial" ))
- (line (pt 144 32)(pt 224 32))
- (line (pt 224 32)(pt 224 200))
- (line (pt 144 200)(pt 224 200))
- (line (pt 144 32)(pt 144 200))
- (line (pt 145 52)(pt 145 76))
- (line (pt 146 52)(pt 146 76))
- (line (pt 145 92)(pt 145 116))
- (line (pt 146 92)(pt 146 116))
- (line (pt 145 132)(pt 145 188))
- (line (pt 146 132)(pt 146 188))
- (line (pt 223 52)(pt 223 108))
- (line (pt 222 52)(pt 222 108))
- (line (pt 0 0)(pt 384 0))
- (line (pt 384 0)(pt 384 216))
- (line (pt 0 216)(pt 384 216))
- (line (pt 0 0)(pt 0 216))
- )
-)
-(symbol
- (rect 1768 240 2152 456)
- (text "rx_ciccomp" (rect 158 -1 237 15)(font "Arial" (font_size 10)))
- (text "RX_CICOMP_Q" (rect 8 200 85 212)(font "Arial" ))
- (port
- (pt 0 72)
- (input)
- (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
- (text "clk" (rect 4 61 19 75)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72))
- )
- (port
- (pt 0 112)
- (input)
- (text "reset_n" (rect 0 0 43 14)(font "Arial" (font_size 8)))
- (text "reset_n" (rect 4 101 47 115)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112))
- )
- (port
- (pt 0 152)
- (input)
- (text "ast_sink_data[15..0]" (rect 0 0 114 14)(font "Arial" (font_size 8)))
- (text "ast_sink_data[15..0]" (rect 4 141 118 155)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "ast_sink_valid" (rect 0 0 80 14)(font "Arial" (font_size 8)))
- (text "ast_sink_valid" (rect 4 157 84 171)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168))
- )
- (port
- (pt 0 184)
- (input)
- (text "ast_sink_error[1..0]" (rect 0 0 110 14)(font "Arial" (font_size 8)))
- (text "ast_sink_error[1..0]" (rect 4 173 114 187)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 384 72)
- (output)
- (text "ast_source_data[29..0]" (rect 0 0 132 14)(font "Arial" (font_size 8)))
- (text "ast_source_data[29..0]" (rect 268 61 379 75)(font "Arial" (font_size 8)))
- (line (pt 384 72)(pt 224 72)(line_width 3))
- )
- (port
- (pt 384 88)
- (output)
- (text "ast_source_valid" (rect 0 0 97 14)(font "Arial" (font_size 8)))
- (text "ast_source_valid" (rect 297 77 379 91)(font "Arial" (font_size 8)))
- (line (pt 384 88)(pt 224 88))
- )
- (port
- (pt 384 104)
- (output)
- (text "ast_source_error[1..0]" (rect 0 0 128 14)(font "Arial" (font_size 8)))
- (text "ast_source_error[1..0]" (rect 273 93 381 107)(font "Arial" (font_size 8)))
- (line (pt 384 104)(pt 224 104)(line_width 3))
- )
- (drawing
- (text "clk" (rect 129 43 146 58)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 67 163 79)(font "Arial" (color 0 0 0)))
- (text "rst" (rect 129 83 145 98)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset_n" (rect 149 107 185 119)(font "Arial" (color 0 0 0)))
- (text "avalon_streaming_sink" (rect 10 123 162 138)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "data" (rect 149 147 170 159)(font "Arial" (color 0 0 0)))
- (text "valid" (rect 149 163 172 175)(font "Arial" (color 0 0 0)))
- (text "error" (rect 149 179 171 191)(font "Arial" (color 0 0 0)))
- (text "avalon_streaming_source" (rect 225 43 394 58)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "data" (rect 203 67 224 79)(font "Arial" (color 0 0 0)))
- (text "valid" (rect 201 83 224 95)(font "Arial" (color 0 0 0)))
- (text "error" (rect 199 99 221 111)(font "Arial" (color 0 0 0)))
- (text " altera_fir_compiler_ii " (rect 289 200 397 212)(font "Arial" ))
- (line (pt 144 32)(pt 224 32))
- (line (pt 224 32)(pt 224 200))
- (line (pt 144 200)(pt 224 200))
- (line (pt 144 32)(pt 144 200))
- (line (pt 145 52)(pt 145 76))
- (line (pt 146 52)(pt 146 76))
- (line (pt 145 92)(pt 145 116))
- (line (pt 146 92)(pt 146 116))
- (line (pt 145 132)(pt 145 188))
- (line (pt 146 132)(pt 146 188))
- (line (pt 223 52)(pt 223 108))
- (line (pt 222 52)(pt 222 108))
- (line (pt 0 0)(pt 384 0))
- (line (pt 384 0)(pt 384 216))
- (line (pt 0 216)(pt 384 216))
- (line (pt 0 0)(pt 0 216))
- )
+ (annotation_block (parameter)(rect 2288 96 2458 153))
)
(connector
(pt 528 32)
@@ -2961,31 +2928,11 @@ refer to the applicable agreement for further details.
(pt 1152 96)
(pt 1200 96)
)
-(connector
- (pt 1152 80)
- (pt 1208 80)
- (bus)
-)
-(connector
- (pt 1208 80)
- (pt 1208 192)
- (bus)
-)
-(connector
- (pt 1208 192)
- (pt 1768 192)
- (bus)
-)
(connector
(pt 1208 424)
(pt 1768 424)
(bus)
)
-(connector
- (pt 1696 392)
- (pt 1768 392)
- (bus)
-)
(connector
(pt 1728 80)
(pt 1768 80)
@@ -3598,10 +3545,6 @@ refer to the applicable agreement for further details.
(pt 5272 320)
(bus)
)
-(connector
- (pt 376 120)
- (pt 776 120)
-)
(connector
(pt 3736 608)
(pt 3952 608)
@@ -4183,139 +4126,15 @@ refer to the applicable agreement for further details.
(pt 520 -104)
(bus)
)
-(connector
- (pt 312 -16)
- (pt 440 -16)
- (bus)
-)
-(connector
- (pt 440 -104)
- (pt 440 -16)
- (bus)
-)
-(connector
- (pt 440 -16)
- (pt 440 32)
- (bus)
-)
(connector
(pt 2392 696)
(pt 2416 696)
)
-(connector
- (pt 1672 160)
- (pt 1768 160)
- (bus)
-)
-(connector
- (pt 1240 240)
- (pt 1240 64)
- (bus)
-)
-(connector
- (pt 1240 240)
- (pt 1296 240)
- (bus)
-)
(connector
(pt 1240 344)
(pt 1152 344)
(bus)
)
-(connector
- (pt 1240 344)
- (pt 1240 272)
- (bus)
-)
-(connector
- (pt 1240 272)
- (pt 1296 272)
- (bus)
-)
-(connector
- (pt 1152 376)
- (pt 1248 376)
-)
-(connector
- (pt 1248 376)
- (pt 1248 288)
-)
-(connector
- (pt 1248 288)
- (pt 1296 288)
-)
-(connector
- (pt 1200 256)
- (pt 1200 96)
-)
-(connector
- (pt 1200 256)
- (pt 1296 256)
-)
-(connector
- (pt 1696 272)
- (pt 1600 272)
- (bus)
-)
-(connector
- (pt 1696 272)
- (pt 1696 392)
- (bus)
-)
-(connector
- (pt 1600 240)
- (pt 1672 240)
- (bus)
-)
-(connector
- (pt 1672 160)
- (pt 1672 240)
- (bus)
-)
-(connector
- (pt 1768 176)
- (pt 1688 176)
-)
-(connector
- (pt 1688 176)
- (pt 1688 256)
-)
-(connector
- (pt 1688 256)
- (pt 1600 256)
-)
-(connector
- (pt 1768 408)
- (pt 1680 408)
-)
-(connector
- (pt 1680 408)
- (pt 1680 288)
-)
-(connector
- (pt 1680 288)
- (pt 1600 288)
-)
-(connector
- (pt 1296 320)
- (pt 1288 320)
-)
-(connector
- (pt 1296 304)
- (pt 1272 304)
- (bus)
-)
-(connector
- (text "RX" (rect 1288 370 1305 384)(font "Intel Clear" )(vertical))
- (pt 1288 320)
- (pt 1288 392)
-)
-(connector
- (text "CIC_GAIN[7..0]" (rect 1248 323 1265 392)(font "Intel Clear" )(vertical))
- (pt 1272 304)
- (pt 1272 392)
- (bus)
-)
(connector
(pt 2552 240)
(pt 2568 240)
@@ -4348,6 +4167,102 @@ refer to the applicable agreement for further details.
(pt 3088 192)
(bus)
)
+(connector
+ (pt 160 -48)
+ (pt 120 -48)
+ (bus)
+)
+(connector
+ (pt 160 -32)
+ (pt 128 -32)
+)
+(connector
+ (pt 128 120)
+ (pt 128 -32)
+)
+(connector
+ (pt 128 120)
+ (pt 376 120)
+)
+(connector
+ (pt 376 120)
+ (pt 776 120)
+)
+(connector
+ (text "RX" (rect 66 -8 80 9)(font "Intel Clear" ))
+ (pt 160 8)
+ (pt 56 8)
+)
+(connector
+ (pt 320 -32)
+ (pt 440 -32)
+ (bus)
+)
+(connector
+ (pt 440 -104)
+ (pt 440 -32)
+ (bus)
+)
+(connector
+ (pt 440 -32)
+ (pt 440 32)
+ (bus)
+)
+(connector
+ (pt 1240 64)
+ (pt 1240 160)
+ (bus)
+)
+(connector
+ (pt 1240 160)
+ (pt 1768 160)
+ (bus)
+)
+(connector
+ (pt 1152 376)
+ (pt 1224 376)
+)
+(connector
+ (pt 1224 376)
+ (pt 1224 408)
+)
+(connector
+ (pt 1768 408)
+ (pt 1224 408)
+)
+(connector
+ (pt 1240 344)
+ (pt 1240 392)
+ (bus)
+)
+(connector
+ (pt 1240 392)
+ (pt 1768 392)
+ (bus)
+)
+(connector
+ (pt 1200 96)
+ (pt 1200 176)
+)
+(connector
+ (pt 1200 176)
+ (pt 1768 176)
+)
+(connector
+ (pt 1152 80)
+ (pt 1216 80)
+ (bus)
+)
+(connector
+ (pt 1216 80)
+ (pt 1216 192)
+ (bus)
+)
+(connector
+ (pt 1768 192)
+ (pt 1216 192)
+ (bus)
+)
(junction (pt 376 120))
(junction (pt 440 32))
(junction (pt 440 448))
@@ -4370,8 +4285,8 @@ refer to the applicable agreement for further details.
(junction (pt 5720 152))
(junction (pt 2744 560))
(junction (pt 2744 696))
-(junction (pt 440 -16))
(junction (pt 3888 432))
(junction (pt 3472 104))
(junction (pt 3048 904))
+(junction (pt 440 -32))
(text "160.8mhz" (rect 3328 760 3388 779)(font "Intel Clear" (font_size 8)))
diff --git a/FPGA/WOLF-LITE.qws b/FPGA/WOLF-LITE.qws
index 7e0a0b0..fa4defe 100644
Binary files a/FPGA/WOLF-LITE.qws and b/FPGA/WOLF-LITE.qws differ
diff --git a/FPGA/clock_buffer.sopcinfo b/FPGA/clock_buffer.sopcinfo
index c90f938..1cfa955 100644
--- a/FPGA/clock_buffer.sopcinfo
+++ b/FPGA/clock_buffer.sopcinfo
@@ -1,11 +1,11 @@
-
+
java.lang.Integer
- 1612209525
+ 1613135551
false
true
false
diff --git a/FPGA/db/WOLF-LITE.db_info b/FPGA/db/WOLF-LITE.db_info
index b97de35..4d2fa70 100644
--- a/FPGA/db/WOLF-LITE.db_info
+++ b/FPGA/db/WOLF-LITE.db_info
@@ -1,3 +1,3 @@
Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
Version_Index = 486699264
-Creation_Time = Mon Feb 01 22:43:24 2021
+Creation_Time = Fri Feb 12 16:12:07 2021
diff --git a/FPGA/nco.sopcinfo b/FPGA/nco.sopcinfo
index c8ed550..370b1b1 100644
--- a/FPGA/nco.sopcinfo
+++ b/FPGA/nco.sopcinfo
@@ -1,11 +1,11 @@
-
+
java.lang.Integer
- 1612209570
+ 1613135597
false
true
false
diff --git a/FPGA/rx_cic.qsys b/FPGA/rx_cic.qsys
index 9d94ebd..dc38509 100644
--- a/FPGA/rx_cic.qsys
+++ b/FPGA/rx_cic.qsys
@@ -81,9 +81,9 @@
-
+
-
+
diff --git a/FPGA/rx_cic.sopcinfo b/FPGA/rx_cic.sopcinfo
index 272390b..04700be 100644
--- a/FPGA/rx_cic.sopcinfo
+++ b/FPGA/rx_cic.sopcinfo
@@ -1,11 +1,11 @@
-
+
java.lang.Integer
- 1612209536
+ 1613135562
false
true
false
@@ -222,7 +222,7 @@ the requested settings for a module instance. -->
java.lang.String
- NONE
+ TRUNCATE
false
true
true
@@ -230,18 +230,18 @@ the requested settings for a module instance. -->
int
- 16
+ 32
false
true
- false
+ true
true
int
- 86
+ 32
true
false
- true
+ false
true
@@ -791,7 +791,7 @@ parameters are a RESULT of the module parameters. -->
out_data
Output
- 86
+ 32
out_data
diff --git a/FPGA/rx_cic/rx_cic.bsf b/FPGA/rx_cic/rx_cic.bsf
index e00c01c..881511c 100644
--- a/FPGA/rx_cic/rx_cic.bsf
+++ b/FPGA/rx_cic/rx_cic.bsf
@@ -82,8 +82,8 @@ refer to the applicable agreement for further details.
(port
(pt 256 72)
(output)
- (text "out_data[85..0]" (rect 0 0 59 12)(font "Arial" (font_size 8)))
- (text "out_data[85..0]" (rect 181 61 271 72)(font "Arial" (font_size 8)))
+ (text "out_data[31..0]" (rect 0 0 57 12)(font "Arial" (font_size 8)))
+ (text "out_data[31..0]" (rect 183 61 273 72)(font "Arial" (font_size 8)))
(line (pt 256 72)(pt 176 72)(line_width 3))
)
(port
diff --git a/FPGA/rx_cic/rx_cic.cmp b/FPGA/rx_cic/rx_cic.cmp
index 045b93e..7a64420 100644
--- a/FPGA/rx_cic/rx_cic.cmp
+++ b/FPGA/rx_cic/rx_cic.cmp
@@ -4,7 +4,7 @@
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(22 downto 0) := (others => 'X'); -- in_data
- out_data : out std_logic_vector(85 downto 0); -- out_data
+ out_data : out std_logic_vector(31 downto 0); -- out_data
out_error : out std_logic_vector(1 downto 0); -- error
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
diff --git a/FPGA/rx_cic/rx_cic.html b/FPGA/rx_cic/rx_cic.html
index 738e1e6..14dde16 100644
--- a/FPGA/rx_cic/rx_cic.html
+++ b/FPGA/rx_cic/rx_cic.html
@@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
- 2021.01.07.18:58:03 |
+ 2021.02.12.17:07:48 |
Datasheet |
@@ -166,15 +166,15 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
ROUND_TYPE |
- NONE |
+ TRUNCATE |
REQ_OUT_WIDTH |
- 16 |
+ 32 |
OUT_WIDTH |
- 86 |
+ 32 |
INT_USE_MEM |
diff --git a/FPGA/rx_cic/rx_cic.ppf b/FPGA/rx_cic/rx_cic.ppf
index 65b1c31..3267af5 100644
--- a/FPGA/rx_cic/rx_cic.ppf
+++ b/FPGA/rx_cic/rx_cic.ppf
@@ -12,7 +12,7 @@
-
+
diff --git a/FPGA/rx_cic/rx_cic.xml b/FPGA/rx_cic/rx_cic.xml
index 46aac8d..147c0be 100644
--- a/FPGA/rx_cic/rx_cic.xml
+++ b/FPGA/rx_cic/rx_cic.xml
@@ -1,7 +1,7 @@
+ date="2021.02.12.17:07:49"
+ outputDirectory="D:/Dropbox/Develop/Projects/Wolf-LITE/FPGA/rx_cic/">
-
+
@@ -86,7 +86,7 @@
-
+
-
+
-
+
@@ -270,7 +270,7 @@
-
+
@@ -278,7 +278,7 @@
-
+
@@ -312,119 +312,119 @@
diff --git a/FPGA/rx_cic/rx_cic_bb.v b/FPGA/rx_cic/rx_cic_bb.v
index fa4e809..bf76238 100644
--- a/FPGA/rx_cic/rx_cic_bb.v
+++ b/FPGA/rx_cic/rx_cic_bb.v
@@ -16,7 +16,7 @@ module rx_cic (
input in_valid;
output in_ready;
input [22:0] in_data;
- output [85:0] out_data;
+ output [31:0] out_data;
output [1:0] out_error;
output out_valid;
input out_ready;
diff --git a/FPGA/rx_cic/rx_cic_generation.rpt b/FPGA/rx_cic/rx_cic_generation.rpt
index c42010d..17955c1 100644
--- a/FPGA/rx_cic/rx_cic_generation.rpt
+++ b/FPGA/rx_cic/rx_cic_generation.rpt
@@ -1,5 +1,5 @@
Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\rx_cic.qsys --block-symbol-file --output-directory=D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\rx_cic --family="Cyclone IV E" --part=EP4CE10E22C8
+Info: qsys-generate D:\Dropbox\Develop\Projects\Wolf-LITE\FPGA\rx_cic.qsys --block-symbol-file --output-directory=D:\Dropbox\Develop\Projects\Wolf-LITE\FPGA\rx_cic --family="Cyclone IV E" --part=EP4CE10E22C8
Progress: Loading FPGA/rx_cic.qsys
Progress: Reading input file
Progress: Adding cic_ii_0 [altera_cic_ii 18.1]
@@ -13,7 +13,7 @@ Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\rx_cic.qsys --synthesis=VERILOG --output-directory=D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\rx_cic\synthesis --family="Cyclone IV E" --part=EP4CE10E22C8
+Info: qsys-generate D:\Dropbox\Develop\Projects\Wolf-LITE\FPGA\rx_cic.qsys --synthesis=VERILOG --output-directory=D:\Dropbox\Develop\Projects\Wolf-LITE\FPGA\rx_cic\synthesis --family="Cyclone IV E" --part=EP4CE10E22C8
Progress: Loading FPGA/rx_cic.qsys
Progress: Reading input file
Progress: Adding cic_ii_0 [altera_cic_ii 18.1]
diff --git a/FPGA/rx_cic/rx_cic_generation_previous.rpt b/FPGA/rx_cic/rx_cic_generation_previous.rpt
index c42010d..b2be827 100644
--- a/FPGA/rx_cic/rx_cic_generation_previous.rpt
+++ b/FPGA/rx_cic/rx_cic_generation_previous.rpt
@@ -1,5 +1,5 @@
Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\rx_cic.qsys --block-symbol-file --output-directory=D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\rx_cic --family="Cyclone IV E" --part=EP4CE10E22C8
+Info: qsys-generate D:\Dropbox\Develop\Projects\Wolf-LITE\FPGA\rx_cic.qsys --block-symbol-file --output-directory=D:\Dropbox\Develop\Projects\Wolf-LITE\FPGA\rx_cic --family="Cyclone IV E" --part=EP4CE10E22C8
Progress: Loading FPGA/rx_cic.qsys
Progress: Reading input file
Progress: Adding cic_ii_0 [altera_cic_ii 18.1]
@@ -8,12 +8,11 @@ Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
-Warning: rx_cic.cic_ii_0: Clock Enable Port is deprecated and may be removed in a future release
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\rx_cic.qsys --synthesis=VERILOG --output-directory=D:\Dropbox\Develop\Projects\WOLF-Lite\FPGA\rx_cic\synthesis --family="Cyclone IV E" --part=EP4CE10E22C8
+Info: qsys-generate D:\Dropbox\Develop\Projects\Wolf-LITE\FPGA\rx_cic.qsys --synthesis=VERILOG --output-directory=D:\Dropbox\Develop\Projects\Wolf-LITE\FPGA\rx_cic\synthesis --family="Cyclone IV E" --part=EP4CE10E22C8
Progress: Loading FPGA/rx_cic.qsys
Progress: Reading input file
Progress: Adding cic_ii_0 [altera_cic_ii 18.1]
@@ -22,7 +21,6 @@ Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
-Warning: rx_cic.cic_ii_0: Clock Enable Port is deprecated and may be removed in a future release
Info: rx_cic: Generating rx_cic "rx_cic" for QUARTUS_SYNTH
Info: cic_ii_0: "rx_cic" instantiated altera_cic_ii "cic_ii_0"
Info: rx_cic: Done "rx_cic" with 2 modules, 30 files
diff --git a/FPGA/rx_cic/rx_cic_inst.vhd b/FPGA/rx_cic/rx_cic_inst.vhd
index 3a1ec62..3d4e098 100644
--- a/FPGA/rx_cic/rx_cic_inst.vhd
+++ b/FPGA/rx_cic/rx_cic_inst.vhd
@@ -4,7 +4,7 @@
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(22 downto 0) := (others => 'X'); -- in_data
- out_data : out std_logic_vector(85 downto 0); -- out_data
+ out_data : out std_logic_vector(31 downto 0); -- out_data
out_error : out std_logic_vector(1 downto 0); -- error
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
diff --git a/FPGA/rx_cic/synthesis/rx_cic.debuginfo b/FPGA/rx_cic/synthesis/rx_cic.debuginfo
index 63caf7d..7dfdf9a 100644
--- a/FPGA/rx_cic/synthesis/rx_cic.debuginfo
+++ b/FPGA/rx_cic/synthesis/rx_cic.debuginfo
@@ -1,7 +1,7 @@
-
+
com.altera.sopcmodel.ensemble.EClockAdapter
@@ -53,7 +53,7 @@
int
- 1610031483
+ 1613135268
false
true
true
@@ -274,7 +274,7 @@ the requested settings for a module instance. -->
java.lang.String
- NONE
+ TRUNCATE
false
true
true
@@ -282,18 +282,18 @@ the requested settings for a module instance. -->
int
- 16
+ 32
false
true
- false
+ true
true
int
- 86
+ 32
true
false
- true
+ false
true
@@ -843,7 +843,7 @@ parameters are a RESULT of the module parameters. -->
out_data
Output
- 86
+ 32
out_data
@@ -899,5 +899,5 @@ parameters are a RESULT of the module parameters. -->
18.1
18.1 625
- 00FF10F684FA00000176DD5ACC0E
+ 00FF10F684FA00000177965ACE70
diff --git a/FPGA/rx_cic/synthesis/rx_cic.qip b/FPGA/rx_cic/synthesis/rx_cic.qip
index dfa289b..345ef35 100644
--- a/FPGA/rx_cic/synthesis/rx_cic.qip
+++ b/FPGA/rx_cic/synthesis/rx_cic.qip
@@ -2,7 +2,7 @@ set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_TOOL_NAME "Qsy
set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_TOOL_VERSION "18.1"
set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "rx_cic" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../rx_cic.sopcinfo"]
-set_global_assignment -entity "rx_cic" -library "rx_cic" -name SLD_INFO "QSYS_NAME rx_cic HAS_SOPCINFO 1 GENERATION_ID 1610031483"
+set_global_assignment -entity "rx_cic" -library "rx_cic" -name SLD_INFO "QSYS_NAME rx_cic HAS_SOPCINFO 1 GENERATION_ID 1613135268"
set_global_assignment -library "rx_cic" -name MISC_FILE [file join $::quartus(qip_path) "../rx_cic.cmp"]
set_global_assignment -library "rx_cic" -name SLD_FILE [file join $::quartus(qip_path) "rx_cic.debuginfo"]
set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E"
@@ -15,7 +15,7 @@ set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_DISP
set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYxMDAzMTQ4Mw==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYxMzEzNTI2OA==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMEUyMkM4::QXV0byBERVZJQ0U="
set_global_assignment -entity "rx_cic" -library "rx_cic" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@@ -42,8 +42,8 @@ set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPO
set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q0hfUEVSX0lOVA==::MQ==::TnVtYmVyIG9mIGNoYW5uZWxzIHBlciBpbnRlcmZhY2U="
set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SU5fV0lEVEg=::MjM=::SW5wdXQgZGF0YSB3aWR0aA=="
set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Q0xLX0VOX1BPUlQ=::dHJ1ZQ==::VXNlIGNsb2NrIGVuYWJsZSBwb3J0"
-set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Uk9VTkRfVFlQRQ==::Tk9ORQ==::T3V0cHV0IFJvdW5kaW5nIE1ldGhvZA=="
-set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "UkVRX09VVF9XSURUSA==::MTY=::T3V0cHV0IGRhdGEgd2lkdGg="
+set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "Uk9VTkRfVFlQRQ==::VFJVTkNBVEU=::T3V0cHV0IFJvdW5kaW5nIE1ldGhvZA=="
+set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "UkVRX09VVF9XSURUSA==::MzI=::T3V0cHV0IGRhdGEgd2lkdGg="
set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "SU5UX01FTQ==::YXV0bw==::SW50ZWdyYXRvciBkYXRhIHN0b3JhZ2UgdHlwZQ=="
set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "UkVRX0lOVF9NRU0=::bG9naWNfZWxlbWVudA==::SW50ZWdyYXRvciBkYXRhIHN0b3JhZ2UgdHlwZQ=="
set_global_assignment -entity "rx_cic_cic_ii_0" -library "rx_cic" -name IP_COMPONENT_PARAMETER "RElGX1VTRV9NRU0=::ZmFsc2U=::TWFwIGRpZmZlcmVudGlhdG9yIGRhdGEgc3RvcmFnZSB0byBtZW1vcnk="
diff --git a/FPGA/rx_cic/synthesis/rx_cic.v b/FPGA/rx_cic/synthesis/rx_cic.v
index 5633fdd..0751cff 100644
--- a/FPGA/rx_cic/synthesis/rx_cic.v
+++ b/FPGA/rx_cic/synthesis/rx_cic.v
@@ -8,7 +8,7 @@ module rx_cic (
input wire in_valid, // .valid
output wire in_ready, // .ready
input wire [22:0] in_data, // .in_data
- output wire [85:0] out_data, // av_st_out.out_data
+ output wire [31:0] out_data, // av_st_out.out_data
output wire [1:0] out_error, // .error
output wire out_valid, // .valid
input wire out_ready, // .ready
diff --git a/FPGA/rx_cic/synthesis/submodules/rx_cic_cic_ii_0.sv b/FPGA/rx_cic/synthesis/submodules/rx_cic_cic_ii_0.sv
index 14cc247..0adebcc 100644
--- a/FPGA/rx_cic/synthesis/submodules/rx_cic_cic_ii_0.sv
+++ b/FPGA/rx_cic/synthesis/submodules/rx_cic_cic_ii_0.sv
@@ -43,8 +43,8 @@ module rx_cic_cic_ii_0 (
parameter DIF_USE_MEM = "false";
parameter DIF_MEM = "auto";
parameter IN_WIDTH = 23;
- parameter OUT_WIDTH = 86;
- parameter ROUND_TYPE = "NONE";
+ parameter OUT_WIDTH = 32;
+ parameter ROUND_TYPE = "TRUNCATE";
parameter PIPELINING = 0;
diff --git a/FPGA/rx_ciccomp.bsf b/FPGA/rx_ciccomp.bsf
index d6e8ae5..82bd3ec 100644
--- a/FPGA/rx_ciccomp.bsf
+++ b/FPGA/rx_ciccomp.bsf
@@ -40,8 +40,8 @@ refer to the applicable agreement for further details.
(port
(pt 0 152)
(input)
- (text "ast_sink_data[15..0]" (rect 0 0 79 12)(font "Arial" (font_size 8)))
- (text "ast_sink_data[15..0]" (rect 4 141 124 152)(font "Arial" (font_size 8)))
+ (text "ast_sink_data[31..0]" (rect 0 0 79 12)(font "Arial" (font_size 8)))
+ (text "ast_sink_data[31..0]" (rect 4 141 124 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 144 152)(line_width 3))
)
(port
@@ -61,8 +61,8 @@ refer to the applicable agreement for further details.
(port
(pt 384 72)
(output)
- (text "ast_source_data[29..0]" (rect 0 0 92 12)(font "Arial" (font_size 8)))
- (text "ast_source_data[29..0]" (rect 268 61 400 72)(font "Arial" (font_size 8)))
+ (text "ast_source_data[45..0]" (rect 0 0 93 12)(font "Arial" (font_size 8)))
+ (text "ast_source_data[45..0]" (rect 268 61 400 72)(font "Arial" (font_size 8)))
(line (pt 384 72)(pt 224 72)(line_width 3))
)
(port
diff --git a/FPGA/rx_ciccomp.cmp b/FPGA/rx_ciccomp.cmp
index 1c10533..2708ed0 100644
--- a/FPGA/rx_ciccomp.cmp
+++ b/FPGA/rx_ciccomp.cmp
@@ -2,10 +2,10 @@
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
- ast_sink_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
+ ast_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
ast_sink_valid : in std_logic := 'X'; -- valid
ast_sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
- ast_source_data : out std_logic_vector(29 downto 0); -- data
+ ast_source_data : out std_logic_vector(45 downto 0); -- data
ast_source_valid : out std_logic; -- valid
ast_source_error : out std_logic_vector(1 downto 0) -- error
);
diff --git a/FPGA/rx_ciccomp.qip b/FPGA/rx_ciccomp.qip
index 4933044..a305534 100644
--- a/FPGA/rx_ciccomp.qip
+++ b/FPGA/rx_ciccomp.qip
@@ -23,7 +23,7 @@ set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_C
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "ZmlsdGVyVHlwZQ==::c2luZ2xl::RmlsdGVyIFR5cGU="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "aW50ZXJwRmFjdG9y::MQ==::SW50ZXJwb2xhdGlvbiBGYWN0b3I="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "ZGVjaW1GYWN0b3I=::MQ==::RGVjaW1hdGlvbiBGYWN0b3I="
-set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "c3ltbWV0cnlNb2Rl::c3lt::U3ltbWV0cnk="
+set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "c3ltbWV0cnlNb2Rl::bnN5bQ==::U3ltbWV0cnk="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "TF9iYW5kc0ZpbHRlcg==::MQ==::TC10aCBCYW5kIEZpbHRlcg=="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "aW5wdXRDaGFubmVsTnVt::MQ==::TWF4IE51bWJlciBvZiBDaGFubmVscw=="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y2xvY2tSYXRl::NjQuMzIw::Q2xvY2sgUmF0ZQ=="
@@ -48,7 +48,7 @@ set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_C
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "bW9kZUZvcm1hdHRlZA==::LS0=::bW9kZUZvcm1hdHRlZA=="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y2hhbm5lbE1vZGVz::MCwxLDIsMw==::Q2hhbm5lbCBNb2RlIE9yZGVy"
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "aW5wdXRUeXBl::aW50::SW5wdXQgVHlwZQ=="
-set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "aW5wdXRCaXRXaWR0aA==::MTY=::SW5wdXQgV2lkdGg="
+set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "aW5wdXRCaXRXaWR0aA==::MzI=::SW5wdXQgV2lkdGg="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRSZWFsVmFsdWU=::NjE2LjA1MDUsLTEyNTQuMzQ4LDIwNzMuNzQzLC0yOTg1LjgwNiwzNjQ0Ljk0MiwtMzIxMS4yMSwzLjM2NzcwOCw4OTM1LjA1NCwtMjg0MDQuNjksNjU2NTEuMzEsLTEzMTEyNS42LDIzOTEyMS44LC00MDg2NTQuMCw2NjM5MTMuNSwtMTAzNTIyOS4wLDE1NTkwODkuMCwtMjI3OTM2MS4wLDMyNDY2OTcuMCwtNDUyMDY2MS4wLDYxNjg1NTMuMCwtODI3MDA1My4wLDEuMDkxNTk1RTcsLTEuNDIxODc4RTcsMS44MzEyOUU3LC0yLjMzNzgyNEU3LDIuOTY0MzhFNywtMy43NDMzOTZFNyw0LjcxNTM1M0U3LC01LjkyNzAwMkU3LDcuMzczMjUzRTcsLTguNzMyODU1RTcsNy44MTQ5MjhFNyw3LjgxNDkyOEU3LC04LjczMjg1NUU3LDcuMzczMjUzRTcsLTUuOTI3MDAyRTcsNC43MTUzNTNFNywtMy43NDMzOTZFNywyLjk2NDM4RTcsLTIuMzM3ODI0RTcsMS44MzEyOUU3LC0xLjQyMTg3OEU3LDEuMDkxNTk1RTcsLTgyNzAwNTMuMCw2MTY4NTUzLjAsLTQ1MjA2NjEuMCwzMjQ2Njk3LjAsLTIyNzkzNjEuMCwxNTU5MDg5LjAsLTEwMzUyMjkuMCw2NjM5MTMuNSwtNDA4NjU0LjAsMjM5MTIxLjgsLTEzMTEyNS42LDY1NjUxLjMxLC0yODQwNC42OSw4OTM1LjA1NCwzLjM2NzcwOCwtMzIxMS4yMSwzNjQ0Ljk0MiwtMjk4NS44MDYsMjA3My43NDMsLTEyNTQuMzQ4LDYxNi4wNTA1::UmVhbCBDb2VmZmljaWVudCBWYWx1ZXM="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZOdW0=::NjQ=::TnVtYmVyIG9mIENvZWZmaWNpZW50cw=="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRSZWFsVmFsdWVJbWFn::MC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgLTAuMDUzMDA5MywgLTAuMDQ0OTgsIDAuMCwgMC4wNzQ5NjkzLCAwLjE1OTAzNCwgMC4yMjQ5MDcsIDAuMjQ5ODA5LCAwLjIyNDkwNywgMC4xNTkwMzQsIDAuMDc0OTY5MywgMC4wLCAtMC4wNDQ5OCwgLTAuMDUzMDA5MywgLTAuMDMyMTI4MywgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjA=::UmVhbCBDb2VmZmljaWVudCBWYWx1ZXMgKEltYWdpbmFyeSBDb21wb25lbnQp"
@@ -70,16 +70,16 @@ set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_C
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "b3V0cHV0SW50ZXJmYWNlTnVt::MQ==::TnVtYmVyIG9mIFBhcmFsbGVsIE91dHB1dCBTeW1ib2xz"
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y2hhblBlcklucHV0SW50ZXJmYWNl::MQ==::TnVtYmVyIG9mIENoYW5uZWxzIHBlciBJbnB1dCBJbnRlcmZhY2U="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y2hhblBlck91dHB1dEludGVyZmFjZQ==::MQ==::TnVtYmVyIG9mIENoYW5uZWxzIHBlciBPdXRwdXQgSW50ZXJmYWNl"
-set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeQ==::MTY=::bGF0ZW5jeQ=="
+set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeQ==::MTc=::bGF0ZW5jeQ=="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "b3V0cHV0Zmlmb2RlcHRo::NA==::b3V0cHV0Zmlmb2RlcHRo"
-set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "ZnVuY1Jlc3VsdA==::LWludGVycD0xIC1kZWNpbT0xIC1pbmN5Y2xlcz0xMzQwIC1sZW49NjQgLWJhbmtjb3VudD0xIC1zeW0gLW5iYW5kPTEgLWNoYW5zPTEgLWZhbWlseT0iQ3ljbG9uZSBJViBFIiAKfHt9fDF8MXwxfDF8MzB8MzF8MTZ8M3xub0NvZGV8TFVUUzogMTkzIERTUHM6IDEgUkFNIEJpdHM6IDEwMjR8::ZnVuY1Jlc3VsdA=="
-set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "YnVzQWRkcmVzc1dpZHRo::NQ==::YnVzQWRkcmVzc1dpZHRo"
+set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "ZnVuY1Jlc3VsdA==::LWludGVycD0xIC1kZWNpbT0xIC1pbmN5Y2xlcz0xMzQwIC1sZW49NjQgLWJhbmtjb3VudD0xIC1uc3ltIC1uYmFuZD0xIC1jaGFucz0xIC1mYW1pbHk9IkN5Y2xvbmUgSVYgRSIgCnx7fXwxfDF8MXwxfDQ2fDMxfDE3fDN8bm9Db2RlfExVVFM6IDI5OSBEU1BzOiAyIFJBTSBCaXRzOiAyMDQ4fA==::ZnVuY1Jlc3VsdA=="
+set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "YnVzQWRkcmVzc1dpZHRo::Ng==::YnVzQWRkcmVzc1dpZHRo"
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "YmFua0NvdW50::MQ==::TnVtYmVyIG9mIENvZWZmaWNpZW50IEJhbmtz"
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "YmFua0luV2lkdGg=::MA==::YmFua0luV2lkdGg="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "YmFua0Rpc3BsYXk=::MA==::YmFua0Rpc3BsYXk="
-set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "bHV0Q291bnQ=::MTkz::TnVtYmVyIG9mIExVVHM="
-set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "ZHNwQ291bnQ=::MQ==::TnVtYmVyIG9mIERTUHM="
-set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "bWVtQml0Q291bnQ=::MTAyNA==::TnVtYmVyIG9mIE1lbW9yeSBCaXRz"
+set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "bHV0Q291bnQ=::Mjk5::TnVtYmVyIG9mIExVVHM="
+set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "ZHNwQ291bnQ=::Mg==::TnVtYmVyIG9mIERTUHM="
+set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "bWVtQml0Q291bnQ=::MjA0OA==::TnVtYmVyIG9mIE1lbW9yeSBCaXRz"
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "ZXJyb3JMaXN0::MA==::ZXJyb3JMaXN0"
set_global_assignment -library "rx_ciccomp" -name VERILOG_FILE [file join $::quartus(qip_path) "rx_ciccomp.v"]
diff --git a/FPGA/rx_ciccomp.v b/FPGA/rx_ciccomp.v
index f1c5f06..2f676e0 100644
--- a/FPGA/rx_ciccomp.v
+++ b/FPGA/rx_ciccomp.v
@@ -8,10 +8,10 @@
module rx_ciccomp (
input wire clk, // clk.clk
input wire reset_n, // rst.reset_n
- input wire [15:0] ast_sink_data, // avalon_streaming_sink.data
+ input wire [31:0] ast_sink_data, // avalon_streaming_sink.data
input wire ast_sink_valid, // .valid
input wire [1:0] ast_sink_error, // .error
- output wire [29:0] ast_source_data, // avalon_streaming_source.data
+ output wire [45:0] ast_source_data, // avalon_streaming_source.data
output wire ast_source_valid, // .valid
output wire [1:0] ast_source_error // .error
);
@@ -58,7 +58,7 @@ endmodule
// Retrieval info:
// Retrieval info:
// Retrieval info:
-// Retrieval info:
+// Retrieval info:
// Retrieval info:
// Retrieval info:
// Retrieval info:
@@ -80,7 +80,7 @@ endmodule
// Retrieval info:
// Retrieval info:
// Retrieval info:
-// Retrieval info:
+// Retrieval info:
// Retrieval info:
// Retrieval info:
// Retrieval info:
diff --git a/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd b/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd
index 66199f2..10dbfa1 100644
--- a/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd
+++ b/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd
@@ -20,10 +20,10 @@ entity rx_ciccomp_0002 is
port (
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
- ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*16) * 1 + 0 - 1 downto 0);
+ ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*32) * 1 + 0 - 1 downto 0);
ast_sink_valid : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
- ast_source_data : out STD_LOGIC_VECTOR(30 * 1*1 - 1 downto 0);
+ ast_source_data : out STD_LOGIC_VECTOR(46 * 1*1 - 1 downto 0);
ast_source_valid : out STD_LOGIC;
ast_source_error : out STD_LOGIC_VECTOR(1 downto 0)
);
@@ -35,13 +35,13 @@ architecture syn of rx_ciccomp_0002 is
port (
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
- ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*16) * 1 + 0 - 1 downto 0);
+ ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*32) * 1 + 0 - 1 downto 0);
ast_sink_valid : in STD_LOGIC;
ast_sink_ready : out STD_LOGIC;
ast_sink_sop : in STD_LOGIC;
ast_sink_eop : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
- ast_source_data : out STD_LOGIC_VECTOR(1*30 * 1 - 1 downto 0);
+ ast_source_data : out STD_LOGIC_VECTOR(1*46 * 1 - 1 downto 0);
ast_source_ready : in STD_LOGIC;
ast_source_valid : out STD_LOGIC;
ast_source_sop : out STD_LOGIC;
diff --git a/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd b/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd
index 1a54281..0f9bbf8 100644
--- a/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd
+++ b/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd
@@ -8,8 +8,8 @@ use work.auk_dspip_math_pkg_hpfir.all;
entity rx_ciccomp_0002_ast is
generic (
- INWIDTH : integer := 16;
- OUT_WIDTH_UNTRIMMED : integer := 30;
+ INWIDTH : integer := 32;
+ OUT_WIDTH_UNTRIMMED : integer := 46;
BANKINWIDTH : integer := 0;
REM_LSB_BIT_g : integer := 0;
REM_LSB_TYPE_g : string := "round";
@@ -194,10 +194,10 @@ real_passthrough : if COMPLEX_CONST = 1 generate
port (
xIn_v : in std_logic_vector(0 downto 0);
xIn_c : in std_logic_vector(7 downto 0);
- xIn_0 : in std_logic_vector(16 - 1 downto 0);
+ xIn_0 : in std_logic_vector(32 - 1 downto 0);
xOut_v : out std_logic_vector(0 downto 0);
xOut_c : out std_logic_vector(7 downto 0);
- xOut_0 : out std_logic_vector(30- 1 downto 0);
+ xOut_0 : out std_logic_vector(46- 1 downto 0);
clk : in std_logic;
areset : in std_logic
);
@@ -219,10 +219,10 @@ end component rx_ciccomp_0002_rtl_core;
port map (
xIn_v => data_valid_core,
xIn_c => "00000000",
- xIn_0 => data_in_core((0 + 16) * 0 + 16 - 1 downto (0 + 16) * 0),
+ xIn_0 => data_in_core((0 + 32) * 0 + 32 - 1 downto (0 + 32) * 0),
xOut_v => core_out_valid_core,
xOut_c => core_out_channel_core,
- xOut_0 => core_out_core(30* 0 + 30- 1 downto 30* 0),
+ xOut_0 => core_out_core(46* 0 + 46- 1 downto 46* 0),
clk => clk,
areset => reset_fir
);
diff --git a/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd b/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd
index 75bb452..3a45c0d 100644
--- a/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd
+++ b/FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd
@@ -16,7 +16,7 @@
-- ---------------------------------------------------------------------------
-- VHDL created from rx_ciccomp_0002_rtl_core
--- VHDL created on Thu Jan 07 18:16:37 2021
+-- VHDL created on Fri Feb 12 16:11:12 2021
library IEEE;
@@ -35,10 +35,10 @@ entity rx_ciccomp_0002_rtl_core is
port (
xIn_v : in std_logic_vector(0 downto 0); -- sfix1
xIn_c : in std_logic_vector(7 downto 0); -- sfix8
- xIn_0 : in std_logic_vector(15 downto 0); -- sfix16
+ xIn_0 : in std_logic_vector(31 downto 0); -- sfix32
xOut_v : out std_logic_vector(0 downto 0); -- ufix1
xOut_c : out std_logic_vector(7 downto 0); -- ufix8
- xOut_0 : out std_logic_vector(29 downto 0); -- sfix30
+ xOut_0 : out std_logic_vector(45 downto 0); -- sfix46
clk : in std_logic;
areset : in std_logic
);
@@ -51,7 +51,7 @@ architecture normal of rx_ciccomp_0002_rtl_core is
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
- signal d_xIn_0_13_q : STD_LOGIC_VECTOR (15 downto 0);
+ signal d_xIn_0_13_q : STD_LOGIC_VECTOR (31 downto 0);
signal d_in0_m0_wi0_wo0_assign_id1_q_13_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_run_count : STD_LOGIC_VECTOR (1 downto 0);
signal u0_m0_wo0_run_preEnaQ : STD_LOGIC_VECTOR (0 downto 0);
@@ -61,8 +61,8 @@ architecture normal of rx_ciccomp_0002_rtl_core is
signal u0_m0_wo0_run_ctrl : STD_LOGIC_VECTOR (2 downto 0);
signal u0_m0_wo0_memread_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_compute_q : STD_LOGIC_VECTOR (0 downto 0);
- signal d_u0_m0_wo0_compute_q_14_q : STD_LOGIC_VECTOR (0 downto 0);
signal d_u0_m0_wo0_compute_q_15_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal d_u0_m0_wo0_compute_q_16_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count0_inner_q : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count0_inner_i : SIGNED (6 downto 0);
attribute preserve : boolean;
@@ -81,34 +81,48 @@ architecture normal of rx_ciccomp_0002_rtl_core is
signal u0_m0_wo0_wi0_r0_wa0_i : UNSIGNED (5 downto 0);
attribute preserve of u0_m0_wo0_wi0_r0_wa0_i : signal is true;
signal u0_m0_wo0_wi0_r0_memr0_reset0 : std_logic;
- signal u0_m0_wo0_wi0_r0_memr0_ia : STD_LOGIC_VECTOR (15 downto 0);
+ signal u0_m0_wo0_wi0_r0_memr0_ia : STD_LOGIC_VECTOR (31 downto 0);
signal u0_m0_wo0_wi0_r0_memr0_aa : STD_LOGIC_VECTOR (5 downto 0);
signal u0_m0_wo0_wi0_r0_memr0_ab : STD_LOGIC_VECTOR (5 downto 0);
- signal u0_m0_wo0_wi0_r0_memr0_iq : STD_LOGIC_VECTOR (15 downto 0);
- signal u0_m0_wo0_wi0_r0_memr0_q : STD_LOGIC_VECTOR (15 downto 0);
+ signal u0_m0_wo0_wi0_r0_memr0_iq : STD_LOGIC_VECTOR (31 downto 0);
+ signal u0_m0_wo0_wi0_r0_memr0_q : STD_LOGIC_VECTOR (31 downto 0);
signal u0_m0_wo0_ca0_q : STD_LOGIC_VECTOR (5 downto 0);
signal u0_m0_wo0_ca0_i : UNSIGNED (5 downto 0);
attribute preserve of u0_m0_wo0_ca0_i : signal is true;
signal u0_m0_wo0_cm0_q : STD_LOGIC_VECTOR (7 downto 0);
- signal u0_m0_wo0_mtree_mult1_0_a0 : STD_LOGIC_VECTOR (7 downto 0);
- signal u0_m0_wo0_mtree_mult1_0_b0 : STD_LOGIC_VECTOR (15 downto 0);
- signal u0_m0_wo0_mtree_mult1_0_s1 : STD_LOGIC_VECTOR (23 downto 0);
- signal u0_m0_wo0_mtree_mult1_0_reset : std_logic;
- signal u0_m0_wo0_mtree_mult1_0_q : STD_LOGIC_VECTOR (23 downto 0);
signal u0_m0_wo0_aseq_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_aseq_eq : std_logic;
- signal u0_m0_wo0_accum_a : STD_LOGIC_VECTOR (29 downto 0);
- signal u0_m0_wo0_accum_b : STD_LOGIC_VECTOR (29 downto 0);
- signal u0_m0_wo0_accum_i : STD_LOGIC_VECTOR (29 downto 0);
- signal u0_m0_wo0_accum_o : STD_LOGIC_VECTOR (29 downto 0);
- signal u0_m0_wo0_accum_q : STD_LOGIC_VECTOR (29 downto 0);
+ signal u0_m0_wo0_accum_a : STD_LOGIC_VECTOR (45 downto 0);
+ signal u0_m0_wo0_accum_b : STD_LOGIC_VECTOR (45 downto 0);
+ signal u0_m0_wo0_accum_i : STD_LOGIC_VECTOR (45 downto 0);
+ signal u0_m0_wo0_accum_o : STD_LOGIC_VECTOR (45 downto 0);
+ signal u0_m0_wo0_accum_q : STD_LOGIC_VECTOR (45 downto 0);
signal u0_m0_wo0_oseq_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_oseq_eq : std_logic;
signal u0_m0_wo0_oseq_gated_reg_q : STD_LOGIC_VECTOR (0 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_im0_a0 : STD_LOGIC_VECTOR (17 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_im0_b0 : STD_LOGIC_VECTOR (7 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_im0_s1 : STD_LOGIC_VECTOR (25 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_im0_reset : std_logic;
+ signal u0_m0_wo0_mtree_mult1_0_im0_q : STD_LOGIC_VECTOR (25 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_im4_a0 : STD_LOGIC_VECTOR (14 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_im4_b0 : STD_LOGIC_VECTOR (7 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_im4_s1 : STD_LOGIC_VECTOR (22 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_im4_reset : std_logic;
+ signal u0_m0_wo0_mtree_mult1_0_im4_q : STD_LOGIC_VECTOR (22 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_result_add_0_0_a : STD_LOGIC_VECTOR (40 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_result_add_0_0_b : STD_LOGIC_VECTOR (40 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_result_add_0_0_o : STD_LOGIC_VECTOR (40 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_result_add_0_0_q : STD_LOGIC_VECTOR (40 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count0_run_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_oseq_gated_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_resize_in : STD_LOGIC_VECTOR (5 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_resize_b : STD_LOGIC_VECTOR (5 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b : STD_LOGIC_VECTOR (16 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c : STD_LOGIC_VECTOR (14 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_align_8_q : STD_LOGIC_VECTOR (39 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_align_8_qint : STD_LOGIC_VECTOR (39 downto 0);
+ signal u0_m0_wo0_mtree_mult1_0_bjB3_q : STD_LOGIC_VECTOR (17 downto 0);
begin
@@ -165,12 +179,12 @@ begin
GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => u0_m0_wo0_memread_q, xout => u0_m0_wo0_compute_q, clk => clk, aclr => areset );
- -- d_u0_m0_wo0_compute_q_14(DELAY,45)@12 + 2
- d_u0_m0_wo0_compute_q_14 : dspba_delay
- GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
- PORT MAP ( xin => u0_m0_wo0_compute_q, xout => d_u0_m0_wo0_compute_q_14_q, clk => clk, aclr => areset );
+ -- d_u0_m0_wo0_compute_q_15(DELAY,57)@12 + 3
+ d_u0_m0_wo0_compute_q_15 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" )
+ PORT MAP ( xin => u0_m0_wo0_compute_q, xout => d_u0_m0_wo0_compute_q_15_q, clk => clk, aclr => areset );
- -- u0_m0_wo0_aseq(SEQUENCE,33)@14 + 1
+ -- u0_m0_wo0_aseq(SEQUENCE,33)@15 + 1
u0_m0_wo0_aseq_clkproc: PROCESS (clk, areset)
variable u0_m0_wo0_aseq_c : SIGNED(8 downto 0);
BEGIN
@@ -179,7 +193,7 @@ begin
u0_m0_wo0_aseq_q <= "0";
u0_m0_wo0_aseq_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
- IF (d_u0_m0_wo0_compute_q_14_q = "1") THEN
+ IF (d_u0_m0_wo0_compute_q_15_q = "1") THEN
IF (u0_m0_wo0_aseq_c = "000000000") THEN
u0_m0_wo0_aseq_eq <= '1';
ELSE
@@ -195,142 +209,10 @@ begin
END IF;
END PROCESS;
- -- d_u0_m0_wo0_compute_q_15(DELAY,46)@14 + 1
- d_u0_m0_wo0_compute_q_15 : dspba_delay
+ -- d_u0_m0_wo0_compute_q_16(DELAY,58)@15 + 1
+ d_u0_m0_wo0_compute_q_16 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
- PORT MAP ( xin => d_u0_m0_wo0_compute_q_14_q, xout => d_u0_m0_wo0_compute_q_15_q, clk => clk, aclr => areset );
-
- -- u0_m0_wo0_wi0_r0_ra0_count1(COUNTER,22)@12
- -- low=0, high=63, step=1, init=0
- u0_m0_wo0_wi0_r0_ra0_count1_clkproc: PROCESS (clk, areset)
- BEGIN
- IF (areset = '1') THEN
- u0_m0_wo0_wi0_r0_ra0_count1_i <= TO_UNSIGNED(0, 6);
- ELSIF (clk'EVENT AND clk = '1') THEN
- IF (u0_m0_wo0_memread_q = "1") THEN
- u0_m0_wo0_wi0_r0_ra0_count1_i <= u0_m0_wo0_wi0_r0_ra0_count1_i + 1;
- END IF;
- END IF;
- END PROCESS;
- u0_m0_wo0_wi0_r0_ra0_count1_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count1_i, 7)));
-
- -- u0_m0_wo0_wi0_r0_ra0_count0_inner(COUNTER,19)@12
- -- low=-1, high=62, step=-1, init=62
- u0_m0_wo0_wi0_r0_ra0_count0_inner_clkproc: PROCESS (clk, areset)
- BEGIN
- IF (areset = '1') THEN
- u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= TO_SIGNED(62, 7);
- ELSIF (clk'EVENT AND clk = '1') THEN
- IF (u0_m0_wo0_memread_q = "1") THEN
- IF (u0_m0_wo0_wi0_r0_ra0_count0_inner_i(6 downto 6) = "1") THEN
- u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= u0_m0_wo0_wi0_r0_ra0_count0_inner_i - 65;
- ELSE
- u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= u0_m0_wo0_wi0_r0_ra0_count0_inner_i - 1;
- END IF;
- END IF;
- END IF;
- END PROCESS;
- u0_m0_wo0_wi0_r0_ra0_count0_inner_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count0_inner_i, 7)));
-
- -- u0_m0_wo0_wi0_r0_ra0_count0_run(LOGICAL,20)@12
- u0_m0_wo0_wi0_r0_ra0_count0_run_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_count0_inner_q(6 downto 6));
-
- -- u0_m0_wo0_wi0_r0_ra0_count0(COUNTER,21)@12
- -- low=0, high=63, step=1, init=0
- u0_m0_wo0_wi0_r0_ra0_count0_clkproc: PROCESS (clk, areset)
- BEGIN
- IF (areset = '1') THEN
- u0_m0_wo0_wi0_r0_ra0_count0_i <= TO_UNSIGNED(0, 6);
- ELSIF (clk'EVENT AND clk = '1') THEN
- IF (u0_m0_wo0_memread_q = "1" and u0_m0_wo0_wi0_r0_ra0_count0_run_q = "1") THEN
- u0_m0_wo0_wi0_r0_ra0_count0_i <= u0_m0_wo0_wi0_r0_ra0_count0_i + 1;
- END IF;
- END IF;
- END PROCESS;
- u0_m0_wo0_wi0_r0_ra0_count0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count0_i, 7)));
-
- -- u0_m0_wo0_wi0_r0_ra0_add_0_0(ADD,23)@12 + 1
- u0_m0_wo0_wi0_r0_ra0_add_0_0_a <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_ra0_count0_q);
- u0_m0_wo0_wi0_r0_ra0_add_0_0_b <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_ra0_count1_q);
- u0_m0_wo0_wi0_r0_ra0_add_0_0_clkproc: PROCESS (clk, areset)
- BEGIN
- IF (areset = '1') THEN
- u0_m0_wo0_wi0_r0_ra0_add_0_0_o <= (others => '0');
- ELSIF (clk'EVENT AND clk = '1') THEN
- u0_m0_wo0_wi0_r0_ra0_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(u0_m0_wo0_wi0_r0_ra0_add_0_0_a) + UNSIGNED(u0_m0_wo0_wi0_r0_ra0_add_0_0_b));
- END IF;
- END PROCESS;
- u0_m0_wo0_wi0_r0_ra0_add_0_0_q <= u0_m0_wo0_wi0_r0_ra0_add_0_0_o(7 downto 0);
-
- -- u0_m0_wo0_wi0_r0_ra0_resize(BITSELECT,24)@13
- u0_m0_wo0_wi0_r0_ra0_resize_in <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_add_0_0_q(5 downto 0));
- u0_m0_wo0_wi0_r0_ra0_resize_b <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_resize_in(5 downto 0));
-
- -- d_xIn_0_13(DELAY,43)@10 + 3
- d_xIn_0_13 : dspba_delay
- GENERIC MAP ( width => 16, depth => 3, reset_kind => "ASYNC" )
- PORT MAP ( xin => xIn_0, xout => d_xIn_0_13_q, clk => clk, aclr => areset );
-
- -- d_in0_m0_wi0_wo0_assign_id1_q_13(DELAY,44)@10 + 3
- d_in0_m0_wi0_wo0_assign_id1_q_13 : dspba_delay
- GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" )
- PORT MAP ( xin => xIn_v, xout => d_in0_m0_wi0_wo0_assign_id1_q_13_q, clk => clk, aclr => areset );
-
- -- u0_m0_wo0_wi0_r0_wa0(COUNTER,25)@13
- -- low=0, high=63, step=1, init=63
- u0_m0_wo0_wi0_r0_wa0_clkproc: PROCESS (clk, areset)
- BEGIN
- IF (areset = '1') THEN
- u0_m0_wo0_wi0_r0_wa0_i <= TO_UNSIGNED(63, 6);
- ELSIF (clk'EVENT AND clk = '1') THEN
- IF (d_in0_m0_wi0_wo0_assign_id1_q_13_q = "1") THEN
- u0_m0_wo0_wi0_r0_wa0_i <= u0_m0_wo0_wi0_r0_wa0_i + 1;
- END IF;
- END IF;
- END PROCESS;
- u0_m0_wo0_wi0_r0_wa0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_wa0_i, 6)));
-
- -- u0_m0_wo0_wi0_r0_memr0(DUALMEM,26)@13
- u0_m0_wo0_wi0_r0_memr0_ia <= STD_LOGIC_VECTOR(d_xIn_0_13_q);
- u0_m0_wo0_wi0_r0_memr0_aa <= u0_m0_wo0_wi0_r0_wa0_q;
- u0_m0_wo0_wi0_r0_memr0_ab <= u0_m0_wo0_wi0_r0_ra0_resize_b;
- u0_m0_wo0_wi0_r0_memr0_dmem : altsyncram
- GENERIC MAP (
- ram_block_type => "M9K",
- operation_mode => "DUAL_PORT",
- width_a => 16,
- widthad_a => 6,
- numwords_a => 64,
- width_b => 16,
- widthad_b => 6,
- numwords_b => 64,
- lpm_type => "altsyncram",
- width_byteena_a => 1,
- address_reg_b => "CLOCK0",
- indata_reg_b => "CLOCK0",
- wrcontrol_wraddress_reg_b => "CLOCK0",
- rdcontrol_reg_b => "CLOCK0",
- byteena_reg_b => "CLOCK0",
- outdata_reg_b => "CLOCK0",
- outdata_aclr_b => "NONE",
- clock_enable_input_a => "NORMAL",
- clock_enable_input_b => "NORMAL",
- clock_enable_output_b => "NORMAL",
- read_during_write_mode_mixed_ports => "DONT_CARE",
- power_up_uninitialized => "FALSE",
- init_file => "UNUSED",
- intended_device_family => "Cyclone IV E"
- )
- PORT MAP (
- clocken0 => '1',
- clock0 => clk,
- address_a => u0_m0_wo0_wi0_r0_memr0_aa,
- data_a => u0_m0_wo0_wi0_r0_memr0_ia,
- wren_a => d_in0_m0_wi0_wo0_assign_id1_q_13_q(0),
- address_b => u0_m0_wo0_wi0_r0_memr0_ab,
- q_b => u0_m0_wo0_wi0_r0_memr0_iq
- );
- u0_m0_wo0_wi0_r0_memr0_q <= u0_m0_wo0_wi0_r0_memr0_iq(15 downto 0);
+ PORT MAP ( xin => d_u0_m0_wo0_compute_q_15_q, xout => d_u0_m0_wo0_compute_q_16_q, clk => clk, aclr => areset );
-- u0_m0_wo0_ca0(COUNTER,27)@12
-- low=0, high=63, step=1, init=0
@@ -423,15 +305,151 @@ begin
END IF;
END PROCESS;
- -- u0_m0_wo0_mtree_mult1_0(MULT,32)@13 + 2
- u0_m0_wo0_mtree_mult1_0_a0 <= STD_LOGIC_VECTOR(u0_m0_wo0_cm0_q);
- u0_m0_wo0_mtree_mult1_0_b0 <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_memr0_q);
- u0_m0_wo0_mtree_mult1_0_reset <= areset;
- u0_m0_wo0_mtree_mult1_0_component : lpm_mult
+ -- u0_m0_wo0_wi0_r0_ra0_count1(COUNTER,22)@12
+ -- low=0, high=63, step=1, init=0
+ u0_m0_wo0_wi0_r0_ra0_count1_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ u0_m0_wo0_wi0_r0_ra0_count1_i <= TO_UNSIGNED(0, 6);
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ IF (u0_m0_wo0_memread_q = "1") THEN
+ u0_m0_wo0_wi0_r0_ra0_count1_i <= u0_m0_wo0_wi0_r0_ra0_count1_i + 1;
+ END IF;
+ END IF;
+ END PROCESS;
+ u0_m0_wo0_wi0_r0_ra0_count1_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count1_i, 7)));
+
+ -- u0_m0_wo0_wi0_r0_ra0_count0_inner(COUNTER,19)@12
+ -- low=-1, high=62, step=-1, init=62
+ u0_m0_wo0_wi0_r0_ra0_count0_inner_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= TO_SIGNED(62, 7);
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ IF (u0_m0_wo0_memread_q = "1") THEN
+ IF (u0_m0_wo0_wi0_r0_ra0_count0_inner_i(6 downto 6) = "1") THEN
+ u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= u0_m0_wo0_wi0_r0_ra0_count0_inner_i - 65;
+ ELSE
+ u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= u0_m0_wo0_wi0_r0_ra0_count0_inner_i - 1;
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+ u0_m0_wo0_wi0_r0_ra0_count0_inner_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count0_inner_i, 7)));
+
+ -- u0_m0_wo0_wi0_r0_ra0_count0_run(LOGICAL,20)@12
+ u0_m0_wo0_wi0_r0_ra0_count0_run_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_count0_inner_q(6 downto 6));
+
+ -- u0_m0_wo0_wi0_r0_ra0_count0(COUNTER,21)@12
+ -- low=0, high=63, step=1, init=0
+ u0_m0_wo0_wi0_r0_ra0_count0_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ u0_m0_wo0_wi0_r0_ra0_count0_i <= TO_UNSIGNED(0, 6);
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ IF (u0_m0_wo0_memread_q = "1" and u0_m0_wo0_wi0_r0_ra0_count0_run_q = "1") THEN
+ u0_m0_wo0_wi0_r0_ra0_count0_i <= u0_m0_wo0_wi0_r0_ra0_count0_i + 1;
+ END IF;
+ END IF;
+ END PROCESS;
+ u0_m0_wo0_wi0_r0_ra0_count0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count0_i, 7)));
+
+ -- u0_m0_wo0_wi0_r0_ra0_add_0_0(ADD,23)@12 + 1
+ u0_m0_wo0_wi0_r0_ra0_add_0_0_a <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_ra0_count0_q);
+ u0_m0_wo0_wi0_r0_ra0_add_0_0_b <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_ra0_count1_q);
+ u0_m0_wo0_wi0_r0_ra0_add_0_0_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ u0_m0_wo0_wi0_r0_ra0_add_0_0_o <= (others => '0');
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ u0_m0_wo0_wi0_r0_ra0_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(u0_m0_wo0_wi0_r0_ra0_add_0_0_a) + UNSIGNED(u0_m0_wo0_wi0_r0_ra0_add_0_0_b));
+ END IF;
+ END PROCESS;
+ u0_m0_wo0_wi0_r0_ra0_add_0_0_q <= u0_m0_wo0_wi0_r0_ra0_add_0_0_o(7 downto 0);
+
+ -- u0_m0_wo0_wi0_r0_ra0_resize(BITSELECT,24)@13
+ u0_m0_wo0_wi0_r0_ra0_resize_in <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_add_0_0_q(5 downto 0));
+ u0_m0_wo0_wi0_r0_ra0_resize_b <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_resize_in(5 downto 0));
+
+ -- d_xIn_0_13(DELAY,55)@10 + 3
+ d_xIn_0_13 : dspba_delay
+ GENERIC MAP ( width => 32, depth => 3, reset_kind => "ASYNC" )
+ PORT MAP ( xin => xIn_0, xout => d_xIn_0_13_q, clk => clk, aclr => areset );
+
+ -- d_in0_m0_wi0_wo0_assign_id1_q_13(DELAY,56)@10 + 3
+ d_in0_m0_wi0_wo0_assign_id1_q_13 : dspba_delay
+ GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" )
+ PORT MAP ( xin => xIn_v, xout => d_in0_m0_wi0_wo0_assign_id1_q_13_q, clk => clk, aclr => areset );
+
+ -- u0_m0_wo0_wi0_r0_wa0(COUNTER,25)@13
+ -- low=0, high=63, step=1, init=63
+ u0_m0_wo0_wi0_r0_wa0_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ u0_m0_wo0_wi0_r0_wa0_i <= TO_UNSIGNED(63, 6);
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ IF (d_in0_m0_wi0_wo0_assign_id1_q_13_q = "1") THEN
+ u0_m0_wo0_wi0_r0_wa0_i <= u0_m0_wo0_wi0_r0_wa0_i + 1;
+ END IF;
+ END IF;
+ END PROCESS;
+ u0_m0_wo0_wi0_r0_wa0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_wa0_i, 6)));
+
+ -- u0_m0_wo0_wi0_r0_memr0(DUALMEM,26)@13
+ u0_m0_wo0_wi0_r0_memr0_ia <= STD_LOGIC_VECTOR(d_xIn_0_13_q);
+ u0_m0_wo0_wi0_r0_memr0_aa <= u0_m0_wo0_wi0_r0_wa0_q;
+ u0_m0_wo0_wi0_r0_memr0_ab <= u0_m0_wo0_wi0_r0_ra0_resize_b;
+ u0_m0_wo0_wi0_r0_memr0_dmem : altsyncram
GENERIC MAP (
- lpm_widtha => 8,
- lpm_widthb => 16,
- lpm_widthp => 24,
+ ram_block_type => "M9K",
+ operation_mode => "DUAL_PORT",
+ width_a => 32,
+ widthad_a => 6,
+ numwords_a => 64,
+ width_b => 32,
+ widthad_b => 6,
+ numwords_b => 64,
+ lpm_type => "altsyncram",
+ width_byteena_a => 1,
+ address_reg_b => "CLOCK0",
+ indata_reg_b => "CLOCK0",
+ wrcontrol_wraddress_reg_b => "CLOCK0",
+ rdcontrol_reg_b => "CLOCK0",
+ byteena_reg_b => "CLOCK0",
+ outdata_reg_b => "CLOCK0",
+ outdata_aclr_b => "NONE",
+ clock_enable_input_a => "NORMAL",
+ clock_enable_input_b => "NORMAL",
+ clock_enable_output_b => "NORMAL",
+ read_during_write_mode_mixed_ports => "DONT_CARE",
+ power_up_uninitialized => "FALSE",
+ init_file => "UNUSED",
+ intended_device_family => "Cyclone IV E"
+ )
+ PORT MAP (
+ clocken0 => '1',
+ clock0 => clk,
+ address_a => u0_m0_wo0_wi0_r0_memr0_aa,
+ data_a => u0_m0_wo0_wi0_r0_memr0_ia,
+ wren_a => d_in0_m0_wi0_wo0_assign_id1_q_13_q(0),
+ address_b => u0_m0_wo0_wi0_r0_memr0_ab,
+ q_b => u0_m0_wo0_wi0_r0_memr0_iq
+ );
+ u0_m0_wo0_wi0_r0_memr0_q <= u0_m0_wo0_wi0_r0_memr0_iq(31 downto 0);
+
+ -- u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select(BITSELECT,54)@13
+ u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_memr0_q(16 downto 0));
+ u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_memr0_q(31 downto 17));
+
+ -- u0_m0_wo0_mtree_mult1_0_im4(MULT,47)@13 + 2
+ u0_m0_wo0_mtree_mult1_0_im4_a0 <= STD_LOGIC_VECTOR(u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c);
+ u0_m0_wo0_mtree_mult1_0_im4_b0 <= STD_LOGIC_VECTOR(u0_m0_wo0_cm0_q);
+ u0_m0_wo0_mtree_mult1_0_im4_reset <= areset;
+ u0_m0_wo0_mtree_mult1_0_im4_component : lpm_mult
+ GENERIC MAP (
+ lpm_widtha => 15,
+ lpm_widthb => 8,
+ lpm_widthp => 23,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
@@ -439,17 +457,62 @@ begin
lpm_pipeline => 2
)
PORT MAP (
- dataa => u0_m0_wo0_mtree_mult1_0_a0,
- datab => u0_m0_wo0_mtree_mult1_0_b0,
+ dataa => u0_m0_wo0_mtree_mult1_0_im4_a0,
+ datab => u0_m0_wo0_mtree_mult1_0_im4_b0,
clken => VCC_q(0),
- aclr => u0_m0_wo0_mtree_mult1_0_reset,
+ aclr => u0_m0_wo0_mtree_mult1_0_im4_reset,
clock => clk,
- result => u0_m0_wo0_mtree_mult1_0_s1
+ result => u0_m0_wo0_mtree_mult1_0_im4_s1
);
- u0_m0_wo0_mtree_mult1_0_q <= u0_m0_wo0_mtree_mult1_0_s1;
+ u0_m0_wo0_mtree_mult1_0_im4_q <= u0_m0_wo0_mtree_mult1_0_im4_s1;
- -- u0_m0_wo0_accum(ADD,34)@15 + 1
- u0_m0_wo0_accum_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((29 downto 24 => u0_m0_wo0_mtree_mult1_0_q(23)) & u0_m0_wo0_mtree_mult1_0_q));
+ -- u0_m0_wo0_mtree_mult1_0_align_8(BITSHIFT,51)@15
+ u0_m0_wo0_mtree_mult1_0_align_8_qint <= u0_m0_wo0_mtree_mult1_0_im4_q & "00000000000000000";
+ u0_m0_wo0_mtree_mult1_0_align_8_q <= u0_m0_wo0_mtree_mult1_0_align_8_qint(39 downto 0);
+
+ -- u0_m0_wo0_mtree_mult1_0_bjB3(BITJOIN,46)@13
+ u0_m0_wo0_mtree_mult1_0_bjB3_q <= GND_q & u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b;
+
+ -- u0_m0_wo0_mtree_mult1_0_im0(MULT,43)@13 + 2
+ u0_m0_wo0_mtree_mult1_0_im0_a0 <= STD_LOGIC_VECTOR(u0_m0_wo0_mtree_mult1_0_bjB3_q);
+ u0_m0_wo0_mtree_mult1_0_im0_b0 <= STD_LOGIC_VECTOR(u0_m0_wo0_cm0_q);
+ u0_m0_wo0_mtree_mult1_0_im0_reset <= areset;
+ u0_m0_wo0_mtree_mult1_0_im0_component : lpm_mult
+ GENERIC MAP (
+ lpm_widtha => 18,
+ lpm_widthb => 8,
+ lpm_widthp => 26,
+ lpm_widths => 1,
+ lpm_type => "LPM_MULT",
+ lpm_representation => "SIGNED",
+ lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
+ lpm_pipeline => 2
+ )
+ PORT MAP (
+ dataa => u0_m0_wo0_mtree_mult1_0_im0_a0,
+ datab => u0_m0_wo0_mtree_mult1_0_im0_b0,
+ clken => VCC_q(0),
+ aclr => u0_m0_wo0_mtree_mult1_0_im0_reset,
+ clock => clk,
+ result => u0_m0_wo0_mtree_mult1_0_im0_s1
+ );
+ u0_m0_wo0_mtree_mult1_0_im0_q <= u0_m0_wo0_mtree_mult1_0_im0_s1;
+
+ -- u0_m0_wo0_mtree_mult1_0_result_add_0_0(ADD,53)@15 + 1
+ u0_m0_wo0_mtree_mult1_0_result_add_0_0_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((40 downto 26 => u0_m0_wo0_mtree_mult1_0_im0_q(25)) & u0_m0_wo0_mtree_mult1_0_im0_q));
+ u0_m0_wo0_mtree_mult1_0_result_add_0_0_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((40 downto 40 => u0_m0_wo0_mtree_mult1_0_align_8_q(39)) & u0_m0_wo0_mtree_mult1_0_align_8_q));
+ u0_m0_wo0_mtree_mult1_0_result_add_0_0_clkproc: PROCESS (clk, areset)
+ BEGIN
+ IF (areset = '1') THEN
+ u0_m0_wo0_mtree_mult1_0_result_add_0_0_o <= (others => '0');
+ ELSIF (clk'EVENT AND clk = '1') THEN
+ u0_m0_wo0_mtree_mult1_0_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(u0_m0_wo0_mtree_mult1_0_result_add_0_0_a) + SIGNED(u0_m0_wo0_mtree_mult1_0_result_add_0_0_b));
+ END IF;
+ END PROCESS;
+ u0_m0_wo0_mtree_mult1_0_result_add_0_0_q <= u0_m0_wo0_mtree_mult1_0_result_add_0_0_o(40 downto 0);
+
+ -- u0_m0_wo0_accum(ADD,34)@16 + 1
+ u0_m0_wo0_accum_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((45 downto 41 => u0_m0_wo0_mtree_mult1_0_result_add_0_0_q(40)) & u0_m0_wo0_mtree_mult1_0_result_add_0_0_q));
u0_m0_wo0_accum_b <= STD_LOGIC_VECTOR(u0_m0_wo0_accum_q);
u0_m0_wo0_accum_i <= u0_m0_wo0_accum_a;
u0_m0_wo0_accum_clkproc: PROCESS (clk, areset)
@@ -457,7 +520,7 @@ begin
IF (areset = '1') THEN
u0_m0_wo0_accum_o <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
- IF (d_u0_m0_wo0_compute_q_15_q = "1") THEN
+ IF (d_u0_m0_wo0_compute_q_16_q = "1") THEN
IF (u0_m0_wo0_aseq_q = "1") THEN
u0_m0_wo0_accum_o <= u0_m0_wo0_accum_i;
ELSE
@@ -466,12 +529,12 @@ begin
END IF;
END IF;
END PROCESS;
- u0_m0_wo0_accum_q <= u0_m0_wo0_accum_o(29 downto 0);
+ u0_m0_wo0_accum_q <= u0_m0_wo0_accum_o(45 downto 0);
-- GND(CONSTANT,0)@0
GND_q <= "0";
- -- u0_m0_wo0_oseq(SEQUENCE,35)@14 + 1
+ -- u0_m0_wo0_oseq(SEQUENCE,35)@15 + 1
u0_m0_wo0_oseq_clkproc: PROCESS (clk, areset)
variable u0_m0_wo0_oseq_c : SIGNED(8 downto 0);
BEGIN
@@ -480,7 +543,7 @@ begin
u0_m0_wo0_oseq_q <= "0";
u0_m0_wo0_oseq_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
- IF (d_u0_m0_wo0_compute_q_14_q = "1") THEN
+ IF (d_u0_m0_wo0_compute_q_15_q = "1") THEN
IF (u0_m0_wo0_oseq_c = "000000000") THEN
u0_m0_wo0_oseq_eq <= '1';
ELSE
@@ -496,10 +559,10 @@ begin
END IF;
END PROCESS;
- -- u0_m0_wo0_oseq_gated(LOGICAL,36)@15
- u0_m0_wo0_oseq_gated_q <= u0_m0_wo0_oseq_q and d_u0_m0_wo0_compute_q_15_q;
+ -- u0_m0_wo0_oseq_gated(LOGICAL,36)@16
+ u0_m0_wo0_oseq_gated_q <= u0_m0_wo0_oseq_q and d_u0_m0_wo0_compute_q_16_q;
- -- u0_m0_wo0_oseq_gated_reg(REG,37)@15 + 1
+ -- u0_m0_wo0_oseq_gated_reg(REG,37)@16 + 1
u0_m0_wo0_oseq_gated_reg_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
@@ -509,7 +572,7 @@ begin
END IF;
END PROCESS;
- -- xOut(PORTOUT,42)@16 + 1
+ -- xOut(PORTOUT,42)@17 + 1
xOut_v <= u0_m0_wo0_oseq_gated_reg_q;
xOut_c <= STD_LOGIC_VECTOR("0000000" & GND_q);
xOut_0 <= u0_m0_wo0_accum_q;
diff --git a/FPGA/rx_ciccomp_sim/aldec/rivierapro_setup.tcl b/FPGA/rx_ciccomp_sim/aldec/rivierapro_setup.tcl
new file mode 100644
index 0000000..48eb011
--- /dev/null
+++ b/FPGA/rx_ciccomp_sim/aldec/rivierapro_setup.tcl
@@ -0,0 +1,308 @@
+
+# (C) 2001-2021 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 18.1 625 win32 2021.02.12.17:11:14
+# ----------------------------------------
+# Auto-generated simulation script rivierapro_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# rx_ciccomp
+#
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "aldec.do", and modify the text as directed.
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR