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FPGA update

master
XGudron 2021-02-12 17:11:16 +03:00
rodzic 270f914a91
commit 02d62d223d
39 zmienionych plików z 916 dodań i 537 usunięć
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4
FPGA/DEBUG.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="DEBUG" kind="DEBUG" version="1.0" fabric="QSYS"> <EnsembleReport name="DEBUG" kind="DEBUG" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) --> <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2021.02.12.17:13:29 --> <!-- 2021.02.12.18:03:22 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID"> <parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type> <type>java.lang.Integer</type>
<value>1613135608</value> <value>1613138602</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>

4
FPGA/DEBUG2.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="DEBUG2" kind="DEBUG2" version="1.0" fabric="QSYS"> <EnsembleReport name="DEBUG2" kind="DEBUG2" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) --> <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2021.02.12.17:13:40 --> <!-- 2021.02.12.18:03:33 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID"> <parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type> <type>java.lang.Integer</type>
<value>1613135620</value> <value>1613138613</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>

22
FPGA/WOLF-LITE.bdf
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@ -2430,21 +2430,21 @@ refer to the applicable agreement for further details.
(pt 256 72) (pt 256 72)
(output) (output)
(text "out_data[31..0]" (rect 0 0 84 14)(font "Arial" (font_size 8))) (text "out_data[31..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "out_data[31..0]" (rect 183 61 254 75)(font "Arial" (font_size 8))) (text "out_data[31..0]" (rect 183 61 267 75)(font "Arial" (font_size 8)))
(line (pt 256 72)(pt 176 72)(line_width 3)) (line (pt 256 72)(pt 176 72)(line_width 3))
) )
(port (port
(pt 256 88) (pt 256 88)
(output) (output)
(text "out_error[1..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) (text "out_error[1..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "out_error[1..0]" (rect 186 77 254 91)(font "Arial" (font_size 8))) (text "out_error[1..0]" (rect 186 77 267 91)(font "Arial" (font_size 8)))
(line (pt 256 88)(pt 176 88)(line_width 3)) (line (pt 256 88)(pt 176 88)(line_width 3))
) )
(port (port
(pt 256 104) (pt 256 104)
(output) (output)
(text "out_valid" (rect 0 0 50 14)(font "Arial" (font_size 8))) (text "out_valid" (rect 0 0 50 14)(font "Arial" (font_size 8)))
(text "out_valid" (rect 210 93 252 107)(font "Arial" (font_size 8))) (text "out_valid" (rect 210 93 260 107)(font "Arial" (font_size 8)))
(line (pt 256 104)(pt 176 104)) (line (pt 256 104)(pt 176 104))
) )
(drawing (drawing
@ -2549,21 +2549,21 @@ refer to the applicable agreement for further details.
(pt 256 72) (pt 256 72)
(output) (output)
(text "out_data[31..0]" (rect 0 0 84 14)(font "Arial" (font_size 8))) (text "out_data[31..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "out_data[31..0]" (rect 183 61 254 75)(font "Arial" (font_size 8))) (text "out_data[31..0]" (rect 183 61 267 75)(font "Arial" (font_size 8)))
(line (pt 256 72)(pt 176 72)(line_width 3)) (line (pt 256 72)(pt 176 72)(line_width 3))
) )
(port (port
(pt 256 88) (pt 256 88)
(output) (output)
(text "out_error[1..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) (text "out_error[1..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "out_error[1..0]" (rect 186 77 254 91)(font "Arial" (font_size 8))) (text "out_error[1..0]" (rect 186 77 267 91)(font "Arial" (font_size 8)))
(line (pt 256 88)(pt 176 88)(line_width 3)) (line (pt 256 88)(pt 176 88)(line_width 3))
) )
(port (port
(pt 256 104) (pt 256 104)
(output) (output)
(text "out_valid" (rect 0 0 50 14)(font "Arial" (font_size 8))) (text "out_valid" (rect 0 0 50 14)(font "Arial" (font_size 8)))
(text "out_valid" (rect 210 93 252 107)(font "Arial" (font_size 8))) (text "out_valid" (rect 210 93 260 107)(font "Arial" (font_size 8)))
(line (pt 256 104)(pt 176 104)) (line (pt 256 104)(pt 176 104))
) )
(drawing (drawing
@ -2646,8 +2646,8 @@ refer to the applicable agreement for further details.
(port (port
(pt 384 72) (pt 384 72)
(output) (output)
(text "ast_source_data[45..0]" (rect 0 0 132 14)(font "Arial" (font_size 8))) (text "ast_source_data[46..0]" (rect 0 0 132 14)(font "Arial" (font_size 8)))
(text "ast_source_data[45..0]" (rect 268 61 379 75)(font "Arial" (font_size 8))) (text "ast_source_data[46..0]" (rect 268 61 379 75)(font "Arial" (font_size 8)))
(line (pt 384 72)(pt 224 72)(line_width 3)) (line (pt 384 72)(pt 224 72)(line_width 3))
) )
(port (port
@ -2738,8 +2738,8 @@ refer to the applicable agreement for further details.
(port (port
(pt 384 72) (pt 384 72)
(output) (output)
(text "ast_source_data[45..0]" (rect 0 0 132 14)(font "Arial" (font_size 8))) (text "ast_source_data[46..0]" (rect 0 0 132 14)(font "Arial" (font_size 8)))
(text "ast_source_data[45..0]" (rect 268 61 379 75)(font "Arial" (font_size 8))) (text "ast_source_data[46..0]" (rect 268 61 379 75)(font "Arial" (font_size 8)))
(line (pt 384 72)(pt 224 72)(line_width 3)) (line (pt 384 72)(pt 224 72)(line_width 3))
) )
(port (port
@ -2864,7 +2864,7 @@ refer to the applicable agreement for further details.
) )
(parameter (parameter
"in_width" "in_width"
"46" "47"
"" ""
(type "PARAMETER_SIGNED_DEC") ) (type "PARAMETER_SIGNED_DEC") )
(parameter (parameter

BIN
FPGA/WOLF-LITE.qws
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Plik binarny nie jest wyświetlany.

4
FPGA/clock_buffer.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="clock_buffer" kind="clock_buffer" version="1.0" fabric="QSYS"> <EnsembleReport name="clock_buffer" kind="clock_buffer" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) --> <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2021.02.12.17:12:31 --> <!-- 2021.02.12.18:02:21 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID"> <parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type> <type>java.lang.Integer</type>
<value>1613135551</value> <value>1613138541</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>

2
FPGA/db/WOLF-LITE.db_info
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@ -1,3 +1,3 @@
Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
Version_Index = 486699264 Version_Index = 486699264
Creation_Time = Fri Feb 12 16:12:07 2021 Creation_Time = Fri Feb 12 16:57:59 2021

4
FPGA/nco.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="nco" kind="nco" version="1.0" fabric="QSYS"> <EnsembleReport name="nco" kind="nco" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) --> <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2021.02.12.17:13:17 --> <!-- 2021.02.12.18:03:11 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID"> <parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type> <type>java.lang.Integer</type>
<value>1613135597</value> <value>1613138591</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>

4
FPGA/rx_cic.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="rx_cic" kind="rx_cic" version="1.0" fabric="QSYS"> <EnsembleReport name="rx_cic" kind="rx_cic" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) --> <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2021.02.12.17:12:42 --> <!-- 2021.02.12.18:02:33 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID"> <parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type> <type>java.lang.Integer</type>
<value>1613135562</value> <value>1613138553</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>

4
FPGA/rx_ciccomp.bsf
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@ -61,8 +61,8 @@ refer to the applicable agreement for further details.
(port (port
(pt 384 72) (pt 384 72)
(output) (output)
(text "ast_source_data[45..0]" (rect 0 0 93 12)(font "Arial" (font_size 8))) (text "ast_source_data[46..0]" (rect 0 0 93 12)(font "Arial" (font_size 8)))
(text "ast_source_data[45..0]" (rect 268 61 400 72)(font "Arial" (font_size 8))) (text "ast_source_data[46..0]" (rect 268 61 400 72)(font "Arial" (font_size 8)))
(line (pt 384 72)(pt 224 72)(line_width 3)) (line (pt 384 72)(pt 224 72)(line_width 3))
) )
(port (port

2
FPGA/rx_ciccomp.cmp
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@ -5,7 +5,7 @@
ast_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data ast_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
ast_sink_valid : in std_logic := 'X'; -- valid ast_sink_valid : in std_logic := 'X'; -- valid
ast_sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error ast_sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
ast_source_data : out std_logic_vector(45 downto 0); -- data ast_source_data : out std_logic_vector(46 downto 0); -- data
ast_source_valid : out std_logic; -- valid ast_source_valid : out std_logic; -- valid
ast_source_error : out std_logic_vector(1 downto 0) -- error ast_source_error : out std_logic_vector(1 downto 0) -- error
); );

20
FPGA/rx_ciccomp.qip
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@ -49,12 +49,12 @@ set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_C
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y2hhbm5lbE1vZGVz::MCwxLDIsMw==::Q2hhbm5lbCBNb2RlIE9yZGVy" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y2hhbm5lbE1vZGVz::MCwxLDIsMw==::Q2hhbm5lbCBNb2RlIE9yZGVy"
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "aW5wdXRUeXBl::aW50::SW5wdXQgVHlwZQ==" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "aW5wdXRUeXBl::aW50::SW5wdXQgVHlwZQ=="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "aW5wdXRCaXRXaWR0aA==::MzI=::SW5wdXQgV2lkdGg=" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "aW5wdXRCaXRXaWR0aA==::MzI=::SW5wdXQgV2lkdGg="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRSZWFsVmFsdWU=::NjE2LjA1MDUsLTEyNTQuMzQ4LDIwNzMuNzQzLC0yOTg1LjgwNiwzNjQ0Ljk0MiwtMzIxMS4yMSwzLjM2NzcwOCw4OTM1LjA1NCwtMjg0MDQuNjksNjU2NTEuMzEsLTEzMTEyNS42LDIzOTEyMS44LC00MDg2NTQuMCw2NjM5MTMuNSwtMTAzNTIyOS4wLDE1NTkwODkuMCwtMjI3OTM2MS4wLDMyNDY2OTcuMCwtNDUyMDY2MS4wLDYxNjg1NTMuMCwtODI3MDA1My4wLDEuMDkxNTk1RTcsLTEuNDIxODc4RTcsMS44MzEyOUU3LC0yLjMzNzgyNEU3LDIuOTY0MzhFNywtMy43NDMzOTZFNyw0LjcxNTM1M0U3LC01LjkyNzAwMkU3LDcuMzczMjUzRTcsLTguNzMyODU1RTcsNy44MTQ5MjhFNyw3LjgxNDkyOEU3LC04LjczMjg1NUU3LDcuMzczMjUzRTcsLTUuOTI3MDAyRTcsNC43MTUzNTNFNywtMy43NDMzOTZFNywyLjk2NDM4RTcsLTIuMzM3ODI0RTcsMS44MzEyOUU3LC0xLjQyMTg3OEU3LDEuMDkxNTk1RTcsLTgyNzAwNTMuMCw2MTY4NTUzLjAsLTQ1MjA2NjEuMCwzMjQ2Njk3LjAsLTIyNzkzNjEuMCwxNTU5MDg5LjAsLTEwMzUyMjkuMCw2NjM5MTMuNSwtNDA4NjU0LjAsMjM5MTIxLjgsLTEzMTEyNS42LDY1NjUxLjMxLC0yODQwNC42OSw4OTM1LjA1NCwzLjM2NzcwOCwtMzIxMS4yMSwzNjQ0Ljk0MiwtMjk4NS44MDYsMjA3My43NDMsLTEyNTQuMzQ4LDYxNi4wNTA1::UmVhbCBDb2VmZmljaWVudCBWYWx1ZXM=" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRSZWFsVmFsdWU=::MzcuNTc3NywtOTIuNzQ4MzUsMTk0LjYzMSwtMzgwLjgzOTUsNzEyLjk3MzQsLTEyODguNzgyLDIyNTQuMTUxLC0zODI1LjE0OCw2MzAzLjgzMywtMTAxMTguNDUsMTU4MzkuNzksLTI0MjU3LjExLDM2Mzg2Ljk2LC01MzYyMS44OSw3NzcxNy4wNCwtMTExMDg4LjcsMTU2NzU5LjksLTIxODk2OS4wLDMwMzA3MC45LC00MTY4MDYuMyw1NzAyNTcuMCwtNzc4NjExLjMsMTA2MjczNy4wLC0xNDU1NzU1LjAsMjAwNjgzNi4wLC0yNzk5NDEzLjAsMzk3MDc4MC4wLC01Nzc1OTczLjAsODY5Mzc0OC4wLC0xLjM3Mjk5NkU3LDIuMzA3NjIyRTcsLTQuMTc0NDgzRTcsNy43MDAwOTVFNywtNC4xNzQ0ODNFNywyLjMwNzYyMkU3LC0xLjM3Mjk5NkU3LDg2OTM3NDguMCwtNTc3NTk3My4wLDM5NzA3ODAuMCwtMjc5OTQxMy4wLDIwMDY4MzYuMCwtMTQ1NTc1NS4wLDEwNjI3MzcuMCwtNzc4NjExLjMsNTcwMjU3LjAsLTQxNjgwNi4zLDMwMzA3MC45LC0yMTg5NjkuMCwxNTY3NTkuOSwtMTExMDg4LjcsNzc3MTcuMDQsLTUzNjIxLjg5LDM2Mzg2Ljk2LC0yNDI1Ny4xMSwxNTgzOS43OSwtMTAxMTguNDUsNjMwMy44MzMsLTM4MjUuMTQ4LDIyNTQuMTUxLC0xMjg4Ljc4Miw3MTIuOTczNCwtMzgwLjgzOTUsMTk0LjYzMSwtOTIuNzQ4MzUsMzcuNTc3Nw==::UmVhbCBDb2VmZmljaWVudCBWYWx1ZXM="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZOdW0=::NjQ=::TnVtYmVyIG9mIENvZWZmaWNpZW50cw==" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZOdW0=::NjU=::TnVtYmVyIG9mIENvZWZmaWNpZW50cw=="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRSZWFsVmFsdWVJbWFn::MC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgLTAuMDUzMDA5MywgLTAuMDQ0OTgsIDAuMCwgMC4wNzQ5NjkzLCAwLjE1OTAzNCwgMC4yMjQ5MDcsIDAuMjQ5ODA5LCAwLjIyNDkwNywgMC4xNTkwMzQsIDAuMDc0OTY5MywgMC4wLCAtMC4wNDQ5OCwgLTAuMDUzMDA5MywgLTAuMDMyMTI4MywgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjA=::UmVhbCBDb2VmZmljaWVudCBWYWx1ZXMgKEltYWdpbmFyeSBDb21wb25lbnQp" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRSZWFsVmFsdWVJbWFn::MC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgLTAuMDUzMDA5MywgLTAuMDQ0OTgsIDAuMCwgMC4wNzQ5NjkzLCAwLjE1OTAzNCwgMC4yMjQ5MDcsIDAuMjQ5ODA5LCAwLjIyNDkwNywgMC4xNTkwMzQsIDAuMDc0OTY5MywgMC4wLCAtMC4wNDQ5OCwgLTAuMDUzMDA5MywgLTAuMDMyMTI4MywgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjA=::UmVhbCBDb2VmZmljaWVudCBWYWx1ZXMgKEltYWdpbmFyeSBDb21wb25lbnQp"
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRTY2FsZVZhbHVl::MC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwtNjgyMjU0LjI5Njg3NSwxMzY0NTA4LjU5Mzc1LC0yMDQ2NzYyLjg5MDYyNSwyNzI5MDE3LjE4NzUsLTQwOTM1MjUuNzgxMjUsNjE0MDI4OC42NzE4NzUsLTgxODcwNTEuNTYyNSwxMDIzMzgxNC40NTMxMjUsLTEzNjQ1MDg1LjkzNzUsMTc3Mzg2MTEuNzE4NzUsLTIzMTk2NjQ2LjA5Mzc1LDI5MzM2OTM0Ljc2NTYyNSwtMzY4NDE3MzIuMDMxMjUsNDcwNzU1NDYuNDg0Mzc1LC01ODY3Mzg2OS41MzEyNSw3MzY4MzQ2NC4wNjI1LC04NzMyODU1MC4wLDc3Nzc2OTg5Ljg0Mzc1LDc3Nzc2OTg5Ljg0Mzc1LC04NzMyODU1MC4wLDczNjgzNDY0LjA2MjUsLTU4NjczODY5LjUzMTI1LDQ3MDc1NTQ2LjQ4NDM3NSwtMzY4NDE3MzIuMDMxMjUsMjkzMzY5MzQuNzY1NjI1LC0yMzE5NjY0Ni4wOTM3NSwxNzczODYxMS43MTg3NSwtMTM2NDUwODUuOTM3NSwxMDIzMzgxNC40NTMxMjUsLTgxODcwNTEuNTYyNSw2MTQwMjg4LjY3MTg3NSwtNDA5MzUyNS43ODEyNSwyNzI5MDE3LjE4NzUsLTIwNDY3NjIuODkwNjI1LDEzNjQ1MDguNTkzNzUsLTY4MjI1NC4yOTY4NzUsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMA==::U2NhbGVkIENvZWZmaWNpZW50IFZhbHVlcw==" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRTY2FsZVZhbHVl::MC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsLTYwNjMwNi42OTI5MTMzODU4LDYwNjMwNi42OTI5MTMzODU4LC0xMjEyNjEzLjM4NTgyNjc3MTYsMTgxODkyMC4wNzg3NDAxNTc0LC0yNDI1MjI2Ljc3MTY1MzU0MywzNjM3ODQwLjE1NzQ4MDMxNSwtNTQ1Njc2MC4yMzYyMjA0NzI1LDg0ODgyOTMuNzAwNzg3NCwtMTMzMzg3NDcuMjQ0MDk0NDg3LDIzMDM5NjU0LjMzMDcwODY2LC00MTIyODg1NS4xMTgxMTAyMyw3NzAwMDk1MC4wLC00MTIyODg1NS4xMTgxMTAyMywyMzAzOTY1NC4zMzA3MDg2NiwtMTMzMzg3NDcuMjQ0MDk0NDg3LDg0ODgyOTMuNzAwNzg3NCwtNTQ1Njc2MC4yMzYyMjA0NzI1LDM2Mzc4NDAuMTU3NDgwMzE1LC0yNDI1MjI2Ljc3MTY1MzU0MywxODE4OTIwLjA3ODc0MDE1NzQsLTEyMTI2MTMuMzg1ODI2NzcxNiw2MDYzMDYuNjkyOTEzMzg1OCwtNjA2MzA2LjY5MjkxMzM4NTgsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMCwwLjA=::U2NhbGVkIENvZWZmaWNpZW50IFZhbHVlcw=="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRTY2FsZVZhbHVlSW1hZw==::MC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMA==::U2NhbGVkIENvZWZmaWNpZW50IFZhbHVlcyAoSW1hZ2luYXJ5IENvbXBvbmVudCk=" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRTY2FsZVZhbHVlSW1hZw==::MC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMA==::U2NhbGVkIENvZWZmaWNpZW50IFZhbHVlcyAoSW1hZ2luYXJ5IENvbXBvbmVudCk="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRGaXhlZFZhbHVl::MCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMCwwLC0xLDIsLTMsNCwtNiw5LC0xMiwxNSwtMjAsMjYsLTM0LDQzLC01NCw2OSwtODYsMTA4LC0xMjgsMTE0LDExNCwtMTI4LDEwOCwtODYsNjksLTU0LDQzLC0zNCwyNiwtMjAsMTUsLTEyLDksLTYsNCwtMywyLC0xLDAsMCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMA==::Rml4ZWQtcG9pbnQgQ29lZmZpY2llbnQgVmFsdWVz" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRGaXhlZFZhbHVl::MCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsLTEsMSwtMiwzLC00LDYsLTksMTQsLTIyLDM4LC02OCwxMjcsLTY4LDM4LC0yMiwxNCwtOSw2LC00LDMsLTIsMSwtMSwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMCwwLDAsMA==::Rml4ZWQtcG9pbnQgQ29lZmZpY2llbnQgVmFsdWVz"
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRGaXhlZFZhbHVlSW1hZw==::MCwwLDAsMCwwLDAsMCww::Rml4ZWQtcG9pbnQgQ29lZmZpY2llbnQgVmFsdWVzIChJbWFnaW5hcnkgQ29tcG9uZW50KQ==" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRGaXhlZFZhbHVlSW1hZw==::MCwwLDAsMCwwLDAsMCww::Rml4ZWQtcG9pbnQgQ29lZmZpY2llbnQgVmFsdWVzIChJbWFnaW5hcnkgQ29tcG9uZW50KQ=="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTY2FsaW5n::YXV0bw==::Q29lZmZpY2llbnQgU2NhbGluZw==" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZTY2FsaW5n::YXV0bw==::Q29lZmZpY2llbnQgU2NhbGluZw=="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZUeXBl::aW50::Q29lZmZpY2llbnQgRGF0YSBUeXBl" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y29lZmZUeXBl::aW50::Q29lZmZpY2llbnQgRGF0YSBUeXBl"
@ -70,16 +70,16 @@ set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_C
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "b3V0cHV0SW50ZXJmYWNlTnVt::MQ==::TnVtYmVyIG9mIFBhcmFsbGVsIE91dHB1dCBTeW1ib2xz" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "b3V0cHV0SW50ZXJmYWNlTnVt::MQ==::TnVtYmVyIG9mIFBhcmFsbGVsIE91dHB1dCBTeW1ib2xz"
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y2hhblBlcklucHV0SW50ZXJmYWNl::MQ==::TnVtYmVyIG9mIENoYW5uZWxzIHBlciBJbnB1dCBJbnRlcmZhY2U=" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y2hhblBlcklucHV0SW50ZXJmYWNl::MQ==::TnVtYmVyIG9mIENoYW5uZWxzIHBlciBJbnB1dCBJbnRlcmZhY2U="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y2hhblBlck91dHB1dEludGVyZmFjZQ==::MQ==::TnVtYmVyIG9mIENoYW5uZWxzIHBlciBPdXRwdXQgSW50ZXJmYWNl" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "Y2hhblBlck91dHB1dEludGVyZmFjZQ==::MQ==::TnVtYmVyIG9mIENoYW5uZWxzIHBlciBPdXRwdXQgSW50ZXJmYWNl"
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeQ==::MTc=::bGF0ZW5jeQ==" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeQ==::MTk=::bGF0ZW5jeQ=="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "b3V0cHV0Zmlmb2RlcHRo::NA==::b3V0cHV0Zmlmb2RlcHRo" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "b3V0cHV0Zmlmb2RlcHRo::NA==::b3V0cHV0Zmlmb2RlcHRo"
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "ZnVuY1Jlc3VsdA==::LWludGVycD0xIC1kZWNpbT0xIC1pbmN5Y2xlcz0xMzQwIC1sZW49NjQgLWJhbmtjb3VudD0xIC1uc3ltIC1uYmFuZD0xIC1jaGFucz0xIC1mYW1pbHk9IkN5Y2xvbmUgSVYgRSIgCnx7fXwxfDF8MXwxfDQ2fDMxfDE3fDN8bm9Db2RlfExVVFM6IDI5OSBEU1BzOiAyIFJBTSBCaXRzOiAyMDQ4fA==::ZnVuY1Jlc3VsdA==" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "ZnVuY1Jlc3VsdA==::LWludGVycD0xIC1kZWNpbT0xIC1pbmN5Y2xlcz0xMzQwIC1sZW49NjUgLWJhbmtjb3VudD0xIC1uc3ltIC1uYmFuZD0xIC1jaGFucz0xIC1mYW1pbHk9IkN5Y2xvbmUgSVYgRSIgCnx7fXwxfDF8MXwxfDQ3fDMxfDE5fDN8bm9Db2RlfExVVFM6IDM1NCBEU1BzOiAyIFJBTSBCaXRzOiA1MTM2fA==::ZnVuY1Jlc3VsdA=="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "YnVzQWRkcmVzc1dpZHRo::Ng==::YnVzQWRkcmVzc1dpZHRo" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "YnVzQWRkcmVzc1dpZHRo::Nw==::YnVzQWRkcmVzc1dpZHRo"
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "YmFua0NvdW50::MQ==::TnVtYmVyIG9mIENvZWZmaWNpZW50IEJhbmtz" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "YmFua0NvdW50::MQ==::TnVtYmVyIG9mIENvZWZmaWNpZW50IEJhbmtz"
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "YmFua0luV2lkdGg=::MA==::YmFua0luV2lkdGg=" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "YmFua0luV2lkdGg=::MA==::YmFua0luV2lkdGg="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "YmFua0Rpc3BsYXk=::MA==::YmFua0Rpc3BsYXk=" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "YmFua0Rpc3BsYXk=::MA==::YmFua0Rpc3BsYXk="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "bHV0Q291bnQ=::Mjk5::TnVtYmVyIG9mIExVVHM=" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "bHV0Q291bnQ=::MzU0::TnVtYmVyIG9mIExVVHM="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "ZHNwQ291bnQ=::Mg==::TnVtYmVyIG9mIERTUHM=" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "ZHNwQ291bnQ=::Mg==::TnVtYmVyIG9mIERTUHM="
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "bWVtQml0Q291bnQ=::MjA0OA==::TnVtYmVyIG9mIE1lbW9yeSBCaXRz" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "bWVtQml0Q291bnQ=::NTEzNg==::TnVtYmVyIG9mIE1lbW9yeSBCaXRz"
set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "ZXJyb3JMaXN0::MA==::ZXJyb3JMaXN0" set_global_assignment -entity "rx_ciccomp_0002" -library "rx_ciccomp" -name IP_COMPONENT_PARAMETER "ZXJyb3JMaXN0::MA==::ZXJyb3JMaXN0"
set_global_assignment -library "rx_ciccomp" -name VERILOG_FILE [file join $::quartus(qip_path) "rx_ciccomp.v"] set_global_assignment -library "rx_ciccomp" -name VERILOG_FILE [file join $::quartus(qip_path) "rx_ciccomp.v"]
@ -92,6 +92,8 @@ set_global_assignment -library "rx_ciccomp" -name VHDL_FILE [file join $::quartu
set_global_assignment -library "rx_ciccomp" -name VHDL_FILE [file join $::quartus(qip_path) "rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd"] set_global_assignment -library "rx_ciccomp" -name VHDL_FILE [file join $::quartus(qip_path) "rx_ciccomp/auk_dspip_avalon_streaming_source_hpfir.vhd"]
set_global_assignment -library "rx_ciccomp" -name VHDL_FILE [file join $::quartus(qip_path) "rx_ciccomp/auk_dspip_roundsat_hpfir.vhd"] set_global_assignment -library "rx_ciccomp" -name VHDL_FILE [file join $::quartus(qip_path) "rx_ciccomp/auk_dspip_roundsat_hpfir.vhd"]
set_global_assignment -library "rx_ciccomp" -name VERILOG_FILE [file join $::quartus(qip_path) "rx_ciccomp/altera_avalon_sc_fifo.v"] set_global_assignment -library "rx_ciccomp" -name VERILOG_FILE [file join $::quartus(qip_path) "rx_ciccomp/altera_avalon_sc_fifo.v"]
set_global_assignment -library "rx_ciccomp" -name SOURCE_FILE [file join $::quartus(qip_path) "rx_ciccomp/rx_ciccomp_0002_rtl_core_u0_m0_wo0_cm0_lutmem.hex"]
set_global_assignment -library "rx_ciccomp" -name SOURCE_FILE [file join $::quartus(qip_path) "rx_ciccomp/rx_ciccomp_0002_rtl_core_u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem.hex"]
set_global_assignment -library "rx_ciccomp" -name VHDL_FILE [file join $::quartus(qip_path) "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd"] set_global_assignment -library "rx_ciccomp" -name VHDL_FILE [file join $::quartus(qip_path) "rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd"]
set_global_assignment -library "rx_ciccomp" -name VHDL_FILE [file join $::quartus(qip_path) "rx_ciccomp/rx_ciccomp_0002_ast.vhd"] set_global_assignment -library "rx_ciccomp" -name VHDL_FILE [file join $::quartus(qip_path) "rx_ciccomp/rx_ciccomp_0002_ast.vhd"]
set_global_assignment -library "rx_ciccomp" -name VHDL_FILE [file join $::quartus(qip_path) "rx_ciccomp/rx_ciccomp_0002.vhd"] set_global_assignment -library "rx_ciccomp" -name VHDL_FILE [file join $::quartus(qip_path) "rx_ciccomp/rx_ciccomp_0002.vhd"]

2
FPGA/rx_ciccomp.sip
Wyświetl plik

@ -12,6 +12,8 @@ set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::qu
set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/auk_dspip_avalon_streaming_source_hpfir.vhd"] set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/auk_dspip_avalon_streaming_source_hpfir.vhd"]
set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/auk_dspip_roundsat_hpfir.vhd"] set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/auk_dspip_roundsat_hpfir.vhd"]
set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/altera_avalon_sc_fifo.v"] set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/altera_avalon_sc_fifo.v"]
set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_rtl_core_u0_m0_wo0_cm0_lutmem.hex"]
set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_rtl_core_u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem.hex"]
set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_rtl_core.vhd"] set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_rtl_core.vhd"]
set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_ast.vhd"] set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp_ast.vhd"]
set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp.vhd"] set_global_assignment -library "lib_rx_ciccomp" -name MISC_FILE [file join $::quartus(sip_path) "rx_ciccomp_sim/rx_ciccomp.vhd"]

6
FPGA/rx_ciccomp.spd
Wyświetl plik

@ -15,6 +15,12 @@
type="VHDL" /> type="VHDL" />
<file path="rx_ciccomp_sim/auk_dspip_roundsat_hpfir.vhd" type="VHDL" /> <file path="rx_ciccomp_sim/auk_dspip_roundsat_hpfir.vhd" type="VHDL" />
<file path="rx_ciccomp_sim/altera_avalon_sc_fifo.v" type="VERILOG" /> <file path="rx_ciccomp_sim/altera_avalon_sc_fifo.v" type="VERILOG" />
<file
path="rx_ciccomp_sim/rx_ciccomp_rtl_core_u0_m0_wo0_cm0_lutmem.hex"
type="HEX" />
<file
path="rx_ciccomp_sim/rx_ciccomp_rtl_core_u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem.hex"
type="HEX" />
<file path="rx_ciccomp_sim/rx_ciccomp_rtl_core.vhd" type="VHDL" /> <file path="rx_ciccomp_sim/rx_ciccomp_rtl_core.vhd" type="VHDL" />
<file path="rx_ciccomp_sim/rx_ciccomp_ast.vhd" type="VHDL" /> <file path="rx_ciccomp_sim/rx_ciccomp_ast.vhd" type="VHDL" />
<file path="rx_ciccomp_sim/rx_ciccomp.vhd" type="VHDL" /> <file path="rx_ciccomp_sim/rx_ciccomp.vhd" type="VHDL" />

4
FPGA/rx_ciccomp.v
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@ -11,7 +11,7 @@ module rx_ciccomp (
input wire [31:0] ast_sink_data, // avalon_streaming_sink.data input wire [31:0] ast_sink_data, // avalon_streaming_sink.data
input wire ast_sink_valid, // .valid input wire ast_sink_valid, // .valid
input wire [1:0] ast_sink_error, // .error input wire [1:0] ast_sink_error, // .error
output wire [45:0] ast_source_data, // avalon_streaming_source.data output wire [46:0] ast_source_data, // avalon_streaming_source.data
output wire ast_source_valid, // .valid output wire ast_source_valid, // .valid
output wire [1:0] ast_source_error // .error output wire [1:0] ast_source_error // .error
); );
@ -82,7 +82,7 @@ endmodule
// Retrieval info: <generic name="inputType" value="int" /> // Retrieval info: <generic name="inputType" value="int" />
// Retrieval info: <generic name="inputBitWidth" value="32" /> // Retrieval info: <generic name="inputBitWidth" value="32" />
// Retrieval info: <generic name="inputFracBitWidth" value="0" /> // Retrieval info: <generic name="inputFracBitWidth" value="0" />
// Retrieval info: <generic name="coeffSetRealValue" value="616.0505,-1254.348,2073.743,-2985.806,3644.942,-3211.21,3.367708,8935.054,-28404.69,65651.31,-131125.6,239121.8,-408654.0,663913.5,-1035229.0,1559089.0,-2279361.0,3246697.0,-4520661.0,6168553.0,-8270053.0,1.091595E7,-1.421878E7,1.83129E7,-2.337824E7,2.96438E7,-3.743396E7,4.715353E7,-5.927002E7,7.373253E7,-8.732855E7,7.814928E7,7.814928E7,-8.732855E7,7.373253E7,-5.927002E7,4.715353E7,-3.743396E7,2.96438E7,-2.337824E7,1.83129E7,-1.421878E7,1.091595E7,-8270053.0,6168553.0,-4520661.0,3246697.0,-2279361.0,1559089.0,-1035229.0,663913.5,-408654.0,239121.8,-131125.6,65651.31,-28404.69,8935.054,3.367708,-3211.21,3644.942,-2985.806,2073.743,-1254.348,616.0505" /> // Retrieval info: <generic name="coeffSetRealValue" value="37.5777,-92.74835,194.631,-380.8395,712.9734,-1288.782,2254.151,-3825.148,6303.833,-10118.45,15839.79,-24257.11,36386.96,-53621.89,77717.04,-111088.7,156759.9,-218969.0,303070.9,-416806.3,570257.0,-778611.3,1062737.0,-1455755.0,2006836.0,-2799413.0,3970780.0,-5775973.0,8693748.0,-1.372996E7,2.307622E7,-4.174483E7,7.700095E7,-4.174483E7,2.307622E7,-1.372996E7,8693748.0,-5775973.0,3970780.0,-2799413.0,2006836.0,-1455755.0,1062737.0,-778611.3,570257.0,-416806.3,303070.9,-218969.0,156759.9,-111088.7,77717.04,-53621.89,36386.96,-24257.11,15839.79,-10118.45,6303.833,-3825.148,2254.151,-1288.782,712.9734,-380.8395,194.631,-92.74835,37.5777" />
// Retrieval info: <generic name="coeffSetRealValueImag" value="0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, -0.0530093, -0.04498, 0.0, 0.0749693, 0.159034, 0.224907, 0.249809, 0.224907, 0.159034, 0.0749693, 0.0, -0.04498, -0.0530093, -0.0321283, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0" /> // Retrieval info: <generic name="coeffSetRealValueImag" value="0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, -0.0530093, -0.04498, 0.0, 0.0749693, 0.159034, 0.224907, 0.249809, 0.224907, 0.159034, 0.0749693, 0.0, -0.04498, -0.0530093, -0.0321283, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0" />
// Retrieval info: <generic name="coeffScaling" value="auto" /> // Retrieval info: <generic name="coeffScaling" value="auto" />
// Retrieval info: <generic name="coeffType" value="int" /> // Retrieval info: <generic name="coeffType" value="int" />

4
FPGA/rx_ciccomp/rx_ciccomp_0002.vhd
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@ -23,7 +23,7 @@ entity rx_ciccomp_0002 is
ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*32) * 1 + 0 - 1 downto 0); ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*32) * 1 + 0 - 1 downto 0);
ast_sink_valid : in STD_LOGIC; ast_sink_valid : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0); ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
ast_source_data : out STD_LOGIC_VECTOR(46 * 1*1 - 1 downto 0); ast_source_data : out STD_LOGIC_VECTOR(47 * 1*1 - 1 downto 0);
ast_source_valid : out STD_LOGIC; ast_source_valid : out STD_LOGIC;
ast_source_error : out STD_LOGIC_VECTOR(1 downto 0) ast_source_error : out STD_LOGIC_VECTOR(1 downto 0)
); );
@ -41,7 +41,7 @@ architecture syn of rx_ciccomp_0002 is
ast_sink_sop : in STD_LOGIC; ast_sink_sop : in STD_LOGIC;
ast_sink_eop : in STD_LOGIC; ast_sink_eop : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0); ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
ast_source_data : out STD_LOGIC_VECTOR(1*46 * 1 - 1 downto 0); ast_source_data : out STD_LOGIC_VECTOR(1*47 * 1 - 1 downto 0);
ast_source_ready : in STD_LOGIC; ast_source_ready : in STD_LOGIC;
ast_source_valid : out STD_LOGIC; ast_source_valid : out STD_LOGIC;
ast_source_sop : out STD_LOGIC; ast_source_sop : out STD_LOGIC;

6
FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd
Wyświetl plik

@ -9,7 +9,7 @@ use work.auk_dspip_math_pkg_hpfir.all;
entity rx_ciccomp_0002_ast is entity rx_ciccomp_0002_ast is
generic ( generic (
INWIDTH : integer := 32; INWIDTH : integer := 32;
OUT_WIDTH_UNTRIMMED : integer := 46; OUT_WIDTH_UNTRIMMED : integer := 47;
BANKINWIDTH : integer := 0; BANKINWIDTH : integer := 0;
REM_LSB_BIT_g : integer := 0; REM_LSB_BIT_g : integer := 0;
REM_LSB_TYPE_g : string := "round"; REM_LSB_TYPE_g : string := "round";
@ -197,7 +197,7 @@ real_passthrough : if COMPLEX_CONST = 1 generate
xIn_0 : in std_logic_vector(32 - 1 downto 0); xIn_0 : in std_logic_vector(32 - 1 downto 0);
xOut_v : out std_logic_vector(0 downto 0); xOut_v : out std_logic_vector(0 downto 0);
xOut_c : out std_logic_vector(7 downto 0); xOut_c : out std_logic_vector(7 downto 0);
xOut_0 : out std_logic_vector(46- 1 downto 0); xOut_0 : out std_logic_vector(47- 1 downto 0);
clk : in std_logic; clk : in std_logic;
areset : in std_logic areset : in std_logic
); );
@ -222,7 +222,7 @@ end component rx_ciccomp_0002_rtl_core;
xIn_0 => data_in_core((0 + 32) * 0 + 32 - 1 downto (0 + 32) * 0), xIn_0 => data_in_core((0 + 32) * 0 + 32 - 1 downto (0 + 32) * 0),
xOut_v => core_out_valid_core, xOut_v => core_out_valid_core,
xOut_c => core_out_channel_core, xOut_c => core_out_channel_core,
xOut_0 => core_out_core(46* 0 + 46- 1 downto 46* 0), xOut_0 => core_out_core(47* 0 + 47- 1 downto 47* 0),
clk => clk, clk => clk,
areset => reset_fir areset => reset_fir
); );

407
FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core.vhd
Wyświetl plik

@ -16,7 +16,7 @@
-- --------------------------------------------------------------------------- -- ---------------------------------------------------------------------------
-- VHDL created from rx_ciccomp_0002_rtl_core -- VHDL created from rx_ciccomp_0002_rtl_core
-- VHDL created on Fri Feb 12 16:11:12 2021 -- VHDL created on Fri Feb 12 16:50:50 2021
library IEEE; library IEEE;
@ -38,7 +38,7 @@ entity rx_ciccomp_0002_rtl_core is
xIn_0 : in std_logic_vector(31 downto 0); -- sfix32 xIn_0 : in std_logic_vector(31 downto 0); -- sfix32
xOut_v : out std_logic_vector(0 downto 0); -- ufix1 xOut_v : out std_logic_vector(0 downto 0); -- ufix1
xOut_c : out std_logic_vector(7 downto 0); -- ufix8 xOut_c : out std_logic_vector(7 downto 0); -- ufix8
xOut_0 : out std_logic_vector(45 downto 0); -- sfix46 xOut_0 : out std_logic_vector(46 downto 0); -- sfix47
clk : in std_logic; clk : in std_logic;
areset : in std_logic areset : in std_logic
); );
@ -51,8 +51,8 @@ architecture normal of rx_ciccomp_0002_rtl_core is
signal GND_q : STD_LOGIC_VECTOR (0 downto 0); signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0); signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal d_xIn_0_13_q : STD_LOGIC_VECTOR (31 downto 0); signal d_xIn_0_15_q : STD_LOGIC_VECTOR (31 downto 0);
signal d_in0_m0_wi0_wo0_assign_id1_q_13_q : STD_LOGIC_VECTOR (0 downto 0); signal d_in0_m0_wi0_wo0_assign_id1_q_15_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_run_count : STD_LOGIC_VECTOR (1 downto 0); signal u0_m0_wo0_run_count : STD_LOGIC_VECTOR (1 downto 0);
signal u0_m0_wo0_run_preEnaQ : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_run_preEnaQ : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_run_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_run_q : STD_LOGIC_VECTOR (0 downto 0);
@ -60,46 +60,64 @@ architecture normal of rx_ciccomp_0002_rtl_core is
signal u0_m0_wo0_run_enableQ : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_run_enableQ : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_run_ctrl : STD_LOGIC_VECTOR (2 downto 0); signal u0_m0_wo0_run_ctrl : STD_LOGIC_VECTOR (2 downto 0);
signal u0_m0_wo0_memread_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_memread_q : STD_LOGIC_VECTOR (0 downto 0);
signal d_u0_m0_wo0_memread_q_13_q : STD_LOGIC_VECTOR (0 downto 0);
signal d_u0_m0_wo0_memread_q_14_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_compute_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_compute_q : STD_LOGIC_VECTOR (0 downto 0);
signal d_u0_m0_wo0_compute_q_15_q : STD_LOGIC_VECTOR (0 downto 0); signal d_u0_m0_wo0_compute_q_17_q : STD_LOGIC_VECTOR (0 downto 0);
signal d_u0_m0_wo0_compute_q_16_q : STD_LOGIC_VECTOR (0 downto 0); signal d_u0_m0_wo0_compute_q_18_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count0_inner_q : STD_LOGIC_VECTOR (6 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count0_inner_q : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count0_inner_i : SIGNED (6 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count0_inner_i : SIGNED (6 downto 0);
attribute preserve : boolean; attribute preserve : boolean;
attribute preserve of u0_m0_wo0_wi0_r0_ra0_count0_inner_i : signal is true; attribute preserve of u0_m0_wo0_wi0_r0_ra0_count0_inner_i : signal is true;
signal u0_m0_wo0_wi0_r0_ra0_count0_q : STD_LOGIC_VECTOR (6 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count0_q : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count0_i : UNSIGNED (5 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count0_i : UNSIGNED (6 downto 0);
attribute preserve of u0_m0_wo0_wi0_r0_ra0_count0_i : signal is true; attribute preserve of u0_m0_wo0_wi0_r0_ra0_count0_i : signal is true;
signal u0_m0_wo0_wi0_r0_ra0_count1_lutreg_q : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count1_q : STD_LOGIC_VECTOR (6 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count1_q : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count1_i : UNSIGNED (5 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count1_i : UNSIGNED (6 downto 0);
attribute preserve of u0_m0_wo0_wi0_r0_ra0_count1_i : signal is true; attribute preserve of u0_m0_wo0_wi0_r0_ra0_count1_i : signal is true;
signal u0_m0_wo0_wi0_r0_ra0_add_0_0_a : STD_LOGIC_VECTOR (7 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count1_eq : std_logic;
signal u0_m0_wo0_wi0_r0_ra0_add_0_0_b : STD_LOGIC_VECTOR (7 downto 0); attribute preserve of u0_m0_wo0_wi0_r0_ra0_count1_eq : signal is true;
signal u0_m0_wo0_wi0_r0_ra0_add_0_0_o : STD_LOGIC_VECTOR (7 downto 0); signal u0_m0_wo0_wi0_r0_ra0_add_0_0_a : STD_LOGIC_VECTOR (8 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_add_0_0_q : STD_LOGIC_VECTOR (7 downto 0); signal u0_m0_wo0_wi0_r0_ra0_add_0_0_b : STD_LOGIC_VECTOR (8 downto 0);
signal u0_m0_wo0_wi0_r0_wa0_q : STD_LOGIC_VECTOR (5 downto 0); signal u0_m0_wo0_wi0_r0_ra0_add_0_0_o : STD_LOGIC_VECTOR (8 downto 0);
signal u0_m0_wo0_wi0_r0_wa0_i : UNSIGNED (5 downto 0); signal u0_m0_wo0_wi0_r0_ra0_add_0_0_q : STD_LOGIC_VECTOR (8 downto 0);
signal u0_m0_wo0_wi0_r0_wa0_q : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_wa0_i : UNSIGNED (6 downto 0);
attribute preserve of u0_m0_wo0_wi0_r0_wa0_i : signal is true; attribute preserve of u0_m0_wo0_wi0_r0_wa0_i : signal is true;
signal u0_m0_wo0_wi0_r0_memr0_reset0 : std_logic; signal u0_m0_wo0_wi0_r0_memr0_reset0 : std_logic;
signal u0_m0_wo0_wi0_r0_memr0_ia : STD_LOGIC_VECTOR (31 downto 0); signal u0_m0_wo0_wi0_r0_memr0_ia : STD_LOGIC_VECTOR (31 downto 0);
signal u0_m0_wo0_wi0_r0_memr0_aa : STD_LOGIC_VECTOR (5 downto 0); signal u0_m0_wo0_wi0_r0_memr0_aa : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_memr0_ab : STD_LOGIC_VECTOR (5 downto 0); signal u0_m0_wo0_wi0_r0_memr0_ab : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_memr0_iq : STD_LOGIC_VECTOR (31 downto 0); signal u0_m0_wo0_wi0_r0_memr0_iq : STD_LOGIC_VECTOR (31 downto 0);
signal u0_m0_wo0_wi0_r0_memr0_q : STD_LOGIC_VECTOR (31 downto 0); signal u0_m0_wo0_wi0_r0_memr0_q : STD_LOGIC_VECTOR (31 downto 0);
signal u0_m0_wo0_ca0_q : STD_LOGIC_VECTOR (5 downto 0); signal u0_m0_wo0_ca0_q : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_ca0_i : UNSIGNED (5 downto 0); signal u0_m0_wo0_ca0_i : UNSIGNED (6 downto 0);
attribute preserve of u0_m0_wo0_ca0_i : signal is true; attribute preserve of u0_m0_wo0_ca0_i : signal is true;
signal u0_m0_wo0_cm0_q : STD_LOGIC_VECTOR (7 downto 0); signal u0_m0_wo0_ca0_eq : std_logic;
attribute preserve of u0_m0_wo0_ca0_eq : signal is true;
signal u0_m0_wo0_aseq_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_aseq_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_aseq_eq : std_logic; signal u0_m0_wo0_aseq_eq : std_logic;
signal u0_m0_wo0_accum_a : STD_LOGIC_VECTOR (45 downto 0); signal u0_m0_wo0_accum_a : STD_LOGIC_VECTOR (46 downto 0);
signal u0_m0_wo0_accum_b : STD_LOGIC_VECTOR (45 downto 0); signal u0_m0_wo0_accum_b : STD_LOGIC_VECTOR (46 downto 0);
signal u0_m0_wo0_accum_i : STD_LOGIC_VECTOR (45 downto 0); signal u0_m0_wo0_accum_i : STD_LOGIC_VECTOR (46 downto 0);
signal u0_m0_wo0_accum_o : STD_LOGIC_VECTOR (45 downto 0); signal u0_m0_wo0_accum_o : STD_LOGIC_VECTOR (46 downto 0);
signal u0_m0_wo0_accum_q : STD_LOGIC_VECTOR (45 downto 0); signal u0_m0_wo0_accum_q : STD_LOGIC_VECTOR (46 downto 0);
signal u0_m0_wo0_oseq_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_oseq_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_oseq_eq : std_logic; signal u0_m0_wo0_oseq_eq : std_logic;
signal u0_m0_wo0_oseq_gated_reg_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_oseq_gated_reg_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_reset0 : std_logic;
signal u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_ia : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_aa : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_ab : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_ir : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_r : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_cm0_lutmem_reset0 : std_logic;
signal u0_m0_wo0_cm0_lutmem_ia : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_cm0_lutmem_aa : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_cm0_lutmem_ab : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_cm0_lutmem_ir : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_cm0_lutmem_r : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_mtree_mult1_0_im0_a0 : STD_LOGIC_VECTOR (17 downto 0); signal u0_m0_wo0_mtree_mult1_0_im0_a0 : STD_LOGIC_VECTOR (17 downto 0);
signal u0_m0_wo0_mtree_mult1_0_im0_b0 : STD_LOGIC_VECTOR (7 downto 0); signal u0_m0_wo0_mtree_mult1_0_im0_b0 : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_mtree_mult1_0_im0_s1 : STD_LOGIC_VECTOR (25 downto 0); signal u0_m0_wo0_mtree_mult1_0_im0_s1 : STD_LOGIC_VECTOR (25 downto 0);
@ -116,8 +134,8 @@ architecture normal of rx_ciccomp_0002_rtl_core is
signal u0_m0_wo0_mtree_mult1_0_result_add_0_0_q : STD_LOGIC_VECTOR (40 downto 0); signal u0_m0_wo0_mtree_mult1_0_result_add_0_0_q : STD_LOGIC_VECTOR (40 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count0_run_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count0_run_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_oseq_gated_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_oseq_gated_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_resize_in : STD_LOGIC_VECTOR (5 downto 0); signal u0_m0_wo0_wi0_r0_ra0_resize_in : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_resize_b : STD_LOGIC_VECTOR (5 downto 0); signal u0_m0_wo0_wi0_r0_ra0_resize_b : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b : STD_LOGIC_VECTOR (16 downto 0); signal u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b : STD_LOGIC_VECTOR (16 downto 0);
signal u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c : STD_LOGIC_VECTOR (14 downto 0); signal u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c : STD_LOGIC_VECTOR (14 downto 0);
signal u0_m0_wo0_mtree_mult1_0_align_8_q : STD_LOGIC_VECTOR (39 downto 0); signal u0_m0_wo0_mtree_mult1_0_align_8_q : STD_LOGIC_VECTOR (39 downto 0);
@ -138,14 +156,14 @@ begin
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_run_q <= "0"; u0_m0_wo0_run_q <= "0";
u0_m0_wo0_run_enable_c := TO_SIGNED(62, 7); u0_m0_wo0_run_enable_c := TO_SIGNED(63, 7);
u0_m0_wo0_run_enableQ <= "0"; u0_m0_wo0_run_enableQ <= "0";
u0_m0_wo0_run_count <= "00"; u0_m0_wo0_run_count <= "00";
u0_m0_wo0_run_inc := (others => '0'); u0_m0_wo0_run_inc := (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (u0_m0_wo0_run_out = "1") THEN IF (u0_m0_wo0_run_out = "1") THEN
IF (u0_m0_wo0_run_enable_c(6) = '1') THEN IF (u0_m0_wo0_run_enable_c(6) = '1') THEN
u0_m0_wo0_run_enable_c := u0_m0_wo0_run_enable_c - (-63); u0_m0_wo0_run_enable_c := u0_m0_wo0_run_enable_c - (-64);
ELSE ELSE
u0_m0_wo0_run_enable_c := u0_m0_wo0_run_enable_c + (-1); u0_m0_wo0_run_enable_c := u0_m0_wo0_run_enable_c + (-1);
END IF; END IF;
@ -174,17 +192,22 @@ begin
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => u0_m0_wo0_run_q, xout => u0_m0_wo0_memread_q, clk => clk, aclr => areset ); PORT MAP ( xin => u0_m0_wo0_run_q, xout => u0_m0_wo0_memread_q, clk => clk, aclr => areset );
-- u0_m0_wo0_compute(DELAY,16)@12 -- d_u0_m0_wo0_memread_q_13(DELAY,61)@12 + 1
d_u0_m0_wo0_memread_q_13 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => u0_m0_wo0_memread_q, xout => d_u0_m0_wo0_memread_q_13_q, clk => clk, aclr => areset );
-- u0_m0_wo0_compute(DELAY,16)@13
u0_m0_wo0_compute : dspba_delay u0_m0_wo0_compute : dspba_delay
GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => u0_m0_wo0_memread_q, xout => u0_m0_wo0_compute_q, clk => clk, aclr => areset ); PORT MAP ( xin => d_u0_m0_wo0_memread_q_13_q, xout => u0_m0_wo0_compute_q, clk => clk, aclr => areset );
-- d_u0_m0_wo0_compute_q_15(DELAY,57)@12 + 3 -- d_u0_m0_wo0_compute_q_17(DELAY,63)@13 + 4
d_u0_m0_wo0_compute_q_15 : dspba_delay d_u0_m0_wo0_compute_q_17 : dspba_delay
GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) GENERIC MAP ( width => 1, depth => 4, reset_kind => "ASYNC" )
PORT MAP ( xin => u0_m0_wo0_compute_q, xout => d_u0_m0_wo0_compute_q_15_q, clk => clk, aclr => areset ); PORT MAP ( xin => u0_m0_wo0_compute_q, xout => d_u0_m0_wo0_compute_q_17_q, clk => clk, aclr => areset );
-- u0_m0_wo0_aseq(SEQUENCE,33)@15 + 1 -- u0_m0_wo0_aseq(SEQUENCE,35)@17 + 1
u0_m0_wo0_aseq_clkproc: PROCESS (clk, areset) u0_m0_wo0_aseq_clkproc: PROCESS (clk, areset)
variable u0_m0_wo0_aseq_c : SIGNED(8 downto 0); variable u0_m0_wo0_aseq_c : SIGNED(8 downto 0);
BEGIN BEGIN
@ -193,14 +216,14 @@ begin
u0_m0_wo0_aseq_q <= "0"; u0_m0_wo0_aseq_q <= "0";
u0_m0_wo0_aseq_eq <= '0'; u0_m0_wo0_aseq_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (d_u0_m0_wo0_compute_q_15_q = "1") THEN IF (d_u0_m0_wo0_compute_q_17_q = "1") THEN
IF (u0_m0_wo0_aseq_c = "000000000") THEN IF (u0_m0_wo0_aseq_c = "000000000") THEN
u0_m0_wo0_aseq_eq <= '1'; u0_m0_wo0_aseq_eq <= '1';
ELSE ELSE
u0_m0_wo0_aseq_eq <= '0'; u0_m0_wo0_aseq_eq <= '0';
END IF; END IF;
IF (u0_m0_wo0_aseq_eq = '1') THEN IF (u0_m0_wo0_aseq_eq = '1') THEN
u0_m0_wo0_aseq_c := u0_m0_wo0_aseq_c + 63; u0_m0_wo0_aseq_c := u0_m0_wo0_aseq_c + 64;
ELSE ELSE
u0_m0_wo0_aseq_c := u0_m0_wo0_aseq_c - 1; u0_m0_wo0_aseq_c := u0_m0_wo0_aseq_c - 1;
END IF; END IF;
@ -209,126 +232,144 @@ begin
END IF; END IF;
END PROCESS; END PROCESS;
-- d_u0_m0_wo0_compute_q_16(DELAY,58)@15 + 1 -- d_u0_m0_wo0_compute_q_18(DELAY,64)@17 + 1
d_u0_m0_wo0_compute_q_16 : dspba_delay d_u0_m0_wo0_compute_q_18 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => d_u0_m0_wo0_compute_q_15_q, xout => d_u0_m0_wo0_compute_q_16_q, clk => clk, aclr => areset ); PORT MAP ( xin => d_u0_m0_wo0_compute_q_17_q, xout => d_u0_m0_wo0_compute_q_18_q, clk => clk, aclr => areset );
-- u0_m0_wo0_ca0(COUNTER,27)@12 -- u0_m0_wo0_ca0(COUNTER,29)@13
-- low=0, high=63, step=1, init=0 -- low=0, high=64, step=1, init=0
u0_m0_wo0_ca0_clkproc: PROCESS (clk, areset) u0_m0_wo0_ca0_clkproc: PROCESS (clk, areset)
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_ca0_i <= TO_UNSIGNED(0, 6); u0_m0_wo0_ca0_i <= TO_UNSIGNED(0, 7);
u0_m0_wo0_ca0_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (u0_m0_wo0_compute_q = "1") THEN IF (u0_m0_wo0_compute_q = "1") THEN
u0_m0_wo0_ca0_i <= u0_m0_wo0_ca0_i + 1; IF (u0_m0_wo0_ca0_i = TO_UNSIGNED(63, 7)) THEN
u0_m0_wo0_ca0_eq <= '1';
ELSE
u0_m0_wo0_ca0_eq <= '0';
END IF;
IF (u0_m0_wo0_ca0_eq = '1') THEN
u0_m0_wo0_ca0_i <= u0_m0_wo0_ca0_i + 64;
ELSE
u0_m0_wo0_ca0_i <= u0_m0_wo0_ca0_i + 1;
END IF;
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
u0_m0_wo0_ca0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_ca0_i, 6))); u0_m0_wo0_ca0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_ca0_i, 7)));
-- u0_m0_wo0_cm0(LOOKUP,31)@12 + 1 -- u0_m0_wo0_cm0_lutmem(DUALMEM,46)@13 + 2
u0_m0_wo0_cm0_clkproc: PROCESS (clk, areset) u0_m0_wo0_cm0_lutmem_aa <= u0_m0_wo0_ca0_q;
BEGIN u0_m0_wo0_cm0_lutmem_reset0 <= areset;
IF (areset = '1') THEN u0_m0_wo0_cm0_lutmem_dmem : altsyncram
u0_m0_wo0_cm0_q <= "00000000"; GENERIC MAP (
ELSIF (clk'EVENT AND clk = '1') THEN ram_block_type => "M9K",
CASE (u0_m0_wo0_ca0_q) IS operation_mode => "ROM",
WHEN "000000" => u0_m0_wo0_cm0_q <= "00000000"; width_a => 8,
WHEN "000001" => u0_m0_wo0_cm0_q <= "00000000"; widthad_a => 7,
WHEN "000010" => u0_m0_wo0_cm0_q <= "00000000"; numwords_a => 65,
WHEN "000011" => u0_m0_wo0_cm0_q <= "00000000"; lpm_type => "altsyncram",
WHEN "000100" => u0_m0_wo0_cm0_q <= "00000000"; width_byteena_a => 1,
WHEN "000101" => u0_m0_wo0_cm0_q <= "00000000"; outdata_reg_a => "CLOCK0",
WHEN "000110" => u0_m0_wo0_cm0_q <= "00000000"; outdata_aclr_a => "CLEAR0",
WHEN "000111" => u0_m0_wo0_cm0_q <= "00000000"; clock_enable_input_a => "NORMAL",
WHEN "001000" => u0_m0_wo0_cm0_q <= "00000000"; power_up_uninitialized => "FALSE",
WHEN "001001" => u0_m0_wo0_cm0_q <= "00000000"; init_file => "rx_ciccomp_0002_rtl_core_u0_m0_wo0_cm0_lutmem.hex",
WHEN "001010" => u0_m0_wo0_cm0_q <= "00000000"; init_file_layout => "PORT_A",
WHEN "001011" => u0_m0_wo0_cm0_q <= "00000000"; intended_device_family => "Cyclone IV E"
WHEN "001100" => u0_m0_wo0_cm0_q <= "00000000"; )
WHEN "001101" => u0_m0_wo0_cm0_q <= "00000000"; PORT MAP (
WHEN "001110" => u0_m0_wo0_cm0_q <= "11111111"; clocken0 => '1',
WHEN "001111" => u0_m0_wo0_cm0_q <= "00000010"; aclr0 => u0_m0_wo0_cm0_lutmem_reset0,
WHEN "010000" => u0_m0_wo0_cm0_q <= "11111101"; clock0 => clk,
WHEN "010001" => u0_m0_wo0_cm0_q <= "00000100"; address_a => u0_m0_wo0_cm0_lutmem_aa,
WHEN "010010" => u0_m0_wo0_cm0_q <= "11111010"; q_a => u0_m0_wo0_cm0_lutmem_ir
WHEN "010011" => u0_m0_wo0_cm0_q <= "00001001"; );
WHEN "010100" => u0_m0_wo0_cm0_q <= "11110100"; u0_m0_wo0_cm0_lutmem_r <= u0_m0_wo0_cm0_lutmem_ir(7 downto 0);
WHEN "010101" => u0_m0_wo0_cm0_q <= "00001111";
WHEN "010110" => u0_m0_wo0_cm0_q <= "11101100";
WHEN "010111" => u0_m0_wo0_cm0_q <= "00011010";
WHEN "011000" => u0_m0_wo0_cm0_q <= "11011110";
WHEN "011001" => u0_m0_wo0_cm0_q <= "00101011";
WHEN "011010" => u0_m0_wo0_cm0_q <= "11001010";
WHEN "011011" => u0_m0_wo0_cm0_q <= "01000101";
WHEN "011100" => u0_m0_wo0_cm0_q <= "10101010";
WHEN "011101" => u0_m0_wo0_cm0_q <= "01101100";
WHEN "011110" => u0_m0_wo0_cm0_q <= "10000000";
WHEN "011111" => u0_m0_wo0_cm0_q <= "01110010";
WHEN "100000" => u0_m0_wo0_cm0_q <= "01110010";
WHEN "100001" => u0_m0_wo0_cm0_q <= "10000000";
WHEN "100010" => u0_m0_wo0_cm0_q <= "01101100";
WHEN "100011" => u0_m0_wo0_cm0_q <= "10101010";
WHEN "100100" => u0_m0_wo0_cm0_q <= "01000101";
WHEN "100101" => u0_m0_wo0_cm0_q <= "11001010";
WHEN "100110" => u0_m0_wo0_cm0_q <= "00101011";
WHEN "100111" => u0_m0_wo0_cm0_q <= "11011110";
WHEN "101000" => u0_m0_wo0_cm0_q <= "00011010";
WHEN "101001" => u0_m0_wo0_cm0_q <= "11101100";
WHEN "101010" => u0_m0_wo0_cm0_q <= "00001111";
WHEN "101011" => u0_m0_wo0_cm0_q <= "11110100";
WHEN "101100" => u0_m0_wo0_cm0_q <= "00001001";
WHEN "101101" => u0_m0_wo0_cm0_q <= "11111010";
WHEN "101110" => u0_m0_wo0_cm0_q <= "00000100";
WHEN "101111" => u0_m0_wo0_cm0_q <= "11111101";
WHEN "110000" => u0_m0_wo0_cm0_q <= "00000010";
WHEN "110001" => u0_m0_wo0_cm0_q <= "11111111";
WHEN "110010" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "110011" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "110100" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "110101" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "110110" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "110111" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111000" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111001" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111010" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111011" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111100" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111101" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111110" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111111" => u0_m0_wo0_cm0_q <= "00000000";
WHEN OTHERS => -- unreachable
u0_m0_wo0_cm0_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
-- u0_m0_wo0_wi0_r0_ra0_count1(COUNTER,22)@12 -- d_u0_m0_wo0_memread_q_14(DELAY,62)@13 + 1
-- low=0, high=63, step=1, init=0 d_u0_m0_wo0_memread_q_14 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => d_u0_m0_wo0_memread_q_13_q, xout => d_u0_m0_wo0_memread_q_14_q, clk => clk, aclr => areset );
-- u0_m0_wo0_wi0_r0_ra0_count1(COUNTER,24)@12
-- low=0, high=64, step=1, init=1
u0_m0_wo0_wi0_r0_ra0_count1_clkproc: PROCESS (clk, areset) u0_m0_wo0_wi0_r0_ra0_count1_clkproc: PROCESS (clk, areset)
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_wi0_r0_ra0_count1_i <= TO_UNSIGNED(0, 6); u0_m0_wo0_wi0_r0_ra0_count1_i <= TO_UNSIGNED(1, 7);
u0_m0_wo0_wi0_r0_ra0_count1_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (u0_m0_wo0_memread_q = "1") THEN IF (u0_m0_wo0_memread_q = "1") THEN
u0_m0_wo0_wi0_r0_ra0_count1_i <= u0_m0_wo0_wi0_r0_ra0_count1_i + 1; IF (u0_m0_wo0_wi0_r0_ra0_count1_i = TO_UNSIGNED(63, 7)) THEN
u0_m0_wo0_wi0_r0_ra0_count1_eq <= '1';
ELSE
u0_m0_wo0_wi0_r0_ra0_count1_eq <= '0';
END IF;
IF (u0_m0_wo0_wi0_r0_ra0_count1_eq = '1') THEN
u0_m0_wo0_wi0_r0_ra0_count1_i <= u0_m0_wo0_wi0_r0_ra0_count1_i + 64;
ELSE
u0_m0_wo0_wi0_r0_ra0_count1_i <= u0_m0_wo0_wi0_r0_ra0_count1_i + 1;
END IF;
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
u0_m0_wo0_wi0_r0_ra0_count1_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count1_i, 7))); u0_m0_wo0_wi0_r0_ra0_count1_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count1_i, 7)));
-- u0_m0_wo0_wi0_r0_ra0_count0_inner(COUNTER,19)@12 -- u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem(DUALMEM,45)@12 + 2
-- low=-1, high=62, step=-1, init=62 u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_aa <= u0_m0_wo0_wi0_r0_ra0_count1_q;
u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_reset0 <= areset;
u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 8,
widthad_a => 7,
numwords_a => 65,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "rx_ciccomp_0002_rtl_core_u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "Cyclone IV E"
)
PORT MAP (
clocken0 => '1',
aclr0 => u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_reset0,
clock0 => clk,
address_a => u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_aa,
q_a => u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_ir
);
u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_r <= u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_ir(7 downto 0);
-- u0_m0_wo0_wi0_r0_ra0_count1_lutreg(REG,23)@14
u0_m0_wo0_wi0_r0_ra0_count1_lutreg_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
u0_m0_wo0_wi0_r0_ra0_count1_lutreg_q <= "01000001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (d_u0_m0_wo0_memread_q_14_q = "1") THEN
u0_m0_wo0_wi0_r0_ra0_count1_lutreg_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_r);
END IF;
END IF;
END PROCESS;
-- u0_m0_wo0_wi0_r0_ra0_count0_inner(COUNTER,19)@14
-- low=-1, high=63, step=-1, init=63
u0_m0_wo0_wi0_r0_ra0_count0_inner_clkproc: PROCESS (clk, areset) u0_m0_wo0_wi0_r0_ra0_count0_inner_clkproc: PROCESS (clk, areset)
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= TO_SIGNED(62, 7); u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= TO_SIGNED(63, 7);
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (u0_m0_wo0_memread_q = "1") THEN IF (d_u0_m0_wo0_memread_q_14_q = "1") THEN
IF (u0_m0_wo0_wi0_r0_ra0_count0_inner_i(6 downto 6) = "1") THEN IF (u0_m0_wo0_wi0_r0_ra0_count0_inner_i(6 downto 6) = "1") THEN
u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= u0_m0_wo0_wi0_r0_ra0_count0_inner_i - 65; u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= u0_m0_wo0_wi0_r0_ra0_count0_inner_i - 64;
ELSE ELSE
u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= u0_m0_wo0_wi0_r0_ra0_count0_inner_i - 1; u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= u0_m0_wo0_wi0_r0_ra0_count0_inner_i - 1;
END IF; END IF;
@ -337,26 +378,26 @@ begin
END PROCESS; END PROCESS;
u0_m0_wo0_wi0_r0_ra0_count0_inner_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count0_inner_i, 7))); u0_m0_wo0_wi0_r0_ra0_count0_inner_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count0_inner_i, 7)));
-- u0_m0_wo0_wi0_r0_ra0_count0_run(LOGICAL,20)@12 -- u0_m0_wo0_wi0_r0_ra0_count0_run(LOGICAL,20)@14
u0_m0_wo0_wi0_r0_ra0_count0_run_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_count0_inner_q(6 downto 6)); u0_m0_wo0_wi0_r0_ra0_count0_run_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_count0_inner_q(6 downto 6));
-- u0_m0_wo0_wi0_r0_ra0_count0(COUNTER,21)@12 -- u0_m0_wo0_wi0_r0_ra0_count0(COUNTER,21)@14
-- low=0, high=63, step=1, init=0 -- low=0, high=127, step=1, init=0
u0_m0_wo0_wi0_r0_ra0_count0_clkproc: PROCESS (clk, areset) u0_m0_wo0_wi0_r0_ra0_count0_clkproc: PROCESS (clk, areset)
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_wi0_r0_ra0_count0_i <= TO_UNSIGNED(0, 6); u0_m0_wo0_wi0_r0_ra0_count0_i <= TO_UNSIGNED(0, 7);
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (u0_m0_wo0_memread_q = "1" and u0_m0_wo0_wi0_r0_ra0_count0_run_q = "1") THEN IF (d_u0_m0_wo0_memread_q_14_q = "1" and u0_m0_wo0_wi0_r0_ra0_count0_run_q = "1") THEN
u0_m0_wo0_wi0_r0_ra0_count0_i <= u0_m0_wo0_wi0_r0_ra0_count0_i + 1; u0_m0_wo0_wi0_r0_ra0_count0_i <= u0_m0_wo0_wi0_r0_ra0_count0_i + 1;
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
u0_m0_wo0_wi0_r0_ra0_count0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count0_i, 7))); u0_m0_wo0_wi0_r0_ra0_count0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count0_i, 8)));
-- u0_m0_wo0_wi0_r0_ra0_add_0_0(ADD,23)@12 + 1 -- u0_m0_wo0_wi0_r0_ra0_add_0_0(ADD,25)@14 + 1
u0_m0_wo0_wi0_r0_ra0_add_0_0_a <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_ra0_count0_q); u0_m0_wo0_wi0_r0_ra0_add_0_0_a <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_ra0_count0_q);
u0_m0_wo0_wi0_r0_ra0_add_0_0_b <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_ra0_count1_q); u0_m0_wo0_wi0_r0_ra0_add_0_0_b <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_ra0_count1_lutreg_q);
u0_m0_wo0_wi0_r0_ra0_add_0_0_clkproc: PROCESS (clk, areset) u0_m0_wo0_wi0_r0_ra0_add_0_0_clkproc: PROCESS (clk, areset)
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
@ -365,38 +406,38 @@ begin
u0_m0_wo0_wi0_r0_ra0_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(u0_m0_wo0_wi0_r0_ra0_add_0_0_a) + UNSIGNED(u0_m0_wo0_wi0_r0_ra0_add_0_0_b)); u0_m0_wo0_wi0_r0_ra0_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(u0_m0_wo0_wi0_r0_ra0_add_0_0_a) + UNSIGNED(u0_m0_wo0_wi0_r0_ra0_add_0_0_b));
END IF; END IF;
END PROCESS; END PROCESS;
u0_m0_wo0_wi0_r0_ra0_add_0_0_q <= u0_m0_wo0_wi0_r0_ra0_add_0_0_o(7 downto 0); u0_m0_wo0_wi0_r0_ra0_add_0_0_q <= u0_m0_wo0_wi0_r0_ra0_add_0_0_o(8 downto 0);
-- u0_m0_wo0_wi0_r0_ra0_resize(BITSELECT,24)@13 -- u0_m0_wo0_wi0_r0_ra0_resize(BITSELECT,26)@15
u0_m0_wo0_wi0_r0_ra0_resize_in <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_add_0_0_q(5 downto 0)); u0_m0_wo0_wi0_r0_ra0_resize_in <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_add_0_0_q(6 downto 0));
u0_m0_wo0_wi0_r0_ra0_resize_b <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_resize_in(5 downto 0)); u0_m0_wo0_wi0_r0_ra0_resize_b <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_resize_in(6 downto 0));
-- d_xIn_0_13(DELAY,55)@10 + 3 -- d_xIn_0_15(DELAY,59)@10 + 5
d_xIn_0_13 : dspba_delay d_xIn_0_15 : dspba_delay
GENERIC MAP ( width => 32, depth => 3, reset_kind => "ASYNC" ) GENERIC MAP ( width => 32, depth => 5, reset_kind => "ASYNC" )
PORT MAP ( xin => xIn_0, xout => d_xIn_0_13_q, clk => clk, aclr => areset ); PORT MAP ( xin => xIn_0, xout => d_xIn_0_15_q, clk => clk, aclr => areset );
-- d_in0_m0_wi0_wo0_assign_id1_q_13(DELAY,56)@10 + 3 -- d_in0_m0_wi0_wo0_assign_id1_q_15(DELAY,60)@10 + 5
d_in0_m0_wi0_wo0_assign_id1_q_13 : dspba_delay d_in0_m0_wi0_wo0_assign_id1_q_15 : dspba_delay
GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) GENERIC MAP ( width => 1, depth => 5, reset_kind => "ASYNC" )
PORT MAP ( xin => xIn_v, xout => d_in0_m0_wi0_wo0_assign_id1_q_13_q, clk => clk, aclr => areset ); PORT MAP ( xin => xIn_v, xout => d_in0_m0_wi0_wo0_assign_id1_q_15_q, clk => clk, aclr => areset );
-- u0_m0_wo0_wi0_r0_wa0(COUNTER,25)@13 -- u0_m0_wo0_wi0_r0_wa0(COUNTER,27)@15
-- low=0, high=63, step=1, init=63 -- low=0, high=127, step=1, init=1
u0_m0_wo0_wi0_r0_wa0_clkproc: PROCESS (clk, areset) u0_m0_wo0_wi0_r0_wa0_clkproc: PROCESS (clk, areset)
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_wi0_r0_wa0_i <= TO_UNSIGNED(63, 6); u0_m0_wo0_wi0_r0_wa0_i <= TO_UNSIGNED(1, 7);
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (d_in0_m0_wi0_wo0_assign_id1_q_13_q = "1") THEN IF (d_in0_m0_wi0_wo0_assign_id1_q_15_q = "1") THEN
u0_m0_wo0_wi0_r0_wa0_i <= u0_m0_wo0_wi0_r0_wa0_i + 1; u0_m0_wo0_wi0_r0_wa0_i <= u0_m0_wo0_wi0_r0_wa0_i + 1;
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
u0_m0_wo0_wi0_r0_wa0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_wa0_i, 6))); u0_m0_wo0_wi0_r0_wa0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_wa0_i, 7)));
-- u0_m0_wo0_wi0_r0_memr0(DUALMEM,26)@13 -- u0_m0_wo0_wi0_r0_memr0(DUALMEM,28)@15
u0_m0_wo0_wi0_r0_memr0_ia <= STD_LOGIC_VECTOR(d_xIn_0_13_q); u0_m0_wo0_wi0_r0_memr0_ia <= STD_LOGIC_VECTOR(d_xIn_0_15_q);
u0_m0_wo0_wi0_r0_memr0_aa <= u0_m0_wo0_wi0_r0_wa0_q; u0_m0_wo0_wi0_r0_memr0_aa <= u0_m0_wo0_wi0_r0_wa0_q;
u0_m0_wo0_wi0_r0_memr0_ab <= u0_m0_wo0_wi0_r0_ra0_resize_b; u0_m0_wo0_wi0_r0_memr0_ab <= u0_m0_wo0_wi0_r0_ra0_resize_b;
u0_m0_wo0_wi0_r0_memr0_dmem : altsyncram u0_m0_wo0_wi0_r0_memr0_dmem : altsyncram
@ -404,11 +445,11 @@ begin
ram_block_type => "M9K", ram_block_type => "M9K",
operation_mode => "DUAL_PORT", operation_mode => "DUAL_PORT",
width_a => 32, width_a => 32,
widthad_a => 6, widthad_a => 7,
numwords_a => 64, numwords_a => 128,
width_b => 32, width_b => 32,
widthad_b => 6, widthad_b => 7,
numwords_b => 64, numwords_b => 128,
lpm_type => "altsyncram", lpm_type => "altsyncram",
width_byteena_a => 1, width_byteena_a => 1,
address_reg_b => "CLOCK0", address_reg_b => "CLOCK0",
@ -431,19 +472,19 @@ begin
clock0 => clk, clock0 => clk,
address_a => u0_m0_wo0_wi0_r0_memr0_aa, address_a => u0_m0_wo0_wi0_r0_memr0_aa,
data_a => u0_m0_wo0_wi0_r0_memr0_ia, data_a => u0_m0_wo0_wi0_r0_memr0_ia,
wren_a => d_in0_m0_wi0_wo0_assign_id1_q_13_q(0), wren_a => d_in0_m0_wi0_wo0_assign_id1_q_15_q(0),
address_b => u0_m0_wo0_wi0_r0_memr0_ab, address_b => u0_m0_wo0_wi0_r0_memr0_ab,
q_b => u0_m0_wo0_wi0_r0_memr0_iq q_b => u0_m0_wo0_wi0_r0_memr0_iq
); );
u0_m0_wo0_wi0_r0_memr0_q <= u0_m0_wo0_wi0_r0_memr0_iq(31 downto 0); u0_m0_wo0_wi0_r0_memr0_q <= u0_m0_wo0_wi0_r0_memr0_iq(31 downto 0);
-- u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select(BITSELECT,54)@13 -- u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select(BITSELECT,58)@15
u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_memr0_q(16 downto 0)); u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_memr0_q(16 downto 0));
u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_memr0_q(31 downto 17)); u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_memr0_q(31 downto 17));
-- u0_m0_wo0_mtree_mult1_0_im4(MULT,47)@13 + 2 -- u0_m0_wo0_mtree_mult1_0_im4(MULT,51)@15 + 2
u0_m0_wo0_mtree_mult1_0_im4_a0 <= STD_LOGIC_VECTOR(u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c); u0_m0_wo0_mtree_mult1_0_im4_a0 <= STD_LOGIC_VECTOR(u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c);
u0_m0_wo0_mtree_mult1_0_im4_b0 <= STD_LOGIC_VECTOR(u0_m0_wo0_cm0_q); u0_m0_wo0_mtree_mult1_0_im4_b0 <= STD_LOGIC_VECTOR(u0_m0_wo0_cm0_lutmem_r);
u0_m0_wo0_mtree_mult1_0_im4_reset <= areset; u0_m0_wo0_mtree_mult1_0_im4_reset <= areset;
u0_m0_wo0_mtree_mult1_0_im4_component : lpm_mult u0_m0_wo0_mtree_mult1_0_im4_component : lpm_mult
GENERIC MAP ( GENERIC MAP (
@ -466,16 +507,16 @@ begin
); );
u0_m0_wo0_mtree_mult1_0_im4_q <= u0_m0_wo0_mtree_mult1_0_im4_s1; u0_m0_wo0_mtree_mult1_0_im4_q <= u0_m0_wo0_mtree_mult1_0_im4_s1;
-- u0_m0_wo0_mtree_mult1_0_align_8(BITSHIFT,51)@15 -- u0_m0_wo0_mtree_mult1_0_align_8(BITSHIFT,55)@17
u0_m0_wo0_mtree_mult1_0_align_8_qint <= u0_m0_wo0_mtree_mult1_0_im4_q & "00000000000000000"; u0_m0_wo0_mtree_mult1_0_align_8_qint <= u0_m0_wo0_mtree_mult1_0_im4_q & "00000000000000000";
u0_m0_wo0_mtree_mult1_0_align_8_q <= u0_m0_wo0_mtree_mult1_0_align_8_qint(39 downto 0); u0_m0_wo0_mtree_mult1_0_align_8_q <= u0_m0_wo0_mtree_mult1_0_align_8_qint(39 downto 0);
-- u0_m0_wo0_mtree_mult1_0_bjB3(BITJOIN,46)@13 -- u0_m0_wo0_mtree_mult1_0_bjB3(BITJOIN,50)@15
u0_m0_wo0_mtree_mult1_0_bjB3_q <= GND_q & u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b; u0_m0_wo0_mtree_mult1_0_bjB3_q <= GND_q & u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b;
-- u0_m0_wo0_mtree_mult1_0_im0(MULT,43)@13 + 2 -- u0_m0_wo0_mtree_mult1_0_im0(MULT,47)@15 + 2
u0_m0_wo0_mtree_mult1_0_im0_a0 <= STD_LOGIC_VECTOR(u0_m0_wo0_mtree_mult1_0_bjB3_q); u0_m0_wo0_mtree_mult1_0_im0_a0 <= STD_LOGIC_VECTOR(u0_m0_wo0_mtree_mult1_0_bjB3_q);
u0_m0_wo0_mtree_mult1_0_im0_b0 <= STD_LOGIC_VECTOR(u0_m0_wo0_cm0_q); u0_m0_wo0_mtree_mult1_0_im0_b0 <= STD_LOGIC_VECTOR(u0_m0_wo0_cm0_lutmem_r);
u0_m0_wo0_mtree_mult1_0_im0_reset <= areset; u0_m0_wo0_mtree_mult1_0_im0_reset <= areset;
u0_m0_wo0_mtree_mult1_0_im0_component : lpm_mult u0_m0_wo0_mtree_mult1_0_im0_component : lpm_mult
GENERIC MAP ( GENERIC MAP (
@ -498,7 +539,7 @@ begin
); );
u0_m0_wo0_mtree_mult1_0_im0_q <= u0_m0_wo0_mtree_mult1_0_im0_s1; u0_m0_wo0_mtree_mult1_0_im0_q <= u0_m0_wo0_mtree_mult1_0_im0_s1;
-- u0_m0_wo0_mtree_mult1_0_result_add_0_0(ADD,53)@15 + 1 -- u0_m0_wo0_mtree_mult1_0_result_add_0_0(ADD,57)@17 + 1
u0_m0_wo0_mtree_mult1_0_result_add_0_0_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((40 downto 26 => u0_m0_wo0_mtree_mult1_0_im0_q(25)) & u0_m0_wo0_mtree_mult1_0_im0_q)); u0_m0_wo0_mtree_mult1_0_result_add_0_0_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((40 downto 26 => u0_m0_wo0_mtree_mult1_0_im0_q(25)) & u0_m0_wo0_mtree_mult1_0_im0_q));
u0_m0_wo0_mtree_mult1_0_result_add_0_0_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((40 downto 40 => u0_m0_wo0_mtree_mult1_0_align_8_q(39)) & u0_m0_wo0_mtree_mult1_0_align_8_q)); u0_m0_wo0_mtree_mult1_0_result_add_0_0_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((40 downto 40 => u0_m0_wo0_mtree_mult1_0_align_8_q(39)) & u0_m0_wo0_mtree_mult1_0_align_8_q));
u0_m0_wo0_mtree_mult1_0_result_add_0_0_clkproc: PROCESS (clk, areset) u0_m0_wo0_mtree_mult1_0_result_add_0_0_clkproc: PROCESS (clk, areset)
@ -511,8 +552,8 @@ begin
END PROCESS; END PROCESS;
u0_m0_wo0_mtree_mult1_0_result_add_0_0_q <= u0_m0_wo0_mtree_mult1_0_result_add_0_0_o(40 downto 0); u0_m0_wo0_mtree_mult1_0_result_add_0_0_q <= u0_m0_wo0_mtree_mult1_0_result_add_0_0_o(40 downto 0);
-- u0_m0_wo0_accum(ADD,34)@16 + 1 -- u0_m0_wo0_accum(ADD,36)@18 + 1
u0_m0_wo0_accum_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((45 downto 41 => u0_m0_wo0_mtree_mult1_0_result_add_0_0_q(40)) & u0_m0_wo0_mtree_mult1_0_result_add_0_0_q)); u0_m0_wo0_accum_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((46 downto 41 => u0_m0_wo0_mtree_mult1_0_result_add_0_0_q(40)) & u0_m0_wo0_mtree_mult1_0_result_add_0_0_q));
u0_m0_wo0_accum_b <= STD_LOGIC_VECTOR(u0_m0_wo0_accum_q); u0_m0_wo0_accum_b <= STD_LOGIC_VECTOR(u0_m0_wo0_accum_q);
u0_m0_wo0_accum_i <= u0_m0_wo0_accum_a; u0_m0_wo0_accum_i <= u0_m0_wo0_accum_a;
u0_m0_wo0_accum_clkproc: PROCESS (clk, areset) u0_m0_wo0_accum_clkproc: PROCESS (clk, areset)
@ -520,7 +561,7 @@ begin
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_accum_o <= (others => '0'); u0_m0_wo0_accum_o <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (d_u0_m0_wo0_compute_q_16_q = "1") THEN IF (d_u0_m0_wo0_compute_q_18_q = "1") THEN
IF (u0_m0_wo0_aseq_q = "1") THEN IF (u0_m0_wo0_aseq_q = "1") THEN
u0_m0_wo0_accum_o <= u0_m0_wo0_accum_i; u0_m0_wo0_accum_o <= u0_m0_wo0_accum_i;
ELSE ELSE
@ -529,28 +570,28 @@ begin
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
u0_m0_wo0_accum_q <= u0_m0_wo0_accum_o(45 downto 0); u0_m0_wo0_accum_q <= u0_m0_wo0_accum_o(46 downto 0);
-- GND(CONSTANT,0)@0 -- GND(CONSTANT,0)@0
GND_q <= "0"; GND_q <= "0";
-- u0_m0_wo0_oseq(SEQUENCE,35)@15 + 1 -- u0_m0_wo0_oseq(SEQUENCE,37)@17 + 1
u0_m0_wo0_oseq_clkproc: PROCESS (clk, areset) u0_m0_wo0_oseq_clkproc: PROCESS (clk, areset)
variable u0_m0_wo0_oseq_c : SIGNED(8 downto 0); variable u0_m0_wo0_oseq_c : SIGNED(8 downto 0);
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_oseq_c := "000111111"; u0_m0_wo0_oseq_c := "001000000";
u0_m0_wo0_oseq_q <= "0"; u0_m0_wo0_oseq_q <= "0";
u0_m0_wo0_oseq_eq <= '0'; u0_m0_wo0_oseq_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (d_u0_m0_wo0_compute_q_15_q = "1") THEN IF (d_u0_m0_wo0_compute_q_17_q = "1") THEN
IF (u0_m0_wo0_oseq_c = "000000000") THEN IF (u0_m0_wo0_oseq_c = "000000000") THEN
u0_m0_wo0_oseq_eq <= '1'; u0_m0_wo0_oseq_eq <= '1';
ELSE ELSE
u0_m0_wo0_oseq_eq <= '0'; u0_m0_wo0_oseq_eq <= '0';
END IF; END IF;
IF (u0_m0_wo0_oseq_eq = '1') THEN IF (u0_m0_wo0_oseq_eq = '1') THEN
u0_m0_wo0_oseq_c := u0_m0_wo0_oseq_c + 63; u0_m0_wo0_oseq_c := u0_m0_wo0_oseq_c + 64;
ELSE ELSE
u0_m0_wo0_oseq_c := u0_m0_wo0_oseq_c - 1; u0_m0_wo0_oseq_c := u0_m0_wo0_oseq_c - 1;
END IF; END IF;
@ -559,10 +600,10 @@ begin
END IF; END IF;
END PROCESS; END PROCESS;
-- u0_m0_wo0_oseq_gated(LOGICAL,36)@16 -- u0_m0_wo0_oseq_gated(LOGICAL,38)@18
u0_m0_wo0_oseq_gated_q <= u0_m0_wo0_oseq_q and d_u0_m0_wo0_compute_q_16_q; u0_m0_wo0_oseq_gated_q <= u0_m0_wo0_oseq_q and d_u0_m0_wo0_compute_q_18_q;
-- u0_m0_wo0_oseq_gated_reg(REG,37)@16 + 1 -- u0_m0_wo0_oseq_gated_reg(REG,39)@18 + 1
u0_m0_wo0_oseq_gated_reg_clkproc: PROCESS (clk, areset) u0_m0_wo0_oseq_gated_reg_clkproc: PROCESS (clk, areset)
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
@ -572,7 +613,7 @@ begin
END IF; END IF;
END PROCESS; END PROCESS;
-- xOut(PORTOUT,42)@17 + 1 -- xOut(PORTOUT,44)@19 + 1
xOut_v <= u0_m0_wo0_oseq_gated_reg_q; xOut_v <= u0_m0_wo0_oseq_gated_reg_q;
xOut_c <= STD_LOGIC_VECTOR("0000000" & GND_q); xOut_c <= STD_LOGIC_VECTOR("0000000" & GND_q);
xOut_0 <= u0_m0_wo0_accum_q; xOut_0 <= u0_m0_wo0_accum_q;

67
FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core_u0_m0_wo0_cm0_lutmem.hex 100644
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@ -0,0 +1,67 @@
:020000040000FA
:0100000000FF
:0100010000FE
:0100020000FD
:0100030000FC
:0100040000FB
:0100050000FA
:0100060000F9
:0100070000F8
:0100080000F7
:0100090000F6
:01000A0000F5
:01000B0000F4
:01000C0000F3
:01000D0000F2
:01000E0000F1
:01000F0000F0
:0100100000EF
:0100110000EE
:0100120000ED
:0100130000EC
:0100140000EB
:01001500FFEB
:0100160001E8
:01001700FEEA
:0100180003E4
:01001900FCEA
:01001A0006DF
:01001B00F7ED
:01001C000ED5
:01001D00EAF8
:01001E0026BB
:01001F00BC24
:010020007F60
:01002100BC22
:0100220026B7
:01002300EAF2
:010024000ECD
:01002500F7E3
:0100260006D3
:01002700FCDC
:0100280003D4
:01002900FED8
:01002A0001D4
:01002B00FFD5
:01002C0000D3
:01002D0000D2
:01002E0000D1
:01002F0000D0
:0100300000CF
:0100310000CE
:0100320000CD
:0100330000CC
:0100340000CB
:0100350000CA
:0100360000C9
:0100370000C8
:0100380000C7
:0100390000C6
:01003A0000C5
:01003B0000C4
:01003C0000C3
:01003D0000C2
:01003E0000C1
:01003F0000C0
:0100400000BF
:00000001ff

67
FPGA/rx_ciccomp/rx_ciccomp_0002_rtl_core_u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem.hex 100644
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@ -0,0 +1,67 @@
:020000040000FA
:0100000041BE
:0100010042BC
:0100020043BA
:0100030044B8
:0100040045B6
:0100050046B4
:0100060047B2
:0100070048B0
:0100080049AE
:010009004AAC
:01000A004BAA
:01000B004CA8
:01000C004DA6
:01000D004EA4
:01000E004FA2
:01000F0050A0
:01001000519E
:01001100529C
:01001200539A
:010013005498
:010014005596
:010015005694
:010016005792
:010017005890
:01001800598E
:010019005A8C
:01001A005B8A
:01001B005C88
:01001C005D86
:01001D005E84
:01001E005F82
:01001F006080
:01002000617E
:01002100627C
:01002200637A
:010023006478
:010024006576
:010025006674
:010026006772
:010027006870
:01002800696E
:010029006A6C
:01002A006B6A
:01002B006C68
:01002C006D66
:01002D006E64
:01002E006F62
:01002F007060
:01003000715E
:01003100725C
:01003200735A
:010033007458
:010034007556
:010035007654
:010036007752
:010037007850
:01003800794E
:010039007A4C
:01003A007B4A
:01003B007C48
:01003C007D46
:01003D007E44
:01003E007F42
:01003F0000C0
:0100400001BE
:00000001ff

2
FPGA/rx_ciccomp_sim.f
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@ -7,6 +7,8 @@ rx_ciccomp_sim/auk_dspip_avalon_streaming_sink_hpfir.vhd
rx_ciccomp_sim/auk_dspip_avalon_streaming_source_hpfir.vhd rx_ciccomp_sim/auk_dspip_avalon_streaming_source_hpfir.vhd
rx_ciccomp_sim/auk_dspip_roundsat_hpfir.vhd rx_ciccomp_sim/auk_dspip_roundsat_hpfir.vhd
rx_ciccomp_sim/altera_avalon_sc_fifo.v rx_ciccomp_sim/altera_avalon_sc_fifo.v
rx_ciccomp_sim/rx_ciccomp_rtl_core_u0_m0_wo0_cm0_lutmem.hex
rx_ciccomp_sim/rx_ciccomp_rtl_core_u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem.hex
rx_ciccomp_sim/rx_ciccomp_rtl_core.vhd rx_ciccomp_sim/rx_ciccomp_rtl_core.vhd
rx_ciccomp_sim/rx_ciccomp_ast.vhd rx_ciccomp_sim/rx_ciccomp_ast.vhd
rx_ciccomp_sim/rx_ciccomp.vhd rx_ciccomp_sim/rx_ciccomp.vhd

4
FPGA/rx_ciccomp_sim/aldec/rivierapro_setup.tcl
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@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable # or its authorized distributors. Please refer to the applicable
# agreement for further details. # agreement for further details.
# ACDS 18.1 625 win32 2021.02.12.17:11:14 # ACDS 18.1 625 win32 2021.02.12.17:50:53
# ---------------------------------------- # ----------------------------------------
# Auto-generated simulation script rivierapro_setup.tcl # Auto-generated simulation script rivierapro_setup.tcl
# ---------------------------------------- # ----------------------------------------
@ -152,6 +152,8 @@ if { [ string match "Active" $Aldec ] } {
# Copy ROM/RAM files to simulation directory # Copy ROM/RAM files to simulation directory
alias file_copy { alias file_copy {
echo "\[exec\] file_copy" echo "\[exec\] file_copy"
file copy -force $QSYS_SIMDIR/rx_ciccomp_rtl_core_u0_m0_wo0_cm0_lutmem.hex ./
file copy -force $QSYS_SIMDIR/rx_ciccomp_rtl_core_u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem.hex ./
} }
# ---------------------------------------- # ----------------------------------------

8
FPGA/rx_ciccomp_sim/cadence/ncsim_setup.sh
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@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable # or its authorized distributors. Please refer to the applicable
# agreement for further details. # agreement for further details.
# ACDS 18.1 625 win32 2021.02.12.17:11:14 # ACDS 18.1 625 win32 2021.02.12.17:50:53
# ---------------------------------------- # ----------------------------------------
# ncsim - auto-generated simulation script # ncsim - auto-generated simulation script
@ -106,7 +106,7 @@
# within the Quartus project, and generate a unified # within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design. # script which supports all the Altera IP within the design.
# ---------------------------------------- # ----------------------------------------
# ACDS 18.1 625 win32 2021.02.12.17:11:14 # ACDS 18.1 625 win32 2021.02.12.17:50:53
# ---------------------------------------- # ----------------------------------------
# initialize variables # initialize variables
TOP_LEVEL_NAME="rx_ciccomp" TOP_LEVEL_NAME="rx_ciccomp"
@ -160,6 +160,10 @@ mkdir -p ./libraries/cycloneive/
# ---------------------------------------- # ----------------------------------------
# copy RAM/ROM files to simulation directory # copy RAM/ROM files to simulation directory
if [ $SKIP_FILE_COPY -eq 0 ]; then
cp -f $QSYS_SIMDIR/rx_ciccomp_rtl_core_u0_m0_wo0_cm0_lutmem.hex ./
cp -f $QSYS_SIMDIR/rx_ciccomp_rtl_core_u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem.hex ./
fi
# ---------------------------------------- # ----------------------------------------
# compile device library files # compile device library files

4
FPGA/rx_ciccomp_sim/mentor/msim_setup.tcl
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@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified # within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design. # script which supports all the Altera IP within the design.
# ---------------------------------------- # ----------------------------------------
# ACDS 18.1 625 win32 2021.02.12.17:11:14 # ACDS 18.1 625 win32 2021.02.12.17:50:53
# ---------------------------------------- # ----------------------------------------
# Initialize variables # Initialize variables
@ -141,6 +141,8 @@ if ![ string match "*-64 vsim*" [ vsim -version ] ] {
# Copy ROM/RAM files to simulation directory # Copy ROM/RAM files to simulation directory
alias file_copy { alias file_copy {
echo "\[exec\] file_copy" echo "\[exec\] file_copy"
file copy -force $QSYS_SIMDIR/rx_ciccomp_rtl_core_u0_m0_wo0_cm0_lutmem.hex ./
file copy -force $QSYS_SIMDIR/rx_ciccomp_rtl_core_u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem.hex ./
} }
# ---------------------------------------- # ----------------------------------------

4
FPGA/rx_ciccomp_sim/rx_ciccomp.vhd
Wyświetl plik

@ -23,7 +23,7 @@ entity rx_ciccomp is
ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*32) * 1 + 0 - 1 downto 0); ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*32) * 1 + 0 - 1 downto 0);
ast_sink_valid : in STD_LOGIC; ast_sink_valid : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0); ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
ast_source_data : out STD_LOGIC_VECTOR(46 * 1*1 - 1 downto 0); ast_source_data : out STD_LOGIC_VECTOR(47 * 1*1 - 1 downto 0);
ast_source_valid : out STD_LOGIC; ast_source_valid : out STD_LOGIC;
ast_source_error : out STD_LOGIC_VECTOR(1 downto 0) ast_source_error : out STD_LOGIC_VECTOR(1 downto 0)
); );
@ -41,7 +41,7 @@ architecture syn of rx_ciccomp is
ast_sink_sop : in STD_LOGIC; ast_sink_sop : in STD_LOGIC;
ast_sink_eop : in STD_LOGIC; ast_sink_eop : in STD_LOGIC;
ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0); ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0);
ast_source_data : out STD_LOGIC_VECTOR(1*46 * 1 - 1 downto 0); ast_source_data : out STD_LOGIC_VECTOR(1*47 * 1 - 1 downto 0);
ast_source_ready : in STD_LOGIC; ast_source_ready : in STD_LOGIC;
ast_source_valid : out STD_LOGIC; ast_source_valid : out STD_LOGIC;
ast_source_sop : out STD_LOGIC; ast_source_sop : out STD_LOGIC;

6
FPGA/rx_ciccomp_sim/rx_ciccomp_ast.vhd
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@ -9,7 +9,7 @@ use work.auk_dspip_math_pkg_hpfir.all;
entity rx_ciccomp_ast is entity rx_ciccomp_ast is
generic ( generic (
INWIDTH : integer := 32; INWIDTH : integer := 32;
OUT_WIDTH_UNTRIMMED : integer := 46; OUT_WIDTH_UNTRIMMED : integer := 47;
BANKINWIDTH : integer := 0; BANKINWIDTH : integer := 0;
REM_LSB_BIT_g : integer := 0; REM_LSB_BIT_g : integer := 0;
REM_LSB_TYPE_g : string := "round"; REM_LSB_TYPE_g : string := "round";
@ -197,7 +197,7 @@ real_passthrough : if COMPLEX_CONST = 1 generate
xIn_0 : in std_logic_vector(32 - 1 downto 0); xIn_0 : in std_logic_vector(32 - 1 downto 0);
xOut_v : out std_logic_vector(0 downto 0); xOut_v : out std_logic_vector(0 downto 0);
xOut_c : out std_logic_vector(7 downto 0); xOut_c : out std_logic_vector(7 downto 0);
xOut_0 : out std_logic_vector(46- 1 downto 0); xOut_0 : out std_logic_vector(47- 1 downto 0);
clk : in std_logic; clk : in std_logic;
areset : in std_logic areset : in std_logic
); );
@ -222,7 +222,7 @@ end component rx_ciccomp_rtl_core;
xIn_0 => data_in_core((0 + 32) * 0 + 32 - 1 downto (0 + 32) * 0), xIn_0 => data_in_core((0 + 32) * 0 + 32 - 1 downto (0 + 32) * 0),
xOut_v => core_out_valid_core, xOut_v => core_out_valid_core,
xOut_c => core_out_channel_core, xOut_c => core_out_channel_core,
xOut_0 => core_out_core(46* 0 + 46- 1 downto 46* 0), xOut_0 => core_out_core(47* 0 + 47- 1 downto 47* 0),
clk => clk, clk => clk,
areset => reset_fir areset => reset_fir
); );

69
FPGA/rx_ciccomp_sim/rx_ciccomp_coef_int.txt
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@ -12,41 +12,35 @@
0 0
0 0
0 0
0
0
0
0
0
0
0
-1 -1
2 1
-3 -2
4 3
-6 -4
9 6
-12 -9
15 14
-20 -22
26 38
-34 -68
43 127
-54 -68
69 38
-86 -22
108 14
-128 -9
114 6
114 -4
-128 3
108 -2
-86 1
69
-54
43
-34
26
-20
15
-12
9
-6
4
-3
2
-1 -1
0 0
0 0
@ -62,3 +56,10 @@
0 0
0 0
0 0
0
0
0
0
0
0
0

132
FPGA/rx_ciccomp_sim/rx_ciccomp_input.txt
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@ -62,6 +62,7 @@
0 0
0 0
0 0
0
2 2
3 3
0 0
@ -127,70 +128,73 @@
0 0
0 0
0 0
-152524643 0
613799617 1487886291
-381277269 1605307169
-35857435 -586951525
-1360488885 645593643
669183061 1404973257
-1559636759 -344652013
-629613231 1344497115
889838999 1140078071
447938485 1443040763
-575548987 -494205477
-985478421 355294657
-1541936083 1432761539
512905015 -1458431485
395228047 -479621537
-1716617889 654438479
-1901546625 -263723381
-442491721 7382941
1924998361 -468962139
-541172375 -581685683
1256622067 -1045713037
1692895471 -292845811
-1664141653 172973447
-401743443 -528134309
-413460333 1344065335
229264961 -1821881095
670536809 -1533724739
-282030593 1082010215
1555716025 454160709
-841653697 922154725
1948580957 -1882500971
674527549 1830235301
-1929140117 208944279
-349844013 -1556749339
-18101005 654614475
719086839 -1600725903
-345462243 274877895
611863387 -1512027079
1436243473 682361845
1227858431 892853935
-701197853 -419639691
357939365 -547989889
-1362271339 -1656186087
776249741 163468205
-1681242185 -1368946725
-47576069 252186883
-747074999 -627776597
-1900107831 1693375579
-2030484727 2110066209
1453311435 337828105
326287067 -69801933
-766499369 -635016669
-1947980077 268569707
834528023 -159560445
-1450699643 -1672807659
620428137 -22418289
-644891273 1172938649
1809824745 -320005717
766113107 -1037033531
-248958063 -445276465
-940020485 -1928521107
-2034584063 1463922469
1275247987 -1722690843
1206120449 -890469447
1841023861
1143645851
0
0 0
0 0
0 0

8
FPGA/rx_ciccomp_sim/rx_ciccomp_mlab.m
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@ -13,20 +13,20 @@
%Input Data Width: 32 %Input Data Width: 32
%Interpolation Factor: 1 %Interpolation Factor: 1
%Decimation Factor: 1 %Decimation Factor: 1
%FIR Width (Full Calculation Width Before Output Width Adjust) :46 %FIR Width (Full Calculation Width Before Output Width Adjust) :47
%----------------------------------------------------------------------------------------------------------- %-----------------------------------------------------------------------------------------------------------
%MegaWizard Scaled Coefficient Values %MegaWizard Scaled Coefficient Values
function output = rx_ciccomp_mlab(stimulation, bank); function output = rx_ciccomp_mlab(stimulation, bank);
coef_matrix_in= [0,0,0,0,0,0,0,0,0,0,0,0,0,0,-1,2,-3,4,-6,9,-12,15,-20,26,-34,43,-54,69,-86,108,-128,114,114,-128,108,-86,69,-54,43,-34,26,-20,15,-12,9,-6,4,-3,2,-1,0,0,0,0,0,0,0,0,0,0,0,0,0,0]; coef_matrix_in= [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,-1,1,-2,3,-4,6,-9,14,-22,38,-68,127,-68,38,-22,14,-9,6,-4,3,-2,1,-1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0];
INTER_FACTOR = 1; INTER_FACTOR = 1;
DECI_FACTOR = 1; DECI_FACTOR = 1;
MSB_RM = 0; MSB_RM = 0;
MSB_TYPE = 0; MSB_TYPE = 0;
LSB_RM = 0; LSB_RM = 0;
LSB_TYPE = 1; LSB_TYPE = 1;
FIR_WIDTH = 46 + MSB_RM + LSB_RM; FIR_WIDTH = 47 + MSB_RM + LSB_RM;
OUT_WIDTH = 46 ; %46 OUT_WIDTH = 47 ; %47
DATA_WIDTH = 32; DATA_WIDTH = 32;

2
FPGA/rx_ciccomp_sim/rx_ciccomp_model.m
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@ -19,7 +19,7 @@
% their respective licensors. No other licenses, including any licenses % their respective licensors. No other licenses, including any licenses
% needed under any third party's intellectual property, are provided herein. % needed under any third party's intellectual property, are provided herein.
% ================================================================================ % ================================================================================
% Generated on: 02/12/2021 16:11:12 % Generated on: 02/12/2021 16:50:51
% Generated by: FIR Compiler II 18.1 % Generated by: FIR Compiler II 18.1
%--------------------------------------------------------------------------------------------------------- %---------------------------------------------------------------------------------------------------------
% %

8
FPGA/rx_ciccomp_sim/rx_ciccomp_param.txt
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@ -4,12 +4,12 @@ ChansPerPhyIn : 1
ChansPerPhyOut : 1 ChansPerPhyOut : 1
InWidth : 32 InWidth : 32
InFracWidth : 0 InFracWidth : 0
OutWidth : 46 OutWidth : 47
OutFullWidth : 46 OutFullWidth : 47
OutFracWidth : 0 OutFracWidth : 0
OutFullFracWidth : 0 OutFullFracWidth : 0
nChans : 64 nChans : 65
nTaps : 64 nTaps : 65
clockRate : 64.320 clockRate : 64.320
inRate : 0.048 inRate : 0.048
interpN : 1 interpN : 1

407
FPGA/rx_ciccomp_sim/rx_ciccomp_rtl_core.vhd
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@ -16,7 +16,7 @@
-- --------------------------------------------------------------------------- -- ---------------------------------------------------------------------------
-- VHDL created from rx_ciccomp_rtl_core -- VHDL created from rx_ciccomp_rtl_core
-- VHDL created on Fri Feb 12 16:11:12 2021 -- VHDL created on Fri Feb 12 16:50:50 2021
library IEEE; library IEEE;
@ -38,7 +38,7 @@ entity rx_ciccomp_rtl_core is
xIn_0 : in std_logic_vector(31 downto 0); -- sfix32 xIn_0 : in std_logic_vector(31 downto 0); -- sfix32
xOut_v : out std_logic_vector(0 downto 0); -- ufix1 xOut_v : out std_logic_vector(0 downto 0); -- ufix1
xOut_c : out std_logic_vector(7 downto 0); -- ufix8 xOut_c : out std_logic_vector(7 downto 0); -- ufix8
xOut_0 : out std_logic_vector(45 downto 0); -- sfix46 xOut_0 : out std_logic_vector(46 downto 0); -- sfix47
clk : in std_logic; clk : in std_logic;
areset : in std_logic areset : in std_logic
); );
@ -51,8 +51,8 @@ architecture normal of rx_ciccomp_rtl_core is
signal GND_q : STD_LOGIC_VECTOR (0 downto 0); signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0); signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal d_xIn_0_13_q : STD_LOGIC_VECTOR (31 downto 0); signal d_xIn_0_15_q : STD_LOGIC_VECTOR (31 downto 0);
signal d_in0_m0_wi0_wo0_assign_id1_q_13_q : STD_LOGIC_VECTOR (0 downto 0); signal d_in0_m0_wi0_wo0_assign_id1_q_15_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_run_count : STD_LOGIC_VECTOR (1 downto 0); signal u0_m0_wo0_run_count : STD_LOGIC_VECTOR (1 downto 0);
signal u0_m0_wo0_run_preEnaQ : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_run_preEnaQ : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_run_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_run_q : STD_LOGIC_VECTOR (0 downto 0);
@ -60,46 +60,64 @@ architecture normal of rx_ciccomp_rtl_core is
signal u0_m0_wo0_run_enableQ : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_run_enableQ : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_run_ctrl : STD_LOGIC_VECTOR (2 downto 0); signal u0_m0_wo0_run_ctrl : STD_LOGIC_VECTOR (2 downto 0);
signal u0_m0_wo0_memread_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_memread_q : STD_LOGIC_VECTOR (0 downto 0);
signal d_u0_m0_wo0_memread_q_13_q : STD_LOGIC_VECTOR (0 downto 0);
signal d_u0_m0_wo0_memread_q_14_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_compute_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_compute_q : STD_LOGIC_VECTOR (0 downto 0);
signal d_u0_m0_wo0_compute_q_15_q : STD_LOGIC_VECTOR (0 downto 0); signal d_u0_m0_wo0_compute_q_17_q : STD_LOGIC_VECTOR (0 downto 0);
signal d_u0_m0_wo0_compute_q_16_q : STD_LOGIC_VECTOR (0 downto 0); signal d_u0_m0_wo0_compute_q_18_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count0_inner_q : STD_LOGIC_VECTOR (6 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count0_inner_q : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count0_inner_i : SIGNED (6 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count0_inner_i : SIGNED (6 downto 0);
attribute preserve : boolean; attribute preserve : boolean;
attribute preserve of u0_m0_wo0_wi0_r0_ra0_count0_inner_i : signal is true; attribute preserve of u0_m0_wo0_wi0_r0_ra0_count0_inner_i : signal is true;
signal u0_m0_wo0_wi0_r0_ra0_count0_q : STD_LOGIC_VECTOR (6 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count0_q : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count0_i : UNSIGNED (5 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count0_i : UNSIGNED (6 downto 0);
attribute preserve of u0_m0_wo0_wi0_r0_ra0_count0_i : signal is true; attribute preserve of u0_m0_wo0_wi0_r0_ra0_count0_i : signal is true;
signal u0_m0_wo0_wi0_r0_ra0_count1_lutreg_q : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count1_q : STD_LOGIC_VECTOR (6 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count1_q : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count1_i : UNSIGNED (5 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count1_i : UNSIGNED (6 downto 0);
attribute preserve of u0_m0_wo0_wi0_r0_ra0_count1_i : signal is true; attribute preserve of u0_m0_wo0_wi0_r0_ra0_count1_i : signal is true;
signal u0_m0_wo0_wi0_r0_ra0_add_0_0_a : STD_LOGIC_VECTOR (7 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count1_eq : std_logic;
signal u0_m0_wo0_wi0_r0_ra0_add_0_0_b : STD_LOGIC_VECTOR (7 downto 0); attribute preserve of u0_m0_wo0_wi0_r0_ra0_count1_eq : signal is true;
signal u0_m0_wo0_wi0_r0_ra0_add_0_0_o : STD_LOGIC_VECTOR (7 downto 0); signal u0_m0_wo0_wi0_r0_ra0_add_0_0_a : STD_LOGIC_VECTOR (8 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_add_0_0_q : STD_LOGIC_VECTOR (7 downto 0); signal u0_m0_wo0_wi0_r0_ra0_add_0_0_b : STD_LOGIC_VECTOR (8 downto 0);
signal u0_m0_wo0_wi0_r0_wa0_q : STD_LOGIC_VECTOR (5 downto 0); signal u0_m0_wo0_wi0_r0_ra0_add_0_0_o : STD_LOGIC_VECTOR (8 downto 0);
signal u0_m0_wo0_wi0_r0_wa0_i : UNSIGNED (5 downto 0); signal u0_m0_wo0_wi0_r0_ra0_add_0_0_q : STD_LOGIC_VECTOR (8 downto 0);
signal u0_m0_wo0_wi0_r0_wa0_q : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_wa0_i : UNSIGNED (6 downto 0);
attribute preserve of u0_m0_wo0_wi0_r0_wa0_i : signal is true; attribute preserve of u0_m0_wo0_wi0_r0_wa0_i : signal is true;
signal u0_m0_wo0_wi0_r0_memr0_reset0 : std_logic; signal u0_m0_wo0_wi0_r0_memr0_reset0 : std_logic;
signal u0_m0_wo0_wi0_r0_memr0_ia : STD_LOGIC_VECTOR (31 downto 0); signal u0_m0_wo0_wi0_r0_memr0_ia : STD_LOGIC_VECTOR (31 downto 0);
signal u0_m0_wo0_wi0_r0_memr0_aa : STD_LOGIC_VECTOR (5 downto 0); signal u0_m0_wo0_wi0_r0_memr0_aa : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_memr0_ab : STD_LOGIC_VECTOR (5 downto 0); signal u0_m0_wo0_wi0_r0_memr0_ab : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_memr0_iq : STD_LOGIC_VECTOR (31 downto 0); signal u0_m0_wo0_wi0_r0_memr0_iq : STD_LOGIC_VECTOR (31 downto 0);
signal u0_m0_wo0_wi0_r0_memr0_q : STD_LOGIC_VECTOR (31 downto 0); signal u0_m0_wo0_wi0_r0_memr0_q : STD_LOGIC_VECTOR (31 downto 0);
signal u0_m0_wo0_ca0_q : STD_LOGIC_VECTOR (5 downto 0); signal u0_m0_wo0_ca0_q : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_ca0_i : UNSIGNED (5 downto 0); signal u0_m0_wo0_ca0_i : UNSIGNED (6 downto 0);
attribute preserve of u0_m0_wo0_ca0_i : signal is true; attribute preserve of u0_m0_wo0_ca0_i : signal is true;
signal u0_m0_wo0_cm0_q : STD_LOGIC_VECTOR (7 downto 0); signal u0_m0_wo0_ca0_eq : std_logic;
attribute preserve of u0_m0_wo0_ca0_eq : signal is true;
signal u0_m0_wo0_aseq_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_aseq_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_aseq_eq : std_logic; signal u0_m0_wo0_aseq_eq : std_logic;
signal u0_m0_wo0_accum_a : STD_LOGIC_VECTOR (45 downto 0); signal u0_m0_wo0_accum_a : STD_LOGIC_VECTOR (46 downto 0);
signal u0_m0_wo0_accum_b : STD_LOGIC_VECTOR (45 downto 0); signal u0_m0_wo0_accum_b : STD_LOGIC_VECTOR (46 downto 0);
signal u0_m0_wo0_accum_i : STD_LOGIC_VECTOR (45 downto 0); signal u0_m0_wo0_accum_i : STD_LOGIC_VECTOR (46 downto 0);
signal u0_m0_wo0_accum_o : STD_LOGIC_VECTOR (45 downto 0); signal u0_m0_wo0_accum_o : STD_LOGIC_VECTOR (46 downto 0);
signal u0_m0_wo0_accum_q : STD_LOGIC_VECTOR (45 downto 0); signal u0_m0_wo0_accum_q : STD_LOGIC_VECTOR (46 downto 0);
signal u0_m0_wo0_oseq_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_oseq_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_oseq_eq : std_logic; signal u0_m0_wo0_oseq_eq : std_logic;
signal u0_m0_wo0_oseq_gated_reg_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_oseq_gated_reg_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_reset0 : std_logic;
signal u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_ia : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_aa : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_ab : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_ir : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_r : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_cm0_lutmem_reset0 : std_logic;
signal u0_m0_wo0_cm0_lutmem_ia : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_cm0_lutmem_aa : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_cm0_lutmem_ab : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_cm0_lutmem_ir : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_cm0_lutmem_r : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_mtree_mult1_0_im0_a0 : STD_LOGIC_VECTOR (17 downto 0); signal u0_m0_wo0_mtree_mult1_0_im0_a0 : STD_LOGIC_VECTOR (17 downto 0);
signal u0_m0_wo0_mtree_mult1_0_im0_b0 : STD_LOGIC_VECTOR (7 downto 0); signal u0_m0_wo0_mtree_mult1_0_im0_b0 : STD_LOGIC_VECTOR (7 downto 0);
signal u0_m0_wo0_mtree_mult1_0_im0_s1 : STD_LOGIC_VECTOR (25 downto 0); signal u0_m0_wo0_mtree_mult1_0_im0_s1 : STD_LOGIC_VECTOR (25 downto 0);
@ -116,8 +134,8 @@ architecture normal of rx_ciccomp_rtl_core is
signal u0_m0_wo0_mtree_mult1_0_result_add_0_0_q : STD_LOGIC_VECTOR (40 downto 0); signal u0_m0_wo0_mtree_mult1_0_result_add_0_0_q : STD_LOGIC_VECTOR (40 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_count0_run_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_wi0_r0_ra0_count0_run_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_oseq_gated_q : STD_LOGIC_VECTOR (0 downto 0); signal u0_m0_wo0_oseq_gated_q : STD_LOGIC_VECTOR (0 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_resize_in : STD_LOGIC_VECTOR (5 downto 0); signal u0_m0_wo0_wi0_r0_ra0_resize_in : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_wi0_r0_ra0_resize_b : STD_LOGIC_VECTOR (5 downto 0); signal u0_m0_wo0_wi0_r0_ra0_resize_b : STD_LOGIC_VECTOR (6 downto 0);
signal u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b : STD_LOGIC_VECTOR (16 downto 0); signal u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b : STD_LOGIC_VECTOR (16 downto 0);
signal u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c : STD_LOGIC_VECTOR (14 downto 0); signal u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c : STD_LOGIC_VECTOR (14 downto 0);
signal u0_m0_wo0_mtree_mult1_0_align_8_q : STD_LOGIC_VECTOR (39 downto 0); signal u0_m0_wo0_mtree_mult1_0_align_8_q : STD_LOGIC_VECTOR (39 downto 0);
@ -138,14 +156,14 @@ begin
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_run_q <= "0"; u0_m0_wo0_run_q <= "0";
u0_m0_wo0_run_enable_c := TO_SIGNED(62, 7); u0_m0_wo0_run_enable_c := TO_SIGNED(63, 7);
u0_m0_wo0_run_enableQ <= "0"; u0_m0_wo0_run_enableQ <= "0";
u0_m0_wo0_run_count <= "00"; u0_m0_wo0_run_count <= "00";
u0_m0_wo0_run_inc := (others => '0'); u0_m0_wo0_run_inc := (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (u0_m0_wo0_run_out = "1") THEN IF (u0_m0_wo0_run_out = "1") THEN
IF (u0_m0_wo0_run_enable_c(6) = '1') THEN IF (u0_m0_wo0_run_enable_c(6) = '1') THEN
u0_m0_wo0_run_enable_c := u0_m0_wo0_run_enable_c - (-63); u0_m0_wo0_run_enable_c := u0_m0_wo0_run_enable_c - (-64);
ELSE ELSE
u0_m0_wo0_run_enable_c := u0_m0_wo0_run_enable_c + (-1); u0_m0_wo0_run_enable_c := u0_m0_wo0_run_enable_c + (-1);
END IF; END IF;
@ -174,17 +192,22 @@ begin
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => u0_m0_wo0_run_q, xout => u0_m0_wo0_memread_q, clk => clk, aclr => areset ); PORT MAP ( xin => u0_m0_wo0_run_q, xout => u0_m0_wo0_memread_q, clk => clk, aclr => areset );
-- u0_m0_wo0_compute(DELAY,16)@12 -- d_u0_m0_wo0_memread_q_13(DELAY,61)@12 + 1
d_u0_m0_wo0_memread_q_13 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => u0_m0_wo0_memread_q, xout => d_u0_m0_wo0_memread_q_13_q, clk => clk, aclr => areset );
-- u0_m0_wo0_compute(DELAY,16)@13
u0_m0_wo0_compute : dspba_delay u0_m0_wo0_compute : dspba_delay
GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" ) GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => u0_m0_wo0_memread_q, xout => u0_m0_wo0_compute_q, clk => clk, aclr => areset ); PORT MAP ( xin => d_u0_m0_wo0_memread_q_13_q, xout => u0_m0_wo0_compute_q, clk => clk, aclr => areset );
-- d_u0_m0_wo0_compute_q_15(DELAY,57)@12 + 3 -- d_u0_m0_wo0_compute_q_17(DELAY,63)@13 + 4
d_u0_m0_wo0_compute_q_15 : dspba_delay d_u0_m0_wo0_compute_q_17 : dspba_delay
GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) GENERIC MAP ( width => 1, depth => 4, reset_kind => "ASYNC" )
PORT MAP ( xin => u0_m0_wo0_compute_q, xout => d_u0_m0_wo0_compute_q_15_q, clk => clk, aclr => areset ); PORT MAP ( xin => u0_m0_wo0_compute_q, xout => d_u0_m0_wo0_compute_q_17_q, clk => clk, aclr => areset );
-- u0_m0_wo0_aseq(SEQUENCE,33)@15 + 1 -- u0_m0_wo0_aseq(SEQUENCE,35)@17 + 1
u0_m0_wo0_aseq_clkproc: PROCESS (clk, areset) u0_m0_wo0_aseq_clkproc: PROCESS (clk, areset)
variable u0_m0_wo0_aseq_c : SIGNED(8 downto 0); variable u0_m0_wo0_aseq_c : SIGNED(8 downto 0);
BEGIN BEGIN
@ -193,14 +216,14 @@ begin
u0_m0_wo0_aseq_q <= "0"; u0_m0_wo0_aseq_q <= "0";
u0_m0_wo0_aseq_eq <= '0'; u0_m0_wo0_aseq_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (d_u0_m0_wo0_compute_q_15_q = "1") THEN IF (d_u0_m0_wo0_compute_q_17_q = "1") THEN
IF (u0_m0_wo0_aseq_c = "000000000") THEN IF (u0_m0_wo0_aseq_c = "000000000") THEN
u0_m0_wo0_aseq_eq <= '1'; u0_m0_wo0_aseq_eq <= '1';
ELSE ELSE
u0_m0_wo0_aseq_eq <= '0'; u0_m0_wo0_aseq_eq <= '0';
END IF; END IF;
IF (u0_m0_wo0_aseq_eq = '1') THEN IF (u0_m0_wo0_aseq_eq = '1') THEN
u0_m0_wo0_aseq_c := u0_m0_wo0_aseq_c + 63; u0_m0_wo0_aseq_c := u0_m0_wo0_aseq_c + 64;
ELSE ELSE
u0_m0_wo0_aseq_c := u0_m0_wo0_aseq_c - 1; u0_m0_wo0_aseq_c := u0_m0_wo0_aseq_c - 1;
END IF; END IF;
@ -209,126 +232,144 @@ begin
END IF; END IF;
END PROCESS; END PROCESS;
-- d_u0_m0_wo0_compute_q_16(DELAY,58)@15 + 1 -- d_u0_m0_wo0_compute_q_18(DELAY,64)@17 + 1
d_u0_m0_wo0_compute_q_16 : dspba_delay d_u0_m0_wo0_compute_q_18 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => d_u0_m0_wo0_compute_q_15_q, xout => d_u0_m0_wo0_compute_q_16_q, clk => clk, aclr => areset ); PORT MAP ( xin => d_u0_m0_wo0_compute_q_17_q, xout => d_u0_m0_wo0_compute_q_18_q, clk => clk, aclr => areset );
-- u0_m0_wo0_ca0(COUNTER,27)@12 -- u0_m0_wo0_ca0(COUNTER,29)@13
-- low=0, high=63, step=1, init=0 -- low=0, high=64, step=1, init=0
u0_m0_wo0_ca0_clkproc: PROCESS (clk, areset) u0_m0_wo0_ca0_clkproc: PROCESS (clk, areset)
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_ca0_i <= TO_UNSIGNED(0, 6); u0_m0_wo0_ca0_i <= TO_UNSIGNED(0, 7);
u0_m0_wo0_ca0_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (u0_m0_wo0_compute_q = "1") THEN IF (u0_m0_wo0_compute_q = "1") THEN
u0_m0_wo0_ca0_i <= u0_m0_wo0_ca0_i + 1; IF (u0_m0_wo0_ca0_i = TO_UNSIGNED(63, 7)) THEN
u0_m0_wo0_ca0_eq <= '1';
ELSE
u0_m0_wo0_ca0_eq <= '0';
END IF;
IF (u0_m0_wo0_ca0_eq = '1') THEN
u0_m0_wo0_ca0_i <= u0_m0_wo0_ca0_i + 64;
ELSE
u0_m0_wo0_ca0_i <= u0_m0_wo0_ca0_i + 1;
END IF;
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
u0_m0_wo0_ca0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_ca0_i, 6))); u0_m0_wo0_ca0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_ca0_i, 7)));
-- u0_m0_wo0_cm0(LOOKUP,31)@12 + 1 -- u0_m0_wo0_cm0_lutmem(DUALMEM,46)@13 + 2
u0_m0_wo0_cm0_clkproc: PROCESS (clk, areset) u0_m0_wo0_cm0_lutmem_aa <= u0_m0_wo0_ca0_q;
BEGIN u0_m0_wo0_cm0_lutmem_reset0 <= areset;
IF (areset = '1') THEN u0_m0_wo0_cm0_lutmem_dmem : altsyncram
u0_m0_wo0_cm0_q <= "00000000"; GENERIC MAP (
ELSIF (clk'EVENT AND clk = '1') THEN ram_block_type => "M9K",
CASE (u0_m0_wo0_ca0_q) IS operation_mode => "ROM",
WHEN "000000" => u0_m0_wo0_cm0_q <= "00000000"; width_a => 8,
WHEN "000001" => u0_m0_wo0_cm0_q <= "00000000"; widthad_a => 7,
WHEN "000010" => u0_m0_wo0_cm0_q <= "00000000"; numwords_a => 65,
WHEN "000011" => u0_m0_wo0_cm0_q <= "00000000"; lpm_type => "altsyncram",
WHEN "000100" => u0_m0_wo0_cm0_q <= "00000000"; width_byteena_a => 1,
WHEN "000101" => u0_m0_wo0_cm0_q <= "00000000"; outdata_reg_a => "CLOCK0",
WHEN "000110" => u0_m0_wo0_cm0_q <= "00000000"; outdata_aclr_a => "CLEAR0",
WHEN "000111" => u0_m0_wo0_cm0_q <= "00000000"; clock_enable_input_a => "NORMAL",
WHEN "001000" => u0_m0_wo0_cm0_q <= "00000000"; power_up_uninitialized => "FALSE",
WHEN "001001" => u0_m0_wo0_cm0_q <= "00000000"; init_file => "rx_ciccomp_rtl_core_u0_m0_wo0_cm0_lutmem.hex",
WHEN "001010" => u0_m0_wo0_cm0_q <= "00000000"; init_file_layout => "PORT_A",
WHEN "001011" => u0_m0_wo0_cm0_q <= "00000000"; intended_device_family => "Cyclone IV E"
WHEN "001100" => u0_m0_wo0_cm0_q <= "00000000"; )
WHEN "001101" => u0_m0_wo0_cm0_q <= "00000000"; PORT MAP (
WHEN "001110" => u0_m0_wo0_cm0_q <= "11111111"; clocken0 => '1',
WHEN "001111" => u0_m0_wo0_cm0_q <= "00000010"; aclr0 => u0_m0_wo0_cm0_lutmem_reset0,
WHEN "010000" => u0_m0_wo0_cm0_q <= "11111101"; clock0 => clk,
WHEN "010001" => u0_m0_wo0_cm0_q <= "00000100"; address_a => u0_m0_wo0_cm0_lutmem_aa,
WHEN "010010" => u0_m0_wo0_cm0_q <= "11111010"; q_a => u0_m0_wo0_cm0_lutmem_ir
WHEN "010011" => u0_m0_wo0_cm0_q <= "00001001"; );
WHEN "010100" => u0_m0_wo0_cm0_q <= "11110100"; u0_m0_wo0_cm0_lutmem_r <= u0_m0_wo0_cm0_lutmem_ir(7 downto 0);
WHEN "010101" => u0_m0_wo0_cm0_q <= "00001111";
WHEN "010110" => u0_m0_wo0_cm0_q <= "11101100";
WHEN "010111" => u0_m0_wo0_cm0_q <= "00011010";
WHEN "011000" => u0_m0_wo0_cm0_q <= "11011110";
WHEN "011001" => u0_m0_wo0_cm0_q <= "00101011";
WHEN "011010" => u0_m0_wo0_cm0_q <= "11001010";
WHEN "011011" => u0_m0_wo0_cm0_q <= "01000101";
WHEN "011100" => u0_m0_wo0_cm0_q <= "10101010";
WHEN "011101" => u0_m0_wo0_cm0_q <= "01101100";
WHEN "011110" => u0_m0_wo0_cm0_q <= "10000000";
WHEN "011111" => u0_m0_wo0_cm0_q <= "01110010";
WHEN "100000" => u0_m0_wo0_cm0_q <= "01110010";
WHEN "100001" => u0_m0_wo0_cm0_q <= "10000000";
WHEN "100010" => u0_m0_wo0_cm0_q <= "01101100";
WHEN "100011" => u0_m0_wo0_cm0_q <= "10101010";
WHEN "100100" => u0_m0_wo0_cm0_q <= "01000101";
WHEN "100101" => u0_m0_wo0_cm0_q <= "11001010";
WHEN "100110" => u0_m0_wo0_cm0_q <= "00101011";
WHEN "100111" => u0_m0_wo0_cm0_q <= "11011110";
WHEN "101000" => u0_m0_wo0_cm0_q <= "00011010";
WHEN "101001" => u0_m0_wo0_cm0_q <= "11101100";
WHEN "101010" => u0_m0_wo0_cm0_q <= "00001111";
WHEN "101011" => u0_m0_wo0_cm0_q <= "11110100";
WHEN "101100" => u0_m0_wo0_cm0_q <= "00001001";
WHEN "101101" => u0_m0_wo0_cm0_q <= "11111010";
WHEN "101110" => u0_m0_wo0_cm0_q <= "00000100";
WHEN "101111" => u0_m0_wo0_cm0_q <= "11111101";
WHEN "110000" => u0_m0_wo0_cm0_q <= "00000010";
WHEN "110001" => u0_m0_wo0_cm0_q <= "11111111";
WHEN "110010" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "110011" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "110100" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "110101" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "110110" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "110111" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111000" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111001" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111010" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111011" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111100" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111101" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111110" => u0_m0_wo0_cm0_q <= "00000000";
WHEN "111111" => u0_m0_wo0_cm0_q <= "00000000";
WHEN OTHERS => -- unreachable
u0_m0_wo0_cm0_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
-- u0_m0_wo0_wi0_r0_ra0_count1(COUNTER,22)@12 -- d_u0_m0_wo0_memread_q_14(DELAY,62)@13 + 1
-- low=0, high=63, step=1, init=0 d_u0_m0_wo0_memread_q_14 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => d_u0_m0_wo0_memread_q_13_q, xout => d_u0_m0_wo0_memread_q_14_q, clk => clk, aclr => areset );
-- u0_m0_wo0_wi0_r0_ra0_count1(COUNTER,24)@12
-- low=0, high=64, step=1, init=1
u0_m0_wo0_wi0_r0_ra0_count1_clkproc: PROCESS (clk, areset) u0_m0_wo0_wi0_r0_ra0_count1_clkproc: PROCESS (clk, areset)
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_wi0_r0_ra0_count1_i <= TO_UNSIGNED(0, 6); u0_m0_wo0_wi0_r0_ra0_count1_i <= TO_UNSIGNED(1, 7);
u0_m0_wo0_wi0_r0_ra0_count1_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (u0_m0_wo0_memread_q = "1") THEN IF (u0_m0_wo0_memread_q = "1") THEN
u0_m0_wo0_wi0_r0_ra0_count1_i <= u0_m0_wo0_wi0_r0_ra0_count1_i + 1; IF (u0_m0_wo0_wi0_r0_ra0_count1_i = TO_UNSIGNED(63, 7)) THEN
u0_m0_wo0_wi0_r0_ra0_count1_eq <= '1';
ELSE
u0_m0_wo0_wi0_r0_ra0_count1_eq <= '0';
END IF;
IF (u0_m0_wo0_wi0_r0_ra0_count1_eq = '1') THEN
u0_m0_wo0_wi0_r0_ra0_count1_i <= u0_m0_wo0_wi0_r0_ra0_count1_i + 64;
ELSE
u0_m0_wo0_wi0_r0_ra0_count1_i <= u0_m0_wo0_wi0_r0_ra0_count1_i + 1;
END IF;
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
u0_m0_wo0_wi0_r0_ra0_count1_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count1_i, 7))); u0_m0_wo0_wi0_r0_ra0_count1_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count1_i, 7)));
-- u0_m0_wo0_wi0_r0_ra0_count0_inner(COUNTER,19)@12 -- u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem(DUALMEM,45)@12 + 2
-- low=-1, high=62, step=-1, init=62 u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_aa <= u0_m0_wo0_wi0_r0_ra0_count1_q;
u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_reset0 <= areset;
u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 8,
widthad_a => 7,
numwords_a => 65,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "rx_ciccomp_rtl_core_u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "Cyclone IV E"
)
PORT MAP (
clocken0 => '1',
aclr0 => u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_reset0,
clock0 => clk,
address_a => u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_aa,
q_a => u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_ir
);
u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_r <= u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_ir(7 downto 0);
-- u0_m0_wo0_wi0_r0_ra0_count1_lutreg(REG,23)@14
u0_m0_wo0_wi0_r0_ra0_count1_lutreg_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
u0_m0_wo0_wi0_r0_ra0_count1_lutreg_q <= "01000001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (d_u0_m0_wo0_memread_q_14_q = "1") THEN
u0_m0_wo0_wi0_r0_ra0_count1_lutreg_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem_r);
END IF;
END IF;
END PROCESS;
-- u0_m0_wo0_wi0_r0_ra0_count0_inner(COUNTER,19)@14
-- low=-1, high=63, step=-1, init=63
u0_m0_wo0_wi0_r0_ra0_count0_inner_clkproc: PROCESS (clk, areset) u0_m0_wo0_wi0_r0_ra0_count0_inner_clkproc: PROCESS (clk, areset)
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= TO_SIGNED(62, 7); u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= TO_SIGNED(63, 7);
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (u0_m0_wo0_memread_q = "1") THEN IF (d_u0_m0_wo0_memread_q_14_q = "1") THEN
IF (u0_m0_wo0_wi0_r0_ra0_count0_inner_i(6 downto 6) = "1") THEN IF (u0_m0_wo0_wi0_r0_ra0_count0_inner_i(6 downto 6) = "1") THEN
u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= u0_m0_wo0_wi0_r0_ra0_count0_inner_i - 65; u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= u0_m0_wo0_wi0_r0_ra0_count0_inner_i - 64;
ELSE ELSE
u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= u0_m0_wo0_wi0_r0_ra0_count0_inner_i - 1; u0_m0_wo0_wi0_r0_ra0_count0_inner_i <= u0_m0_wo0_wi0_r0_ra0_count0_inner_i - 1;
END IF; END IF;
@ -337,26 +378,26 @@ begin
END PROCESS; END PROCESS;
u0_m0_wo0_wi0_r0_ra0_count0_inner_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count0_inner_i, 7))); u0_m0_wo0_wi0_r0_ra0_count0_inner_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count0_inner_i, 7)));
-- u0_m0_wo0_wi0_r0_ra0_count0_run(LOGICAL,20)@12 -- u0_m0_wo0_wi0_r0_ra0_count0_run(LOGICAL,20)@14
u0_m0_wo0_wi0_r0_ra0_count0_run_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_count0_inner_q(6 downto 6)); u0_m0_wo0_wi0_r0_ra0_count0_run_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_count0_inner_q(6 downto 6));
-- u0_m0_wo0_wi0_r0_ra0_count0(COUNTER,21)@12 -- u0_m0_wo0_wi0_r0_ra0_count0(COUNTER,21)@14
-- low=0, high=63, step=1, init=0 -- low=0, high=127, step=1, init=0
u0_m0_wo0_wi0_r0_ra0_count0_clkproc: PROCESS (clk, areset) u0_m0_wo0_wi0_r0_ra0_count0_clkproc: PROCESS (clk, areset)
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_wi0_r0_ra0_count0_i <= TO_UNSIGNED(0, 6); u0_m0_wo0_wi0_r0_ra0_count0_i <= TO_UNSIGNED(0, 7);
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (u0_m0_wo0_memread_q = "1" and u0_m0_wo0_wi0_r0_ra0_count0_run_q = "1") THEN IF (d_u0_m0_wo0_memread_q_14_q = "1" and u0_m0_wo0_wi0_r0_ra0_count0_run_q = "1") THEN
u0_m0_wo0_wi0_r0_ra0_count0_i <= u0_m0_wo0_wi0_r0_ra0_count0_i + 1; u0_m0_wo0_wi0_r0_ra0_count0_i <= u0_m0_wo0_wi0_r0_ra0_count0_i + 1;
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
u0_m0_wo0_wi0_r0_ra0_count0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count0_i, 7))); u0_m0_wo0_wi0_r0_ra0_count0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_ra0_count0_i, 8)));
-- u0_m0_wo0_wi0_r0_ra0_add_0_0(ADD,23)@12 + 1 -- u0_m0_wo0_wi0_r0_ra0_add_0_0(ADD,25)@14 + 1
u0_m0_wo0_wi0_r0_ra0_add_0_0_a <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_ra0_count0_q); u0_m0_wo0_wi0_r0_ra0_add_0_0_a <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_ra0_count0_q);
u0_m0_wo0_wi0_r0_ra0_add_0_0_b <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_ra0_count1_q); u0_m0_wo0_wi0_r0_ra0_add_0_0_b <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_ra0_count1_lutreg_q);
u0_m0_wo0_wi0_r0_ra0_add_0_0_clkproc: PROCESS (clk, areset) u0_m0_wo0_wi0_r0_ra0_add_0_0_clkproc: PROCESS (clk, areset)
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
@ -365,38 +406,38 @@ begin
u0_m0_wo0_wi0_r0_ra0_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(u0_m0_wo0_wi0_r0_ra0_add_0_0_a) + UNSIGNED(u0_m0_wo0_wi0_r0_ra0_add_0_0_b)); u0_m0_wo0_wi0_r0_ra0_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(u0_m0_wo0_wi0_r0_ra0_add_0_0_a) + UNSIGNED(u0_m0_wo0_wi0_r0_ra0_add_0_0_b));
END IF; END IF;
END PROCESS; END PROCESS;
u0_m0_wo0_wi0_r0_ra0_add_0_0_q <= u0_m0_wo0_wi0_r0_ra0_add_0_0_o(7 downto 0); u0_m0_wo0_wi0_r0_ra0_add_0_0_q <= u0_m0_wo0_wi0_r0_ra0_add_0_0_o(8 downto 0);
-- u0_m0_wo0_wi0_r0_ra0_resize(BITSELECT,24)@13 -- u0_m0_wo0_wi0_r0_ra0_resize(BITSELECT,26)@15
u0_m0_wo0_wi0_r0_ra0_resize_in <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_add_0_0_q(5 downto 0)); u0_m0_wo0_wi0_r0_ra0_resize_in <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_add_0_0_q(6 downto 0));
u0_m0_wo0_wi0_r0_ra0_resize_b <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_resize_in(5 downto 0)); u0_m0_wo0_wi0_r0_ra0_resize_b <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_ra0_resize_in(6 downto 0));
-- d_xIn_0_13(DELAY,55)@10 + 3 -- d_xIn_0_15(DELAY,59)@10 + 5
d_xIn_0_13 : dspba_delay d_xIn_0_15 : dspba_delay
GENERIC MAP ( width => 32, depth => 3, reset_kind => "ASYNC" ) GENERIC MAP ( width => 32, depth => 5, reset_kind => "ASYNC" )
PORT MAP ( xin => xIn_0, xout => d_xIn_0_13_q, clk => clk, aclr => areset ); PORT MAP ( xin => xIn_0, xout => d_xIn_0_15_q, clk => clk, aclr => areset );
-- d_in0_m0_wi0_wo0_assign_id1_q_13(DELAY,56)@10 + 3 -- d_in0_m0_wi0_wo0_assign_id1_q_15(DELAY,60)@10 + 5
d_in0_m0_wi0_wo0_assign_id1_q_13 : dspba_delay d_in0_m0_wi0_wo0_assign_id1_q_15 : dspba_delay
GENERIC MAP ( width => 1, depth => 3, reset_kind => "ASYNC" ) GENERIC MAP ( width => 1, depth => 5, reset_kind => "ASYNC" )
PORT MAP ( xin => xIn_v, xout => d_in0_m0_wi0_wo0_assign_id1_q_13_q, clk => clk, aclr => areset ); PORT MAP ( xin => xIn_v, xout => d_in0_m0_wi0_wo0_assign_id1_q_15_q, clk => clk, aclr => areset );
-- u0_m0_wo0_wi0_r0_wa0(COUNTER,25)@13 -- u0_m0_wo0_wi0_r0_wa0(COUNTER,27)@15
-- low=0, high=63, step=1, init=63 -- low=0, high=127, step=1, init=1
u0_m0_wo0_wi0_r0_wa0_clkproc: PROCESS (clk, areset) u0_m0_wo0_wi0_r0_wa0_clkproc: PROCESS (clk, areset)
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_wi0_r0_wa0_i <= TO_UNSIGNED(63, 6); u0_m0_wo0_wi0_r0_wa0_i <= TO_UNSIGNED(1, 7);
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (d_in0_m0_wi0_wo0_assign_id1_q_13_q = "1") THEN IF (d_in0_m0_wi0_wo0_assign_id1_q_15_q = "1") THEN
u0_m0_wo0_wi0_r0_wa0_i <= u0_m0_wo0_wi0_r0_wa0_i + 1; u0_m0_wo0_wi0_r0_wa0_i <= u0_m0_wo0_wi0_r0_wa0_i + 1;
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
u0_m0_wo0_wi0_r0_wa0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_wa0_i, 6))); u0_m0_wo0_wi0_r0_wa0_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_wa0_i, 7)));
-- u0_m0_wo0_wi0_r0_memr0(DUALMEM,26)@13 -- u0_m0_wo0_wi0_r0_memr0(DUALMEM,28)@15
u0_m0_wo0_wi0_r0_memr0_ia <= STD_LOGIC_VECTOR(d_xIn_0_13_q); u0_m0_wo0_wi0_r0_memr0_ia <= STD_LOGIC_VECTOR(d_xIn_0_15_q);
u0_m0_wo0_wi0_r0_memr0_aa <= u0_m0_wo0_wi0_r0_wa0_q; u0_m0_wo0_wi0_r0_memr0_aa <= u0_m0_wo0_wi0_r0_wa0_q;
u0_m0_wo0_wi0_r0_memr0_ab <= u0_m0_wo0_wi0_r0_ra0_resize_b; u0_m0_wo0_wi0_r0_memr0_ab <= u0_m0_wo0_wi0_r0_ra0_resize_b;
u0_m0_wo0_wi0_r0_memr0_dmem : altsyncram u0_m0_wo0_wi0_r0_memr0_dmem : altsyncram
@ -404,11 +445,11 @@ begin
ram_block_type => "M9K", ram_block_type => "M9K",
operation_mode => "DUAL_PORT", operation_mode => "DUAL_PORT",
width_a => 32, width_a => 32,
widthad_a => 6, widthad_a => 7,
numwords_a => 64, numwords_a => 128,
width_b => 32, width_b => 32,
widthad_b => 6, widthad_b => 7,
numwords_b => 64, numwords_b => 128,
lpm_type => "altsyncram", lpm_type => "altsyncram",
width_byteena_a => 1, width_byteena_a => 1,
address_reg_b => "CLOCK0", address_reg_b => "CLOCK0",
@ -431,19 +472,19 @@ begin
clock0 => clk, clock0 => clk,
address_a => u0_m0_wo0_wi0_r0_memr0_aa, address_a => u0_m0_wo0_wi0_r0_memr0_aa,
data_a => u0_m0_wo0_wi0_r0_memr0_ia, data_a => u0_m0_wo0_wi0_r0_memr0_ia,
wren_a => d_in0_m0_wi0_wo0_assign_id1_q_13_q(0), wren_a => d_in0_m0_wi0_wo0_assign_id1_q_15_q(0),
address_b => u0_m0_wo0_wi0_r0_memr0_ab, address_b => u0_m0_wo0_wi0_r0_memr0_ab,
q_b => u0_m0_wo0_wi0_r0_memr0_iq q_b => u0_m0_wo0_wi0_r0_memr0_iq
); );
u0_m0_wo0_wi0_r0_memr0_q <= u0_m0_wo0_wi0_r0_memr0_iq(31 downto 0); u0_m0_wo0_wi0_r0_memr0_q <= u0_m0_wo0_wi0_r0_memr0_iq(31 downto 0);
-- u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select(BITSELECT,54)@13 -- u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select(BITSELECT,58)@15
u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_memr0_q(16 downto 0)); u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_memr0_q(16 downto 0));
u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_memr0_q(31 downto 17)); u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_memr0_q(31 downto 17));
-- u0_m0_wo0_mtree_mult1_0_im4(MULT,47)@13 + 2 -- u0_m0_wo0_mtree_mult1_0_im4(MULT,51)@15 + 2
u0_m0_wo0_mtree_mult1_0_im4_a0 <= STD_LOGIC_VECTOR(u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c); u0_m0_wo0_mtree_mult1_0_im4_a0 <= STD_LOGIC_VECTOR(u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_c);
u0_m0_wo0_mtree_mult1_0_im4_b0 <= STD_LOGIC_VECTOR(u0_m0_wo0_cm0_q); u0_m0_wo0_mtree_mult1_0_im4_b0 <= STD_LOGIC_VECTOR(u0_m0_wo0_cm0_lutmem_r);
u0_m0_wo0_mtree_mult1_0_im4_reset <= areset; u0_m0_wo0_mtree_mult1_0_im4_reset <= areset;
u0_m0_wo0_mtree_mult1_0_im4_component : lpm_mult u0_m0_wo0_mtree_mult1_0_im4_component : lpm_mult
GENERIC MAP ( GENERIC MAP (
@ -466,16 +507,16 @@ begin
); );
u0_m0_wo0_mtree_mult1_0_im4_q <= u0_m0_wo0_mtree_mult1_0_im4_s1; u0_m0_wo0_mtree_mult1_0_im4_q <= u0_m0_wo0_mtree_mult1_0_im4_s1;
-- u0_m0_wo0_mtree_mult1_0_align_8(BITSHIFT,51)@15 -- u0_m0_wo0_mtree_mult1_0_align_8(BITSHIFT,55)@17
u0_m0_wo0_mtree_mult1_0_align_8_qint <= u0_m0_wo0_mtree_mult1_0_im4_q & "00000000000000000"; u0_m0_wo0_mtree_mult1_0_align_8_qint <= u0_m0_wo0_mtree_mult1_0_im4_q & "00000000000000000";
u0_m0_wo0_mtree_mult1_0_align_8_q <= u0_m0_wo0_mtree_mult1_0_align_8_qint(39 downto 0); u0_m0_wo0_mtree_mult1_0_align_8_q <= u0_m0_wo0_mtree_mult1_0_align_8_qint(39 downto 0);
-- u0_m0_wo0_mtree_mult1_0_bjB3(BITJOIN,46)@13 -- u0_m0_wo0_mtree_mult1_0_bjB3(BITJOIN,50)@15
u0_m0_wo0_mtree_mult1_0_bjB3_q <= GND_q & u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b; u0_m0_wo0_mtree_mult1_0_bjB3_q <= GND_q & u0_m0_wo0_mtree_mult1_0_bs2_merged_bit_select_b;
-- u0_m0_wo0_mtree_mult1_0_im0(MULT,43)@13 + 2 -- u0_m0_wo0_mtree_mult1_0_im0(MULT,47)@15 + 2
u0_m0_wo0_mtree_mult1_0_im0_a0 <= STD_LOGIC_VECTOR(u0_m0_wo0_mtree_mult1_0_bjB3_q); u0_m0_wo0_mtree_mult1_0_im0_a0 <= STD_LOGIC_VECTOR(u0_m0_wo0_mtree_mult1_0_bjB3_q);
u0_m0_wo0_mtree_mult1_0_im0_b0 <= STD_LOGIC_VECTOR(u0_m0_wo0_cm0_q); u0_m0_wo0_mtree_mult1_0_im0_b0 <= STD_LOGIC_VECTOR(u0_m0_wo0_cm0_lutmem_r);
u0_m0_wo0_mtree_mult1_0_im0_reset <= areset; u0_m0_wo0_mtree_mult1_0_im0_reset <= areset;
u0_m0_wo0_mtree_mult1_0_im0_component : lpm_mult u0_m0_wo0_mtree_mult1_0_im0_component : lpm_mult
GENERIC MAP ( GENERIC MAP (
@ -498,7 +539,7 @@ begin
); );
u0_m0_wo0_mtree_mult1_0_im0_q <= u0_m0_wo0_mtree_mult1_0_im0_s1; u0_m0_wo0_mtree_mult1_0_im0_q <= u0_m0_wo0_mtree_mult1_0_im0_s1;
-- u0_m0_wo0_mtree_mult1_0_result_add_0_0(ADD,53)@15 + 1 -- u0_m0_wo0_mtree_mult1_0_result_add_0_0(ADD,57)@17 + 1
u0_m0_wo0_mtree_mult1_0_result_add_0_0_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((40 downto 26 => u0_m0_wo0_mtree_mult1_0_im0_q(25)) & u0_m0_wo0_mtree_mult1_0_im0_q)); u0_m0_wo0_mtree_mult1_0_result_add_0_0_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((40 downto 26 => u0_m0_wo0_mtree_mult1_0_im0_q(25)) & u0_m0_wo0_mtree_mult1_0_im0_q));
u0_m0_wo0_mtree_mult1_0_result_add_0_0_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((40 downto 40 => u0_m0_wo0_mtree_mult1_0_align_8_q(39)) & u0_m0_wo0_mtree_mult1_0_align_8_q)); u0_m0_wo0_mtree_mult1_0_result_add_0_0_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((40 downto 40 => u0_m0_wo0_mtree_mult1_0_align_8_q(39)) & u0_m0_wo0_mtree_mult1_0_align_8_q));
u0_m0_wo0_mtree_mult1_0_result_add_0_0_clkproc: PROCESS (clk, areset) u0_m0_wo0_mtree_mult1_0_result_add_0_0_clkproc: PROCESS (clk, areset)
@ -511,8 +552,8 @@ begin
END PROCESS; END PROCESS;
u0_m0_wo0_mtree_mult1_0_result_add_0_0_q <= u0_m0_wo0_mtree_mult1_0_result_add_0_0_o(40 downto 0); u0_m0_wo0_mtree_mult1_0_result_add_0_0_q <= u0_m0_wo0_mtree_mult1_0_result_add_0_0_o(40 downto 0);
-- u0_m0_wo0_accum(ADD,34)@16 + 1 -- u0_m0_wo0_accum(ADD,36)@18 + 1
u0_m0_wo0_accum_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((45 downto 41 => u0_m0_wo0_mtree_mult1_0_result_add_0_0_q(40)) & u0_m0_wo0_mtree_mult1_0_result_add_0_0_q)); u0_m0_wo0_accum_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((46 downto 41 => u0_m0_wo0_mtree_mult1_0_result_add_0_0_q(40)) & u0_m0_wo0_mtree_mult1_0_result_add_0_0_q));
u0_m0_wo0_accum_b <= STD_LOGIC_VECTOR(u0_m0_wo0_accum_q); u0_m0_wo0_accum_b <= STD_LOGIC_VECTOR(u0_m0_wo0_accum_q);
u0_m0_wo0_accum_i <= u0_m0_wo0_accum_a; u0_m0_wo0_accum_i <= u0_m0_wo0_accum_a;
u0_m0_wo0_accum_clkproc: PROCESS (clk, areset) u0_m0_wo0_accum_clkproc: PROCESS (clk, areset)
@ -520,7 +561,7 @@ begin
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_accum_o <= (others => '0'); u0_m0_wo0_accum_o <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (d_u0_m0_wo0_compute_q_16_q = "1") THEN IF (d_u0_m0_wo0_compute_q_18_q = "1") THEN
IF (u0_m0_wo0_aseq_q = "1") THEN IF (u0_m0_wo0_aseq_q = "1") THEN
u0_m0_wo0_accum_o <= u0_m0_wo0_accum_i; u0_m0_wo0_accum_o <= u0_m0_wo0_accum_i;
ELSE ELSE
@ -529,28 +570,28 @@ begin
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
u0_m0_wo0_accum_q <= u0_m0_wo0_accum_o(45 downto 0); u0_m0_wo0_accum_q <= u0_m0_wo0_accum_o(46 downto 0);
-- GND(CONSTANT,0)@0 -- GND(CONSTANT,0)@0
GND_q <= "0"; GND_q <= "0";
-- u0_m0_wo0_oseq(SEQUENCE,35)@15 + 1 -- u0_m0_wo0_oseq(SEQUENCE,37)@17 + 1
u0_m0_wo0_oseq_clkproc: PROCESS (clk, areset) u0_m0_wo0_oseq_clkproc: PROCESS (clk, areset)
variable u0_m0_wo0_oseq_c : SIGNED(8 downto 0); variable u0_m0_wo0_oseq_c : SIGNED(8 downto 0);
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
u0_m0_wo0_oseq_c := "000111111"; u0_m0_wo0_oseq_c := "001000000";
u0_m0_wo0_oseq_q <= "0"; u0_m0_wo0_oseq_q <= "0";
u0_m0_wo0_oseq_eq <= '0'; u0_m0_wo0_oseq_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN ELSIF (clk'EVENT AND clk = '1') THEN
IF (d_u0_m0_wo0_compute_q_15_q = "1") THEN IF (d_u0_m0_wo0_compute_q_17_q = "1") THEN
IF (u0_m0_wo0_oseq_c = "000000000") THEN IF (u0_m0_wo0_oseq_c = "000000000") THEN
u0_m0_wo0_oseq_eq <= '1'; u0_m0_wo0_oseq_eq <= '1';
ELSE ELSE
u0_m0_wo0_oseq_eq <= '0'; u0_m0_wo0_oseq_eq <= '0';
END IF; END IF;
IF (u0_m0_wo0_oseq_eq = '1') THEN IF (u0_m0_wo0_oseq_eq = '1') THEN
u0_m0_wo0_oseq_c := u0_m0_wo0_oseq_c + 63; u0_m0_wo0_oseq_c := u0_m0_wo0_oseq_c + 64;
ELSE ELSE
u0_m0_wo0_oseq_c := u0_m0_wo0_oseq_c - 1; u0_m0_wo0_oseq_c := u0_m0_wo0_oseq_c - 1;
END IF; END IF;
@ -559,10 +600,10 @@ begin
END IF; END IF;
END PROCESS; END PROCESS;
-- u0_m0_wo0_oseq_gated(LOGICAL,36)@16 -- u0_m0_wo0_oseq_gated(LOGICAL,38)@18
u0_m0_wo0_oseq_gated_q <= u0_m0_wo0_oseq_q and d_u0_m0_wo0_compute_q_16_q; u0_m0_wo0_oseq_gated_q <= u0_m0_wo0_oseq_q and d_u0_m0_wo0_compute_q_18_q;
-- u0_m0_wo0_oseq_gated_reg(REG,37)@16 + 1 -- u0_m0_wo0_oseq_gated_reg(REG,39)@18 + 1
u0_m0_wo0_oseq_gated_reg_clkproc: PROCESS (clk, areset) u0_m0_wo0_oseq_gated_reg_clkproc: PROCESS (clk, areset)
BEGIN BEGIN
IF (areset = '1') THEN IF (areset = '1') THEN
@ -572,7 +613,7 @@ begin
END IF; END IF;
END PROCESS; END PROCESS;
-- xOut(PORTOUT,42)@17 + 1 -- xOut(PORTOUT,44)@19 + 1
xOut_v <= u0_m0_wo0_oseq_gated_reg_q; xOut_v <= u0_m0_wo0_oseq_gated_reg_q;
xOut_c <= STD_LOGIC_VECTOR("0000000" & GND_q); xOut_c <= STD_LOGIC_VECTOR("0000000" & GND_q);
xOut_0 <= u0_m0_wo0_accum_q; xOut_0 <= u0_m0_wo0_accum_q;

67
FPGA/rx_ciccomp_sim/rx_ciccomp_rtl_core_u0_m0_wo0_cm0_lutmem.hex 100644
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@ -0,0 +1,67 @@
:020000040000FA
:0100000000FF
:0100010000FE
:0100020000FD
:0100030000FC
:0100040000FB
:0100050000FA
:0100060000F9
:0100070000F8
:0100080000F7
:0100090000F6
:01000A0000F5
:01000B0000F4
:01000C0000F3
:01000D0000F2
:01000E0000F1
:01000F0000F0
:0100100000EF
:0100110000EE
:0100120000ED
:0100130000EC
:0100140000EB
:01001500FFEB
:0100160001E8
:01001700FEEA
:0100180003E4
:01001900FCEA
:01001A0006DF
:01001B00F7ED
:01001C000ED5
:01001D00EAF8
:01001E0026BB
:01001F00BC24
:010020007F60
:01002100BC22
:0100220026B7
:01002300EAF2
:010024000ECD
:01002500F7E3
:0100260006D3
:01002700FCDC
:0100280003D4
:01002900FED8
:01002A0001D4
:01002B00FFD5
:01002C0000D3
:01002D0000D2
:01002E0000D1
:01002F0000D0
:0100300000CF
:0100310000CE
:0100320000CD
:0100330000CC
:0100340000CB
:0100350000CA
:0100360000C9
:0100370000C8
:0100380000C7
:0100390000C6
:01003A0000C5
:01003B0000C4
:01003C0000C3
:01003D0000C2
:01003E0000C1
:01003F0000C0
:0100400000BF
:00000001ff

67
FPGA/rx_ciccomp_sim/rx_ciccomp_rtl_core_u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem.hex 100644
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@ -0,0 +1,67 @@
:020000040000FA
:0100000041BE
:0100010042BC
:0100020043BA
:0100030044B8
:0100040045B6
:0100050046B4
:0100060047B2
:0100070048B0
:0100080049AE
:010009004AAC
:01000A004BAA
:01000B004CA8
:01000C004DA6
:01000D004EA4
:01000E004FA2
:01000F0050A0
:01001000519E
:01001100529C
:01001200539A
:010013005498
:010014005596
:010015005694
:010016005792
:010017005890
:01001800598E
:010019005A8C
:01001A005B8A
:01001B005C88
:01001C005D86
:01001D005E84
:01001E005F82
:01001F006080
:01002000617E
:01002100627C
:01002200637A
:010023006478
:010024006576
:010025006674
:010026006772
:010027006870
:01002800696E
:010029006A6C
:01002A006B6A
:01002B006C68
:01002C006D66
:01002D006E64
:01002E006F62
:01002F007060
:01003000715E
:01003100725C
:01003200735A
:010033007458
:010034007556
:010035007654
:010036007752
:010037007850
:01003800794E
:010039007A4C
:01003A007B4A
:01003B007C48
:01003C007D46
:01003D007E44
:01003E007F42
:01003F0000C0
:0100400001BE
:00000001ff

10
FPGA/rx_ciccomp_sim/rx_ciccomp_tb.vhd
Wyświetl plik

@ -27,7 +27,7 @@ entity rx_ciccomp_tb is
constant PHYSCHANIN_c : natural := 1; constant PHYSCHANIN_c : natural := 1;
constant PHYSCHANOUT_c : natural := 1; constant PHYSCHANOUT_c : natural := 1;
constant INWIDTH_c : natural := 32; constant INWIDTH_c : natural := 32;
constant OUTWIDTH_c : natural := 46; constant OUTWIDTH_c : natural := 47;
constant BANKINWIDTH_c : natural := 0; constant BANKINWIDTH_c : natural := 0;
constant BANKCOUNT_c : natural := 1; constant BANKCOUNT_c : natural := 1;
constant DATA_WIDTH_c : natural := (INWIDTH_c+BANKINWIDTH_c) * PHYSCHANIN_c; constant DATA_WIDTH_c : natural := (INWIDTH_c+BANKINWIDTH_c) * PHYSCHANIN_c;
@ -42,11 +42,11 @@ entity rx_ciccomp_tb is
constant INTERP_FACTOR_c : natural := 1; constant INTERP_FACTOR_c : natural := 1;
constant TOTAL_INCHANS_ALLOWED : natural := PHYSCHANIN_c * CHANSPERPHYIN_c; constant TOTAL_INCHANS_ALLOWED : natural := PHYSCHANIN_c * CHANSPERPHYIN_c;
constant TOTAL_OUTCHANS_ALLOWED : natural := PHYSCHANOUT_c * CHANSPERPHYOUT_c; constant TOTAL_OUTCHANS_ALLOWED : natural := PHYSCHANOUT_c * CHANSPERPHYOUT_c;
constant NUM_OF_TAPS_c : natural := 64; constant NUM_OF_TAPS_c : natural := 65;
constant TOTAL_EFF_COEF_c : natural := 64; constant TOTAL_EFF_COEF_c : natural := 65;
constant COEFF_BIT_WIDTH_c : natural := 8; constant COEFF_BIT_WIDTH_c : natural := 8;
constant COEFF_BUS_DATA_WIDTH_c : natural := 16; constant COEFF_BUS_DATA_WIDTH_c : natural := 16;
constant COEFF_BUS_ADDR_WIDTH : natural := 6; constant COEFF_BUS_ADDR_WIDTH : natural := 7;
end entity rx_ciccomp_tb; end entity rx_ciccomp_tb;
@ -461,7 +461,7 @@ begin -- process resetgen
reset_design <= '1'; reset_design <= '1';
wait for tclk*64*2; wait for tclk*65*2;
reset_design <= '1'; reset_design <= '1';
wait; wait;
end process reset_design_gen; end process reset_design_gen;

8
FPGA/rx_ciccomp_sim/synopsys/vcsmx/vcsmx_setup.sh
Wyświetl plik

@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable # or its authorized distributors. Please refer to the applicable
# agreement for further details. # agreement for further details.
# ACDS 18.1 625 win32 2021.02.12.17:11:14 # ACDS 18.1 625 win32 2021.02.12.17:50:53
# ---------------------------------------- # ----------------------------------------
# vcsmx - auto-generated simulation script # vcsmx - auto-generated simulation script
@ -107,7 +107,7 @@
# within the Quartus project, and generate a unified # within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design. # script which supports all the Altera IP within the design.
# ---------------------------------------- # ----------------------------------------
# ACDS 18.1 625 win32 2021.02.12.17:11:14 # ACDS 18.1 625 win32 2021.02.12.17:50:53
# ---------------------------------------- # ----------------------------------------
# initialize variables # initialize variables
TOP_LEVEL_NAME="rx_ciccomp" TOP_LEVEL_NAME="rx_ciccomp"
@ -162,6 +162,10 @@ mkdir -p ./libraries/cycloneive/
# ---------------------------------------- # ----------------------------------------
# copy RAM/ROM files to simulation directory # copy RAM/ROM files to simulation directory
if [ $SKIP_FILE_COPY -eq 0 ]; then
cp -f $QSYS_SIMDIR/rx_ciccomp_rtl_core_u0_m0_wo0_cm0_lutmem.hex ./
cp -f $QSYS_SIMDIR/rx_ciccomp_rtl_core_u0_m0_wo0_wi0_r0_ra0_count1_lut_lutmem.hex ./
fi
# ---------------------------------------- # ----------------------------------------
# compile device library files # compile device library files

4
FPGA/tx_cic.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="tx_cic" kind="tx_cic" version="1.0" fabric="QSYS"> <EnsembleReport name="tx_cic" kind="tx_cic" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) --> <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2021.02.12.17:12:54 --> <!-- 2021.02.12.18:02:45 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID"> <parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type> <type>java.lang.Integer</type>
<value>1613135574</value> <value>1613138565</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>

4
FPGA/tx_nco.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="tx_nco" kind="tx_nco" version="1.0" fabric="QSYS"> <EnsembleReport name="tx_nco" kind="tx_nco" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) --> <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2021.02.12.17:13:05 --> <!-- 2021.02.12.18:02:58 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID"> <parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type> <type>java.lang.Integer</type>
<value>1613135585</value> <value>1613138578</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>

4
Stuff/CIC_Filters/rx.m
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@ -60,9 +60,9 @@ M = 1; % Differential delay (only 1)
% ---- FIR filter parameters % ---- FIR filter parameters
% ------------------------------------------------------------------------ % ------------------------------------------------------------------------
NFIR = 64; % Filter order, must be odd when Fo = 0.5 !!! NFIR = 65; % Filter order, must be odd when Fo = 0.5 !!!
Bc = 32; % Coef. Bit-width Bc = 32; % Coef. Bit-width
Fo = 0.49; % Normalized Cutoff: 0.2 < Fo < 0.5; Fo = 0.5; % Normalized Cutoff: 0.2 < Fo < 0.5;
BETA = 8; % BETA parameter for Kaiser window (if IS_WIND = 'Y') BETA = 8; % BETA parameter for Kaiser window (if IS_WIND = 'Y')
%% ------------------------------------------------------------------------ %% ------------------------------------------------------------------------

2
Stuff/CIC_Filters/rx_fir_filter.coe
Wyświetl plik

@ -1 +1 @@
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