open-ocd-cfg

2023-06-18 18:55:46 +02:00 · 2023-06-18 18:55:46 +02:00 · ec3959a619
commit ec3959a619
--- a/.vscode/clone_stm32g0x.cfg
+++ b/.vscode/clone_stm32g0x.cfg
@ -0,0 +1,84 @@
+transport select swd
+adapter speed 100
+
+# Create a new dap, with name chip and role CPU, -enable let's OpenOCD to know to add it to the scan
+swd newdap chip cpu -enable
+
+# Create the DAP instance, this must be explicitly created according to the OpenOCD docs
+dap create chip.dap -chain-position chip.cpu
+
+# Set up the GDB target for the CPU, cortex_m is the CPU type, 
+target create chip.cpu cortex_m -dap chip.dap
+
+
+# init reads out all of the necessary information from the DAP, kicks off the debugging session, etc
+init
+
+# Read out the information from the DAP, including the ROM table
+dap info
+
+reset halt
+
+proc uv_clear_flash_sector {sector_number} {
+    echo [format "Eerasing sector 0x%02x = offset 0x%04x" [expr {$sector_number}]  [expr {$sector_number*512}]  ]
+    write_memory 0x4006F000 32 {0x09}                           ;#set erasing mode
+    write_memory 0x4006F004 32 [expr {$sector_number << 6}]
+    write_memory 0x4006F01c 32 {0xAA}                           ;#unlock flash
+    write_memory 0x4006F010 32 {0x01}                           ;#set OPSTART=1
+    read_memory 0x4006F014 32 1                                 ;#check status for 0x02
+    write_memory 0x4006F018 32 {0x55}                           ;#lock flash
+}
+
+proc uv_clear_whole_flash {} {
+    for {set i 0} {$i < 0x100} {incr i} {
+        uv_clear_flash_sector $i
+    }
+}
+
+proc uv_flash_unlock {} {
+    write_memory 0x4006F01c 32 {0xAA}     ;#unlock flash
+}
+
+proc uv_flash_lock {} {
+    write_memory 0x4006F018 32 {0x55}     ;#lock flash
+}
+
+proc uv_flash_write {address value} {
+    echo [format "Writing 0x%04x to address 0x%04x (FLASH_ADDR_REG=0x%04x)" $value $address [expr {($address>>2)+0xC000}]  ]
+    write_memory 0x4006F000 32 {0x05}                          ;#set writing mode
+    write_memory 0x4006F004 32 [expr {($address>>2)+0xC000}]   ;#set address in flash
+    write_memory 0x4006F008 32 $value                          ;#set data
+    write_memory 0x4006F010 32 {0x01}                          ;#set OPSTART=1
+    while {1} {
+        set status [read_memory 0x4006F014 32 1]
+        if {($status & 0x4) != 0} {
+            break
+	}
+}
+
+proc program {filename address} {
+    global _CHIPNAME
+
+    # Odblokuj flash
+    uv_flash_unlock
+
+    # Otwórz plik i odczytaj jego zawartość
+    set fd [open $filename "rb"]
+    set data [read $fd]
+    close $fd
+
+    # Zapisz każde słowo do flasha
+    set addr $address
+    foreach word [split $data " "] {
+        uv_flash_write $addr $word
+        incr addr 4
+    }
+
+    # Zablokuj flash
+    uv_flash_lock
+}
+
+# proc program {filename {address 0x0} {pre-verify {true}} {verify {true}} {reset {true}} {exit {true}}} {
+#     global _CHIPNAME
+#     my_program $filename $address
+# }
--- a/.vscode/launch.json
+++ b/.vscode/launch.json
@ -0,0 +1,28 @@
+{
+    "version": "0.2.0",
+    "configurations": [
+        {
+            "svdFile": "./.vscode/stm32g030.svd",
+            "cwd": "${workspaceRoot}",
+            "executable": "./build/src/decompiled/decompiled",
+            "name": "kwaczek DBG",
+            "request": "launch",
+            "type": "cortex-debug",
+            "servertype": "openocd",
+            "configFiles": [
+                "interface/cmsis-dap.cfg",
+                "./.vscode/clone_stm32g0x.cfg" // "target/swm050.cfg", //
+            ],
+            "searchDir": [
+                ".",
+                "${workspaceRoot}",
+                "${workspaceRoot}/.vscode/",
+            ],
+            "runToEntryPoint": "main",
+            "showDevDebugOutput": "both",
+            // "postLaunchCommands": [
+            //     "monitor gdb_memory_map disable",
+            // ]
+        },
+    ]
+}
--- a/.vscode/stm32g030.svd
+++ b/.vscode/stm32g030.svd
--- a/.vscode/tasks.json
+++ b/.vscode/tasks.json
@ -0,0 +1,20 @@
+{
+   "version": "2.0.0",
+   "tasks": [
+       {
+           "label": "OpenOCD",
+           "type": "shell",
+           "command": "openocd -f interface/stlink.cfg -f target/stm32g0x.cfg -c \"set CPUTAPID 0x0bb11477\"",
+           "isBackground": true,
+           "presentation": {
+               "reveal": "always",
+               "panel": "dedicated"
+           },
+           "group": {
+               "kind": "build",
+               "isDefault": true
+           },
+           "problemMatcher": []
+       }
+   ]
+}
--- a/build/.cmake/api/v1/reply/cache-v2-e7f8638ee66add4fdc98.json
+++ b/build/.cmake/api/v1/reply/cache-v2-e7f8638ee66add4fdc98.json
@ -875,7 +875,7 @@
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@ -142,6 +142,9 @@
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@ -74,6 +75,21 @@
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 C:/Users/plewa/dev/UV_K5_playground/build/src/decompiled/CMakeFiles/rebuild_cache.dir
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+  description = Building C object $out
+
+
+#############################################
+# Rule for linking C executable.
+
+rule C_EXECUTABLE_LINKER__ocl_loader_Debug
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+  command = cmd.exe /C "$PRE_LINK && C:\PROGRA~2\GNUARM~1\102021~1.10\bin\AR19DD~1.EXE $FLAGS $LINK_FLAGS $in -o $TARGET_FILE $LINK_PATH $LINK_LIBRARIES && $POST_BUILD"
+  description = Linking C executable $TARGET_FILE
+  restat = $RESTAT
+
+
 #############################################
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 build src/decompiled/rebuild_cache: phony src/decompiled/CMakeFiles/rebuild_cache.util

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+# =============================================================================
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+
+#############################################
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+
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+
+
+#############################################
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+build src/ocl_loader/ocl_loader: C_EXECUTABLE_LINKER__ocl_loader_Debug src/ocl_loader/CMakeFiles/ocl_loader.dir/main.c.obj
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+  OBJECT_DIR = src\ocl_loader\CMakeFiles\ocl_loader.dir
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+  PRE_LINK = cd .
+  TARGET_FILE = src\ocl_loader\ocl_loader
+  TARGET_PDB = ocl_loader.dbg
+
+
+#############################################
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+build src/ocl_loader/CMakeFiles/edit_cache.util: CUSTOM_COMMAND
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+  DESC = Running CMake cache editor...
+  pool = console
+  restat = 1
+
+build src/ocl_loader/edit_cache: phony src/ocl_loader/CMakeFiles/edit_cache.util
+
+
+#############################################
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+
+build src/ocl_loader/CMakeFiles/rebuild_cache.util: CUSTOM_COMMAND
+  COMMAND = cmd.exe /C "cd /D C:\Users\plewa\dev\UV_K5_playground\build\src\ocl_loader && "C:\Program Files\CMake\bin\cmake.exe" --regenerate-during-build -SC:\Users\plewa\dev\UV_K5_playground -BC:\Users\plewa\dev\UV_K5_playground\build"
+  DESC = Running CMake to regenerate build system...
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+  restat = 1
+
+build src/ocl_loader/rebuild_cache: phony src/ocl_loader/CMakeFiles/rebuild_cache.util
+
 # =============================================================================
 # Target aliases.

 build decompiled: phony src/decompiled/decompiled

+build ocl_loader: phony src/ocl_loader/ocl_loader
+
 # =============================================================================
 # Folder targets.

@ -273,7 +339,7 @@ build libs/g030_drivers/all: phony
 #############################################
 # Folder: C:/Users/plewa/dev/UV_K5_playground/build/src

-build src/all: phony src/decompiled/all
+build src/all: phony src/decompiled/all src/ocl_loader/all

 # =============================================================================

@ -282,6 +348,13 @@ build src/all: phony src/decompiled/all

 build src/decompiled/all: phony src/decompiled/decompiled

+# =============================================================================
+
+#############################################
+# Folder: C:/Users/plewa/dev/UV_K5_playground/build/src/ocl_loader
+
+build src/ocl_loader/all: phony src/ocl_loader/ocl_loader
+
 # =============================================================================
 # Built-in targets

@ -289,14 +362,14 @@ build src/decompiled/all: phony src/decompiled/decompiled
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  "file": "C:\\Users\\plewa\\dev\\UV_K5_playground\\src\\decompiled\\decompiled.c",
  "output": "src\\decompiled\\CMakeFiles\\decompiled.dir\\decompiled.c.obj"
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+  "file": "C:\\Users\\plewa\\dev\\UV_K5_playground\\src\\ocl_loader\\main.c",
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 endif()

+if(NOT CMAKE_INSTALL_LOCAL_ONLY)
+  # Include the install script for the subdirectory.
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+endif()
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+:1000000010B500F000F8002380219A0089035218EF
+:0A00100013600133642BF7D1FEE703
+:04001C00F8B5C0462D
+:04002000F8B5C04629
+:0400000520000001D6
+:00000001FF
--- a/build/uv-k5-custom-build.map
+++ b/build/uv-k5-custom-build.map
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@ -1 +1,2 @@
-add_subdirectory(decompiled)
+add_subdirectory(decompiled)
+add_subdirectory(ocl_loader)
--- a/src/ocl_loader/CMakeLists.txt
+++ b/src/ocl_loader/CMakeLists.txt
@ -0,0 +1,62 @@
+set(NAME ocl_loader)
+set(MCU_TARGET_FILES_DIR ../mcu_target_common)
+
+
+add_executable(${NAME}  
+        main.c
+)
+
+target_link_libraries(${NAME}
+   mcu_drivers
+)
+
+target_include_directories(${NAME} PUBLIC
+        ./
+        Drivers/CMSIS/Device/ST/STM32G0xx/Include
+        Drivers/CMSIS/DSP/Include
+        Drivers/CMSIS/Include
+)
+
+target_compile_definitions(${NAME} PRIVATE
+        ${STM32_DEFINES}
+        $<$<CONFIG:Debug>:DEBUG_ENABLED>
+)
+
+target_compile_options(${NAME} PRIVATE
+        -mthumb -mcpu=cortex-m0plus -mfpu=auto -mfloat-abi=soft -fno-exceptions 
+        -msoft-float -Wall $<$<COMPILE_LANGUAGE:CXX>:-Wno-register> -Wno-unknown-pragmas 
+        -O${OPTI_FLAG} $<$<COMPILE_LANGUAGE:CXX>:-fno-rtti>
+        $<$<CONFIG:Debug>:--debug -DDEBUG>
+        -ffunction-sections -fdata-sections -gdwarf-3
+        -nostartfiles -fno-strict-aliasing
+)
+
+target_link_options(${NAME} PRIVATE
+        #-print-multi-lib
+        -T ${CMAKE_CURRENT_SOURCE_DIR}/ram.lds #${CMAKE_SOURCE_DIR}/
+        -mcpu=cortex-m0plus
+        -mthumb
+        -mfpu=auto
+        -mfloat-abi=soft #lets go fpu
+        -specs=nosys.specs
+        -specs=nano.specs
+        -lc
+        -lm
+        -lnosys
+        -Wl,-Map=${PROJECT_NAME}.map,--cref
+        -Wl,--gc-sections
+        -Wl,--print-memory-usage
+        -Wstack-usage=128
+        -Wno-register
+)
+
+add_custom_command(TARGET ${NAME}
+        POST_BUILD
+        COMMAND arm-none-eabi-size ${NAME}
+)
+#convert to hex
+add_custom_command(TARGET ${NAME}
+        POST_BUILD
+        COMMAND arm-none-eabi-objcopy -O ihex ${NAME} ${NAME}.hex
+        COMMAND arm-none-eabi-objcopy -O binary ${NAME} ${NAME}.bin
+)
--- a/src/ocl_loader/main.c
+++ b/src/ocl_loader/main.c
@ -0,0 +1,189 @@
+#include "registers.hpp"
+#include <stdint.h>
+#include "stm32l4x.h"
+
+static inline __attribute__((always_inline))
+void copy_buffer_u32(uint32_t *dst, uint32_t *src, int len)
+{
+	for (int i = 0; i < len; i++)
+		dst[i] = src[i];
+}
+
+/* this function is assumes that fifo_size is multiple of flash_word_size
+ * this condition is ensured by target_run_flash_async_algorithm
+ */
+
+void write(volatile struct stm32l4_work_area *work_area,
+		   uint8_t *fifo_end,
+		   uint8_t *target_address,
+		   uint32_t count)
+{
+	volatile uint32_t *flash_sr = (uint32_t *) work_area->params.flash_sr_addr;
+	volatile uint32_t *flash_cr = (uint32_t *) work_area->params.flash_cr_addr;
+
+	/* optimization to avoid reading from memory each time */
+	uint8_t *rp_cache  = work_area->fifo.rp;
+
+	/* fifo_start is used to wrap when we reach fifo_end */
+	uint8_t *fifo_start = rp_cache;
+
+	/* enable flash programming */
+	*flash_cr = FLASH_PG;
+
+	while (count) {
+		/* optimization to avoid reading from memory each time */
+		uint8_t *wp_cache  = work_area->fifo.wp;
+		if (wp_cache == 0)
+			break; /* aborted by target_run_flash_async_algorithm */
+
+		int32_t fifo_size = wp_cache - rp_cache;
+		if (fifo_size < 0) {
+			/* consider the linear fifo, we will wrap later */
+			fifo_size = fifo_end - rp_cache;
+		}
+
+		/* wait for at least a flash word */
+		while (fifo_size >= work_area->params.flash_word_size) {
+			copy_buffer_u32((uint32_t *)target_address,
+					(uint32_t *)rp_cache,
+					work_area->params.flash_word_size / 4);
+
+			/* update target_address and rp_cache */
+			target_address += work_area->params.flash_word_size;
+			rp_cache += work_area->params.flash_word_size;
+
+			/* wait for the busy flag */
+			while (*flash_sr & work_area->params.flash_sr_bsy_mask)
+				;
+
+			if (*flash_sr & FLASH_ERROR) {
+				work_area->fifo.rp = 0; /* set rp to zero 0 on error */
+				goto write_end;
+			}
+
+			/* wrap if reach the fifo_end, and update rp in memory */
+			if (rp_cache >= fifo_end)
+				rp_cache = fifo_start;
+
+			/* flush the rp cache value,
+			 * so target_run_flash_async_algorithm can fill the circular fifo */
+			work_area->fifo.rp = rp_cache;
+
+			/* update fifo_size and count */
+			fifo_size -= work_area->params.flash_word_size;
+			count--;
+		}
+	}
+
+write_end:
+	/* disable flash programming */
+	*flash_cr = 0;
+
+	/* soft break the loader */
+	__asm("bkpt 0");
+}
+
+/* by enabling this define 'DEBUG':
+ * the main() function can help help debugging the loader algo
+ * note: the application should be linked into RAM */
+
+/* #define DEBUG */
+
+#ifdef DEBUG
+/* device selector: STM32L5 | STM32U5 | STM32WB | STM32WL | STM32WL_CPU2 | STM32G0Bx | ... */
+#define STM32U5
+
+/* when using a secure device, and want to test the secure programming enable this define */
+/* #define SECURE */
+
+#if defined(STM32U5)
+#  define FLASH_WORD_SIZE   16
+#else
+#  define FLASH_WORD_SIZE   8
+#endif
+
+#if defined(STM32WB) || defined(STM32WL)
+#  define FLASH_BASE        0x58004000
+#else
+#  define FLASH_BASE        0x40022000
+#endif
+
+#if defined(STM32G0Bx)
+#  define FLASH_BSY_MASK      (FLASH_BSY | FLASH_BSY2)
+#else
+#  define FLASH_BSY_MASK      FLASH_BSY
+#endif
+
+#if defined(STM32L5) || defined(STM32U5)
+#  ifdef SECURE
+#    define FLASH_KEYR_OFFSET 0x0c
+#    define FLASH_SR_OFFSET   0x24
+#    define FLASH_CR_OFFSET   0x2c
+#  else
+#    define FLASH_KEYR_OFFSET 0x08
+#    define FLASH_SR_OFFSET   0x20
+#    define FLASH_CR_OFFSET   0x28
+#  endif
+#elif defined(STM32WL_CPU2)
+#  define FLASH_KEYR_OFFSET 0x08
+#  define FLASH_SR_OFFSET   0x60
+#  define FLASH_CR_OFFSET   0x64
+#else
+#  define FLASH_KEYR_OFFSET 0x08
+#  define FLASH_SR_OFFSET   0x10
+#  define FLASH_CR_OFFSET   0x14
+#endif
+
+#define FLASH_KEYR        (uint32_t *)((FLASH_BASE) + (FLASH_KEYR_OFFSET))
+#define FLASH_SR          (uint32_t *)((FLASH_BASE) + (FLASH_SR_OFFSET))
+#define FLASH_CR          (uint32_t *)((FLASH_BASE) + (FLASH_CR_OFFSET))
+
+int main()
+{
+	const uint32_t count = 2;
+	const uint32_t buf_size = count * FLASH_WORD_SIZE;
+	const uint32_t work_area_size = sizeof(struct stm32l4_work_area) + buf_size;
+
+	uint8_t work_area_buf[work_area_size];
+	struct stm32l4_work_area *workarea = (struct stm32l4_work_area *)work_area_buf;
+
+	/* fill the workarea struct */
+	workarea->params.flash_sr_addr = (uint32_t)(FLASH_SR);
+	workarea->params.flash_cr_addr = (uint32_t)(FLASH_CR);
+	workarea->params.flash_word_size = FLASH_WORD_SIZE;
+	workarea->params.flash_sr_bsy_mask = FLASH_BSY_MASK;
+	/* note: the workarea->stack is not used, in this configuration */
+
+	/* programming the existing memory raw content in workarea->fifo.buf */
+	/* feel free to fill the memory with magical values ... */
+
+	workarea->fifo.wp =  (uint8_t *)(&workarea->fifo.buf + buf_size);
+	workarea->fifo.rp =  (uint8_t *)&workarea->fifo.buf;
+
+	/* unlock the flash */
+	*FLASH_KEYR = KEY1;
+	*FLASH_KEYR = KEY2;
+
+	/* erase sector 0 */
+	*FLASH_CR = FLASH_PER | FLASH_STRT;
+	while (*FLASH_SR & FLASH_BSY)
+		;
+
+	/* flash address, should be aligned to FLASH_WORD_SIZE */
+	uint8_t *target_address = (uint8_t *) 0x8000000;
+
+	write(workarea,
+		  (uint8_t *)(workarea + work_area_size),
+		  target_address,
+		  count);
+
+	while (1)
+		;
+}
+#endif /* DEBUG */
+
+__attribute__ ((section(".entry"))) void entry(void)
+{
+   main();
+}
+
--- a/src/ocl_loader/ocl.h
+++ b/src/ocl_loader/ocl.h
--- a/src/ocl_loader/ram.lds
+++ b/src/ocl_loader/ram.lds
@ -0,0 +1,44 @@
+ENTRY( entry )
+
+/* System memory map */
+MEMORY
+{
+	/* Application is stored in and executes from SRAM */
+	PROGRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x1BD8
+}
+
+/* Section allocation in memory */
+SECTIONS
+{
+	.text :
+	{
+		_text = .;
+		*(.entry*)
+		*(.text*)
+		_etext = .;
+	} > PROGRAM
+
+	.data :
+	{	_data = .;
+		*(.rodata*)
+		*(.data*)
+		_edata = .;
+	}
+
+	.bss :
+	{
+		__bss_start__ = .;
+		_bss = .;
+		*(.bss*)
+		*(COMMON)
+		_ebss = .;
+		__bss_end__ = .;
+	} > PROGRAM
+
+	.stack :
+	{
+		_stack = .;
+		*(.stack*)
+		_estack = .;
+	} > PROGRAM
+}
--- a/src/ocl_loader/registers.hpp
+++ b/src/ocl_loader/registers.hpp
@ -0,0 +1,18 @@
+#pragma once
+
+struct TFlash
+{
+   unsigned int CFG;
+   unsigned int ADDR;
+   unsigned int WDATA;
+   unsigned int START;
+   unsigned int ST;
+   unsigned int LOCK;
+   unsigned int UNLOCK;
+   unsigned int MASK;
+   unsigned int ERASETIME;
+   unsigned int PROGTIME;
+};
+
+#define FLASH_BASAE 0x4006F000
+#define FLASH ((TFlash*)FLASH_BASAE)
--- a/src/ocl_loader/stm32l4x.h
+++ b/src/ocl_loader/stm32l4x.h
@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ *   Copyright (C) 2015 by Uwe Bonnes                                      *
+ *   bon@elektron.ikp.physik.tu-darmstadt.de                               *
+ ***************************************************************************/
+
+#ifndef OPENOCD_FLASH_NOR_STM32L4X
+#define OPENOCD_FLASH_NOR_STM32L4X
+#include <stdint.h>
+
+/* IMPORTANT: this file is included by stm32l4x driver and flashloader,
+ * so please when changing this file, do not forget to check the flashloader */
+
+/* FIXME: #include "helper/bits.h" cause build errors when compiling
+ * the flashloader, for now just redefine the needed 'BIT 'macro */
+
+#ifndef BIT
+#define BIT(nr)                 (1UL << (nr))
+#endif
+
+/* FLASH_CR register bits */
+#define FLASH_PG				BIT(0)
+#define FLASH_PER				BIT(1)
+#define FLASH_MER1				BIT(2)
+#define FLASH_PAGE_SHIFT		3
+#define FLASH_BKER				BIT(11)
+#define FLASH_BKER_G0			BIT(13)
+#define FLASH_MER2				BIT(15)
+#define FLASH_STRT				BIT(16)
+#define FLASH_OPTSTRT			BIT(17)
+#define FLASH_EOPIE				BIT(24)
+#define FLASH_ERRIE				BIT(25)
+#define FLASH_OBL_LAUNCH		BIT(27)
+#define FLASH_OPTLOCK			BIT(30)
+#define FLASH_LOCK				BIT(31)
+
+/* FLASH_SR register bits */
+#define FLASH_BSY				BIT(16)
+#define FLASH_BSY2				BIT(17)
+
+/* Fast programming not used => related errors not used*/
+#define FLASH_PGSERR			BIT(7) /* Programming sequence error */
+#define FLASH_SIZERR			BIT(6) /* Size error */
+#define FLASH_PGAERR			BIT(5) /* Programming alignment error */
+#define FLASH_WRPERR			BIT(4) /* Write protection error */
+#define FLASH_PROGERR			BIT(3) /* Programming error */
+#define FLASH_OPERR				BIT(1) /* Operation error */
+#define FLASH_EOP				BIT(0) /* End of operation */
+#define FLASH_ERROR				(FLASH_PGSERR | FLASH_SIZERR | FLASH_PGAERR | \
+								FLASH_WRPERR | FLASH_PROGERR | FLASH_OPERR)
+
+/* register unlock keys */
+#define KEY1					0x45670123
+#define KEY2					0xCDEF89AB
+
+/* option register unlock key */
+#define OPTKEY1					0x08192A3B
+#define OPTKEY2					0x4C5D6E7F
+
+/* FLASH_OPTR register bits */
+#define FLASH_RDP_MASK			0xFF
+#define FLASH_G0_DUAL_BANK		BIT(21)
+#define FLASH_G4_DUAL_BANK		BIT(22)
+#define FLASH_L4_DUAL_BANK		BIT(21)
+#define FLASH_L4R_DBANK			BIT(22)
+#define FLASH_LRR_DB1M			BIT(21)
+#define FLASH_L5_DBANK			BIT(22)
+#define FLASH_L5_DB256			BIT(21)
+#define FLASH_U5_DUALBANK		BIT(21)
+#define FLASH_TZEN				BIT(31)
+
+/* FLASH secure block based bank 1/2 register offsets */
+#define FLASH_SECBB1(X) (0x80 + 4 * (X - 1))
+#define FLASH_SECBB2(X) (0xA0 + 4 * (X - 1))
+
+#define FLASH_SECBB_SECURE      0xFFFFFFFF
+#define FLASH_SECBB_NON_SECURE  0
+
+/* IDCODE register possible addresses */
+#define DBGMCU_IDCODE_G0		0x40015800
+#define DBGMCU_IDCODE_L4_G4		0xE0042000
+#define DBGMCU_IDCODE_L5		0xE0044000
+#define UID64_DEVNUM			0x1FFF7580
+#define UID64_IDS				0x1FFF7584
+#define UID64_IDS_STM32WL		0x0080E115
+
+/* Supported device IDs */
+#define DEVID_STM32L47_L48XX	0x415
+#define DEVID_STM32L43_L44XX	0x435
+#define DEVID_STM32C01XX		0x443
+#define DEVID_STM32C03XX		0x453
+#define DEVID_STM32G05_G06XX	0x456
+#define DEVID_STM32G07_G08XX	0x460
+#define DEVID_STM32L49_L4AXX	0x461
+#define DEVID_STM32L45_L46XX	0x462
+#define DEVID_STM32L41_L42XX	0x464
+#define DEVID_STM32G03_G04XX	0x466
+#define DEVID_STM32G0B_G0CXX	0x467
+#define DEVID_STM32G43_G44XX	0x468
+#define DEVID_STM32G47_G48XX	0x469
+#define DEVID_STM32L4R_L4SXX	0x470
+#define DEVID_STM32L4P_L4QXX	0x471
+#define DEVID_STM32L55_L56XX	0x472
+#define DEVID_STM32G49_G4AXX	0x479
+#define DEVID_STM32U57_U58XX	0x482
+#define DEVID_STM32WB1XX		0x494
+#define DEVID_STM32WB5XX		0x495
+#define DEVID_STM32WB3XX		0x496
+#define DEVID_STM32WLE_WL5XX	0x497
+
+/* known Flash base addresses */
+#define STM32_FLASH_BANK_BASE	0x08000000
+#define STM32_FLASH_S_BANK_BASE	0x0C000000
+
+/* offset between non-secure and secure flash registers */
+#define STM32L5_REGS_SEC_OFFSET 0x10000000
+
+/* 100 bytes as loader stack should be large enough for the loader to operate */
+#define LDR_STACK_SIZE			100
+
+struct stm32l4_work_area {
+	struct stm32l4_loader_params {
+		uint32_t flash_sr_addr;
+		uint32_t flash_cr_addr;
+		uint32_t flash_word_size;
+		uint32_t flash_sr_bsy_mask;
+	} params;
+	uint8_t stack[LDR_STACK_SIZE];
+	struct flash_async_algorithm_circbuf {
+		/* note: stm32l4_work_area struct is shared between the loader
+		 * and stm32l4x flash driver.
+		 *
+		 * '*wp' and '*rp' pointers' size is 4 bytes each since stm32l4x
+		 * devices have 32-bit processors.
+		 * however when used in openocd code, their size depends on the host
+		 *   if the host is 32-bit, then the size is 4 bytes each.
+		 *   if the host is 64-bit, then the size is 8 bytes each.
+		 * to avoid this size difference, change their types depending on the
+		 * usage (pointers for the loader, and 32-bit integers in openocd code).
+		 */
+#ifdef OPENOCD_CONTRIB_LOADERS_FLASH_STM32_STM32L4X
+		uint8_t *wp;
+		uint8_t *rp;
+#else
+		uint32_t wp;
+		uint32_t rp;
+#endif /* OPENOCD_CONTRIB_LOADERS_FLASH_STM32_STM32L4X */
+	} fifo;
+};
+
+#endif
--- a/tools/dumps/Piotr
+++ b/tools/dumps/Piotr
--- a/tools/dumps/dp32g030.cfg
+++ b/tools/dumps/dp32g030.cfg
@ -0,0 +1,105 @@
+transport select swd
+adapter speed 8000
+
+set _CHIP_NAME DP32G0xx
+# Create a new dap, with name chip and role CPU, -enable let's OpenOCD to know to add it to the scan
+swd newdap $_CHIP_NAME cpu -enable
+
+# Create the DAP instance, this must be explicitly created according to the OpenOCD docs
+dap create $_CHIP_NAME.dap -chain-position $_CHIP_NAME.cpu
+
+# Set up the GDB target for the CPU, cortex_m is the CPU type, 
+target create $_CHIP_NAME.cpu cortex_m -dap $_CHIP_NAME.dap
+
+
+# init reads out all of the necessary information from the DAP, kicks off the debugging session, etc
+init
+
+# Read out the information from the DAP, including the ROM table
+dap info
+
+set _SECTOR_SIZE 512
+proc uv_clear_flash_sector {sector_number} {
+    echo [format "Eerasing sector 0x%02x = offset 0x%04x" [expr {$sector_number}]  [expr {$sector_number*512}]  ]
+    write_memory 0x4006F000 32 {0x09}                           ;#set erasing mode
+    write_memory 0x4006F004 32 [expr {$sector_number << 6}]
+    write_memory 0x4006F01c 32 {0xAA}                           ;#unlock flash
+    write_memory 0x4006F010 32 {0x01}                           ;#set OPSTART=1
+    read_memory 0x4006F014 32 1                                 ;#check status for 0x02
+    uv_wait_busy
+	write_memory 0x4006F018 32 {0x55}                           ;#lock flash
+}
+
+proc uv_clear_whole_flash {} {
+    for {set i 0} {$i < 0x100} {incr i} {
+        uv_clear_flash_sector $i
+    }
+}
+
+proc uv_clear_sectors {sectors_count} {
+	for {set i 0} {$i < $sectors_count} {incr i} {
+        uv_clear_flash_sector $i
+    }
+}
+
+proc uv_flash_unlock {} {
+    write_memory 0x4006F01c 32 {0xAA}     ;#unlock flash
+	uv_wait_busy
+}
+
+proc uv_flash_lock {} {
+    write_memory 0x4006F018 32 {0x55}     ;#lock flash
+	uv_wait_busy
+}
+
+proc uv_flash_write {address value} {
+    write_memory 0x4006F000 32 {0x05}                          ;#set writing mode
+    write_memory 0x4006F004 32 [expr {($address>>2)+0xC000}]   ;#set address in flash
+    write_memory 0x4006F008 32 $value                          ;#set data
+    write_memory 0x4006F010 32 {0x01}                          ;#set OPSTART=1
+    while {1} {
+        set status [read_memory 0x4006F014 32 1]
+        if {($status & 0x4) != 0} {
+            break
+		}
+	}
+	uv_wait_busy
+}
+
+proc uv_wait_busy {} {
+	while {1} {
+        set status [read_memory 0x4006F014 32 1]
+        if {($status & 0x2) == 0} {
+            break
+		}
+	}
+}
+
+proc write_image {filename address} {
+	global _SECTOR_SIZE 
+	
+	set fs [file size $filename]
+    set fd [open $filename "rb"]
+	
+	uv_clear_sectors [expr {2*($fs+$_SECTOR_SIZE-1)/$_SECTOR_SIZE}]
+	uv_flash_unlock
+	
+	set addr $address
+    while {![eof $fd]} {
+        set data [read $fd 4]
+        if {[string length $data] == 4} {
+            set b0 [scan [string index $data 0] %c]
+            set b1 [scan [string index $data 1] %c]
+            set b2 [scan [string index $data 2] %c]
+            set b3 [scan [string index $data 3] %c]
+            set i_data [expr {$b0 | $b1 << 8 | $b2 << 16 | $b3 << 24}]
+			
+			echo [format "Writing 0x%04x to address 0x%04x (%02d %%)" $i_data $addr [expr {(100*($addr+3)/$fs)}]]
+            uv_flash_write $addr $i_data
+            incr addr 4
+        }
+    }
+	uv_flash_lock
+	
+    close $fd
+}
--- a/tools/dumps/dump1.bin
+++ b/tools/dumps/dump1.bin
--- a/tools/dumps/output.bin
+++ b/tools/dumps/output.bin
--- a/tools/dumps/output2.bin
+++ b/tools/dumps/output2.bin
--- a/tools/dumps/output_00000_10000.bin
+++ b/tools/dumps/output_00000_10000.bin
--- a/tools/dumps/test.bin
+++ b/tools/dumps/test.bin