kopia lustrzana https://github.com/dasm78/Si4463
282 wiersze
7.8 KiB
C
282 wiersze
7.8 KiB
C
/**
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******************************************************************************
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* @file stm8l15x_itc.c
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* @author MCD Application Team
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* @version V1.3.0
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* @date 07/14/2010
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* @brief This file provides all the ITC firmware functions.
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******************************************************************************
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* @copy
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm8l15x_itc.h"
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/** @addtogroup STM8L15x_StdPeriph_Driver
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @addtogroup ITC_Private_Functions
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* @{
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*/
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/**
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* @brief Utility function used to read CC register.
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* @param None
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* @retval CPU CC register value
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*/
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uint8_t ITC_GetCPUCC(void)
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{
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#ifdef _COSMIC_
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_asm("push cc");
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_asm("pop a");
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return; /* Ignore compiler warning, the returned value is in A register */
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#elif defined _RAISONANCE_ /* _RAISONANCE_ */
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return _getCC_();
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#else /* _IAR_ */
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asm("push cc");
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asm("pop a");
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return 0;
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#endif /* _COSMIC_*/
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}
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/**
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* @}
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*/
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/** @addtogroup ITC_Public_Functions
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* @{
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*/
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/**
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* @brief Deinitializes the ITC registers to their default reset value.
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* @param None
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* @retval None
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*/
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void ITC_DeInit(void)
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{
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ITC->ISPR1 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR2 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR3 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR4 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR5 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR6 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR7 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR8 = ITC_SPRX_RESET_VALUE;
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}
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/**
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* @brief Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
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* @param None
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* @retval The interrupt software priority bits value.
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*/
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uint8_t ITC_GetSoftIntStatus(void)
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{
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return ((uint8_t)(ITC_GetCPUCC() & CPU_SOFT_INT_DISABLED));
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}
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/**
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* @brief Gets the software priority of the specified interrupt source.
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* @param IRQn : Specifies the peripheral interrupt source.
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* @retval ITC_PriorityLevel_TypeDef : Specifies the software priority of the interrupt source.
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*/
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ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(IRQn_TypeDef IRQn)
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{
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uint8_t Value = 0;
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uint8_t Mask = 0;
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/* Check function parameters */
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assert_param(IS_ITC_IRQ(IRQn));
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/* Define the mask corresponding to the bits position in the SPR register */
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Mask = (uint8_t)(0x03U << ((IRQn % 4U) * 2U));
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switch (IRQn)
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{
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case FLASH_IRQn:
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case DMA1_CHANNEL0_1_IRQn:
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case DMA1_CHANNEL2_3_IRQn:
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Value = (uint8_t)(ITC->ISPR1 & Mask); /* Read software priority */
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break;
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case RTC_IRQn:
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case EXTIE_F_PVD_IRQn:
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case EXTIB_IRQn:
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case EXTID_IRQn:
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Value = (uint8_t)(ITC->ISPR2 & Mask); /* Read software priority */
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break;
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case EXTI0_IRQn:
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case EXTI1_IRQn:
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case EXTI2_IRQn:
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case EXTI3_IRQn:
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Value = (uint8_t)(ITC->ISPR3 & Mask); /* Read software priority */
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break;
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case EXTI4_IRQn:
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case EXTI5_IRQn:
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case EXTI6_IRQn:
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case EXTI7_IRQn:
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Value = (uint8_t)(ITC->ISPR4 & Mask); /* Read software priority */
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break;
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case LCD_IRQn:
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case SWITCH_CSS_BREAK_DAC_IRQn:
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case ADC1_COMP_IRQn:
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case TIM2_UPD_OVF_TRG_BRK_IRQn:
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Value = (uint8_t)(ITC->ISPR5 & Mask); /* Read software priority */
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break;
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case TIM2_CAP_IRQn:
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case TIM3_UPD_OVF_TRG_BRK_IRQn :
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case TIM3_CAP_IRQn:
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case TIM1_UPD_OVF_TRG_IRQn:
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Value = (uint8_t)(ITC->ISPR6 & Mask); /* Read software priority */
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break;
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case TIM1_CAP_IRQn:
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case TIM4_UPD_OVF_TRG_IRQn:
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case SPI1_IRQn:
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case USART1_TX_IRQn:
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Value = (uint8_t)(ITC->ISPR7 & Mask); /* Read software priority */
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break;
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case USART1_RX_IRQn:
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case I2C1_IRQn:
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Value = (uint8_t)(ITC->ISPR8 & Mask); /* Read software priority */
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break;
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default:
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break;
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}
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Value >>= (uint8_t)((IRQn % 4u) * 2u);
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return((ITC_PriorityLevel_TypeDef)Value);
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}
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/**
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* @brief Sets the software priority of the specified interrupt source.
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* @param IRQn : Specifies the peripheral interrupt source.
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* @param ITC_PriorityLevel : Specifies the software priority value to set,
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* can be a value of @ref ITC_PriorityLevel_TypeDef .
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* @retval None
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* @par Required preconditions:
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* - The modification of the software priority is only possible when the interrupts are disabled.
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* - The normal behavior is to disable the interrupt before calling this function, and re-enable it after.
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* - The priority level 0 cannot be set (see product specification for more details).
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*/
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void ITC_SetSoftwarePriority(IRQn_TypeDef IRQn, ITC_PriorityLevel_TypeDef ITC_PriorityLevel)
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{
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uint8_t Mask = 0;
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uint8_t NewPriority = 0;
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/* Check function parameters */
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assert_param(IS_ITC_IRQ(IRQn));
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assert_param(IS_ITC_PRIORITY(ITC_PriorityLevel));
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/* Check if interrupts are disabled */
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assert_param(IS_ITC_INTERRUPTS_DISABLED);
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/* Define the mask corresponding to the bits position in the SPR register */
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/* The mask is reversed in order to clear the 2 bits after more easily */
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Mask = (uint8_t)(~(uint8_t)(0x03U << ((IRQn % 4U) * 2U)));
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/* Define the new priority to write */
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NewPriority = (uint8_t)((uint8_t)(ITC_PriorityLevel) << ((IRQn % 4U) * 2U));
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switch (IRQn)
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{
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case FLASH_IRQn:
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case DMA1_CHANNEL0_1_IRQn:
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case DMA1_CHANNEL2_3_IRQn:
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ITC->ISPR1 &= Mask;
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ITC->ISPR1 |= NewPriority;
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break;
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case RTC_IRQn:
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case EXTIE_F_PVD_IRQn:
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case EXTIB_IRQn:
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case EXTID_IRQn:
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ITC->ISPR2 &= Mask;
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ITC->ISPR2 |= NewPriority;
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break;
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case EXTI0_IRQn:
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case EXTI1_IRQn:
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case EXTI2_IRQn:
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case EXTI3_IRQn:
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ITC->ISPR3 &= Mask;
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ITC->ISPR3 |= NewPriority;
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break;
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case EXTI4_IRQn:
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case EXTI5_IRQn:
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case EXTI6_IRQn:
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case EXTI7_IRQn:
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ITC->ISPR4 &= Mask;
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ITC->ISPR4 |= NewPriority;
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break;
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case LCD_IRQn:
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case SWITCH_CSS_BREAK_DAC_IRQn:
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case ADC1_COMP_IRQn:
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case TIM2_UPD_OVF_TRG_BRK_IRQn:
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ITC->ISPR5 &= Mask;
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ITC->ISPR5 |= NewPriority;
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break;
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case TIM2_CAP_IRQn:
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case TIM3_UPD_OVF_TRG_BRK_IRQn :
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case TIM3_CAP_IRQn:
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case TIM1_UPD_OVF_TRG_IRQn:
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ITC->ISPR6 &= Mask;
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ITC->ISPR6 |= NewPriority;
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break;
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case TIM1_CAP_IRQn:
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case TIM4_UPD_OVF_TRG_IRQn:
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case SPI1_IRQn:
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case USART1_TX_IRQn:
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ITC->ISPR7 &= Mask;
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ITC->ISPR7 |= NewPriority;
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break;
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case USART1_RX_IRQn:
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case I2C1_IRQn:
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ITC->ISPR8 &= Mask;
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ITC->ISPR8 |= NewPriority;
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break;
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default:
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break;
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}
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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