kopia lustrzana https://github.com/SP8EBC/ParaTNC
210 wiersze
3.5 KiB
C
210 wiersze
3.5 KiB
C
/*
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* io.h
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*
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* Created on: 11.06.2020
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* Author: mateusz
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*/
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#ifndef IO_H_
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#define IO_H_
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/**
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* This header file (and corresponding .c file is responsible for configuring and servicing
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* various things connected to GPIO pins. Watchdog, Output collector out (for ParaTNC) and
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* switching on/off different voltages across both ParaTNC and ParaMETEO
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*/
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#ifdef STM32F10X_MD_VL
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#include <stm32f10x.h>
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#endif
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#ifdef STM32L471xx
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#include <stm32l4xx.h>
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#endif
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void io_uart_init(void);
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void io_oc_init(void);
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void io_oc_output_low(void);
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void io_oc_output_hiz(void);
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void io_pwr_init(void);
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void io_ext_watchdog_config(void);
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void io_ext_watchdog_service(void);
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void io_buttons_init(void);
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#ifdef PARAMETEO
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void io_vbat_meas_init(int16_t a_coeff, int16_t b_coeff);
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uint16_t io_vbat_meas_get(void);
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uint16_t io_vbat_meas_average(uint16_t sample);
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void io_vbat_meas_disable(void);
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void io_vbat_meas_enable(void);
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void io_pool_vbat_r(int16_t minutes_to_wx);
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#endif
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/**
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* Keep this uncommented to configure ADC which monitor Vbatt to
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* continous mode, instead of single shot
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*/
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//#define VBAT_MEAS_CONTINOUS
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inline void io_5v_isol_sw_enable(void) {
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// ParaMETEO - UC_CNTRL_VS
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GPIOB->BSRR |= GPIO_BSRR_BS8;
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}
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inline void io_5v_isol_sw_disable(void) {
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// ParaMETEO - UC_CNTRL_VS
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GPIOB->BSRR |= GPIO_BSRR_BR8;
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}
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inline void io_12v_sw_enable(void) {
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// ParaMETEO - UC_CNTRL_VG
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GPIOA->BSRR |= GPIO_BSRR_BS6;
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}
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inline void io_12v_sw_disable(void) {
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// ParaMETEO - UC_CNTRL_VG
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GPIOA->BSRR |= GPIO_BSRR_BR6;
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}
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inline uint8_t io_get_5v_isol_sw___cntrl_vbat_s(void) {
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if ((GPIOB->ODR & (1 << 8)) != 0) {
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return 1;
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}
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else {
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return 0;
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}
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}
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inline uint8_t io_get_12v_sw___cntrl_vbat_g(void) {
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if ((GPIOA->ODR & (1 << 6)) != 0) {
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return 1;
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}
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else {
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return 0;
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}
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}
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#ifdef PARAMETEO
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inline void io___cntrl_vbat_g_enable(void) {
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GPIOA->BSRR |= GPIO_BSRR_BS6;
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}
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inline void io___cntrl_vbat_g_disable(void) {
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GPIOA->BSRR |= GPIO_BSRR_BR6;
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}
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inline void io___cntrl_vbat_s_enable(void) {
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GPIOC->BSRR |= GPIO_BSRR_BS13;
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}
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inline void io___cntrl_vbat_s_disable(void) {
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GPIOC->BSRR |= GPIO_BSRR_BR13;
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}
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inline void io___cntrl_vbat_c_enable(void) {
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GPIOA->BSRR |= GPIO_BSRR_BS1;
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}
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inline void io___cntrl_vbat_c_disable(void) {
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GPIOA->BSRR |= GPIO_BSRR_BR1;
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}
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inline void io___cntrl_vbat_r_enable(void) {
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GPIOB->BSRR |= GPIO_BSRR_BS1;
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}
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inline void io___cntrl_vbat_r_disable(void) {
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GPIOB->BSRR |= GPIO_BSRR_BR1;
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}
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inline void io___cntrl_vbat_m_enable(void) {
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GPIOB->BSRR |= GPIO_BSRR_BS0;
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}
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inline void io___cntrl_vbat_m_disable(void) {
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GPIOB->BSRR |= GPIO_BSRR_BR0;
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}
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inline void io___cntrl_gprs_pwrkey_press() {
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GPIOA->BSRR |= GPIO_BSRR_BS7;
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}
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inline void io___cntrl_gprs_pwrkey_release() {
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GPIOA->BSRR |= GPIO_BSRR_BR7;
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}
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inline void io___cntrl_gprs_dtr_low() {
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GPIOB->BSRR |= GPIO_BSRR_BR8;
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}
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inline void io___cntrl_gprs_dtr_high() {
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GPIOB->BSRR |= GPIO_BSRR_BS8;
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}
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inline uint8_t io_get_cntrl_vbat_g(void) {
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uint8_t out = 0;
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if ((GPIOA->ODR & GPIO_ODR_ODR_6) != 0) {
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out = 1;
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}
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return out;
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}
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inline uint8_t io_get_cntrl_vbat_c(void) {
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uint8_t out = 0;
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if ((GPIOA->ODR & GPIO_ODR_ODR_1) != 0) {
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out = 1;
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}
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return out;
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}
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inline uint8_t io_get_cntrl_vbat_s(void) {
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uint8_t out = 0;
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if ((GPIOC->ODR & GPIO_ODR_ODR_13) != 0) {
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out = 1;
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}
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return out;
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}
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inline uint8_t io_get_cntrl_vbat_m(void) {
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uint8_t out = 0;
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if ((GPIOB->ODR & GPIO_BSRR_BS0) != 0) {
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out = 1;
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}
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return out;
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}
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#else
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inline uint8_t io_get_cntrl_vbat_s(void) {
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return 0;
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}
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inline uint8_t io_get_cntrl_vbat_m(void) {
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return 1;
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}
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#endif
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#endif /* IO_H_ */
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