kopia lustrzana https://github.com/SP8EBC/ParaTNC
powersave rework around handling an exit from STOP2 sleep
Mateusz Lubecki
rodzic
b650142c6f
commit
cf5f6687aa
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@ -112,18 +112,15 @@
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extern int8_t pwr_save_currently_cutoff;
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void pwr_save_init(config_data_powersave_mode_t mode);
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void pwr_save_enter_stop2(void);
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void pwr_save_check_stop2_cycles(void);
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void pwr_save_exit_from_stop2(void);
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int pwr_save_switch_mode_to_c0(void);
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int pwr_save_switch_mode_to_c1(void);
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void pwr_save_switch_mode_to_c2(void);
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void pwr_save_switch_mode_to_c3(void);
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int pwr_save_switch_mode_to_m4(void);
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int pwr_save_switch_mode_to_m4a(void);
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void pwr_save_switch_mode_to_i5(void);
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void pwr_save_switch_mode_to_l6(uint16_t sleep_time);
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void pwr_save_switch_mode_to_l7(uint16_t sleep_time);
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//void pwr_save_switch_mode_to_c2(void);
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//void pwr_save_switch_mode_to_c3(void);
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//int pwr_save_switch_mode_to_m4(void);
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//int pwr_save_switch_mode_to_m4a(void);
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//void pwr_save_switch_mode_to_i5(void);
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//void pwr_save_switch_mode_to_l6(uint16_t sleep_time);
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//void pwr_save_switch_mode_to_l7(uint16_t sleep_time);
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config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t * config, const config_data_basic_t * timers, int16_t minutes_to_wx, uint16_t vbatt); // this should be called from 10 seconds pooler
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#endif
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237
src/pwr_save.c
237
src/pwr_save.c
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@ -100,80 +100,11 @@ static void pwr_save_clear_powersave_idication_bits() {
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pwr_save_lock_rtc_backup_regs();
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}
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/**
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* This function initializes everything related to power saving features
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* including programming Flash memory option bytes
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*/
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void pwr_save_init(config_data_powersave_mode_t mode) {
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// make a pointer to option byte
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uint32_t* option_byte = (uint32_t*)0x1FFF7800;
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// content of option byte read from the flash memory
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uint32_t option_byte_content = *option_byte;
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// definition of bitmask
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#define IWDG_STBY_STOP (0x3 << 17)
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// check if IWDG_STDBY and IWDG_STOP is set in ''User and read protection option bytes''
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// at 0x1FFF7800
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if ((option_byte_content & IWDG_STBY_STOP) != IWDG_STBY_STOP) {
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// unlock write/erase operations on flash memory
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FLASH->KEYR = 0x45670123;
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FLASH->KEYR = 0xCDEF89AB;
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// wait for any possible flash operation to finish (rather impossible here, but ST manual recommend doing this)
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while((FLASH->SR & FLASH_SR_BSY) != 0);
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// unlock operations on option bytes
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FLASH->OPTKEYR = 0x08192A3B;
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FLASH->OPTKEYR = 0x4C5D6E7F;
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// set the flash option register (in RAM!!)
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FLASH->OPTR |= FLASH_OPTR_IWDG_STDBY;
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FLASH->OPTR |= FLASH_OPTR_IWDG_STOP;
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// trigger an update of flash option bytes with values from RAM (from FLASH->OPTR)
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FLASH->CR |= FLASH_CR_OPTSTRT;
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// wait for option bytes to be updated
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while((FLASH->SR & FLASH_SR_BSY) != 0);
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// lock flash memory
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FLASH-> CR |= FLASH_CR_LOCK;
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// forcre reloading option bytes
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FLASH->CR |= FLASH_CR_OBL_LAUNCH;
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}
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pwr_save_unclock_rtc_backup_regs();
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// reset a status register
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REGISTER = 0;
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// switch power switch handler inhibition if it is needed
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switch (mode) {
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case PWSAVE_NONE:
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break;
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case PWSAVE_NORMAL:
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case PWSAVE_AGGRESV:
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REGISTER |= INHIBIT_PWR_SWITCH_PERIODIC_H;
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break;
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}
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pwr_save_lock_rtc_backup_regs();
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}
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/**
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* Entering STOP2 power save mode. In this mode all clocks except LSI and LSE are disabled. StaticRAM content
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* is preserved, optionally GPIO and few other peripherals can be kept power up depending on configuration
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*/
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void pwr_save_enter_stop2(void) {
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uint16_t counter = 0;
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static void pwr_save_enter_stop2(void) {
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// set 31st monitor bit
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main_set_monitor(31);
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@ -205,15 +136,6 @@ void pwr_save_enter_stop2(void) {
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// save a timestamp when micro has been switched to STOP2 mode
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REGISTER_LAST_SLEEP = RTC->TR;
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// increment the STOP2 sleep counters
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counter = (uint16_t)(REGISTER_COUNTERS & 0xFFFF);
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counter++;
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rte_main_going_sleep_count = counter;
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REGISTER_COUNTERS = (REGISTER_COUNTERS & 0xFFFF0000) | counter;
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pwr_save_lock_rtc_backup_regs();
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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@ -228,7 +150,12 @@ void pwr_save_enter_stop2(void) {
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}
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void pwr_save_check_stop2_cycles(void) {
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/**
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* Used after each of 30 seconds long STOP2 sleep, to check
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* how many sleeps the micro must be put in, to complete
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* L6/L7 powersave mode
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*/
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static void pwr_save_check_stop2_cycles(void) {
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while(1) {
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// decrement stop2 cycles for current L7 or L6 powersave mode
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@ -254,9 +181,10 @@ void pwr_save_check_stop2_cycles(void) {
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}
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/**
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* This function has to be called within RTC wakepup interrupt.
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* This function has to be called after last 30 second long cycle of STOP2 sleep,
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* to bounce all frames transmission counters.
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*/
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void pwr_save_exit_from_stop2(void) {
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static void pwr_save_exit_after_last_stop2_cycle(void) {
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uint32_t counter = 0;
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@ -333,6 +261,29 @@ void pwr_save_exit_from_stop2(void) {
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main_set_monitor(29);
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}
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/**
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* This function is called in two places within a pooler, just after the micro
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* wakes up from STOP2 deep slepp and returns from RTC interrupt handler
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*/
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static void pwr_save_after_stop2_rtc_wakeup_it(void) {
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// check if we are just after waking up from STOP2 mode
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if (rte_main_woken_up == RTE_MAIN_WOKEN_UP_RTC_INTERRUPT) {
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// if yes set curent state
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rte_main_woken_up = RTE_MAIN_WOKEN_UP_AFTER_RTC_IT;
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// check if this is an intermediate wakeup from STOP2
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pwr_save_check_stop2_cycles();
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system_clock_configure_l4();
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pwr_save_exit_after_last_stop2_cycle();
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rte_main_woken_up = RTE_MAIN_WOKEN_UP_EXITED;
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}
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}
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int pwr_save_switch_mode_to_c0(void) {
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if ((REGISTER & ALL_STATES_BITMASK) == IN_C0_STATE) {
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@ -417,7 +368,7 @@ int pwr_save_switch_mode_to_c1(void) {
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// this mode is not avaliable in HW Revision B as internal radio
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// is powered from +5V_S and external one is switched on with the same
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// line which controls +4V_G
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void pwr_save_switch_mode_to_c2(void) {
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static void pwr_save_switch_mode_to_c2(void) {
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if ((REGISTER & ALL_STATES_BITMASK) == IN_C2_STATE) {
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return;
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@ -457,7 +408,7 @@ void pwr_save_switch_mode_to_c2(void) {
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}
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void pwr_save_switch_mode_to_c3(void) {
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static void pwr_save_switch_mode_to_c3(void) {
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if ((REGISTER & ALL_STATES_BITMASK) == IN_C3_STATE) {
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return;
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@ -495,7 +446,7 @@ void pwr_save_switch_mode_to_c3(void) {
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}
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// in HW-RevB this will keep internal VHF radio module working!
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int pwr_save_switch_mode_to_m4(void) {
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static int pwr_save_switch_mode_to_m4(void) {
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if ((REGISTER & ALL_STATES_BITMASK) == IN_M4_STATE) {
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return 0;
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@ -536,7 +487,7 @@ int pwr_save_switch_mode_to_m4(void) {
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return 1;
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}
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int pwr_save_switch_mode_to_m4a(void) {
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static int pwr_save_switch_mode_to_m4a(void) {
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if ((REGISTER & ALL_STATES_BITMASK) == IN_M4_STATE) {
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return 0;
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}
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@ -573,7 +524,7 @@ int pwr_save_switch_mode_to_m4a(void) {
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return 1;
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}
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void pwr_save_switch_mode_to_i5(void) {
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static void pwr_save_switch_mode_to_i5(void) {
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if ((REGISTER & ALL_STATES_BITMASK) == IN_I5_STATE) {
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return;
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@ -614,7 +565,9 @@ void pwr_save_switch_mode_to_i5(void) {
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}
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// this will keep external VHF radio working in HW-RevB
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void pwr_save_switch_mode_to_l6(uint16_t sleep_time) {
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static void pwr_save_switch_mode_to_l6(uint16_t sleep_time) {
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uint16_t counter = 0;
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if (sleep_time > 3000u) {
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// this is an error situation
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@ -671,6 +624,15 @@ void pwr_save_switch_mode_to_l6(uint16_t sleep_time) {
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REGISTER_LAST_SLTIM = sleep_time;
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// increment the STOP2 sleep counters
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counter = (uint16_t)(REGISTER_COUNTERS & 0xFFFF);
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counter++;
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rte_main_going_sleep_count = counter;
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REGISTER_COUNTERS = (REGISTER_COUNTERS & 0xFFFF0000) | counter;
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// lock access to backup
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pwr_save_lock_rtc_backup_regs();
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@ -690,7 +652,9 @@ void pwr_save_switch_mode_to_l6(uint16_t sleep_time) {
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}
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void pwr_save_switch_mode_to_l7(uint16_t sleep_time) {
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static void pwr_save_switch_mode_to_l7(uint16_t sleep_time) {
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uint16_t counter = 0;
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if (sleep_time > 3000u) {
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// this is an error situation
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@ -751,6 +715,15 @@ void pwr_save_switch_mode_to_l7(uint16_t sleep_time) {
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REGISTER_LAST_SLTIM = sleep_time;
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// increment the STOP2 sleep counters
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counter = (uint16_t)(REGISTER_COUNTERS & 0xFFFF);
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counter++;
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rte_main_going_sleep_count = counter;
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REGISTER_COUNTERS = (REGISTER_COUNTERS & 0xFFFF0000) | counter;
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// lock access to backup
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pwr_save_lock_rtc_backup_regs();
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@ -769,6 +742,73 @@ void pwr_save_switch_mode_to_l7(uint16_t sleep_time) {
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main_set_monitor(25);
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}
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/**
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* This function initializes everything related to power saving features
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* including programming Flash memory option bytes
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*/
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void pwr_save_init(config_data_powersave_mode_t mode) {
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// make a pointer to option byte
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uint32_t* option_byte = (uint32_t*)0x1FFF7800;
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// content of option byte read from the flash memory
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uint32_t option_byte_content = *option_byte;
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// definition of bitmask
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#define IWDG_STBY_STOP (0x3 << 17)
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// check if IWDG_STDBY and IWDG_STOP is set in ''User and read protection option bytes''
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// at 0x1FFF7800
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if ((option_byte_content & IWDG_STBY_STOP) != IWDG_STBY_STOP) {
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// unlock write/erase operations on flash memory
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FLASH->KEYR = 0x45670123;
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FLASH->KEYR = 0xCDEF89AB;
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// wait for any possible flash operation to finish (rather impossible here, but ST manual recommend doing this)
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while((FLASH->SR & FLASH_SR_BSY) != 0);
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// unlock operations on option bytes
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FLASH->OPTKEYR = 0x08192A3B;
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FLASH->OPTKEYR = 0x4C5D6E7F;
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// set the flash option register (in RAM!!)
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FLASH->OPTR |= FLASH_OPTR_IWDG_STDBY;
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FLASH->OPTR |= FLASH_OPTR_IWDG_STOP;
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// trigger an update of flash option bytes with values from RAM (from FLASH->OPTR)
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FLASH->CR |= FLASH_CR_OPTSTRT;
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// wait for option bytes to be updated
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while((FLASH->SR & FLASH_SR_BSY) != 0);
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// lock flash memory
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FLASH-> CR |= FLASH_CR_LOCK;
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// forcre reloading option bytes
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FLASH->CR |= FLASH_CR_OBL_LAUNCH;
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}
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pwr_save_unclock_rtc_backup_regs();
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// reset a status register
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REGISTER = 0;
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// switch power switch handler inhibition if it is needed
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switch (mode) {
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case PWSAVE_NONE:
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break;
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case PWSAVE_NORMAL:
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case PWSAVE_AGGRESV:
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REGISTER |= INHIBIT_PWR_SWITCH_PERIODIC_H;
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break;
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}
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pwr_save_lock_rtc_backup_regs();
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}
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config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t * config, const config_data_basic_t * timers, int16_t minutes_to_wx, uint16_t vbatt) {
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// this function should be called from 10 seconds pooler
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@ -836,6 +876,9 @@ config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t *
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// go sleep immediately and periodically check if battery has been charged above restore level
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pwr_save_switch_mode_to_l7(60 * PWR_SAVE_CUTOFF_SLEEP_TIME_IN_MINUTES);
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// RTC interrupt is between this call and previous one (switching to l7)
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pwr_save_after_stop2_rtc_wakeup_it();
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return psave_mode;
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}
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@ -1101,21 +1144,7 @@ config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t *
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main_set_monitor(16);
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// check if we are just after waking up from STOP2 mode
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if (rte_main_woken_up == RTE_MAIN_WOKEN_UP_RTC_INTERRUPT) {
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// if yes set curent state
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rte_main_woken_up = RTE_MAIN_WOKEN_UP_AFTER_RTC_IT;
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// check if this is an intermediate wakeup from STOP2
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pwr_save_check_stop2_cycles();
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system_clock_configure_l4();
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pwr_save_exit_from_stop2();
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rte_main_woken_up = RTE_MAIN_WOKEN_UP_EXITED;
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}
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pwr_save_after_stop2_rtc_wakeup_it();
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main_set_monitor(13);
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