kopia lustrzana https://github.com/SP8EBC/ParaTNC
refactoring rtc backup registers set/get/reset to separate code module
Mateusz Lubecki
rodzic
11deee654a
commit
973fbd46e6
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@ -10,6 +10,7 @@ C_SRCS += \
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../src/_write.c \
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../src/api.c \
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../src/aprsis.c \
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../src/backup_registers.c \
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../src/button_parameteo.c \
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../src/delay.c \
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../src/dummy.c \
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@ -38,6 +39,7 @@ OBJS += \
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./src/_write.o \
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./src/api.o \
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./src/aprsis.o \
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./src/backup_registers.o \
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./src/button_parameteo.o \
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./src/delay.o \
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./src/dummy.o \
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@ -66,6 +68,7 @@ C_DEPS += \
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./src/_write.d \
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./src/api.d \
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./src/aprsis.d \
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./src/backup_registers.d \
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./src/button_parameteo.d \
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./src/delay.d \
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./src/dummy.d \
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@ -0,0 +1,99 @@
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/*
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* backup_registers.h
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*
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* Created on: Oct 19, 2023
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* Author: mateusz
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*/
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#ifndef BACKUP_REGISTERS_H_
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#define BACKUP_REGISTERS_H_
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#ifdef STM32L471xx
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#include <stm32l4xx.h>
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#endif
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#ifdef STM32F10X_MD_VL
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#include <stm32f10x.h>
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#endif
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// backup registers (ParaTNC)
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// 0 ->
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// 2 -> boot and hard fault count
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// 3 -> controller configuration status
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// 4 ->
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// 5 ->
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// 6 -> weather and telemetry timers & counters
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// backup registers (ParaMETEO)
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// 0 -> powersave status - not handled here
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// 1 -> last sleep rtc time
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// 2 -> last wakeup rtc time
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// 3 -> controller configuration status
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// 4 -> wakeup events MSB, sleep events LSB
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// 5 -> monitor
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// 7 -> weather and telemetry timers & counters
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#define REGISTER_MONITOR RTC->BKP5R
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/**
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* Inline used to trace an execution flow across main for(;;) loop and some
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* powersaving functions. In case of software fault it's value may help to trace
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* at witch point the crash has occured
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*/
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inline void backup_reg_set_monitor(int8_t bit) {
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#ifdef STM32L471xx
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// enable access to backup domain
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PWR->CR1 |= PWR_CR1_DBP;
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if (bit >= 0) {
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REGISTER_MONITOR |= (1 << bit);
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}
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else {
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REGISTER_MONITOR = 0;
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}
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PWR->CR1 &= (0xFFFFFFFF ^ PWR_CR1_DBP);
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#endif
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}
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inline uint32_t backup_reg_get_monitor(void) {
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return REGISTER_MONITOR;
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}
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uint32_t backup_reg_get_configuration(void);
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void backup_reg_set_configuration(uint32_t value);
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void backup_reg_set_bits_configuration(uint32_t value);
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void backup_reg_clear_bits_configuration(uint32_t value);
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void backup_reg_reset_all_powersave_states(void);
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int backup_reg_is_in_powersave_state(uint32_t state);
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void backup_reg_set_powersave_state(uint32_t state);
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uint16_t backup_reg_get_powersave_state(void);
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uint32_t backup_reg_get_wakeup_counter(void);
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void backup_reg_set_wakeup_counter(uint32_t in);
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uint32_t backup_reg_get_sleep_counter(void);
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void backup_reg_set_sleep_counter(uint32_t in);
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uint32_t backup_reg_get_last_sleep_timestamp(void);
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void backup_reg_set_last_sleep_timestamp(void);
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uint32_t backup_reg_get_last_wakeup_timestamp(void);
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void backup_reg_set_last_wakeup_timestamp(void);
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void backup_reg_reset_inhibit_periodic_pwr_switch(void);
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void backup_reg_inhibit_periodic_pwr_switch(void);
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uint32_t backup_reg_is_periodic_pwr_switch_inhibited(void);
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uint32_t backup_reg_get_last_sleep_duration(void);
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void backup_reg_set_last_sleep_duration(uint32_t);
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uint8_t backup_reg_get_telemetry(void);
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void backup_reg_set_telemetry(void);
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#endif /* BACKUP_REGISTERS_H_ */
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@ -22,22 +22,6 @@
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#define OWN_APRS_MSG_LN 256
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// backup registers (ParaMETEO)
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// 0 -> powersave status
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// 1 -> last sleep rtc time
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// 2 -> last wakeup rtc time
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// 3 -> controller configuration status
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// 4 -> wakeup events MSB, sleep events LSB
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#ifdef STM32L471xx
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#define REGISTER RTC->BKP0R
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#define REGISTER_LAST_SLEEP RTC->BKP1R
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#define REGISTER_LAST_WKUP RTC->BKP2R
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#define REGISTER_COUNTERS RTC->BKP4R
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#define REGISTER_MONITOR RTC->BKP5R
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#define REGISTER_LAST_SLTIM RTC->BKP6R
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#endif
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typedef enum main_usart_mode_t {
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USART_MODE_UNDEF,
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USART_MODE_KISS,
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@ -110,28 +94,6 @@ extern uint32_t rte_main_rx_total;
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extern uint32_t rte_main_tx_total;
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#endif
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/**
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* Inline used to trace an execution flow across main for(;;) loop and some
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* powersaving functions. In case of software fault it's value may help to trace
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* at witch point the crash has occured
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*/
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inline void main_set_monitor(int8_t bit) {
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#ifdef STM32L471xx
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// enable access to backup domain
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PWR->CR1 |= PWR_CR1_DBP;
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if (bit >= 0) {
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REGISTER_MONITOR |= (1 << bit);
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}
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else {
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REGISTER_MONITOR = 0;
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}
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PWR->CR1 &= (0xFFFFFFFF ^ PWR_CR1_DBP);
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#endif
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}
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/**
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* Block I/O function which waits for all transmission to end
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*/
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@ -22,6 +22,7 @@ typedef struct packet_tx_counter_values_t {
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void packet_tx_send_wx_frame(void);
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void packet_tx_configure(uint8_t meteo_interval, uint8_t beacon_interval, config_data_powersave_mode_t powersave);
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void packet_tx_restore_from_backupregs(void);
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void packet_tx_tcp_handler(void);
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void packet_tx_handler(const config_data_basic_t * const config_basic, const config_data_mode_t * const config_mode);
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void packet_tx_get_current_counters(packet_tx_counter_values_t * out);
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@ -0,0 +1,303 @@
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/*
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* backup_registers.cpp
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*
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* Created on: Oct 19, 2023
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* Author: mateusz
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*/
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#include "backup_registers.h"
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#ifdef STM32L471xx
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#define REGISTER RTC->BKP0R
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#define REGISTER_LAST_SLEEP RTC->BKP1R
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#define REGISTER_LAST_WKUP RTC->BKP2R
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#define REGISTER_COUNTERS RTC->BKP4R
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#define REGISTER_LAST_SLTIM RTC->BKP6R
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#endif
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#define BACKUP_REG_INHIBIT_PWR_SWITCH_PERIODIC_H 1u
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#define BACKUP_REG_ALL_PWRSAVE_STATES_BITMASK (0xFFu << 2)
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static void backup_reg_unclock(void) {
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// enable access to backup domain
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PWR->CR1 |= PWR_CR1_DBP;
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}
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static void backup_reg_lock(void) {
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PWR->CR1 &= (0xFFFFFFFFu ^ PWR_CR1_DBP);
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}
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/**
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*
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* @return
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*/
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uint32_t backup_reg_get_configuration(void) {
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uint32_t out = 0;
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#ifdef PARATNC
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out = BKP->DR3;
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#endif
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#ifdef PARAMETEO
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out = RTC->BKP3R;
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#endif
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return out;
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}
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void backup_reg_set_configuration(uint32_t value) {
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#ifdef PARATNC
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BKP->DR3 = value;
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#endif
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#ifdef PARAMETEO
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backup_reg_unclock();
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RTC->BKP3R = value;
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backup_reg_lock();
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#endif
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}
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void backup_reg_set_bits_configuration(uint32_t value) {
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#ifdef PARATNC
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BKP->DR3 |= value;
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#endif
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#ifdef PARAMETEO
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// enable access to backup domain
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backup_reg_unclock();
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RTC->BKP3R |= value;
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backup_reg_lock();
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#endif
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}
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void backup_reg_clear_bits_configuration(uint32_t value) {
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#ifdef PARATNC
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BKP->DR3 &= (0xFFFF ^ value);
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#endif
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#ifdef PARAMETEO
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// enable access to backup domain
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backup_reg_unclock();
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RTC->BKP3R &= (0xFFFFFFFFu ^ value);
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backup_reg_lock();
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#endif
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}
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/**
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*
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*/
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void backup_reg_reset_all_powersave_states(void) {
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backup_reg_unclock();
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#ifdef PARAMETEO
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REGISTER &= 0xFFFFFFFFu ^ BACKUP_REG_ALL_PWRSAVE_STATES_BITMASK;
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#endif
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backup_reg_lock();
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}
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int backup_reg_is_in_powersave_state(uint32_t state) {
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int out = 0;
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#ifdef PARAMETEO
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if ((REGISTER & BACKUP_REG_ALL_PWRSAVE_STATES_BITMASK) == state) {
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out = 1;
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}
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#endif
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return out;
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}
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void backup_reg_set_powersave_state(uint32_t state) {
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#ifdef PARAMETEO
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backup_reg_unclock();
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REGISTER |= state;
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backup_reg_lock();
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#endif
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}
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uint16_t backup_reg_get_powersave_state(void) {
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int out = 0;
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#ifdef PARAMETEO
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out = (uint16_t)(REGISTER & BACKUP_REG_ALL_PWRSAVE_STATES_BITMASK);
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#endif
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return out;
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}
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/**
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*
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* @return
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*/
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uint32_t backup_reg_get_wakeup_counter(void) {
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uint32_t out = 0;
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#ifdef PARAMETEO
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out = (uint32_t)((REGISTER_COUNTERS & 0xFFFF0000u) >> 16);
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#endif
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return out;
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}
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void backup_reg_set_wakeup_counter(uint32_t in) {
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backup_reg_unclock();
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#ifdef PARAMETEO
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REGISTER_COUNTERS = (REGISTER_COUNTERS & 0x0000FFFFu) | ((in & 0xFFFFu) << 16);
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#endif
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backup_reg_lock();
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}
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/**
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*
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* @return
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*/
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uint32_t backup_reg_get_sleep_counter(void) {
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uint32_t out = 0;
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#ifdef PARAMETEO
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out = (uint16_t)(REGISTER_COUNTERS & 0xFFFFu);
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#endif
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return out;
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}
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void backup_reg_set_sleep_counter(uint32_t in) {
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backup_reg_unclock();
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#ifdef PARAMETEO
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REGISTER_COUNTERS = (REGISTER_COUNTERS & 0xFFFF0000u) | (uint16_t)(in & 0xFFFFu);
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#endif
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backup_reg_lock();
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}
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/**
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*
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*/
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uint32_t backup_reg_get_last_sleep_timestamp(void) {
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uint32_t out = 0;
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#ifdef PARAMETEO
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out = REGISTER_LAST_SLEEP;
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#endif
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return out;
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}
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void backup_reg_set_last_sleep_timestamp(void) {
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#ifdef PARAMETEO
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backup_reg_unclock();
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REGISTER_LAST_SLEEP = RTC->TR;
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backup_reg_lock();
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#endif
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}
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/**
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*
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*/
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void backup_reg_reset_inhibit_periodic_pwr_switch(void) {
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backup_reg_unclock();
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#ifdef PARAMETEO
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REGISTER &= 0xFFFFFFFFu ^ BACKUP_REG_INHIBIT_PWR_SWITCH_PERIODIC_H;
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#endif
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backup_reg_lock();
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}
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void backup_reg_inhibit_periodic_pwr_switch(void) {
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backup_reg_unclock();
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#ifdef PARAMETEO
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REGISTER |= BACKUP_REG_INHIBIT_PWR_SWITCH_PERIODIC_H;
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#endif
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backup_reg_lock();
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}
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uint32_t backup_reg_is_periodic_pwr_switch_inhibited(void) {
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int out = 0;
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#ifdef PARAMETEO
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if ((REGISTER & BACKUP_REG_INHIBIT_PWR_SWITCH_PERIODIC_H) != 0) {
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out = 1u;
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}
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#endif
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return out;
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}
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/**
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*
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* @return
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*/
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uint32_t backup_reg_get_last_wakeup_timestamp(void) {
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uint32_t out = 0;
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#ifdef PARAMETEO
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out = REGISTER_LAST_WKUP;
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#endif
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return out;
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}
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void backup_reg_set_last_wakeup_timestamp(void) {
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#ifdef PARAMETEO
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backup_reg_unclock();
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REGISTER_LAST_WKUP = RTC->TR;
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backup_reg_lock();
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#endif
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}
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/**
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*
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* @return
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*/
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uint32_t backup_reg_get_last_sleep_duration(void) {
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uint32_t out = 0;
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#ifdef PARAMETEO
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out = REGISTER_LAST_SLTIM;
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#endif
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return out;
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}
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void backup_reg_set_last_sleep_duration(uint32_t in) {
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#ifdef PARAMETEO
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backup_reg_unclock();
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REGISTER_LAST_SLTIM = in;
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backup_reg_lock();
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#endif
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}
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@ -37,6 +37,7 @@
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#include "diag/Trace.h"
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#include "io.h"
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#include "button.h"
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#include "backup_registers.h"
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#include "rte_main.h"
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@ -99,7 +100,7 @@ void RTC_WKUP_IRQHandler(void) {
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rte_main_woken_up = RTE_MAIN_WOKEN_UP_RTC_INTERRUPT;
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main_set_monitor(13);
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backup_reg_set_monitor(13);
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main_reload_internal_wdg();
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68
src/main.c
68
src/main.c
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@ -48,6 +48,7 @@
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#include "TimerConfig.h"
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#include "PathConfig.h"
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#include "LedConfig.h"
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#include "backup_registers.h"
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#include "io.h"
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#include "float_to_string.h"
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#include "pwr_save.h"
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@ -108,7 +109,7 @@
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// 3 -> controller configuration status
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// 4 ->
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// 5 ->
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// 6 ->
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// 6 -> weather and telemetry timers & counters
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// backup registers (ParaMETEO)
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// 0 -> powersave status
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|
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@ -117,6 +118,7 @@
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// 3 -> controller configuration status
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// 4 -> wakeup events MSB, sleep events LSB
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// 5 -> monitor
|
||||
// 6 -> weather and telemetry timers & counters
|
||||
|
||||
|
||||
#define CONFIG_FIRST_RESTORED (1)
|
||||
|
|
@ -406,7 +408,7 @@ int main(int argc, char* argv[]){
|
|||
if (main_reset_config_to_default == 1) {
|
||||
main_crc_result = 0;
|
||||
|
||||
configuration_set_register(0);
|
||||
backup_reg_set_configuration(0);
|
||||
|
||||
#if defined(PARAMETEO)
|
||||
nvm_erase_all();
|
||||
|
|
@ -416,32 +418,32 @@ int main(int argc, char* argv[]){
|
|||
}
|
||||
|
||||
// if first section has wrong CRC and it hasn't been restored before
|
||||
if ((main_crc_result & 0x01) == 0 && (configuration_get_register() & CONFIG_FIRST_FAIL_RESTORING) == 0) {
|
||||
if ((main_crc_result & 0x01) == 0 && (backup_reg_get_configuration() & CONFIG_FIRST_FAIL_RESTORING) == 0) {
|
||||
// restore default configuration
|
||||
if (configuration_handler_restore_default_first() == 0) {
|
||||
|
||||
// if configuration has been restored successfully
|
||||
configuration_set_bits_register(CONFIG_FIRST_RESTORED);
|
||||
backup_reg_set_bits_configuration(CONFIG_FIRST_RESTORED);
|
||||
|
||||
// set also CRC flag because if restoring is successfull the region has good CRC
|
||||
configuration_set_bits_register(CONFIG_FIRST_CRC_OK);
|
||||
backup_reg_set_bits_configuration(CONFIG_FIRST_CRC_OK);
|
||||
|
||||
}
|
||||
else {
|
||||
// if not store the flag in the backup register to block
|
||||
// reinitializing once again in the consecutive restart
|
||||
configuration_set_bits_register(CONFIG_FIRST_FAIL_RESTORING);
|
||||
backup_reg_set_bits_configuration(CONFIG_FIRST_FAIL_RESTORING);
|
||||
|
||||
configuration_clear_bits_register(CONFIG_FIRST_CRC_OK);
|
||||
backup_reg_clear_bits_configuration(CONFIG_FIRST_CRC_OK);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
else {
|
||||
// if the combined confition is not met check failed restoring flag
|
||||
if ((configuration_get_register() & CONFIG_FIRST_FAIL_RESTORING) == 0) {
|
||||
if ((backup_reg_get_configuration() & CONFIG_FIRST_FAIL_RESTORING) == 0) {
|
||||
// a CRC checksum is ok, so first configuration section can be used further
|
||||
configuration_set_bits_register(CONFIG_FIRST_CRC_OK);
|
||||
backup_reg_set_bits_configuration(CONFIG_FIRST_CRC_OK);
|
||||
}
|
||||
else {
|
||||
;
|
||||
|
|
@ -449,31 +451,31 @@ int main(int argc, char* argv[]){
|
|||
}
|
||||
|
||||
// if second section has wrong CRC and it hasn't been restored before
|
||||
if ((main_crc_result & 0x02) == 0 && (configuration_get_register() & CONFIG_SECOND_FAIL_RESTORING) == 0) {
|
||||
if ((main_crc_result & 0x02) == 0 && (backup_reg_get_configuration() & CONFIG_SECOND_FAIL_RESTORING) == 0) {
|
||||
// restore default configuration
|
||||
if (configuration_handler_restore_default_second() == 0) {
|
||||
|
||||
// if configuration has been restored successfully
|
||||
configuration_set_bits_register(CONFIG_SECOND_RESTORED);
|
||||
backup_reg_set_bits_configuration(CONFIG_SECOND_RESTORED);
|
||||
|
||||
// set also CRC flag as if restoring is successfull the region has good CRC
|
||||
configuration_set_bits_register(CONFIG_SECOND_CRC_OK);
|
||||
backup_reg_set_bits_configuration(CONFIG_SECOND_CRC_OK);
|
||||
|
||||
}
|
||||
else {
|
||||
// if not store the flag in the backup register
|
||||
configuration_set_bits_register(CONFIG_SECOND_FAIL_RESTORING);
|
||||
backup_reg_set_bits_configuration(CONFIG_SECOND_FAIL_RESTORING);
|
||||
|
||||
configuration_clear_bits_register(CONFIG_SECOND_CRC_OK);
|
||||
backup_reg_clear_bits_configuration(CONFIG_SECOND_CRC_OK);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
else {
|
||||
// check failed restoring flag
|
||||
if ((configuration_get_register() & CONFIG_SECOND_FAIL_RESTORING) == 0) {
|
||||
if ((backup_reg_get_configuration() & CONFIG_SECOND_FAIL_RESTORING) == 0) {
|
||||
// second configuration section has good CRC and can be used further
|
||||
configuration_set_bits_register(CONFIG_SECOND_CRC_OK);
|
||||
backup_reg_set_bits_configuration(CONFIG_SECOND_CRC_OK);
|
||||
}
|
||||
else {
|
||||
;
|
||||
|
|
@ -481,7 +483,7 @@ int main(int argc, char* argv[]){
|
|||
}
|
||||
|
||||
// at this point both sections have either verified CRC or restored values to default
|
||||
if ((configuration_get_register() & CONFIG_FIRST_CRC_OK) != 0 && (configuration_get_register() & CONFIG_SECOND_CRC_OK) != 0) {
|
||||
if ((backup_reg_get_configuration() & CONFIG_FIRST_CRC_OK) != 0 && (backup_reg_get_configuration() & CONFIG_SECOND_CRC_OK) != 0) {
|
||||
// if both sections are OK check programming counters
|
||||
if (config_data_pgm_cntr_first > config_data_pgm_cntr_second) {
|
||||
// if first section has bigger programing counter use it
|
||||
|
|
@ -492,11 +494,11 @@ int main(int argc, char* argv[]){
|
|||
|
||||
}
|
||||
}
|
||||
else if ((configuration_get_register() & CONFIG_FIRST_CRC_OK) != 0 && (configuration_get_register() & CONFIG_SECOND_CRC_OK) == 0) {
|
||||
else if ((backup_reg_get_configuration() & CONFIG_FIRST_CRC_OK) != 0 && (backup_reg_get_configuration() & CONFIG_SECOND_CRC_OK) == 0) {
|
||||
// if only first region is OK use it
|
||||
configuration_handler_load_configuration(REGION_FIRST);
|
||||
}
|
||||
else if ((configuration_get_register() & CONFIG_FIRST_CRC_OK) == 0 && (configuration_get_register() & CONFIG_SECOND_CRC_OK) != 0) {
|
||||
else if ((backup_reg_get_configuration() & CONFIG_FIRST_CRC_OK) == 0 && (backup_reg_get_configuration() & CONFIG_SECOND_CRC_OK) != 0) {
|
||||
// if only first region is OK use it
|
||||
configuration_handler_load_configuration(REGION_FIRST);
|
||||
}
|
||||
|
|
@ -1101,7 +1103,7 @@ int main(int argc, char* argv[]){
|
|||
#endif
|
||||
|
||||
#if defined(PARAMETEO)
|
||||
status_send_powersave_registers(REGISTER_LAST_SLEEP, REGISTER_LAST_WKUP, REGISTER_COUNTERS, REGISTER_MONITOR, REGISTER_LAST_SLTIM);
|
||||
status_send_powersave_registers();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -1112,7 +1114,7 @@ int main(int argc, char* argv[]){
|
|||
// Infinite loop
|
||||
while (1)
|
||||
{
|
||||
main_set_monitor(-1);
|
||||
backup_reg_set_monitor(-1);
|
||||
|
||||
// incrementing current cpu ticks
|
||||
main_current_cpu_idle_ticks++;
|
||||
|
|
@ -1124,7 +1126,7 @@ int main(int argc, char* argv[]){
|
|||
;
|
||||
}
|
||||
|
||||
main_set_monitor(0);
|
||||
backup_reg_set_monitor(0);
|
||||
|
||||
#if defined(PARAMETEO)
|
||||
if (rte_main_woken_up == RTE_MAIN_WOKEN_UP_EXITED) {
|
||||
|
|
@ -1158,11 +1160,11 @@ int main(int argc, char* argv[]){
|
|||
|
||||
main_check_adc = 1;
|
||||
|
||||
main_set_monitor(1);
|
||||
backup_reg_set_monitor(1);
|
||||
}
|
||||
#endif
|
||||
|
||||
main_set_monitor(11);
|
||||
backup_reg_set_monitor(11);
|
||||
|
||||
// if new packet has been received from radio channel
|
||||
if(ax25_new_msg_rx_flag == 1) {
|
||||
|
|
@ -1339,7 +1341,7 @@ int main(int argc, char* argv[]){
|
|||
|
||||
button_check_all(main_button_one_left, main_button_two_right);
|
||||
|
||||
main_set_monitor(2);
|
||||
backup_reg_set_monitor(2);
|
||||
|
||||
// get all meteo measuremenets each 65 seconds. some values may not be
|
||||
// downloaded from sensors if _METEO and/or _DALLAS_AS_TELEM aren't defined
|
||||
|
|
@ -1397,7 +1399,7 @@ int main(int argc, char* argv[]){
|
|||
|
||||
}
|
||||
|
||||
main_set_monitor(3);
|
||||
backup_reg_set_monitor(3);
|
||||
|
||||
main_wx_sensors_pool_timer = 65500;
|
||||
}
|
||||
|
|
@ -1407,7 +1409,7 @@ int main(int argc, char* argv[]){
|
|||
*/
|
||||
if (main_one_minute_pool_timer < 10) {
|
||||
|
||||
main_set_monitor(4);
|
||||
backup_reg_set_monitor(4);
|
||||
|
||||
main_nvm_timestamp = main_get_nvm_timestamp();
|
||||
|
||||
|
|
@ -1415,7 +1417,7 @@ int main(int argc, char* argv[]){
|
|||
packet_tx_handler(main_config_data_basic, main_config_data_mode);
|
||||
#endif
|
||||
|
||||
main_set_monitor(5);
|
||||
backup_reg_set_monitor(5);
|
||||
|
||||
#ifdef STM32L471xx
|
||||
if (main_config_data_mode->gsm == 1) {
|
||||
|
|
@ -1446,7 +1448,7 @@ int main(int argc, char* argv[]){
|
|||
*/
|
||||
if (main_one_second_pool_timer < 10) {
|
||||
|
||||
main_set_monitor(6);
|
||||
backup_reg_set_monitor(6);
|
||||
|
||||
digi_pool_viscous();
|
||||
|
||||
|
|
@ -1499,7 +1501,7 @@ int main(int argc, char* argv[]){
|
|||
analog_anemometer_direction_handler();
|
||||
}
|
||||
|
||||
main_set_monitor(7);
|
||||
backup_reg_set_monitor(7);
|
||||
|
||||
main_one_second_pool_timer = 1000;
|
||||
}
|
||||
|
|
@ -1542,7 +1544,7 @@ int main(int argc, char* argv[]){
|
|||
*/
|
||||
if (main_ten_second_pool_timer < 10) {
|
||||
|
||||
main_set_monitor(8);
|
||||
backup_reg_set_monitor(8);
|
||||
|
||||
// check if consecutive weather frame has been triggered from 'packet_tx_handler'
|
||||
if (rte_main_trigger_wx_packet == 1) {
|
||||
|
|
@ -1577,7 +1579,7 @@ int main(int argc, char* argv[]){
|
|||
}
|
||||
#endif
|
||||
|
||||
main_set_monitor(9);
|
||||
backup_reg_set_monitor(9);
|
||||
|
||||
#ifdef PARAMETEO
|
||||
if (main_config_data_mode->gsm == 1) {
|
||||
|
|
@ -1619,7 +1621,7 @@ int main(int argc, char* argv[]){
|
|||
main_ten_second_pool_timer = 10000;
|
||||
}
|
||||
|
||||
main_set_monitor(10);
|
||||
backup_reg_set_monitor(10);
|
||||
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
#include "packet_tx_handler.h"
|
||||
#include "wx_handler.h"
|
||||
#include "backup_registers.h"
|
||||
|
||||
#include "rte_wx.h"
|
||||
#include "rte_pv.h"
|
||||
|
|
@ -92,6 +93,10 @@ void packet_tx_configure(uint8_t meteo_interval, uint8_t beacon_interval, config
|
|||
|
||||
}
|
||||
|
||||
void packet_tx_restore_from_backupregs(void) {
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* This function is called from the inside of 'packet_rx_handler' to put an extra wait
|
||||
* if more than one packet is sent from the single call to that function. This is required
|
||||
|
|
@ -508,7 +513,7 @@ void packet_tx_handler(const config_data_basic_t * const config_basic, const con
|
|||
|
||||
#ifdef PARAMETEO
|
||||
rte_main_trigger_gsm_status_packet = 1;
|
||||
status_send_powersave_registers(REGISTER_LAST_SLEEP, REGISTER_LAST_WKUP, REGISTER_COUNTERS, REGISTER_MONITOR, REGISTER_LAST_SLTIM);
|
||||
status_send_powersave_registers();
|
||||
#endif
|
||||
|
||||
packet_tx_multi_per_call_handler();
|
||||
|
|
@ -521,14 +526,12 @@ void packet_tx_handler(const config_data_basic_t * const config_basic, const con
|
|||
rte_main_reboot_req = 1;
|
||||
}
|
||||
|
||||
//telemetry_send_status_pv(&rte_pv_average, &rte_pv_last_error, rte_pv_struct.system_state);
|
||||
}
|
||||
else {
|
||||
telemetry_send_chns_description(config_basic, config_mode);
|
||||
|
||||
packet_tx_multi_per_call_handler();
|
||||
|
||||
//telemetry_send_status();
|
||||
}
|
||||
|
||||
status_send();
|
||||
|
|
|
|||
206
src/pwr_save.c
206
src/pwr_save.c
|
|
@ -18,6 +18,7 @@
|
|||
#include "packet_tx_handler.h"
|
||||
#include "wx_handler.h"
|
||||
#include "main.h"
|
||||
#include "backup_registers.h"
|
||||
#include "status.h"
|
||||
#include "afsk_pr.h"
|
||||
#include "gsm/sim800c.h"
|
||||
|
|
@ -27,7 +28,6 @@
|
|||
|
||||
#include "drivers/analog_anemometer.h"
|
||||
|
||||
#define INHIBIT_PWR_SWITCH_PERIODIC_H 1
|
||||
#define IN_STOP2_MODE (1 << 1)
|
||||
#define IN_C0_STATE (1 << 2)
|
||||
#define IN_C1_STATE (1 << 3)
|
||||
|
|
@ -38,8 +38,6 @@
|
|||
#define IN_L6_STATE (1 << 8)
|
||||
#define IN_L7_STATE (1 << 9)
|
||||
|
||||
#define ALL_STATES_BITMASK (0xFF << 2)
|
||||
|
||||
#define MINIMUM_SENSEFUL_VBATT_VOLTAGE 678u
|
||||
|
||||
#if defined(STM32L471xx)
|
||||
|
|
@ -94,7 +92,8 @@ static void pwr_save_clear_powersave_idication_bits() {
|
|||
pwr_save_unclock_rtc_backup_regs();
|
||||
|
||||
// clear all previous powersave indication bits
|
||||
REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
//REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
backup_reg_reset_all_powersave_states();
|
||||
|
||||
// lock access to backup
|
||||
pwr_save_lock_rtc_backup_regs();
|
||||
|
|
@ -107,7 +106,7 @@ static void pwr_save_clear_powersave_idication_bits() {
|
|||
static void pwr_save_enter_stop2(void) {
|
||||
|
||||
// set 31st monitor bit
|
||||
main_set_monitor(31);
|
||||
backup_reg_set_monitor(31);
|
||||
|
||||
// reload internal watchdog
|
||||
main_reload_internal_wdg();
|
||||
|
|
@ -134,7 +133,8 @@ static void pwr_save_enter_stop2(void) {
|
|||
RTC->BKP0R |= IN_STOP2_MODE;
|
||||
|
||||
// save a timestamp when micro has been switched to STOP2 mode
|
||||
REGISTER_LAST_SLEEP = RTC->TR;
|
||||
//REGISTER_LAST_SLEEP = RTC->TR;
|
||||
backup_reg_set_last_sleep_timestamp();
|
||||
|
||||
pwr_save_lock_rtc_backup_regs();
|
||||
|
||||
|
|
@ -163,7 +163,7 @@ static void pwr_save_check_stop2_cycles(void) {
|
|||
|
||||
// if there is time left to exit from depp sleep
|
||||
if (pwr_save_number_of_sleep_cycles > 0) {
|
||||
main_set_monitor(15);
|
||||
backup_reg_set_monitor(15);
|
||||
|
||||
// go back to sleep
|
||||
// configure how long micro should sleep
|
||||
|
|
@ -172,7 +172,7 @@ static void pwr_save_check_stop2_cycles(void) {
|
|||
pwr_save_enter_stop2();
|
||||
}
|
||||
else {
|
||||
main_set_monitor(14);
|
||||
backup_reg_set_monitor(14);
|
||||
|
||||
// we are done sleeping so exit from this loop
|
||||
break;
|
||||
|
|
@ -189,16 +189,18 @@ static void pwr_save_exit_after_last_stop2_cycle(void) {
|
|||
uint32_t counter = 0;
|
||||
|
||||
// set 30th minitor bit
|
||||
main_set_monitor(30);
|
||||
backup_reg_set_monitor(30);
|
||||
|
||||
// unlock access to backup registers
|
||||
pwr_save_unclock_rtc_backup_regs();
|
||||
|
||||
// save a timestamp of this wakeup event
|
||||
REGISTER_LAST_WKUP = RTC->TR;
|
||||
//REGISTER_LAST_WKUP = RTC->TR;
|
||||
backup_reg_set_last_wakeup_timestamp();
|
||||
|
||||
// increase wakeup counter
|
||||
counter = (uint32_t)((REGISTER_COUNTERS & 0xFFFF0000) >> 16);
|
||||
//counter = (uint32_t)((REGISTER_COUNTERS & 0xFFFF0000) >> 16);
|
||||
counter = backup_reg_get_wakeup_counter();
|
||||
|
||||
counter++;
|
||||
|
||||
|
|
@ -210,7 +212,8 @@ static void pwr_save_exit_after_last_stop2_cycle(void) {
|
|||
counter = 0;
|
||||
}
|
||||
|
||||
REGISTER_COUNTERS = (REGISTER_COUNTERS & 0x0000FFFF) | (counter << 16);
|
||||
//REGISTER_COUNTERS = (REGISTER_COUNTERS & 0x0000FFFF) | (counter << 16);
|
||||
backup_reg_set_wakeup_counter(counter);
|
||||
|
||||
pwr_save_lock_rtc_backup_regs();
|
||||
|
||||
|
|
@ -218,7 +221,7 @@ static void pwr_save_exit_after_last_stop2_cycle(void) {
|
|||
packet_tx_counter_values_t timers;
|
||||
|
||||
// check power saving mode set before switching uC to SLEEP2
|
||||
uint16_t powersave_mode = (uint16_t)(REGISTER & ALL_STATES_BITMASK);
|
||||
uint16_t powersave_mode = backup_reg_get_powersave_state();//(uint16_t)(REGISTER & ALL_STATES_BITMASK);
|
||||
|
||||
// check if sleep time is valid
|
||||
if (pwr_save_sleep_time_in_seconds <= 0) {
|
||||
|
|
@ -258,7 +261,7 @@ static void pwr_save_exit_after_last_stop2_cycle(void) {
|
|||
break;
|
||||
}
|
||||
|
||||
main_set_monitor(29);
|
||||
backup_reg_set_monitor(29);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -286,9 +289,10 @@ static void pwr_save_after_stop2_rtc_wakeup_it(void) {
|
|||
|
||||
int pwr_save_switch_mode_to_c0(void) {
|
||||
|
||||
if ((REGISTER & ALL_STATES_BITMASK) == IN_C0_STATE) {
|
||||
if (backup_reg_is_in_powersave_state(IN_C0_STATE) != 0) {
|
||||
return 0;
|
||||
}
|
||||
//backup_reg_is_in_powersave_state
|
||||
|
||||
// turn ON +5V_S
|
||||
io___cntrl_vbat_s_enable();
|
||||
|
|
@ -311,10 +315,12 @@ int pwr_save_switch_mode_to_c0(void) {
|
|||
pwr_save_unclock_rtc_backup_regs();
|
||||
|
||||
// clear all previous powersave indication bits
|
||||
REGISTER &= 0xFFFFFFFF ^ ALL_STATES_BITMASK;
|
||||
//REGISTER &= 0xFFFFFFFF ^ ALL_STATES_BITMASK;
|
||||
backup_reg_reset_all_powersave_states();
|
||||
|
||||
// set for C0 mode
|
||||
REGISTER |= IN_C0_STATE;
|
||||
//REGISTER |= IN_C0_STATE;
|
||||
backup_reg_set_powersave_state(IN_C0_STATE);
|
||||
|
||||
// lock access to backup
|
||||
pwr_save_lock_rtc_backup_regs();
|
||||
|
|
@ -326,7 +332,10 @@ int pwr_save_switch_mode_to_c0(void) {
|
|||
// in HW-RevB this will disable external VHF radio!!
|
||||
int pwr_save_switch_mode_to_c1(void) {
|
||||
|
||||
if ((REGISTER & ALL_STATES_BITMASK) == IN_C1_STATE) {
|
||||
// if ((REGISTER & ALL_STATES_BITMASK) == IN_C1_STATE) {
|
||||
// return 0;
|
||||
// }
|
||||
if (backup_reg_is_in_powersave_state(IN_C0_STATE) != 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -354,10 +363,12 @@ int pwr_save_switch_mode_to_c1(void) {
|
|||
pwr_save_unclock_rtc_backup_regs();
|
||||
|
||||
// clear all previous powersave indication bits
|
||||
REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
//REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
backup_reg_reset_all_powersave_states();
|
||||
|
||||
// set for C0 mode
|
||||
REGISTER |= IN_C1_STATE;
|
||||
//REGISTER |= IN_C1_STATE;
|
||||
backup_reg_set_powersave_state(IN_C1_STATE);
|
||||
|
||||
// lock access to backup
|
||||
pwr_save_lock_rtc_backup_regs();
|
||||
|
|
@ -370,7 +381,10 @@ int pwr_save_switch_mode_to_c1(void) {
|
|||
// line which controls +4V_G
|
||||
void pwr_save_switch_mode_to_c2(void) {
|
||||
|
||||
if ((REGISTER & ALL_STATES_BITMASK) == IN_C2_STATE) {
|
||||
// if ((REGISTER & ALL_STATES_BITMASK) == IN_C2_STATE) {
|
||||
// return;
|
||||
// }
|
||||
if (backup_reg_is_in_powersave_state(IN_C0_STATE) != 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -398,10 +412,12 @@ void pwr_save_switch_mode_to_c2(void) {
|
|||
pwr_save_unclock_rtc_backup_regs();
|
||||
|
||||
// clear all previous powersave indication bits
|
||||
REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
//REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
backup_reg_reset_all_powersave_states();
|
||||
|
||||
// set for C2 mode
|
||||
REGISTER |= IN_C2_STATE;
|
||||
//REGISTER |= IN_C2_STATE;
|
||||
backup_reg_set_powersave_state(IN_C2_STATE);
|
||||
|
||||
// lock access to backup
|
||||
pwr_save_lock_rtc_backup_regs();
|
||||
|
|
@ -410,7 +426,10 @@ void pwr_save_switch_mode_to_c2(void) {
|
|||
|
||||
void pwr_save_switch_mode_to_c3(void) {
|
||||
|
||||
if ((REGISTER & ALL_STATES_BITMASK) == IN_C3_STATE) {
|
||||
// if ((REGISTER & ALL_STATES_BITMASK) == IN_C3_STATE) {
|
||||
// return;
|
||||
// }
|
||||
if (backup_reg_is_in_powersave_state(IN_C3_STATE) != 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -435,10 +454,12 @@ void pwr_save_switch_mode_to_c3(void) {
|
|||
pwr_save_unclock_rtc_backup_regs();
|
||||
|
||||
// clear all previous powersave indication bits
|
||||
REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
//REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
backup_reg_reset_all_powersave_states();
|
||||
|
||||
// set for C3 mode
|
||||
REGISTER |= IN_C3_STATE;
|
||||
//REGISTER |= IN_C3_STATE;
|
||||
backup_reg_set_powersave_state(IN_C3_STATE);
|
||||
|
||||
// lock access to backup
|
||||
pwr_save_lock_rtc_backup_regs();
|
||||
|
|
@ -448,7 +469,10 @@ void pwr_save_switch_mode_to_c3(void) {
|
|||
// in HW-RevB this will keep internal VHF radio module working!
|
||||
int pwr_save_switch_mode_to_m4(void) {
|
||||
|
||||
if ((REGISTER & ALL_STATES_BITMASK) == IN_M4_STATE) {
|
||||
// if ((REGISTER & ALL_STATES_BITMASK) == IN_M4_STATE) {
|
||||
// return 0;
|
||||
// }
|
||||
if (backup_reg_is_in_powersave_state(IN_M4_STATE) != 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -476,10 +500,12 @@ int pwr_save_switch_mode_to_m4(void) {
|
|||
pwr_save_unclock_rtc_backup_regs();
|
||||
|
||||
// clear all previous powersave indication bits
|
||||
REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
//REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
backup_reg_reset_all_powersave_states();
|
||||
|
||||
// set for C3 mode
|
||||
REGISTER |= IN_M4_STATE;
|
||||
//REGISTER |= IN_M4_STATE;
|
||||
backup_reg_set_powersave_state(IN_M4_STATE);
|
||||
|
||||
// lock access to backup
|
||||
pwr_save_lock_rtc_backup_regs();
|
||||
|
|
@ -488,7 +514,10 @@ int pwr_save_switch_mode_to_m4(void) {
|
|||
}
|
||||
|
||||
int pwr_save_switch_mode_to_m4a(void) {
|
||||
if ((REGISTER & ALL_STATES_BITMASK) == IN_M4_STATE) {
|
||||
// if ((REGISTER & ALL_STATES_BITMASK) == IN_M4_STATE) {
|
||||
// return 0;
|
||||
// }
|
||||
if (backup_reg_is_in_powersave_state(IN_M4_STATE) != 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -513,10 +542,12 @@ int pwr_save_switch_mode_to_m4a(void) {
|
|||
pwr_save_unclock_rtc_backup_regs();
|
||||
|
||||
// clear all previous powersave indication bits
|
||||
REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
//REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
backup_reg_reset_all_powersave_states();
|
||||
|
||||
// set for C3 mode
|
||||
REGISTER |= IN_M4_STATE;
|
||||
//REGISTER |= IN_M4_STATE;
|
||||
backup_reg_set_powersave_state(IN_M4_STATE);
|
||||
|
||||
// lock access to backup
|
||||
pwr_save_lock_rtc_backup_regs();
|
||||
|
|
@ -526,7 +557,10 @@ int pwr_save_switch_mode_to_m4a(void) {
|
|||
|
||||
void pwr_save_switch_mode_to_i5(void) {
|
||||
|
||||
if ((REGISTER & ALL_STATES_BITMASK) == IN_I5_STATE) {
|
||||
// if ((REGISTER & ALL_STATES_BITMASK) == IN_I5_STATE) {
|
||||
// return;
|
||||
// }
|
||||
if (backup_reg_is_in_powersave_state(IN_I5_STATE) != 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -554,10 +588,12 @@ void pwr_save_switch_mode_to_i5(void) {
|
|||
pwr_save_unclock_rtc_backup_regs();
|
||||
|
||||
// clear all previous powersave indication bits
|
||||
REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
//REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
backup_reg_reset_all_powersave_states();
|
||||
|
||||
// set for C3 mode
|
||||
REGISTER |= IN_I5_STATE;
|
||||
//REGISTER |= IN_I5_STATE;
|
||||
backup_reg_set_powersave_state(IN_I5_STATE);
|
||||
|
||||
// lock access to backup
|
||||
pwr_save_lock_rtc_backup_regs();
|
||||
|
|
@ -580,14 +616,17 @@ void pwr_save_switch_mode_to_l6(uint16_t sleep_time) {
|
|||
return;
|
||||
}
|
||||
|
||||
if ((REGISTER & ALL_STATES_BITMASK) == IN_L6_STATE) {
|
||||
// if ((REGISTER & ALL_STATES_BITMASK) == IN_L6_STATE) {
|
||||
// return;
|
||||
// }
|
||||
if (backup_reg_is_in_powersave_state(IN_L6_STATE) != 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
// calculate amount of STOP2 cycles
|
||||
pwr_save_number_of_sleep_cycles = (int8_t)(sleep_time / PWR_SAVE_STOP2_CYCLE_LENGHT_SEC) & 0x7Fu;
|
||||
|
||||
main_set_monitor(28);
|
||||
backup_reg_set_monitor(28);
|
||||
|
||||
// disable ADC used for vbat measurement
|
||||
io_vbat_meas_disable();
|
||||
|
|
@ -617,21 +656,25 @@ void pwr_save_switch_mode_to_l6(uint16_t sleep_time) {
|
|||
pwr_save_unclock_rtc_backup_regs();
|
||||
|
||||
// clear all previous powersave indication bits
|
||||
REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
//REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
backup_reg_reset_all_powersave_states();
|
||||
|
||||
// set for C3 mode
|
||||
REGISTER |= IN_L6_STATE;
|
||||
//REGISTER |= IN_L6_STATE;
|
||||
backup_reg_set_powersave_state(IN_L6_STATE);
|
||||
|
||||
REGISTER_LAST_SLTIM = sleep_time;
|
||||
//REGISTER_LAST_SLTIM = sleep_time;
|
||||
backup_reg_set_last_sleep_timestamp();
|
||||
|
||||
// increment the STOP2 sleep counters
|
||||
counter = (uint16_t)(REGISTER_COUNTERS & 0xFFFF);
|
||||
counter = backup_reg_get_sleep_counter();//(uint16_t)(REGISTER_COUNTERS & 0xFFFF);
|
||||
|
||||
counter++;
|
||||
|
||||
rte_main_going_sleep_count = counter;
|
||||
|
||||
REGISTER_COUNTERS = (REGISTER_COUNTERS & 0xFFFF0000) | counter;
|
||||
//REGISTER_COUNTERS = (REGISTER_COUNTERS & 0xFFFF0000) | counter;
|
||||
backup_reg_set_sleep_counter(counter);
|
||||
|
||||
// lock access to backup
|
||||
pwr_save_lock_rtc_backup_regs();
|
||||
|
|
@ -647,7 +690,7 @@ void pwr_save_switch_mode_to_l6(uint16_t sleep_time) {
|
|||
|
||||
pwr_save_enter_stop2();
|
||||
|
||||
main_set_monitor(27);
|
||||
backup_reg_set_monitor(27);
|
||||
|
||||
|
||||
}
|
||||
|
|
@ -668,14 +711,17 @@ void pwr_save_switch_mode_to_l7(uint16_t sleep_time) {
|
|||
return;
|
||||
}
|
||||
|
||||
if ((REGISTER & ALL_STATES_BITMASK) == IN_L7_STATE) {
|
||||
// if ((REGISTER & ALL_STATES_BITMASK) == IN_L7_STATE) {
|
||||
// return;
|
||||
// }
|
||||
if (backup_reg_is_in_powersave_state(IN_L7_STATE) != 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
// calculate amount of STOP2 cycles
|
||||
pwr_save_number_of_sleep_cycles = (int8_t)(sleep_time / PWR_SAVE_STOP2_CYCLE_LENGHT_SEC) & 0x7Fu;
|
||||
|
||||
main_set_monitor(26);
|
||||
backup_reg_set_monitor(26);
|
||||
|
||||
// disconnect APRS-IS connection if it is established
|
||||
aprsis_disconnect();
|
||||
|
|
@ -705,27 +751,42 @@ void pwr_save_switch_mode_to_l7(uint16_t sleep_time) {
|
|||
gsm_sim800_inhibit(1);
|
||||
|
||||
// unlock access to backup registers
|
||||
pwr_save_unclock_rtc_backup_regs();
|
||||
//pwr_save_unclock_rtc_backup_regs();
|
||||
|
||||
// clear all previous powersave indication bits
|
||||
REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
//REGISTER &= (0xFFFFFFFF ^ ALL_STATES_BITMASK);
|
||||
backup_reg_reset_all_powersave_states();
|
||||
|
||||
// set for C3 mode
|
||||
REGISTER |= IN_L7_STATE;
|
||||
//REGISTER |= IN_L7_STATE;
|
||||
backup_reg_set_powersave_state(IN_L7_STATE);
|
||||
|
||||
REGISTER_LAST_SLTIM = sleep_time;
|
||||
// REGISTER_LAST_SLTIM = sleep_time;
|
||||
//
|
||||
// // increment the STOP2 sleep counters
|
||||
// counter = (uint16_t)(REGISTER_COUNTERS & 0xFFFF);
|
||||
//
|
||||
// counter++;
|
||||
//
|
||||
// rte_main_going_sleep_count = counter;
|
||||
//
|
||||
// REGISTER_COUNTERS = (REGISTER_COUNTERS & 0xFFFF0000) | counter;
|
||||
|
||||
//REGISTER_LAST_SLTIM = sleep_time;
|
||||
backup_reg_set_last_sleep_timestamp();
|
||||
|
||||
// increment the STOP2 sleep counters
|
||||
counter = (uint16_t)(REGISTER_COUNTERS & 0xFFFF);
|
||||
counter = backup_reg_get_sleep_counter();//(uint16_t)(REGISTER_COUNTERS & 0xFFFF);
|
||||
|
||||
counter++;
|
||||
|
||||
rte_main_going_sleep_count = counter;
|
||||
|
||||
REGISTER_COUNTERS = (REGISTER_COUNTERS & 0xFFFF0000) | counter;
|
||||
//REGISTER_COUNTERS = (REGISTER_COUNTERS & 0xFFFF0000) | counter;
|
||||
backup_reg_set_sleep_counter(counter);
|
||||
|
||||
// lock access to backup
|
||||
pwr_save_lock_rtc_backup_regs();
|
||||
//pwr_save_lock_rtc_backup_regs();
|
||||
|
||||
// configure how long micro should sleep
|
||||
system_clock_configure_auto_wakeup_l4(PWR_SAVE_STOP2_CYCLE_LENGHT_SEC);
|
||||
|
|
@ -739,7 +800,7 @@ void pwr_save_switch_mode_to_l7(uint16_t sleep_time) {
|
|||
|
||||
pwr_save_enter_stop2();
|
||||
|
||||
main_set_monitor(25);
|
||||
backup_reg_set_monitor(25);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -790,10 +851,12 @@ void pwr_save_init(config_data_powersave_mode_t mode) {
|
|||
|
||||
}
|
||||
|
||||
pwr_save_unclock_rtc_backup_regs();
|
||||
//pwr_save_unclock_rtc_backup_regs();
|
||||
|
||||
// reset a status register
|
||||
REGISTER = 0;
|
||||
//REGISTER = 0;
|
||||
backup_reg_reset_all_powersave_states();
|
||||
backup_reg_reset_inhibit_periodic_pwr_switch();
|
||||
|
||||
// switch power switch handler inhibition if it is needed
|
||||
switch (mode) {
|
||||
|
|
@ -801,11 +864,12 @@ void pwr_save_init(config_data_powersave_mode_t mode) {
|
|||
break;
|
||||
case PWSAVE_NORMAL:
|
||||
case PWSAVE_AGGRESV:
|
||||
REGISTER |= INHIBIT_PWR_SWITCH_PERIODIC_H;
|
||||
//REGISTER |= INHIBIT_PWR_SWITCH_PERIODIC_H;
|
||||
backup_reg_inhibit_periodic_pwr_switch();
|
||||
break;
|
||||
}
|
||||
|
||||
pwr_save_lock_rtc_backup_regs();
|
||||
//pwr_save_lock_rtc_backup_regs();
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -819,7 +883,7 @@ config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t *
|
|||
// by default use powersave mode from controller configuration
|
||||
config_data_powersave_mode_t psave_mode = config->powersave;
|
||||
|
||||
main_set_monitor(24);
|
||||
backup_reg_set_monitor(24);
|
||||
|
||||
// save previous state
|
||||
pwr_save_previously_cutoff = pwr_save_currently_cutoff;
|
||||
|
|
@ -838,11 +902,11 @@ config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t *
|
|||
if (vbatt > PWR_SAVE_STARTUP_RESTORE_VOLTAGE_DEF) {
|
||||
pwr_save_currently_cutoff = 0;
|
||||
|
||||
main_set_monitor(23);
|
||||
backup_reg_set_monitor(23);
|
||||
}
|
||||
else {
|
||||
if (vbatt <= PWR_SAVE_CUTOFF_VOLTAGE_DEF) {
|
||||
main_set_monitor(22);
|
||||
backup_reg_set_monitor(22);
|
||||
|
||||
// if the battery voltage is below cutoff level and the ParaMETEO controller is currently not cut off
|
||||
pwr_save_currently_cutoff |= CURRENTLY_CUTOFF;
|
||||
|
|
@ -850,7 +914,7 @@ config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t *
|
|||
|
||||
// check if battery voltage is below low voltage level
|
||||
if (vbatt <= PWR_SAVE_AGGRESIVE_POWERSAVE_VOLTAGE) {
|
||||
main_set_monitor(21);
|
||||
backup_reg_set_monitor(21);
|
||||
|
||||
// if battery voltage is low swtich to aggressive powersave mode
|
||||
pwr_save_currently_cutoff |= CURRENTLY_VBATT_LOW;
|
||||
|
|
@ -859,7 +923,7 @@ config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t *
|
|||
|
||||
}
|
||||
|
||||
main_set_monitor(20);
|
||||
backup_reg_set_monitor(20);
|
||||
|
||||
// check if cutoff status has changed
|
||||
if (pwr_save_currently_cutoff != pwr_save_previously_cutoff) {
|
||||
|
|
@ -868,7 +932,7 @@ config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t *
|
|||
|
||||
|
||||
if ((pwr_save_currently_cutoff & CURRENTLY_CUTOFF) != 0) {
|
||||
main_set_monitor(19);
|
||||
backup_reg_set_monitor(19);
|
||||
|
||||
// clear all previous powersave indication bits as we want to go sleep being already in L7 state
|
||||
pwr_save_clear_powersave_idication_bits();
|
||||
|
|
@ -883,7 +947,7 @@ config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t *
|
|||
}
|
||||
|
||||
if ((pwr_save_currently_cutoff & CURRENTLY_VBATT_LOW) != 0) {
|
||||
main_set_monitor(18);
|
||||
backup_reg_set_monitor(18);
|
||||
|
||||
psave_mode = PWSAVE_AGGRESV;
|
||||
}
|
||||
|
|
@ -1017,7 +1081,7 @@ config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t *
|
|||
}
|
||||
else { // WX
|
||||
if (minutes_to_wx > 2) {
|
||||
main_set_monitor(17);
|
||||
backup_reg_set_monitor(17);
|
||||
|
||||
// if there is more than two minutes to send wx packet
|
||||
pwr_save_switch_mode_to_l7((timers->wx_transmit_period * 60) - 120);
|
||||
|
|
@ -1061,7 +1125,7 @@ config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t *
|
|||
// if stations is configured to send wx packet less frequent than every 5 minutes
|
||||
|
||||
if (minutes_to_wx > 1) {
|
||||
main_set_monitor(17);
|
||||
backup_reg_set_monitor(17);
|
||||
|
||||
// if there is more than one minute to wx packet
|
||||
pwr_save_switch_mode_to_l7((timers->wx_transmit_period * 60) - 60); // TODO: !!!
|
||||
|
|
@ -1086,7 +1150,7 @@ config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t *
|
|||
// if station is configured to sent wx packet in every 5 minutes or more often
|
||||
|
||||
if (minutes_to_wx > 1) {
|
||||
main_set_monitor(17);
|
||||
backup_reg_set_monitor(17);
|
||||
|
||||
pwr_save_switch_mode_to_l6((timers->wx_transmit_period * 60) - 60); // TODO: !!!
|
||||
}
|
||||
|
|
@ -1108,7 +1172,7 @@ config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t *
|
|||
}
|
||||
else { // WX
|
||||
if (minutes_to_wx > 1) {
|
||||
main_set_monitor(17);
|
||||
backup_reg_set_monitor(17);
|
||||
|
||||
// if there is more than one minute to send wx packet
|
||||
pwr_save_switch_mode_to_l7((timers->wx_transmit_period * 60) - 60);
|
||||
|
|
@ -1142,11 +1206,11 @@ config_data_powersave_mode_t pwr_save_pooling_handler(const config_data_mode_t *
|
|||
}
|
||||
}
|
||||
|
||||
main_set_monitor(16);
|
||||
backup_reg_set_monitor(16);
|
||||
|
||||
pwr_save_after_stop2_rtc_wakeup_it();
|
||||
|
||||
main_set_monitor(13);
|
||||
backup_reg_set_monitor(13);
|
||||
|
||||
if (reinit_sensors != 0) {
|
||||
// reinitialize all i2c sensors
|
||||
|
|
@ -1180,7 +1244,7 @@ int pwr_save_is_currently_cutoff(void) {
|
|||
|
||||
uint8_t pwr_save_get_inhibit_pwr_switch_periodic(void) {
|
||||
|
||||
if ((REGISTER & INHIBIT_PWR_SWITCH_PERIODIC_H) != 0){
|
||||
if (backup_reg_is_periodic_pwr_switch_inhibited() != 0){
|
||||
return 1;
|
||||
}
|
||||
else if ((pwr_save_currently_cutoff & CURRENTLY_CUTOFF) != 0) {
|
||||
|
|
|
|||
|
|
@ -729,69 +729,7 @@ kiss_communication_nrc_t configuration_handler_program_startup(uint8_t * data, u
|
|||
|
||||
}
|
||||
|
||||
uint32_t configuration_get_register(void) {
|
||||
|
||||
uint32_t out = 0;
|
||||
|
||||
#ifdef STM32F10X_MD_VL
|
||||
out = BKP->DR3;
|
||||
#endif
|
||||
|
||||
#ifdef STM32L471xx
|
||||
out = RTC->BKP3R;
|
||||
|
||||
#endif
|
||||
|
||||
return out;
|
||||
}
|
||||
|
||||
void configuration_set_register(uint32_t value) {
|
||||
#ifdef STM32F10X_MD_VL
|
||||
BKP->DR3 = value;
|
||||
#endif
|
||||
|
||||
#ifdef STM32L471xx
|
||||
// enable access to backup domain
|
||||
PWR->CR1 |= PWR_CR1_DBP;
|
||||
|
||||
RTC->BKP3R = value;
|
||||
|
||||
PWR->CR1 &= (0xFFFFFFFF ^ PWR_CR1_DBP);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void configuration_set_bits_register(uint32_t value) {
|
||||
#ifdef STM32F10X_MD_VL
|
||||
BKP->DR3 |= value;
|
||||
#endif
|
||||
|
||||
#ifdef STM32L471xx
|
||||
// enable access to backup domain
|
||||
PWR->CR1 |= PWR_CR1_DBP;
|
||||
|
||||
RTC->BKP3R |= value;
|
||||
|
||||
PWR->CR1 &= (0xFFFFFFFF ^ PWR_CR1_DBP);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void configuration_clear_bits_register(uint32_t value) {
|
||||
#ifdef STM32F10X_MD_VL
|
||||
BKP->DR3 &= (0xFFFF ^ value);
|
||||
#endif
|
||||
|
||||
#ifdef STM32L471xx
|
||||
// enable access to backup domain
|
||||
PWR->CR1 |= PWR_CR1_DBP;
|
||||
|
||||
RTC->BKP3R &= (0xFFFFFFFF ^ value);
|
||||
|
||||
PWR->CR1 &= (0xFFFFFFFF ^ PWR_CR1_DBP);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
configuration_handler_region_t configuration_get_current(uint32_t * size) {
|
||||
if (size != 0x00) {
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ void status_send(void);
|
|||
void status_send_raw_values_modbus(void);
|
||||
|
||||
void status_send_powersave_cutoff(uint16_t battery_voltage, int8_t vbatt_low, int8_t cutoff);
|
||||
void status_send_powersave_registers(uint32_t register_last_sleep, uint32_t register_last_wakeup, uint32_t register_counters, uint32_t monitor, uint32_t last_sleep_time);
|
||||
void status_send_powersave_registers(void);
|
||||
|
||||
void status_send_gsm(void);
|
||||
void status_send_aprsis_timeout(uint8_t unsuccessfull_conn_cntr);
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
#include "status.h"
|
||||
|
||||
#include "main.h"
|
||||
#include "backup_registers.h"
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
|
@ -97,11 +98,25 @@ void status_send_powersave_cutoff(uint16_t battery_voltage, int8_t previous_cuto
|
|||
#endif
|
||||
}
|
||||
|
||||
void status_send_powersave_registers(uint32_t register_last_sleep, uint32_t register_last_wakeup, uint32_t register_counters, uint32_t monitor, uint32_t last_sleep_time) {
|
||||
void status_send_powersave_registers(void) {
|
||||
|
||||
const uint32_t last_sleep = backup_reg_get_last_sleep_timestamp();
|
||||
const uint32_t last_wakeup = backup_reg_get_last_wakeup_timestamp();
|
||||
const uint32_t sleep_counter = backup_reg_get_sleep_counter();
|
||||
const uint32_t wakeup_counter = backup_reg_get_wakeup_counter();
|
||||
const uint32_t last_monitor = backup_reg_get_monitor();
|
||||
|
||||
main_wait_for_tx_complete();
|
||||
|
||||
memset(main_own_aprs_msg, 0x00, sizeof(main_own_aprs_msg));
|
||||
main_own_aprs_msg_len = sprintf(main_own_aprs_msg, ">[powersave registers][last_sleep_ts: 0x%lX][last_wakeup_ts: 0x%lX][sleep_wakeup_cntrs: 0x%lX][monitor: 0x%lX][last_sleep_time: 0x%lX]",register_last_sleep, register_last_wakeup, register_counters, monitor, last_sleep_time);
|
||||
main_own_aprs_msg_len = sprintf(
|
||||
main_own_aprs_msg,
|
||||
">[powersave registers][last_sleep_ts: 0x%lX][last_wakeup_ts: 0x%lX][sleep_cntr: 0x%lX][wakeup_cntr: 0x%lX][monitor: 0x%lX]",
|
||||
last_sleep,
|
||||
last_wakeup,
|
||||
sleep_counter,
|
||||
wakeup_counter,
|
||||
last_monitor);
|
||||
ax25_sendVia(&main_ax25, main_own_path, main_own_path_ln, main_own_aprs_msg, main_own_aprs_msg_len);
|
||||
//while (main_ax25.dcd == 1);
|
||||
afsk_txStart(&main_afsk);
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue