kopia lustrzana https://github.com/SP8EBC/ParaTNC
clock initializing
Mateusz Lubecki
rodzic
cf18fe17ae
commit
8147078e84
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@ -13,6 +13,7 @@
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#include <stm32l4xx_ll_iwdg.h>
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#include <stm32l4xx_ll_rcc.h>
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#include <stm32l4xx_ll_gpio.h>
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#include "cmsis/stm32l4xx/system_stm32l4xx.h"
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#endif
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#include <delay.h>
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@ -255,11 +256,13 @@ int main(int argc, char* argv[]){
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#endif
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#if defined(PARAMETEO)
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if (SystemClock_Config() != 0) {
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SystemCoreClockUpdateL4();
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if (SystemClock_Config_L4() != 0) {
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HAL_NVIC_SystemReset();
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}
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SystemCoreClockUpdate();
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SystemCoreClockUpdateL4();
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RCC->APB1ENR1 |= (RCC_APB1ENR1_TIM2EN | RCC_APB1ENR1_TIM3EN | RCC_APB1ENR1_TIM4EN | RCC_APB1ENR1_TIM7EN | RCC_APB1ENR1_USART2EN | RCC_APB1ENR1_USART3EN | RCC_APB1ENR1_DAC1EN);
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RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN | RCC_APB2ENR_USART1EN);
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@ -0,0 +1,15 @@
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/*
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* system_stm32l4xx.h
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*
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* Created on: Jul 3, 2021
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* Author: mateusz
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*/
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#ifndef INCLUDE_CMSIS_STM32L4XX_SYSTEM_STM32L4XX_H_
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#define INCLUDE_CMSIS_STM32L4XX_SYSTEM_STM32L4XX_H_
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void SystemCoreClockUpdateL4(void);
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int SystemClock_Config_L4(void);
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#endif /* INCLUDE_CMSIS_STM32L4XX_SYSTEM_STM32L4XX_H_ */
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@ -272,7 +272,7 @@ void SystemInit(void)
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*
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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void SystemCoreClockUpdateL4(void)
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{
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uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr;
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@ -344,76 +344,92 @@ void SystemCoreClockUpdate(void)
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* @brief System Clock Configuration
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* @retval None
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*/
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int SystemClock_Config(void)
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int SystemClock_Config_L4(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
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/** Configure LSE Drive Capability
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*/
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HAL_PWR_EnableBkUpAccess();
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__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
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// set the flash latency
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FLASH->ACR |= FLASH_ACR_LATENCY_2WS;
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
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|RCC_OSCILLATORTYPE_LSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.LSIState = RCC_LSI_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 1;
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RCC_OscInitStruct.PLL.PLLN = 12;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV4;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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return -1;
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
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{
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return -2;
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}
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
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|RCC_PERIPHCLK_USART2|RCC_PERIPHCLK_USART3
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|RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_RNG
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|RCC_PERIPHCLK_ADC;
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PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
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PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
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PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
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PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
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PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
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PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
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PeriphClkInit.RngClockSelection = RCC_RNGCLKSOURCE_PLLSAI1;
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PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
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PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
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PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
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PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
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PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV4;
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PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV4;
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PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
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{
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return -3;
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}
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/** Configure the main internal regulator output voltage
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*/
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if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
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{
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return -4;
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}
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// turn on high speed external quartz oscilator
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RCC->CR |= RCC_CR_HSEON;
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// turn of the PLL1 before any configuration change
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RCC->CR &= (0xFFFFFFFF ^ RCC_CR_PLLON);
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// be sure that PLL is not running
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while ((RCC->CR & RCC_CR_PLLRDY) != 0);
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// set the clock source for PLL
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
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// R division factor for PLL to /4 (DIV4)
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLR_0;
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// Q divistion factor for PLL to /2 (DIV2)
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RCC->PLLCFGR &= (0xFFFFFFFF ^ (RCC_PLLCFGR_PLLQ_Msk));
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// P division factor for PLL to /7 (DIV7)
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RCC->PLLCFGR &= (0xFFFFFFFF ^ (RCC_PLLCFGR_PLLP_Msk));
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// M multiplication factor to 1
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RCC->PLLCFGR &= (0xFFFFFFFF ^ (RCC_PLLCFGR_PLLM_Msk));
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// N multiplication factor to 12
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RCC->PLLCFGR |= (12 << RCC_PLLCFGR_PLLN_Pos);
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// turn on the PLL
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RCC->CR |= RCC_CR_PLLON;
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// wait for PLL to startup and lock
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while ((RCC->CR & RCC_CR_PLLRDY) == 0);
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// turn on all PLL outputs
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN;
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLPEN;
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLQEN;
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// turn on LSI
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RCC->CSR |= RCC_CSR_LSION;
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// turn on LSE
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RCC->BDCR |= RCC_BDCR_LSEON;
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// select PLL as a system clock
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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// wait for the clock to switch
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while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);
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// if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
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// {
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// return -2;
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// }
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// PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
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// |RCC_PERIPHCLK_USART2|RCC_PERIPHCLK_USART3
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// |RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_RNG
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// |RCC_PERIPHCLK_ADC;
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// PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
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// PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
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// PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
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// PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
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// PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
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// PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
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// PeriphClkInit.RngClockSelection = RCC_RNGCLKSOURCE_PLLSAI1;
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// PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
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// PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
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// PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
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// PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
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// PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV4;
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// PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV4;
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// PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK;
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return 0;
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}
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