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spi, something not work

tatry_variant
Mateusz Lubecki 2022-09-28 02:52:26 +02:00
rodzic 9c5632ffe5
commit 7f5368ae08
2 zmienionych plików z 19 dodań i 12 usunięć
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17
system/src/drivers/l4/spi_stm32l4xx.c
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@ -462,6 +462,7 @@ uint8_t * spi_get_rx_data(void) {
uint8_t spi_wait_for_comms_done(void) {
if (spi_tx_state == SPI_TX_TXING) {
while (spi_tx_state == SPI_TX_TXING);
while ((SPI2->SR & SPI_SR_BSY) != 0);
}
if (spi_rx_state == SPI_RX_RXING) {
@ -502,11 +503,8 @@ void spi_irq_handler(void) {
// true.
if ((SPI2->SR & SPI_SR_RXNE) != 0) {
if (spi_rx_state == SPI_RX_WAITING_FOR_RX) {
spi_garbage = SPI2->DR & 0xFF;
}
// check if receiving is pending
else if (spi_rx_state == SPI_RX_RXING) {
if (spi_rx_state == SPI_RX_RXING) {
// get all data from RX FIFO
do {
@ -528,6 +526,11 @@ void spi_irq_handler(void) {
}
} while ((SPI2->SR & SPI_SR_RXNE) != 0);
}
else {
do {
spi_garbage = SPI2->DR & 0xFF;
} while ((SPI2->SR & SPI_SR_RXNE) != 0);
}
}
// The TXE flag is set when transmission TXFIFO has enough space to store data to send.
@ -547,12 +550,16 @@ void spi_irq_handler(void) {
SPI2->DR = spi_tx_buffer[spi_current_tx_cntr++];
}
else {
while((SPI2->SR & SPI_SR_BSY) != 0); // blocking!!
// finish transmission
spi_tx_state = SPI_TX_DONE;
// check if reception shall begin
if (spi_rx_state == SPI_RX_WAITING_FOR_RX) {
spi_rx_state = SPI_RX_RXING;
SPI2->DR = 0xFF;
}
break;
@ -683,6 +690,8 @@ void spi_disable(uint8_t immediately) {
}
}
else {
LL_GPIO_SetOutputPin((GPIO_TypeDef *)spi_slaves_cfg[spi_current_slave - 1][1], spi_slaves_cfg[spi_current_slave - 1][2]);
// disable all interrupts
SPI2->CR2 &= (0xFFFFFFFF ^ SPI_CR2_ERRIE);
SPI2->CR2 &= (0xFFFFFFFF ^ SPI_CR2_RXNEIE);

14
system/src/drivers/max31865.c
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@ -70,8 +70,6 @@ static uint8_t max31865_get_config_register(void) {
void max31865_init(uint8_t rdt_type) {
uint8_t bytes[2];
if (rdt_type == MAX_3WIRE) {
max31865_rdt_sensor_type = 1;
}
@ -84,19 +82,19 @@ void max31865_init(uint8_t rdt_type) {
max31865_vbias = 1;
bytes[0] = 0x80;
bytes[1] = max31865_get_config_register();
max31865_buffer[0] = 0x80;
max31865_buffer[1] = max31865_get_config_register();
spi_tx_data(1, bytes, 2);
spi_tx_data(1, max31865_buffer, 2);
spi_wait_for_comms_done();
// read adres of configuation register
bytes[0] = 0x00;
bytes[1] = 0x00;
max31865_buffer[0] = 0x03;
max31865_buffer[1] = 0x03;
// read data for verifiaction
spi_rx_tx_data(1, 0, bytes, 30, 1);
spi_rx_tx_data(1, 0, max31865_buffer, 30, 1);
spi_wait_for_comms_done();