kopia lustrzana https://github.com/SP8EBC/ParaTNC
power save function but not yet working
Mateusz Lubecki
rodzic
0d8a02e7fb
commit
13de42e7e0
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@ -20,6 +20,7 @@ C_SRCS += \
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../src/it_handlers.c \
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../src/main.c \
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../src/packet_tx_handler.c \
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../src/pwr_save.c \
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../src/rte_main.c \
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../src/rte_pv.c \
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../src/rte_rtu.c \
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@ -46,6 +47,7 @@ OBJS += \
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./src/it_handlers.o \
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./src/main.o \
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./src/packet_tx_handler.o \
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./src/pwr_save.o \
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./src/rte_main.o \
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./src/rte_pv.o \
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./src/rte_rtu.o \
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@ -72,6 +74,7 @@ C_DEPS += \
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./src/it_handlers.d \
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./src/main.d \
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./src/packet_tx_handler.d \
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./src/pwr_save.d \
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./src/rte_main.d \
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./src/rte_pv.d \
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./src/rte_rtu.d \
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@ -1,6 +1,6 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals> <peripheral name="RTC"/> </peripherals> "/>
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<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals> <peripheral name="RTC"/> <peripheral name="FLASH"/> <peripheral name="SCB"/> <peripheral name="DBGMCU"/> <peripheral name="EXTI"/> <peripheral name="PWR"/> <peripheral name="USART2"/> </peripherals> "/>
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<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
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<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
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<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
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@ -0,0 +1,21 @@
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/*
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* pwr_save.h
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*
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* Created on: Aug 22, 2021
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* Author: mateusz
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*/
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#ifndef PWR_SAVE_H_
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#define PWR_SAVE_H_
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#include "station_config_target_hw.h"
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#if defined(STM32L471xx)
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void pwr_save_init(void);
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void pwr_save_enter_stop2(void);
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#endif
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#endif /* PWR_SAVE_H_ */
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5
src/io.h
5
src/io.h
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@ -22,11 +22,6 @@ void io_oc_output_hiz(void);
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void io_ext_watchdog_config(void);
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void io_ext_watchdog_service(void);
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//void io_5v_isol_sw_cntrl_vbat_s_enable(void);
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//void io_5v_isol_sw_cntrl_vbat_s_disable(void);
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//
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//void io_12v_sw_cntrl_vbat_g_enable(void);
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//void io_12v_sw_cntrl_vbat_g_disable(void);
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inline void io_5v_isol_sw_cntrl_vbat_s_enable(void) {
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GPIOB->BSRR |= GPIO_BSRR_BS8;
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20
src/main.c
20
src/main.c
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@ -37,6 +37,7 @@
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#include "LedConfig.h"
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#include "io.h"
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#include "float_to_string.h"
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#include "pwr_save.h"
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#include "it_handlers.h"
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@ -82,12 +83,12 @@
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// Niebieska dioda -> DCD
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// Zielona dioda -> anemometr albo TX
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// backup registers
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// 2 -> 4bit hard-faults | 4bit boot-counter
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// 3 -> hard fault PC LSB
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// 4 -> hard fault PC MSB
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// 5 -> hard fault LR LSB
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// 6 -> hard fault LR MSB
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// backup registers (ParaTNC)
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// 2 -> boot and hard fault count
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// 3 -> controller configuration status
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// backup registers (ParaMETEO)
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#define CONFIG_FIRST_RESTORED (1)
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#define CONFIG_FIRST_FAIL_RESTORING (1 << 1)
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@ -430,6 +431,11 @@ int main(int argc, char* argv[]){
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#endif
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#if defined(STM32L471xx)
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// initialize all powersaving functions
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pwr_save_init();
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#endif
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// initalizing separated Open Collector output
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io_oc_init();
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@ -806,6 +812,8 @@ int main(int argc, char* argv[]){
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io_ext_watchdog_service();
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pwr_save_enter_stop2();
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// Infinite loop
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while (1)
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{
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@ -0,0 +1,97 @@
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/*
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* pwr_save.c
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*
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* Created on: Aug 22, 2021
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* Author: mateusz
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*/
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#include "pwr_save.h"
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#include "stm32l4xx.h"
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#include <stdint.h>
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#define IN_STOP2_MODE (1 << 1)
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#if defined(STM32L471xx)
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/**
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* This function initializes everything related to power saving features
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* including programming Flash memory option bytes
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*/
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void pwr_save_init(void) {
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// make a pointer to option byte
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uint32_t* option_byte = (uint32_t*)0x1FFF7800;
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// content of option byte read from the flash memory
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uint32_t option_byte_content = *option_byte;
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// definition of bitmask
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#define IWDG_STBY_STOP (0x3 << 17)
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// check if IWDG_STDBY and IWDG_STOP is not set in ''User and read protection option bytes''
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// at 0x1FFF7800
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if ((option_byte_content & IWDG_STBY_STOP) == IWDG_STBY_STOP) {
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// unlock write/erase operations on flash memory
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FLASH->KEYR = 0x45670123;
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FLASH->KEYR = 0xCDEF89AB;
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// wait for any possible flash operation to finish (rather impossible here, but ST manual recommend doing this)
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while((FLASH->SR & FLASH_SR_BSY) != 0);
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// unlock operations on option bytes
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FLASH->OPTKEYR = 0x08192A3B;
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FLASH->OPTKEYR = 0x4C5D6E7F;
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// set the flash option register (in RAM!!)
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FLASH->OPTR &= (0xFFFFFFFF ^ (FLASH_OPTR_IWDG_STDBY | FLASH_OPTR_IWDG_STOP));
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// trigger an update of flash option bytes with values from RAM (from FLASH->OPTR)
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FLASH->CR |= FLASH_CR_OPTSTRT;
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// wait for option bytes to be updated
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while((FLASH->SR & FLASH_SR_BSY) != 0);
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// lock flash memory
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FLASH-> CR |= FLASH_CR_LOCK;
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// forcre reloading option bytes
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FLASH->CR |= FLASH_CR_OBL_LAUNCH;
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}
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}
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/**
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* Entering STOP2 power save mode. In this mode all clocks except LSI and LSE are disabled. StaticRAM content
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* is preserved, optionally GPIO and few other peripherals can be kept power up depending on configuration
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*/
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void pwr_save_enter_stop2(void) {
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// clear previous low power mode selection
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PWR->CR1 &= (0xFFFFFFFF ^ PWR_CR1_LPMS_Msk);
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// select STOP2
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PWR->CR1 |= PWR_CR1_LPMS_STOP2;
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// enable write access to RTC registers by writing two magic words
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RTC->WPR = 0xCA;
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RTC->WPR = 0x53;
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// save an information that STOP2 mode has been applied
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RTC->BKP4R |= IN_STOP2_MODE;
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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DBGMCU->CR &= (0xFFFFFFFF ^ (DBGMCU_CR_DBG_SLEEP_Msk | DBGMCU_CR_DBG_STOP_Msk | DBGMCU_CR_DBG_STANDBY_Msk));
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// disabling all IRQs
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__disable_irq();
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asm ("wfe");
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}
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#endif
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