2017-08-20 12:41:17 +00:00
|
|
|
/*
|
|
|
|
* TimerConfig.c
|
|
|
|
*
|
|
|
|
* Created on: 19.03.2017
|
|
|
|
* Author: mateusz
|
|
|
|
*/
|
|
|
|
|
2021-06-04 04:54:02 +00:00
|
|
|
|
2017-08-20 12:41:17 +00:00
|
|
|
#include "TimerConfig.h"
|
|
|
|
#include "station_config.h"
|
2021-06-04 04:54:02 +00:00
|
|
|
#include "station_config_target_hw.h"
|
|
|
|
|
|
|
|
#ifdef STM32F10X_MD_VL
|
|
|
|
#include <stm32f10x.h>
|
|
|
|
#include <stm32f10x_tim.h>
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef STM32L471xx
|
|
|
|
#include <stm32l4xx.h>
|
|
|
|
#include <stm32l4xx_ll_tim.h>
|
|
|
|
#endif
|
2017-08-20 12:41:17 +00:00
|
|
|
|
|
|
|
|
2020-06-24 18:29:12 +00:00
|
|
|
#if (_DELAY_BASE > 22)
|
|
|
|
#error "Transmit delay shouldn't be longer that 1100msec. Decrease _DELAY_BASE in config below 22"
|
2017-08-20 12:41:17 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
void TimerConfig(void) {
|
|
|
|
///////////////////////////////////////////
|
|
|
|
/// konfiguracja TIM2 -- dallas delay ///
|
|
|
|
///////////////////////////////////////////
|
2019-01-27 12:14:36 +00:00
|
|
|
//NVIC_SetPriority(TIM2_IRQn, 1);
|
2017-08-20 12:41:17 +00:00
|
|
|
TIM2->PSC = 0;
|
|
|
|
TIM2->ARR = 119;
|
|
|
|
TIM2->CR1 |= TIM_CR1_DIR;
|
|
|
|
TIM2->CR1 &= (0xFFFFFFFF ^ TIM_CR1_DIR);
|
|
|
|
// TIM2->CR1 |= TIM_CR1_CEN;
|
|
|
|
TIM2->DIER |= 1;
|
|
|
|
NVIC_EnableIRQ( TIM2_IRQn );
|
|
|
|
|
2021-09-21 19:00:52 +00:00
|
|
|
#ifdef STM32F10X_MD_VL
|
2017-08-20 12:41:17 +00:00
|
|
|
// //////////////////////////////
|
|
|
|
// //// konfiguracja TIM4 -- dac ///
|
|
|
|
// //////////////////////////////
|
2019-01-27 12:14:36 +00:00
|
|
|
//NVIC_SetPriority(TIM4_IRQn, 2);
|
2017-08-20 12:41:17 +00:00
|
|
|
TIM4->PSC = 0;
|
|
|
|
TIM4->ARR = 2499;
|
|
|
|
TIM4->CR1 |= TIM_CR1_DIR;
|
|
|
|
TIM4->CR1 &= (0xFFFFFFFF ^ TIM_CR1_DIR);
|
|
|
|
// TIM4->CR1 |= TIM_CR1_CEN; /* timer powinien byc uruchamiany tylko przy wysylaniu danych */
|
|
|
|
TIM4->DIER |= 1;
|
|
|
|
NVIC_EnableIRQ( TIM4_IRQn );
|
2021-09-21 19:00:52 +00:00
|
|
|
#else
|
|
|
|
// //////////////////////////////
|
|
|
|
// //// konfiguracja TIM4 -- dac ///
|
|
|
|
// //////////////////////////////
|
|
|
|
//NVIC_SetPriority(TIM4_IRQn, 2);
|
|
|
|
TIM5->PSC = 0;
|
|
|
|
TIM5->ARR = 2499;
|
|
|
|
TIM5->CR1 |= TIM_CR1_DIR;
|
|
|
|
TIM5->CR1 &= (0xFFFFFFFF ^ TIM_CR1_DIR);
|
|
|
|
// TIM4->CR1 |= TIM_CR1_CEN; /* timer powinien byc uruchamiany tylko przy wysylaniu danych */
|
|
|
|
TIM5->DIER |= 1;
|
|
|
|
NVIC_EnableIRQ( TIM5_IRQn );
|
|
|
|
#endif
|
2017-08-20 12:41:17 +00:00
|
|
|
///////////////////////////////////////////
|
|
|
|
/// konfiguracja TIM7 --adc ///
|
|
|
|
///////////////////////////////////////////
|
2019-01-27 12:14:36 +00:00
|
|
|
//NVIC_SetPriority(TIM7_IRQn, 3);
|
2017-08-20 12:41:17 +00:00
|
|
|
TIM7->PSC = 0;
|
|
|
|
TIM7->ARR = 624; /// 2499
|
|
|
|
TIM7->CR1 |= TIM_CR1_DIR;
|
|
|
|
TIM7->CR1 &= (0xFFFFFFFF ^ TIM_CR1_DIR);
|
|
|
|
TIM7->CR1 |= TIM_CR1_CEN;
|
|
|
|
TIM7->DIER |= 1;
|
|
|
|
NVIC_EnableIRQ( TIM7_IRQn );
|
|
|
|
|
|
|
|
}
|