kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
146 wiersze
5.5 KiB
ArmAsm
146 wiersze
5.5 KiB
ArmAsm
#include "rpi-base.h"
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#include "defs.h"
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#include "macros.S"
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.text
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.global capture_line_fast_sixbits_8bpp
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.global capture_line_fast_sixbits_16bpp
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// The capture line function is provided the following:
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// r0 = pointer to current line in frame buffer
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// r1 = number of complete psync cycles to capture (=param_chars_per_line)
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// r2 = frame buffer line pitch in bytes (=param_fb_pitch)
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// r3 = flags register
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// r4 = GPLEV0 constant
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// r5 = line number count down to 0 (initial value =param_nlines)
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// r6 = scan line count modulo 10
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// r7 = number of psyncs to skip
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// r8 = frame buffer height (=param_fb_height)
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//
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// All registers are available as scratch registers (i.e. nothing needs to be preserved)
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// 4bpp not currently used but left in in case
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.align 6
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b preload_capture_line_fast_sixbits
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capture_line_fast_sixbits_4bpp:
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push {lr}
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SETUP_VSYNC_DEBUG_R11
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SKIP_PSYNC_NO_OLD_CPLD
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mov r1, r1, lsr #2
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loop:
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_0_BITS_WIDE r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_1_BITS_WIDE // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_2_BITS_WIDE // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_3_BITS_WIDE r7 // input in r8
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cmp r1, #1
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stmeqia r0, {r7}
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popeq {r0, pc}
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_0_BITS_WIDE r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_1_BITS_WIDE // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_2_BITS_WIDE // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_3_BITS_WIDE r10 // input in r8
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stmia r0!, {r7, r10}
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subs r1, r1, #2
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bne loop
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pop {r0, pc}
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preload_capture_line_fast_sixbits:
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SETUP_DUMMY_PARAMETERS
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b capture_line_fast_sixbits_4bpp
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.ltorg
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// *** 8 bit ***
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.align 6
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b preload_capture_line_fast_sixbits_8bpp
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capture_line_fast_sixbits_8bpp:
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push {lr}
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SETUP_VSYNC_DEBUG_R11_R12
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SKIP_PSYNC_NO_OLD_CPLD
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mov r1, r1, lsr #2
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loop_8bpp:
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_LOW_BITS_8BPP_WIDE r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_HIGH_BITS_8BPP_WIDE r5 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_LOW_BITS_8BPP_WIDE r12 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_HIGH_BITS_8BPP_WIDE r6 // input in r8
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cmp r1, #1
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stmeqia r0, {r5, r6}
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popeq {r0, pc}
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_LOW_BITS_8BPP_WIDE r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_HIGH_BITS_8BPP_WIDE r7 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_LOW_BITS_8BPP_WIDE r12 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_HIGH_BITS_8BPP_WIDE r10 // input in r8
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stmia r0!, {r5, r6, r7, r10}
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subs r1, r1, #2
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bne loop_8bpp
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pop {r0, pc}
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preload_capture_line_fast_sixbits_8bpp:
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SETUP_DUMMY_PARAMETERS
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b capture_line_fast_sixbits_8bpp
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.ltorg
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// *** 16 bit ***
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.align 6
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b preload_capture_line_fast_sixbits_16bpp
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capture_line_fast_sixbits_16bpp:
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push {lr}
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SETUP_VSYNC_DEBUG_16BPP_R11
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SKIP_PSYNC_NO_OLD_CPLD
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mov r1, r1, lsr #2
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ldr r14, =palette_data_16
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loop_16bpp:
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_SIX_BITS_16BPP r11 r5 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_SIX_BITS_16BPP r11 r6 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_SIX_BITS_16BPP r11 r7 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_SIX_BITS_16BPP r11 r10 // input in r8
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stmia r0!, {r5, r6, r7, r10}
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subs r1, r1, #1
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bne loop_16bpp
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pop {r0, pc}
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preload_capture_line_fast_sixbits_16bpp:
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ldr r0, =palette_data_16
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mov r1, #64
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preload_loop:
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ldr r2, [r0], #4
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subs r1, r1, #1
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bne preload_loop
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SETUP_DUMMY_PARAMETERS
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b capture_line_fast_sixbits_16bpp
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