kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
Old V8 version of RGB CPLD with BBC support (may be deprecated)
IanSB
rodzic
d79c19f3e4
commit
b01a545cc3
|
|
@ -0,0 +1,70 @@
|
|||
# Global Clock Nets
|
||||
NET "clk" BUFG=CLK;
|
||||
|
||||
# Global Clock Nets
|
||||
NET "sp_clk" BUFG=CLK;
|
||||
|
||||
# 96MHz clock domain
|
||||
NET "clk" TNM_NET = clk_period_grp_1;
|
||||
TIMESPEC TS_clk_period_1 = PERIOD "clk_period_grp_1" 10.4ns HIGH;
|
||||
|
||||
# 10MHz clock domain
|
||||
#NET "sp_clk" TNM_NET = clk_period_grp_2;
|
||||
#TIMESPEC TS_clk_period_2 = PERIOD "clk_period_grp_2" 100ns HIGH;
|
||||
|
||||
NET "clk" LOC = "P43"; # input gpio21 (gclk)
|
||||
|
||||
NET "R3_I" LOC = "P32"; # input
|
||||
NET "G3_I" LOC = "P31"; # input
|
||||
NET "B3_I" LOC = "P30"; # input
|
||||
NET "R2_I" LOC = "P34"; # input
|
||||
NET "G2_I" LOC = "P36"; # input
|
||||
NET "B2_I" LOC = "P37"; # input
|
||||
NET "R1_I" LOC = "P39"; # input (was gpio26)
|
||||
NET "G1_I" LOC = "P40"; # input (was gpio19)
|
||||
NET "B1_I" LOC = "P38"; # input (was gpio16)
|
||||
NET "R0_I" LOC = "P21"; # input (was gpio27)
|
||||
NET "G0_I" LOC = "P42"; # input (was gpio25)
|
||||
NET "B0_I" LOC = "P18"; # input (was gpio24)
|
||||
|
||||
NET "csync_I" LOC = "P23"; # input
|
||||
NET "vsync_I" LOC = "P41"; # input (connects to vsync)
|
||||
|
||||
NET "analog" LOC = "P19"; # input gpio22
|
||||
|
||||
NET "version" LOC = "P33"; # input gpio18 (gsr)
|
||||
|
||||
NET "sp_clk" LOC = "P44"; # input gpio20 (gclk)
|
||||
NET "sp_data" LOC = "P7"; # input gpio0 (input only)
|
||||
NET "sp_clken" LOC = "P6"; # input gpio1 (input only)
|
||||
|
||||
NET "quad(0)" LOC = "P29"; # output gpio2
|
||||
NET "quad(1)" LOC = "P28"; # output gpio3
|
||||
NET "quad(2)" LOC = "P27"; # output gpio4
|
||||
NET "quad(3)" LOC = "P5"; # output gpio5
|
||||
NET "quad(4)" LOC = "P2"; # output gpio6
|
||||
NET "quad(5)" LOC = "P8"; # output gpio7
|
||||
NET "quad(6)" LOC = "P12"; # output gpio8
|
||||
NET "quad(7)" LOC = "P14"; # output gpio9
|
||||
NET "quad(8)" LOC = "P16"; # output gpio10
|
||||
NET "quad(9)" LOC = "P13"; # output gpio11
|
||||
NET "quad(10)" LOC = "P3"; # output gpio12
|
||||
NET "quad(11)" LOC = "P1"; # output gpio13
|
||||
|
||||
NET "psync" LOC = "P22"; # output gpio17
|
||||
NET "csync" LOC = "P20"; # output gpio23
|
||||
|
||||
NET "quad(0)" SLOW;
|
||||
NET "quad(1)" SLOW;
|
||||
NET "quad(2)" SLOW;
|
||||
NET "quad(3)" SLOW;
|
||||
NET "quad(4)" SLOW;
|
||||
NET "quad(5)" SLOW;
|
||||
NET "quad(6)" SLOW;
|
||||
NET "quad(7)" SLOW;
|
||||
NET "quad(8)" SLOW;
|
||||
NET "quad(9)" SLOW;
|
||||
NET "quad(10)" SLOW;
|
||||
NET "quad(11)" SLOW;
|
||||
NET "psync" SLOW;
|
||||
NET "csync" SLOW;
|
||||
|
|
@ -0,0 +1,407 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Engineer: David Banks
|
||||
--
|
||||
-- Create Date: 15/7/2018
|
||||
-- Module Name: RGBtoHDMI CPLD
|
||||
-- Project Name: RGBtoHDMI
|
||||
-- Target Devices: XC9572XL
|
||||
--
|
||||
-- Version: 1.0
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity RGBtoHDMI is
|
||||
Port (
|
||||
-- From RGB Connector
|
||||
R3_I: in std_logic;
|
||||
G3_I: in std_logic;
|
||||
B3_I: in std_logic;
|
||||
R2_I: in std_logic;
|
||||
G2_I: in std_logic;
|
||||
B2_I: in std_logic;
|
||||
R1_I: in std_logic;
|
||||
G1_I: in std_logic;
|
||||
B1_I: in std_logic;
|
||||
R0_I: in std_logic;
|
||||
G0_I: in std_logic;
|
||||
B0_I: in std_logic;
|
||||
|
||||
csync_I: in std_logic;
|
||||
vsync_I: in std_logic;
|
||||
|
||||
analog: inout std_logic;
|
||||
|
||||
-- From Pi
|
||||
clk: in std_logic;
|
||||
sp_clk: in std_logic;
|
||||
sp_clken: in std_logic;
|
||||
sp_data: in std_logic;
|
||||
|
||||
-- To PI GPIO
|
||||
quad: out std_logic_vector(11 downto 0);
|
||||
psync: out std_logic;
|
||||
csync: out std_logic;
|
||||
|
||||
-- User interface
|
||||
version: in std_logic
|
||||
);
|
||||
end RGBtoHDMI;
|
||||
|
||||
architecture Behavorial of RGBtoHDMI is
|
||||
|
||||
subtype counter_type is unsigned(6 downto 0);
|
||||
|
||||
-- Version number: Design_Major_Minor
|
||||
-- Design: 0 = BBC CPLD
|
||||
-- 1 = Alternative CPLD
|
||||
-- 2 = Atom CPLD
|
||||
-- 3 = six bit CPLD (if required);
|
||||
-- 4 = RGB CPLD (TTL)
|
||||
-- C = RGB CPLD (Analog)
|
||||
constant VERSION_NUM_RGB_TTL : std_logic_vector(11 downto 0) := x"485";
|
||||
constant VERSION_NUM_RGB_ANALOG : std_logic_vector(11 downto 0) := x"C85";
|
||||
|
||||
-- Sampling points
|
||||
constant INIT_SAMPLING_POINTS : std_logic_vector(25 downto 0) := "00000000011011011011011011";
|
||||
|
||||
signal shift_R : std_logic_vector(3 downto 0);
|
||||
signal shift_G : std_logic_vector(3 downto 0);
|
||||
signal shift_B : std_logic_vector(3 downto 0);
|
||||
|
||||
signal csync1 : std_logic;
|
||||
signal csync2 : std_logic;
|
||||
signal last : std_logic;
|
||||
|
||||
signal csync_counter : unsigned(1 downto 0);
|
||||
|
||||
-- The sampling counter runs at 96MHz
|
||||
-- - In modes 0..6 it is 6x the pixel clock
|
||||
-- - In mode 7 it is 8x the pixel clock
|
||||
--
|
||||
-- It serves several purposes:
|
||||
-- 1. Counts the 12us between the rising edge of nCSYNC and the first pixel
|
||||
-- 2. Counts within each pixel (bits 0, 1, 2)
|
||||
-- 3. Counts counts pixels within a quad pixel (bits 3 and 4)
|
||||
-- 4. Handles double buffering of alternative quad pixels (bit 5)
|
||||
--
|
||||
-- At the moment we don't count pixels with the line, the Pi does that
|
||||
signal counter : counter_type;
|
||||
|
||||
-- Sample point register;
|
||||
--
|
||||
-- In Mode 7 each pixel lasts 8 clocks (96MHz / 12MHz). The original
|
||||
-- pixel clock is a regenerated 6Mhz clock, and both edges are used.
|
||||
-- Due to the way it is generated, there are three distinct phases,
|
||||
-- each with different rising/falling edge speeds, hence six sampling
|
||||
-- points are used.
|
||||
--
|
||||
-- In Modes 0..6 each pixel lasts 6 clocks (96MHz / 16MHz). The original
|
||||
-- pixel clock is a clean 16Mhz clock, so only one sample point is needed.
|
||||
-- To achieve this, all six values are set to be the same. This minimises
|
||||
-- the logic in the CPLD.
|
||||
signal sp_reg : std_logic_vector(25 downto 0) := INIT_SAMPLING_POINTS;
|
||||
|
||||
-- Break out of sp_reg
|
||||
signal invert : std_logic;
|
||||
signal rate : std_logic_vector(1 downto 0);
|
||||
signal delay : unsigned(1 downto 0);
|
||||
signal half : std_logic;
|
||||
signal offset_A : std_logic_vector(2 downto 0);
|
||||
signal offset_B : std_logic_vector(2 downto 0);
|
||||
signal offset_C : std_logic_vector(2 downto 0);
|
||||
signal offset_D : std_logic_vector(2 downto 0);
|
||||
signal offset_E : std_logic_vector(2 downto 0);
|
||||
signal offset_F : std_logic_vector(2 downto 0);
|
||||
|
||||
-- Pipelined offset mux output
|
||||
signal offset : std_logic_vector(2 downto 0);
|
||||
|
||||
-- Index to cycle through offsets A..F
|
||||
signal index : std_logic_vector(2 downto 0);
|
||||
|
||||
-- Sample pixel on next clock; pipelined to reduce the number of product terms
|
||||
signal sample : std_logic;
|
||||
|
||||
-- New sample available, toggle psync on next cycle
|
||||
signal toggle : std_logic;
|
||||
|
||||
-- RGB Input Mux
|
||||
signal R3 :std_logic;
|
||||
signal G3 :std_logic;
|
||||
signal B3 :std_logic;
|
||||
signal R2 :std_logic;
|
||||
signal G2 :std_logic;
|
||||
signal B2 :std_logic;
|
||||
|
||||
signal divider : std_logic;
|
||||
signal mux : std_logic;
|
||||
signal mux_sync : std_logic;
|
||||
signal psync_pulse : std_logic;
|
||||
signal clamp_output : std_logic;
|
||||
signal clamp_pulse : std_logic;
|
||||
signal clamp_enable : std_logic;
|
||||
|
||||
signal swap_bits_R :std_logic;
|
||||
signal swap_bits_G :std_logic;
|
||||
signal swap_bits_B :std_logic;
|
||||
|
||||
begin
|
||||
offset_A <= sp_reg(2 downto 0);
|
||||
offset_B <= sp_reg(5 downto 3);
|
||||
offset_C <= sp_reg(8 downto 6);
|
||||
offset_D <= sp_reg(11 downto 9);
|
||||
offset_E <= sp_reg(14 downto 12);
|
||||
offset_F <= sp_reg(17 downto 15);
|
||||
half <= sp_reg(18);
|
||||
delay <= unsigned(sp_reg(20 downto 19));
|
||||
rate <= sp_reg(22 downto 21);
|
||||
invert <= sp_reg(23);
|
||||
divider <= sp_reg(24);
|
||||
mux <= sp_reg(25);
|
||||
|
||||
mux_sync <= vsync_I when mux = '1' and version = '1' else csync_I;
|
||||
|
||||
-- sp_data is overloaded as clamp on/off when rate = 00 or 01 and multiplex on/off when rate = 10 or 11
|
||||
-- rate = 00 is 3 bit capture with sp_data = clamp on/off
|
||||
-- rate = 01 is 6 bit capture with sp_data = clamp on/off
|
||||
-- rate = 10 and sp_data = 0 is 6 bit capture with 3 bit to 4 level encoding (clamp not usable in 4 level mode)
|
||||
-- rate = 10 and sp_data = 1 is 6 bit capture with multiplex enabled for 12 bit capture
|
||||
-- rate = 11 and mux = 0 is 12 bit capture
|
||||
-- rate = 11 and mux = 1 is 9 bit capture using vsync_I as replacement G1 bit (will work on 8 bit board)
|
||||
|
||||
swap_bits_G <= vsync_I when rate = "10" and sp_data = '0' else '0';
|
||||
swap_bits_B <= B1_I when rate = "10" and sp_data = '0' else '0';
|
||||
swap_bits_R <= R1_I when rate = "10" and sp_data = '0' else '0';
|
||||
|
||||
G3 <= G2_I when swap_bits_G = '1' else G3_I;
|
||||
G2 <= G3_I when swap_bits_G = '1' else G2_I;
|
||||
|
||||
B3 <= B2_I when swap_bits_B = '1' else B3_I;
|
||||
B2 <= B3_I when swap_bits_B = '1' else B2_I;
|
||||
|
||||
R3 <= R2_I when swap_bits_R = '1' else R3_I;
|
||||
R2 <= R3_I when swap_bits_R = '1' else R2_I;
|
||||
|
||||
-- Shift the bits in LSB first
|
||||
process(sp_clk)
|
||||
begin
|
||||
if rising_edge(sp_clk) then
|
||||
if sp_clken = '1' then
|
||||
sp_reg <= sp_data & sp_reg(sp_reg'left downto sp_reg'right + 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
|
||||
-- synchronize CSYNC to the sampling clock
|
||||
-- if link fitted sync is inverted. If +ve vsync connected to link & +ve hsync to S then generate -ve composite sync
|
||||
csync1 <= mux_sync xor invert;
|
||||
|
||||
-- De-glitch CSYNC
|
||||
-- csync1 is the possibly glitchy input
|
||||
-- csync2 is the filtered output
|
||||
if csync1 = csync2 then
|
||||
-- output same as input, reset the counter
|
||||
csync_counter <= to_unsigned(0, csync_counter'length);
|
||||
else
|
||||
-- output different to input
|
||||
csync_counter <= csync_counter + 1;
|
||||
-- if the difference lasts for N-1 cycles, update the output
|
||||
if csync_counter = 3 then
|
||||
csync2 <= csync1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Counter is used to find sampling point for first pixel
|
||||
last <= csync2;
|
||||
-- reset counter on the rising edge of csync
|
||||
if last = '0' and csync2 = '1' then
|
||||
counter(6 downto 3) <= "10" & delay;
|
||||
if half = '1' then
|
||||
counter(2 downto 0) <= "000";
|
||||
elsif divider = '1' then
|
||||
counter(2 downto 0) <= "100";
|
||||
else
|
||||
counter(2 downto 0) <= "011";
|
||||
end if;
|
||||
elsif divider = '1' or counter(2 downto 0) /= 5 then
|
||||
if counter(counter'left) = '1' then
|
||||
counter <= counter + 1;
|
||||
else
|
||||
counter(counter'left - 1 downto 0) <= counter(counter'left - 1 downto 0) + 1;
|
||||
end if;
|
||||
else
|
||||
if counter(counter'left) = '1' then
|
||||
counter <= counter + 3;
|
||||
else
|
||||
counter(counter'left - 1 downto 0) <= counter(counter'left - 1 downto 0) + 3;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Sample point offset index
|
||||
if counter(counter'left) = '1' then
|
||||
index <= "000";
|
||||
else
|
||||
-- so index offset changes at the same time counter wraps 7->0
|
||||
-- so index offset changes at the same time counter wraps ->0
|
||||
if (divider = '0' and counter(2 downto 0) = 4) or (divider = '1' and counter(2 downto 0) = 6) then
|
||||
case index is
|
||||
when "000" =>
|
||||
index <= "001";
|
||||
when "001" =>
|
||||
index <= "010";
|
||||
when "010" =>
|
||||
index <= "011";
|
||||
when "011" =>
|
||||
index <= "100";
|
||||
when "100" =>
|
||||
index <= "101";
|
||||
when others =>
|
||||
index <= "000";
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Sample point offset
|
||||
case index is
|
||||
when "000" =>
|
||||
offset <= offset_B;
|
||||
when "001" =>
|
||||
offset <= offset_C;
|
||||
when "010" =>
|
||||
offset <= offset_D;
|
||||
when "011" =>
|
||||
offset <= offset_E;
|
||||
when "100" =>
|
||||
offset <= offset_F;
|
||||
when others =>
|
||||
offset <= offset_A;
|
||||
end case;
|
||||
|
||||
-- sample/shift control
|
||||
if counter(counter'left) = '0' and counter(2 downto 0) = unsigned(offset) then
|
||||
sample <= '1';
|
||||
else
|
||||
sample <= '0';
|
||||
end if;
|
||||
|
||||
if sample = '1' then
|
||||
if rate = "11" and sp_data = '1' then
|
||||
shift_R <= R1_I & G2_I & B3_I & B0_I; -- 12 bpp
|
||||
elsif rate = "11" and sp_data = '0' then
|
||||
shift_R <= R1_I & G2_I & B3_I & B3_I; -- 9 bpp
|
||||
elsif rate = "10" and sp_data = '1' then
|
||||
shift_R <= shift_B(3) & G2_I & B3_I & shift_B(0); -- 6x2 multiplex 12 bpp
|
||||
elsif rate = "10" and sp_data = '0' then
|
||||
shift_R <= R2 & R3 & shift_R(3 downto 2); -- 6 bpp 4 level
|
||||
elsif rate = "01" then
|
||||
shift_R <= R2_I & R3_I & shift_R(3 downto 2); -- 6 bpp
|
||||
else
|
||||
shift_R <= R3_I & shift_R(3 downto 1); -- 3 bpp
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- G Sample/shift register
|
||||
if sample = '1' then
|
||||
if rate = "11" and sp_data = '1' then
|
||||
shift_G <= R2_I & G3_I & G0_I & B1_I; -- 12 bpp
|
||||
elsif rate = "11" and sp_data = '0' then
|
||||
shift_G <= R2_I & G3_I & G3_I & B1_I; -- 9 bpp
|
||||
elsif rate = "10" and sp_data = '1' then
|
||||
shift_G <= R2_I & G3_I & shift_R(2) & shift_R(1); -- 6x2 multiplex 12 bpp
|
||||
elsif rate = "10" and sp_data = '0' then
|
||||
shift_G <= G2 & G3 & shift_G(3 downto 2); -- 6 bpp 4 level
|
||||
elsif rate = "01" then
|
||||
shift_G <= G2_I & G3_I & shift_G(3 downto 2); -- 6 bpp
|
||||
else
|
||||
shift_G <= G3_I & shift_G(3 downto 1); -- 3 bpp
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- B Sample/shift register
|
||||
if sample = '1' then
|
||||
if rate = "11" and sp_data = '1' then
|
||||
shift_B <= R3_I & R0_I & G1_I & B2_I; -- 12 bpp
|
||||
elsif rate = "11" and sp_data = '0' then
|
||||
shift_B <= R3_I & R3_I & vsync_I & B2_I; -- 9 bpp with G1 on vsync_I
|
||||
elsif rate = "10" and sp_data = '1' then
|
||||
shift_B <= R3_I & shift_G(3) & shift_G(2) & B2_I; -- 6x2 multiplex 12 bpp
|
||||
elsif rate = "10" and sp_data = '0' then
|
||||
shift_B <= B2 & B3 & shift_B(3 downto 2); -- 6 bpp 4 level
|
||||
elsif rate = "01" then
|
||||
shift_B <= B2_I & B3_I & shift_B(3 downto 2); -- 6 bpp
|
||||
else
|
||||
shift_B <= B3_I & shift_B(3 downto 1); -- 3 bpp
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Pipeline when to update the quad
|
||||
if counter(counter'left) = '0' and (
|
||||
(rate = "00" and counter(4 downto 0) = 0) or -- single
|
||||
(rate = "01" and counter(3 downto 0) = 0) or -- double
|
||||
(rate = "10" and counter(3 downto 0) = 0) or -- double
|
||||
(rate = "11" and counter(2 downto 0) = 0) ) then -- quadruple
|
||||
-- toggle is asserted in cycle 1
|
||||
toggle <= '1';
|
||||
else
|
||||
toggle <= '0';
|
||||
end if;
|
||||
|
||||
-- Output quad register
|
||||
if version = '0' then
|
||||
if analog = '1' then
|
||||
quad <= VERSION_NUM_RGB_ANALOG;
|
||||
else
|
||||
quad <= VERSION_NUM_RGB_TTL;
|
||||
end if;
|
||||
elsif counter(counter'left) = '1' then
|
||||
quad <= (others => '0');
|
||||
elsif toggle = '1' then
|
||||
-- quad changes at the start of cycle 2
|
||||
quad(11) <= shift_B(3);
|
||||
quad(10) <= shift_G(3);
|
||||
quad(9) <= shift_R(3);
|
||||
quad(8) <= shift_B(2);
|
||||
quad(7) <= shift_G(2);
|
||||
quad(6) <= shift_R(2);
|
||||
quad(5) <= shift_B(1);
|
||||
quad(4) <= shift_G(1);
|
||||
quad(3) <= shift_R(1);
|
||||
quad(2) <= shift_B(0);
|
||||
quad(1) <= shift_G(0);
|
||||
quad(0) <= shift_R(0);
|
||||
end if;
|
||||
|
||||
-- Output a skewed version of psync
|
||||
if version = '0' then
|
||||
psync <= vsync_I;
|
||||
elsif counter(counter'left) = '1' then
|
||||
psync <= '0';
|
||||
elsif counter(2 downto 0) = 2 then -- comparing with N gives N-1 cycles of skew
|
||||
if rate = "00" then
|
||||
psync <= counter(5); -- normal
|
||||
elsif rate = "11" then
|
||||
psync <= counter(3); -- quadruple
|
||||
else
|
||||
psync <= counter(4); -- double
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
csync <= csync2; -- output the registered version to save a macro-cell
|
||||
|
||||
-- csync2 is cleaned but delayed so OR with csync1 to remove delay on trailing edge of sync pulse
|
||||
-- clamp not usable in 4 LEVEL mode (rate = 10) or 8/12 bit mode (rate = 11) so use as multiplex signal instead
|
||||
clamp_pulse <= not(sample) when rate = "10" or rate = "11" else not(csync1 or csync2);
|
||||
clamp_enable <= '1' when mux = '1' else version;
|
||||
-- spdata is overloaded as clamp on/off
|
||||
analog <= 'Z' when clamp_enable = '0' else clamp_pulse and sp_data;
|
||||
|
||||
end Behavorial;
|
||||
|
|
@ -0,0 +1,238 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="RGBtoHDMI.vhdl" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="RGBtoHDMI.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-10" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="None" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|RGBtoHDMI|Behavorial" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="../RGBtoHDMI.vhdl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/RGBtoHDMI" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="RGBtoHDMI" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="VQ44" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="RGBtoHDMI_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="RGBtoHDMI_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="RGBtoHDMI_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="RGBtoHDMI_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="RGBtoHDMI" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Report Format" xil_pn:value="Detail" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="iMPACT Project File" xil_pn:value="../auto_project.ipf" xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="RGBtoHDMI" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-04-24T12:02:15" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="D441DEAB2BF331CCD57BEACA4EE893A0" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
|
|
@ -0,0 +1,89 @@
|
|||
<?xml version='1.0' encoding='utf-8'?>
|
||||
<!--This is an ISE project configuration file.-->
|
||||
<!--It holds project specific layout data for the projectmgr plugin.-->
|
||||
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
|
||||
<Project version="2" owner="projectmgr" name="RGBtoHDMI" >
|
||||
<!--This is an ISE project configuration file.-->
|
||||
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>2</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem>RGBtoHDMI - Behavorial (C:/Github/RGBtoHDMI/vhdl_RGB_12bit_old_V8/RGBtoHDMI.vhdl)</SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000123000000020000000000000000000000000200000064ffffffff000000810000000300000002000001230000000100000003000000000000000100000003</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>RGBtoHDMI - Behavorial (C:/Github/RGBtoHDMI/vhdl_RGB_12bit_old_V8/RGBtoHDMI.vhdl)</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>Design Utilities</ClosedNode>
|
||||
<ClosedNode>Implement Design/Optional Implementation Tools/Generate Timing</ClosedNode>
|
||||
<ClosedNode>Implement Design/Synthesize - XST</ClosedNode>
|
||||
<ClosedNode>User Constraints</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem>Manage Configuration Project (iMPACT)</SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>Manage Configuration Project (iMPACT)</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView guiview="File" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems/>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000004e1000000040101000100000000000000000000000064ffffffff0000008100000000000000040000006c00000001000000000000009d0000000100000000000000660000000100000000000003720000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>RGBtoHDMI.ucf</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView guiview="Library" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>work</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems/>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>work</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem>Edit Constraints (Text)</SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>Edit Constraints (Text)</CurrentItem>
|
||||
</ItemView>
|
||||
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000040100000002</SourceProcessView>
|
||||
<CurrentView>Implementation</CurrentView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>Design Utilities</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem/>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem/>
|
||||
</ItemView>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2020-10-02T23:53:08</DateModified>
|
||||
<ModuleName>RGBtoHDMI</ModuleName>
|
||||
<SummaryTimeStamp>2020-10-02T09:23:46</SummaryTimeStamp>
|
||||
<SavedFilePath>C:/Github/RGBtoHDMI/vhdl_RGB_12bit_old_V8/iseconfig/RGBtoHDMI.xreport</SavedFilePath>
|
||||
<ImplementationReportsDirectory>C:/Github/RGBtoHDMI/vhdl_RGB_12bit_old_V8/working\</ImplementationReportsDirectory>
|
||||
<DateInitialized>2019-12-05T17:57:48</DateInitialized>
|
||||
<EnableMessageFiltering>false</EnableMessageFiltering>
|
||||
</header>
|
||||
<body>
|
||||
<viewgroup label="Design Overview" >
|
||||
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="RGBtoHDMI_summary.html" label="Summary" >
|
||||
<toc-item title="Design Overview" target="Design Overview" />
|
||||
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
|
||||
<toc-item title="Performance Summary" target="Performance Summary" />
|
||||
<toc-item title="Failing Constraints" target="Failing Constraints" />
|
||||
<toc-item title="Detailed Reports" target="Detailed Reports" />
|
||||
</view>
|
||||
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="RGBtoHDMI_envsettings.html" label="System Settings" />
|
||||
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" hidden="true" type="IOBProperties" file="RGBtoHDMI_map.xrpt" label="IOB Properties" />
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="RGBtoHDMI_map.xrpt" label="Control Set Information" />
|
||||
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" hidden="true" type="Module_Utilization" file="RGBtoHDMI_map.xrpt" label="Module Level Utilization" />
|
||||
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" hidden="true" type="ConstraintsData" file="RGBtoHDMI.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
|
||||
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" hidden="true" type="PinoutData" file="RGBtoHDMI_par.xrpt" label="Pinout Report" />
|
||||
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" hidden="true" type="ClocksData" file="RGBtoHDMI_par.xrpt" label="Clock Report" />
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" hidden="true" type="Timing_Analyzer" file="RGBtoHDMI.twx" label="Static Timing" />
|
||||
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="false" type="EXTERNAL_HTML" file="RGBtoHDMI_html/fit/report.htm" label="CPLD Fitter Report" />
|
||||
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="false" type="EXTERNAL_HTML" file="RGBtoHDMI_html/tim/report.htm" label="CPLD Timing Report" />
|
||||
</viewgroup>
|
||||
<viewgroup label="XPS Errors and Warnings" >
|
||||
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
|
||||
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
|
||||
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
|
||||
</viewgroup>
|
||||
<viewgroup label="XPS Reports" >
|
||||
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
|
||||
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
|
||||
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
|
||||
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="RGBtoHDMI.log" label="System Log File" />
|
||||
</viewgroup>
|
||||
<viewgroup label="Errors and Warnings" >
|
||||
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
|
||||
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
|
||||
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
|
||||
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
|
||||
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
|
||||
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
|
||||
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
|
||||
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
|
||||
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
|
||||
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
|
||||
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="false" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
|
||||
</viewgroup>
|
||||
<viewgroup label="Detailed Reports" >
|
||||
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="RGBtoHDMI.syr" label="Synthesis Report" >
|
||||
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
|
||||
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
|
||||
<toc-item title="HDL Compilation" target=" HDL Compilation " />
|
||||
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
|
||||
<toc-item title="HDL Analysis" target=" HDL Analysis " />
|
||||
<toc-item title="HDL Parsing" target=" HDL Parsing " />
|
||||
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
|
||||
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
|
||||
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
|
||||
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
|
||||
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
|
||||
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
|
||||
<toc-item title="Partition Report" target=" Partition Report " />
|
||||
<toc-item title="Final Report" target=" Final Report " />
|
||||
<toc-item title="Design Summary" target=" Design Summary " />
|
||||
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
|
||||
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
|
||||
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
|
||||
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
|
||||
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
|
||||
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
|
||||
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
|
||||
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
|
||||
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
|
||||
</view>
|
||||
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="RGBtoHDMI.srr" label="Synplify Report" />
|
||||
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="RGBtoHDMI.prec_log" label="Precision Report" />
|
||||
<view inputState="Synthesized" program="ngdbuild" type="Report" file="RGBtoHDMI.bld" label="Translation Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Command Line" target="Command Line:" />
|
||||
<toc-item title="Partition Status" target="Partition Implementation Status" />
|
||||
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
|
||||
</view>
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Report" file="RGBtoHDMI_map.mrp" label="Map Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
|
||||
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
|
||||
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
|
||||
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
|
||||
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
|
||||
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
|
||||
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
|
||||
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
|
||||
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
|
||||
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
|
||||
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
|
||||
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
|
||||
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Report" file="RGBtoHDMI.par" label="Place and Route Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
|
||||
<toc-item title="Router Information" target="Starting Router" />
|
||||
<toc-item title="Partition Status" target="Partition Implementation Status" />
|
||||
<toc-item title="Clock Report" target="Generating Clock Report" />
|
||||
<toc-item title="Timing Results" target="Timing Score:" />
|
||||
<toc-item title="Final Summary" target="Peak Memory Usage:" />
|
||||
</view>
|
||||
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" hidden="true" type="Report" file="RGBtoHDMI.twr" label="Post-PAR Static Timing Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Timing Report Description" target="Device,package,speed:" />
|
||||
<toc-item title="Informational Messages" target="INFO:" />
|
||||
<toc-item title="Warning Messages" target="WARNING:" />
|
||||
<toc-item title="Timing Constraints" target="Timing constraint:" />
|
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
|
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
|
||||
<toc-item title="Timing Summary" target="Timing summary:" />
|
||||
<toc-item title="Trace Settings" target="Trace Settings:" />
|
||||
</view>
|
||||
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="false" type="Report" file="RGBtoHDMI.rpt" label="CPLD Fitter Report (Text)" >
|
||||
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
|
||||
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
|
||||
<toc-item title="Pin Resources" target="** Pin Resources **" />
|
||||
<toc-item title="Global Resources" target="** Global Control Resources **" />
|
||||
</view>
|
||||
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="false" type="Report" file="RGBtoHDMI.tim" label="CPLD Timing Report (Text)" >
|
||||
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
|
||||
<toc-item title="Performance Summary" target="Performance Summary:" />
|
||||
</view>
|
||||
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="RGBtoHDMI.pwr" label="Power Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Power summary" target="Power summary" />
|
||||
<toc-item title="Thermal summary" target="Thermal summary" />
|
||||
</view>
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="true" type="Report" file="RGBtoHDMI.bgn" label="Bitgen Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
|
||||
<toc-item title="Final Summary" target="DRC detected" />
|
||||
</view>
|
||||
</viewgroup>
|
||||
<viewgroup label="Secondary Reports" >
|
||||
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
|
||||
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/RGBtoHDMI_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/RGBtoHDMI_translate.nlf" label="Post-Translate Simulation Model Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="RGBtoHDMI_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="RGBtoHDMI_map.map" label="Map Log File" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
<toc-item title="Design Information" target="Design Information" />
|
||||
<toc-item title="Design Summary" target="Design Summary" />
|
||||
</view>
|
||||
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
|
||||
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="RGBtoHDMI_preroute.twr" label="Post-Map Static Timing Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Timing Report Description" target="Device,package,speed:" />
|
||||
<toc-item title="Informational Messages" target="INFO:" />
|
||||
<toc-item title="Warning Messages" target="WARNING:" />
|
||||
<toc-item title="Timing Constraints" target="Timing constraint:" />
|
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
|
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
|
||||
<toc-item title="Timing Summary" target="Timing summary:" />
|
||||
<toc-item title="Trace Settings" target="Trace Settings:" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/RGBtoHDMI_map.nlf" label="Post-Map Simulation Model Report" />
|
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="RGBtoHDMI_map.psr" label="Physical Synthesis Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="RGBtoHDMI_pad.txt" label="Pad Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="RGBtoHDMI.unroutes" label="Unroutes Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="RGBtoHDMI_preroute.tsi" label="Post-Map Constraints Interaction Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="RGBtoHDMI.grf" label="Guide Results Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="RGBtoHDMI.dly" label="Asynchronous Delay Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="RGBtoHDMI.clk_rgn" label="Clock Region Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="RGBtoHDMI.tsi" label="Post-Place and Route Constraints Interaction Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="RGBtoHDMI_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
|
||||
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="netgen/par/RGBtoHDMI_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
|
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="RGBtoHDMI_sta.nlf" label="Primetime Netlist Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="RGBtoHDMI.ibs" label="IBIS Model" >
|
||||
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
|
||||
<toc-item title="Component" target="Component " />
|
||||
</view>
|
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="RGBtoHDMI.lck" label="Back-annotate Pin Report" >
|
||||
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
|
||||
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
|
||||
</view>
|
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="RGBtoHDMI.lpc" label="Locked Pin Constraints" >
|
||||
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
|
||||
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="false" type="Secondary_Report" file="netgen/fit/RGBtoHDMI_timesim.nlf" label="Post-Fit Simulation Model Report" />
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
|
||||
</viewgroup>
|
||||
</body>
|
||||
</report-views>
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="../RGBtoHDMI.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,76 @@
|
|||
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>RGBtoHDMI Project Status</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>RGBtoHDMI.xise</TD>
|
||||
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
|
||||
<TD>RGBtoHDMI</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
|
||||
<TD>New</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
|
||||
<TD>xc9572xl-10VQ44</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
|
||||
<TD>Balanced</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
|
||||
<TD>
|
||||
</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
|
||||
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
|
||||
<TD> </TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Post-Fit Simulation Model Report</TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 10/02/2020 - 23:53:08</center>
|
||||
</BODY></HTML>
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="Cpld" num="0" delta="new" >Unable to retrieve the path to the iSE Project Repository. Will use the default filename of '<arg fmt="%s" index="1">RGBtoHDMI.ise</arg>'.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
</messages>
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
</messages>
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
</messages>
|
||||
|
||||
Ładowanie…
Reference in New Issue