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Refactor xilinx projects so vhdl_bbc and vhdl_RGB_6bit share same vhdl/ucf file 

Change-Id: I7c6db57f6b1fe8331dbeaacc81e49e8239349625
pull/115/head
David Banks 2019-12-05 14:34:59 +00:00
rodzic b7ba4a2da0
commit 98170366a5
10 zmienionych plików z 37 dodań i 1036 usunięć
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8
.gitignore vendored
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@ -1,7 +1,11 @@
#*
*~
vhdl/iseconfig/
vhdl/working/
vhdl_bbc/iseconfig/
vhdl_bbc/working/
vhdl_RGB_6bit/iseconfig/
vhdl_RGB_6bit/working/
vhdl_YUV_6bit/iseconfig/
vhdl_YUV_6bit/working/
vhdl_alt/iseconfig/
vhdl_alt/working/
vhdl_atom/iseconfig/

2
vhdl/RGBtoHDMI.ucf
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@ -27,7 +27,7 @@ NET "SW1" LOC = "P38"; # input gpio16 (connects to sw1)
NET "SW2" LOC = "P39"; # input gpio26 (connects to sw2)
NET "SW3" LOC = "P40"; # input gpio19 (connects to sw3)
NET "vsync" LOC = "P41"; # input (connects to vsync)
NET "spare" LOC = "P19"; # input gpio22
NET "analog" LOC = "P19"; # input gpio22
NET "mode7" LOC = "P42"; # input gpio25 (connects to LED2, driven from Pi)
NET "mux" LOC = "P18"; # input gpio24

26
vhdl/RGBtoHDMI.vhdl
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@ -14,6 +14,9 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RGBtoHDMI is
Generic (
SupportAnalog : boolean := false
);
Port (
-- From Beeb RGB Connector
R0: in std_logic;
@ -23,6 +26,7 @@ entity RGBtoHDMI is
G1: in std_logic;
B1: in std_logic;
S: in std_logic;
analog: in std_logic;
-- From Pi
clk: in std_logic;
@ -43,7 +47,6 @@ entity RGBtoHDMI is
SW2: in std_logic;
SW3: in std_logic;
vsync: in std_logic;
spare: in std_logic; -- currently unused
LED1: in std_logic -- allow it to be driven from the Pi
);
end RGBtoHDMI;
@ -53,8 +56,15 @@ architecture Behavorial of RGBtoHDMI is
subtype counter_type is unsigned(7 downto 0);
-- Version number: Design_Major_Minor
-- Design: 0 = Normal CPLD, 1 = Alternative CPLD, 2=Atom CPLD; 3= six bit CPLD (if required)
constant VERSION_NUM : std_logic_vector(11 downto 0) := x"065";
-- Design: 0 = BBC CPLD
-- 1 = Alternative CPLD
-- 2 = Atom CPLD
-- 3 = six bit CPLD (if required);
-- 4 = RGB CPLD (TTL)
-- C = RGB CPLD (Analog)
constant VERSION_NUM_BBC : std_logic_vector(11 downto 0) := x"065";
constant VERSION_NUM_RGB_TTL : std_logic_vector(11 downto 0) := x"470";
constant VERSION_NUM_RGB_ANALOG : std_logic_vector(11 downto 0) := x"C70";
-- Sampling points
constant INIT_SAMPLING_POINTS : std_logic_vector(23 downto 0) := "000000011011011011011011";
@ -316,7 +326,15 @@ begin
-- Output quad register
if version = '0' then
quad <= VERSION_NUM;
if SupportAnalog then
if analog = '1' then
quad <= VERSION_NUM_RGB_ANALOG;
else
quad <= VERSION_NUM_RGB_TTL;
end if;
else
quad <= VERSION_NUM_BBC;
end if;
elsif counter(counter'left) = '1' then
quad <= (others => '0');
elsif toggle = '1' then

69
vhdl_RGB_6bit/RGBtoHDMI.ucf
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@ -1,69 +0,0 @@
# Global Clock Nets
NET "clk" BUFG=CLK;
# Global Clock Nets
NET "sp_clk" BUFG=CLK;
# 96MHz clock domain
NET "clk" TNM_NET = clk_period_grp_1;
TIMESPEC TS_clk_period_1 = PERIOD "clk_period_grp_1" 10.4ns HIGH;
# 10MHz clock domain
#NET "sp_clk" TNM_NET = clk_period_grp_2;
#TIMESPEC TS_clk_period_2 = PERIOD "clk_period_grp_2" 100ns HIGH;
NET "clk" LOC = "P43"; # input gpio21 (gclk)
NET "R0" LOC = "P32"; # input
NET "G0" LOC = "P31"; # input
NET "B0" LOC = "P30"; # input
NET "R1" LOC = "P34"; # input
NET "G1" LOC = "P36"; # input
NET "B1" LOC = "P37"; # input
NET "S" LOC = "P23"; # input
NET "version" LOC = "P33"; # input gpio18 (gsr)
NET "SW1" LOC = "P38"; # input gpio16 (connects to sw1)
NET "SW2" LOC = "P39"; # input gpio26 (connects to sw2)
NET "SW3" LOC = "P40"; # input gpio19 (connects to sw3)
NET "vsync" LOC = "P41"; # input (connects to vsync)
NET "analog" LOC = "P19"; # input gpio22
NET "mode7" LOC = "P42"; # input gpio25 (connects to LED2, driven from Pi)
NET "mux" LOC = "P18"; # input gpio24
NET "sp_clk" LOC = "P44"; # input gpio20 (gclk)
NET "sp_data" LOC = "P7"; # input gpio0 (input only)
NET "sp_clken" LOC = "P6"; # input gpio1 (input only)
NET "quad(0)" LOC = "P29"; # output gpio2
NET "quad(1)" LOC = "P28"; # output gpio3
NET "quad(2)" LOC = "P27"; # output gpio4
NET "quad(3)" LOC = "P5"; # output gpio5
NET "quad(4)" LOC = "P2"; # output gpio6
NET "quad(5)" LOC = "P8"; # output gpio7
NET "quad(6)" LOC = "P12"; # output gpio8
NET "quad(7)" LOC = "P14"; # output gpio9
NET "quad(8)" LOC = "P16"; # output gpio10
NET "quad(9)" LOC = "P13"; # output gpio11
NET "quad(10)" LOC = "P3"; # output gpio12
NET "quad(11)" LOC = "P1"; # output gpio13
NET "psync" LOC = "P22"; # output gpio17
NET "csync" LOC = "P20"; # output gpio23
NET "LED1" LOC = "P21"; # input gpio27 (connects to LED1, driven from Pi)
NET "quad(0)" SLOW;
NET "quad(1)" SLOW;
NET "quad(2)" SLOW;
NET "quad(3)" SLOW;
NET "quad(4)" SLOW;
NET "quad(5)" SLOW;
NET "quad(6)" SLOW;
NET "quad(7)" SLOW;
NET "quad(8)" SLOW;
NET "quad(9)" SLOW;
NET "quad(10)" SLOW;
NET "quad(11)" SLOW;
NET "psync" SLOW;
NET "csync" SLOW;

359
vhdl_RGB_6bit/RGBtoHDMI.vhdl
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@ -1,359 +0,0 @@
----------------------------------------------------------------------------------
-- Engineer: David Banks
--
-- Create Date: 15/7/2018
-- Module Name: RGBtoHDMI CPLD
-- Project Name: RGBtoHDMI
-- Target Devices: XC9572XL
--
-- Version: 1.0
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RGBtoHDMI is
Port (
-- From Beeb RGB Connector
R0: in std_logic;
G0: in std_logic;
B0: in std_logic;
R1: in std_logic;
G1: in std_logic;
B1: in std_logic;
S: in std_logic;
analog: in std_logic;
-- From Pi
clk: in std_logic;
mode7: in std_logic;
mux: in std_logic;
sp_clk: in std_logic;
sp_clken: in std_logic;
sp_data: in std_logic;
-- To PI GPIO
quad: out std_logic_vector(11 downto 0);
psync: out std_logic;
csync: out std_logic;
-- User interface
version: in std_logic;
SW1: in std_logic;
SW2: in std_logic;
SW3: in std_logic;
vsync: in std_logic;
spare: in std_logic; -- currently unused
LED1: in std_logic -- allow it to be driven from the Pi
);
end RGBtoHDMI;
architecture Behavorial of RGBtoHDMI is
subtype counter_type is unsigned(7 downto 0);
-- Version number: Design_Major_Minor
-- Design: 0 = Normal CPLD, 1 = Alternative CPLD, 2=Atom CPLD; 3= six bit CPLD (if required); 4 = RGB CPLD
constant VERSION_NUM : std_logic_vector(11 downto 0) := x"470";
-- Sampling points
constant INIT_SAMPLING_POINTS : std_logic_vector(23 downto 0) := "000000011011011011011011";
signal shift_R : std_logic_vector(3 downto 0);
signal shift_G : std_logic_vector(3 downto 0);
signal shift_B : std_logic_vector(3 downto 0);
signal csync1 : std_logic;
signal csync2 : std_logic;
signal last : std_logic;
signal csync_counter : unsigned(1 downto 0);
-- The sampling counter runs at 96MHz
-- - In modes 0..6 it is 6x the pixel clock
-- - In mode 7 it is 8x the pixel clock
--
-- It serves several purposes:
-- 1. Counts the 12us between the rising edge of nCSYNC and the first pixel
-- 2. Counts within each pixel (bits 0, 1, 2)
-- 3. Counts counts pixels within a quad pixel (bits 3 and 4)
-- 4. Handles double buffering of alternative quad pixels (bit 5)
--
-- At the moment we don't count pixels with the line, the Pi does that
signal counter : counter_type;
-- Sample point register;
--
-- In Mode 7 each pixel lasts 8 clocks (96MHz / 12MHz). The original
-- pixel clock is a regenerated 6Mhz clock, and both edges are used.
-- Due to the way it is generated, there are three distinct phases,
-- each with different rising/falling edge speeds, hence six sampling
-- points are used.
--
-- In Modes 0..6 each pixel lasts 6 clocks (96MHz / 16MHz). The original
-- pixel clock is a clean 16Mhz clock, so only one sample point is needed.
-- To achieve this, all six values are set to be the same. This minimises
-- the logic in the CPLD.
signal sp_reg : std_logic_vector(23 downto 0) := INIT_SAMPLING_POINTS;
-- Break out of sp_reg
signal invert : std_logic;
signal rate : std_logic_vector(1 downto 0);
signal delay : unsigned(1 downto 0);
signal half : std_logic;
signal offset_A : std_logic_vector(2 downto 0);
signal offset_B : std_logic_vector(2 downto 0);
signal offset_C : std_logic_vector(2 downto 0);
signal offset_D : std_logic_vector(2 downto 0);
signal offset_E : std_logic_vector(2 downto 0);
signal offset_F : std_logic_vector(2 downto 0);
-- Pipelined offset mux output
signal offset : std_logic_vector(2 downto 0);
-- Index to cycle through offsets A..F
signal index : std_logic_vector(2 downto 0);
-- Sample pixel on next clock; pipelined to reduce the number of product terms
signal sample : std_logic;
-- New sample available, toggle psync on next cycle
signal toggle : std_logic;
-- RGB Input Mux
signal R : std_logic;
signal G : std_logic;
signal B : std_logic;
signal R0M : std_logic;
signal G0M : std_logic;
signal B0M : std_logic;
signal R1M : std_logic;
signal G1M : std_logic;
signal B1M : std_logic;
begin
R <= R1 when mux = '1' else R0;
G <= G1 when mux = '1' else G0;
B <= B1 when mux = '1' else B0;
R0M <= vsync when mux = '1' else R0;
G0M <= vsync when mux = '1' else G0;
B0M <= vsync when mux = '1' else B0;
R1M <= vsync when mux = '1' else R1;
G1M <= vsync when mux = '1' else G1;
B1M <= vsync when mux = '1' else B1;
offset_A <= sp_reg(2 downto 0);
offset_B <= sp_reg(5 downto 3);
offset_C <= sp_reg(8 downto 6);
offset_D <= sp_reg(11 downto 9);
offset_E <= sp_reg(14 downto 12);
offset_F <= sp_reg(17 downto 15);
half <= sp_reg(18);
delay <= unsigned(sp_reg(20 downto 19));
rate <= sp_reg(22 downto 21);
invert <= sp_reg(23);
-- Shift the bits in LSB first
process(sp_clk, SW1)
begin
if rising_edge(sp_clk) then
if sp_clken = '1' then
sp_reg <= sp_data & sp_reg(sp_reg'left downto sp_reg'right + 1);
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
-- synchronize CSYNC to the sampling clock
-- if link fitted sync is inverted. If +ve vsync connected to link & +ve hsync to S then generate -ve composite sync
csync1 <= S xor invert;
-- De-glitch CSYNC
-- csync1 is the possibly glitchy input
-- csync2 is the filtered output
if csync1 = csync2 then
-- output same as input, reset the counter
csync_counter <= to_unsigned(0, csync_counter'length);
else
-- output different to input
csync_counter <= csync_counter + 1;
-- if the difference lasts for N-1 cycles, update the output
if csync_counter = 3 then
csync2 <= csync1;
end if;
end if;
-- Counter is used to find sampling point for first pixel
last <= csync2;
-- reset counter on the rising edge of csync
if last = '0' and csync2 = '1' then
if rate(1) = '1' then
counter(7 downto 3) <= "10" & delay & "0";
if half = '1' then
counter(2 downto 0) <= "000";
elsif mode7 = '1' then
counter(2 downto 0) <= "100";
else
counter(2 downto 0) <= "011";
end if;
else
counter(7 downto 3) <= "110" & delay;
if half = '1' then
counter(2 downto 0) <= "000";
elsif mode7 = '1' then
counter(2 downto 0) <= "100";
else
counter(2 downto 0) <= "011";
end if;
end if;
elsif mode7 = '1' or counter(2 downto 0) /= 5 then
if counter(counter'left) = '1' then
counter <= counter + 1;
else
counter(counter'left - 1 downto 0) <= counter(counter'left - 1 downto 0) + 1;
end if;
else
if counter(counter'left) = '1' then
counter <= counter + 3;
else
counter(counter'left - 1 downto 0) <= counter(counter'left - 1 downto 0) + 3;
end if;
end if;
-- Sample point offset index
if counter(counter'left) = '1' then
index <= "000";
else
-- so index offset changes at the same time counter wraps 7->0
-- so index offset changes at the same time counter wraps ->0
if (mode7 = '0' and counter(2 downto 0) = 4) or (mode7 = '1' and counter(2 downto 0) = 6) then
case index is
when "000" =>
index <= "001";
when "001" =>
index <= "010";
when "010" =>
index <= "011";
when "011" =>
index <= "100";
when "100" =>
index <= "101";
when others =>
index <= "000";
end case;
end if;
end if;
-- Sample point offset
case index is
when "000" =>
offset <= offset_B;
when "001" =>
offset <= offset_C;
when "010" =>
offset <= offset_D;
when "011" =>
offset <= offset_E;
when "100" =>
offset <= offset_F;
when others =>
offset <= offset_A;
end case;
-- sample/shift control
if counter(counter'left) = '0' and counter(2 downto 0) = unsigned(offset) and (rate(1) = '0' or rate(0) = counter(3)) then
sample <= '1';
else
sample <= '0';
end if;
-- R Sample/shift register
if sample = '1' then
if rate = "01" then
shift_R <= R1M & R0M & shift_R(3 downto 2); -- double
else
shift_R <= R & shift_R(3 downto 1);
end if;
end if;
-- G Sample/shift register
if sample = '1' then
if rate = "01" then
shift_G <= G1M & G0M & shift_G(3 downto 2); -- double
else
shift_G <= G & shift_G(3 downto 1);
end if;
end if;
-- B Sample/shift register
if sample = '1' then
if rate = "01" then
shift_B <= B1M & B0M & shift_B(3 downto 2); -- double
else
shift_B <= B & shift_B(3 downto 1);
end if;
end if;
-- Pipeline when to update the quad
if counter(counter'left) = '0' and (
(rate = "00" and counter(4 downto 0) = 0) or -- normal
(rate = "01" and counter(3 downto 0) = 0) or -- double
(rate = "10" and counter(5 downto 0) = 0) or -- subsample even
(rate = "11" and counter(5 downto 0) = 32)) then -- subsample odd
-- toggle is asserted in cycle 1
toggle <= '1';
else
toggle <= '0';
end if;
-- Output quad register
if version = '0' then
quad <= analog & VERSION_NUM(10 downto 0);
elsif counter(counter'left) = '1' then
quad <= (others => '0');
elsif toggle = '1' then
-- quad changes at the start of cycle 2
quad(11) <= shift_B(3);
quad(10) <= shift_G(3);
quad(9) <= shift_R(3);
quad(8) <= shift_B(2);
quad(7) <= shift_G(2);
quad(6) <= shift_R(2);
quad(5) <= shift_B(1);
quad(4) <= shift_G(1);
quad(3) <= shift_R(1);
quad(2) <= shift_B(0);
quad(1) <= shift_G(0);
quad(0) <= shift_R(0);
end if;
-- Output a skewed version of psync
if version = '0' then
psync <= vsync;
elsif counter(counter'left) = '1' then
psync <= '0';
elsif counter(3 downto 0) = 3 then -- comparing with N gives N-1 cycles of skew
if rate = "00" then
psync <= counter(5); -- normal
elsif rate = "01" then
psync <= counter(4); -- double
elsif counter(5) = rate(0) then
psync <= counter(6); -- subsample
end if;
end if;
end if;
end process;
csync <= csync2; -- output the registered version to save a macro-cell
end Behavorial;

8
vhdl_RGB_6bit/RGBtoHDMI.xise
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@ -15,11 +15,11 @@
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="RGBtoHDMI.vhdl" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../vhdl/RGBtoHDMI.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="RGBtoHDMI.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="../vhdl/RGBtoHDMI.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
@ -69,7 +69,7 @@
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SupportAnalog=true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
@ -78,7 +78,7 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|RGBtoHDMI|Behavorial" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../RGBtoHDMI.vhdl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../vhdl/RGBtoHDMI.vhdl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/RGBtoHDMI" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>

593
vhdl_RGB_6bit/fitting.notes
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@ -1,593 +0,0 @@
1. Original design:
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 27/54 69/90 6/ 9
FB2 18/18* 34/54 60/90 8/ 9
FB3 18/18* 19/54 32/90 5/ 9
FB4 18/18* 37/54 56/90 7/ 7*
----- ----- ----- -----
72/72 117/216 217/360 26/34
2. New design, with RGB mux, switch pass throughs, etc commented out
(failed to map sp_reg<9>, hence one less macrocell)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 26/54 51/90 7/ 9
FB2 18/18* 25/54 33/90 6/ 9
FB3 18/18* 35/54 61/90 8/ 9
FB4 17/18 53/54 70/90 4/ 7
----- ----- ----- -----
71/72 139/216 215/360 25/34
3. Change from csync=>S to csync=>CSYNC1 (as passthroughs still use up a macro cell).
(now fits)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 17/18 33/54 64/90 7/ 9
FB2 18/18* 25/54 33/90 6/ 9
FB3 18/18* 35/54 61/90 8/ 9
FB4 18/18* 37/54 58/90 4/ 7
----- ----- ----- -----
71/72 130/216 216/360 25/34
4. Add in RGB mux:
(still fits)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 17/18 33/54 64/90 7/ 9
FB2 18/18* 25/54 33/90 9/ 9*
FB3 18/18* 37/54 61/90 8/ 9
FB4 18/18* 41/54 61/90 5/ 7
----- ----- ----- -----
71/72 136/216 219/360 29/34
5. Add in SW2out <= SW2:
(still fits)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 28/54 62/90 8/ 9
FB2 18/18* 25/54 33/90 9/ 9*
FB3 18/18* 37/54 61/90 8/ 9
FB4 18/18* 48/54 64/90 6/ 7
----- ----- ----- -----
72/72 138/216 220/360 31/34
6. Change to optimization effort normal->high:
(no difference)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 28/54 62/90 8/ 9
FB2 18/18* 25/54 33/90 9/ 9*
FB3 18/18* 37/54 61/90 8/ 9
FB4 18/18* 48/54 64/90 6/ 7
----- ----- ----- -----
72/72 138/216 220/360 31/34
7. Change to optimization effort speed->area:
(no difference)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 28/54 62/90 8/ 9
FB2 18/18* 25/54 33/90 9/ 9*
FB3 18/18* 37/54 61/90 8/ 9
FB4 18/18* 48/54 64/90 6/ 7
----- ----- ----- -----
72/72 138/216 220/360 31/34
8. Fitter Implmenetation Template: Optimize Balance-> Optimize Speed:
(no difference)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 28/54 62/90 8/ 9
FB2 18/18* 25/54 33/90 9/ 9*
FB3 18/18* 37/54 61/90 8/ 9
FB4 18/18* 48/54 64/90 6/ 7
----- ----- ----- -----
72/72 138/216 220/360 31/34
9. Fitter Implmenetation Template: Optimize Speed -> Optimize Density:
(no difference)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 28/54 62/90 8/ 9
FB2 18/18* 25/54 33/90 9/ 9*
FB3 18/18* 37/54 61/90 8/ 9
FB4 18/18* 48/54 64/90 6/ 7
----- ----- ----- -----
72/72 138/216 220/360 31/34
10. Reverted to original .xise file
Cleaned up design to remove SW2/3 pass throughs
Used gpio22/23 for mode7 / sp_data
Used gpio19/26 for sw2/3 (not via cpld)
(same result as 4 above)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 17/18 33/54 64/90 5/ 9
FB2 18/18* 25/54 33/90 9/ 9*
FB3 18/18* 37/54 61/90 8/ 9
FB4 18/18* 41/54 61/90 7/ 7*
----- ----- ----- -----
71/72 136/216 219/360 29/34
11. Final design on 5/6/2018
(Added SW2, SW3, Link as unused inputs)
(Added LED1 as output, driven to Z, still uses one macro cell)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 27/54 61/90 5/ 9
FB2 18/18* 25/54 33/90 9/ 9*
FB3 18/18* 37/54 61/90 9/ 9*
FB4 18/18* 48/54 64/90 7/ 7*
----- ----- ----- -----
72/72 137/216 219/360 30/34
12. Minor changes 1.15pm on 5/5/2018
(Removed SW1Out passthrough)
(csync output is back to being passthrough)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 25/54 35/90 4/ 9
FB2 18/18* 34/54 65/90 9/ 9*
FB3 18/18* 37/54 61/90 9/ 9*
FB4 18/18* 39/54 58/90 7/ 7*
----- ----- ----- -----
72/72 135/216 219/360 29/34
13. Removed SW1 from sp_reg assignment block
(the is prone to noise on the prototype, as it clamped at 2V by an LED)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 25/54 35/90 3/ 9
FB2 18/18* 34/54 65/90 9/ 9*
FB3 18/18* 37/54 61/90 9/ 9*
FB4 18/18* 39/54 58/90 7/ 7*
----- ----- ----- -----
72/72 135/216 219/360 28/34
14. Added sp_clken and spare
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 30/54 63/90 5/ 9
FB2 18/18* 26/54 46/90 9/ 9*
FB3 18/18* 35/54 60/90 8/ 9
FB4 18/18* 47/54 71/90 7/ 7*
----- ----- ----- -----
72/72 138/216 240/360 29/34
15. Replaced counter2(5..3) with load saving two registers
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 40/54 72/90 5/ 9
FB2 17/18 24/54 49/90 9/ 9*
FB3 18/18* 34/54 60/90 8/ 9
FB4 17/18 35/54 63/90 7/ 7*
----- ----- ----- -----
70/72 133/216 244/360 29/34
16. Mostly cosmetic seperation of the logic into several blocks
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 38/54 56/90 5/ 9
FB2 16/18 21/54 45/90 9/ 9*
FB3 18/18* 33/54 57/90 8/ 9
FB4 18/18* 37/54 70/90 7/ 7*
----- ----- ----- -----
70/72 129/216 228/360 29/34
17. Update counter to hopefully implement more efficiently
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 38/54 54/90 5/ 9
FB2 16/18 21/54 45/90 9/ 9*
FB3 18/18* 30/54 49/90 8/ 9
FB4 18/18* 35/54 65/90 7/ 7*
----- ----- ----- -----
70/72 124/216 213/360 29/34
18. Load always in cycle 0
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 38/54 53/90 5/ 9
FB2 16/18 21/54 45/90 9/ 9*
FB3 18/18* 30/54 45/90 8/ 9
FB4 18/18* 37/54 63/90 7/ 7*
----- ----- ----- -----
70/72 126/216 206/360 29/34
19. Dropped seperate sp_default stage
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 30/54 42/90 5/ 9
FB2 17/18 25/54 34/90 9/ 9*
FB3 18/18* 29/54 55/90 8/ 9
FB4 13/18 35/54 44/90 7/ 7*
----- ----- ----- -----
66/72 119/216 175/360 29/34
20. Added CPLD version output on Quad()
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 31/54 45/90 5/ 9
FB2 17/18 26/54 35/90 9/ 9*
FB3 18/18* 30/54 61/90 9/ 9*
FB4 13/18 36/54 47/90 7/ 7*
----- ----- ----- -----
66/72 123/216 188/360 30/34
21. Added configurable half-pixel delay
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 31/54 45/90 5/ 9
FB2 18/18* 27/54 37/90 9/ 9*
FB3 18/18* 31/54 65/90 9/ 9*
FB4 13/18 38/54 48/90 7/ 7*
----- ----- ----- -----
67/72 127/216 195/360 30/34
22. Final pinout changes - remove LED1 and LED2 as outputs
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 32/54 47/90 6/ 9
FB2 18/18* 32/54 41/90 8/ 9
FB3 18/18* 31/54 65/90 9/ 9*
FB4 11/18 32/54 41/90 5/ 7
----- ----- ----- -----
65/72 127/216 194/360 28/34
23. Made csync output registered and de-glitch csync (csync1..csync3)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 35/54 50/90 6/ 9
FB2 16/18 25/54 34/90 8/ 9
FB3 16/18 30/54 81/90 9/ 9*
FB4 16/18 40/54 61/90 5/ 7
----- ----- ----- -----
66/72 130/216 226/360 28/34
24. Increased de-glitch to include csync4
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 40/54 54/90 6/ 9
FB2 18/18* 29/54 43/90 8/ 9
FB3 15/18 35/54 81/90 9/ 9*
FB4 17/18 32/54 83/90 5/ 7
----- ----- ----- -----
68/72 136/216 261/360 28/34
25. Increased de-glitch to include csync5
... doesn't fit ...
26. Revert to 23, then use a 3-bit counter for csync deglitch
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 35/54 49/90 6/ 9
FB2 18/18* 29/54 43/90 8/ 9
FB3 17/18 33/54 81/90 9/ 9*
FB4 14/18 36/54 61/90 5/ 7
----- ----- ----- -----
67/72 133/216 234/360 28/34
27. Increase csync de-glitch counter to 4 bits
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 40/54 54/90 6/ 9
FB2 17/18 26/54 36/90 8/ 9
FB3 16/18 32/54 82/90 9/ 9*
FB4 17/18 37/54 80/90 5/ 7
----- ----- ----- -----
68/72 135/216 252/360 28/34
28. De-glitch both states of csync
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 31/54 45/90 6/ 9
FB2 16/18 25/54 34/90 8/ 9
FB3 18/18* 29/54 79/90 9/ 9*
FB4 18/18* 46/54 71/90 5/ 7
----- ----- ----- -----
70/72 131/216 229/360 28/34
29. Reduce csync de-glitch counter to 3 bits
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 31/54 45/90 6/ 9
FB2 16/18 25/54 34/90 8/ 9
FB3 18/18* 29/54 79/90 9/ 9*
FB4 17/18 45/54 67/90 5/ 7
----- ----- ----- -----
69/72 130/216 225/360 28/34
30. Reduce csync de-glitch counter to 2 bits
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 31/54 45/90 6/ 9
FB2 16/18 25/54 34/90 8/ 9
FB3 18/18* 29/54 79/90 9/ 9*
FB4 16/18 44/54 63/90 5/ 7
----- ----- ----- -----
68/72 129/216 221/360 28/34
31. Added 4-bit mode 7 delay register to the scan chain
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 29/54 43/90 6/ 9
FB2 18/18* 27/54 38/90 8/ 9
FB3 18/18* 36/54 81/90 9/ 9*
FB4 18/18* 52/54 70/90 5/ 7
----- ----- ----- -----
72/72 144/216 232/360 28/34
32. Start sampling 8us earlier, delay applied to all modes
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 29/54 43/90 6/ 9
FB2 18/18* 27/54 38/90 8/ 9
FB3 18/18* 33/54 78/90 9/ 9*
FB4 18/18* 49/54 69/90 5/ 7
----- ----- ----- -----
72/72 138/216 228/360 28/34
33. Corrected delay in 6 clocks/pixel mode
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 30/54 44/90 6/ 9
FB2 18/18* 27/54 38/90 8/ 9
FB3 18/18* 36/54 85/90 9/ 9*
FB4 18/18* 49/54 74/90 5/ 7
----- ----- ----- -----
72/72 142/216 241/360 28/34
34. XOR in delay
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 30/54 44/90 6/ 9
FB2 18/18* 27/54 38/90 8/ 9
FB3 18/18* 38/54 85/90 9/ 9*
FB4 18/18* 49/54 76/90 5/ 7
----- ----- ----- -----
72/72 144/216 243/360 28/34
35. Add in delay
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 30/54 44/90 6/ 9
FB2 18/18* 27/54 38/90 8/ 9
FB3 18/18* 38/54 85/90 9/ 9*
FB4 18/18* 49/54 78/90 5/ 7
----- ----- ----- -----
72/72 144/216 245/360 28/34
36. Add separate H and V sync support to CPLD
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 30/54 44/90 7/ 9
FB2 18/18* 27/54 38/90 8/ 9
FB3 18/18* 38/54 85/90 9/ 9*
FB4 18/18* 50/54 79/90 5/ 7
----- ----- ----- -----
72/72 145/216 246/360 29/34
37. Reduce counter from 12 bits to 8 bits
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 30/54 44/90 7/ 9
FB2 18/18* 27/54 38/90 8/ 9
FB3 17/18 36/54 82/90 9/ 9*
FB4 15/18 45/54 56/90 5/ 7
----- ----- ----- -----
68/72 138/216 220/360 29/34
38. Added rate option to scan chain
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 27/54 49/90 7/ 9
FB2 18/18* 28/54 40/90 8/ 9
FB3 15/18 32/54 83/90 9/ 9*
FB4 18/18* 52/54 82/90 5/ 7
----- ----- ----- -----
69/72 139/216 254/360 29/34
39. Re-order bits when rate=1
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 30/54 54/90 7/ 9
FB2 18/18* 28/54 40/90 8/ 9
FB3 15/18 32/54 83/90 9/ 9*
FB4 18/18* 52/54 83/90 5/ 7
----- ----- ----- -----
69/72 142/216 260/360 29/34
40. CPLD: Halt the counter during HSYNC
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 17/18 40/54 61/90 7/ 9
FB2 16/18 26/54 36/90 8/ 9
FB3 17/18 35/54 81/90 9/ 9*
FB4 18/18* 39/54 65/90 5/ 7
----- ----- ----- -----
68/72 140/216 243/360 29/34
41. Allow PSYNC duty cycle to be asymmetric
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 17/18 40/54 61/90 7/ 9
FB2 16/18 26/54 36/90 8/ 9
FB3 17/18 35/54 81/90 9/ 9*
FB4 18/18* 39/54 65/90 5/ 7
----- ----- ----- -----
68/72 140/216 243/360 29/34
42. Added Half-Even and Half Add Sampling (now v4.0)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 39/54 55/90 7/ 9
FB2 18/18* 23/54 36/90 8/ 9
FB3 18/18* 29/54 62/90 9/ 9*
FB4 18/18* 33/54 72/90 5/ 7
----- ----- ----- -----
72/72 124/216 225/360 29/34
43. Optimize generation of PSync, and allow more skew
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 35/54 53/90 7/ 9
FB2 17/18 22/54 34/90 8/ 9
FB3 18/18* 28/54 64/90 9/ 9*
FB4 18/18* 33/54 81/90 5/ 7
----- ----- ----- -----
71/72 118/216 232/360 29/34
44. Align quad timing back to cycle 0 as before
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 38/54 54/90 7/ 9
FB2 18/18* 23/54 36/90 8/ 9
FB3 18/18* 28/54 64/90 9/ 9*
FB4 17/18 33/54 82/90 5/ 7
----- ----- ----- -----
71/72 122/216 236/360 29/34
45. Fix long-standing bug concerning offset selection in Mode0..6
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 40/54 57/90 7/ 9
FB2 18/18* 23/54 36/90 8/ 9
FB3 18/18* 28/54 64/90 9/ 9*
FB4 17/18 35/54 86/90 5/ 7
----- ----- ----- -----
71/72 126/216 243/360 29/34
46. Reverted: Align quad timing back to cycle 0 as before (issues at offset 0)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 40/54 55/90 7/ 9
FB2 18/18* 23/54 36/90 8/ 9
FB3 18/18* 28/54 64/90 9/ 9*
FB4 17/18 35/54 84/90 5/ 7
----- ----- ----- -----
71/72 126/216 239/360 29/34
47. Added sync invert function (now v5.0)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 40/54 58/90 7/ 9
FB2 18/18* 23/54 36/90 8/ 9
FB3 18/18* 28/54 64/90 9/ 9*
FB4 18/18* 36/54 85/90 5/ 7
----- ----- ----- -----
72/72 127/216 243/360 29/34
48. Delay reduced to 2 bits plus psync changes (now v6.0)
- Remove 2 msbs of delay
- Make psync run during hsync
- Make Vsync appear on psync when version bit active
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 41/54 61/90 7/ 9
FB2 18/18* 23/54 36/90 8/ 9
FB3 18/18* 28/54 65/90 9/ 9*
FB4 16/18 35/54 86/90 5/ 7
----- ----- ----- -----
70/72 127/216 248/360 29/34
49. Increased counter from 7 back to 8 bits (now v6.1)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 41/54 65/90 7/ 9
FB2 18/18* 23/54 37/90 8/ 9
FB3 18/18* 28/54 65/90 9/ 9*
FB4 17/18 34/54 88/90 5/ 7
----- ----- ----- -----
71/72 126/216 255/360 29/34
50. Fixed a bug with half-pixel delay (now v6.2)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 41/54 66/90 7/ 9
FB2 18/18* 23/54 36/90 8/ 9
FB3 18/18* 28/54 65/90 9/ 9*
FB4 17/18 37/54 88/90 5/ 7
----- ----- ----- -----
71/72 129/216 255/360 29/34
51. Send csync2 to Pi and change csync to psync delay (now v6.3)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 42/54 66/90 7/ 9
FB2 18/18* 23/54 37/90 8/ 9
FB3 18/18* 28/54 65/90 9/ 9*
FB4 16/18 32/54 83/90 5/ 7
----- ----- ----- -----
70/72 125/216 251/360 29/34
52. Separate vsync (now v6.4)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 41/54 65/90 7/ 9
FB2 18/18* 23/54 36/90 8/ 9
FB3 18/18* 28/54 65/90 9/ 9*
FB4 16/18 32/54 83/90 5/ 7
----- ----- ----- -----
70/72 124/216 249/360 29/34

0
vhdl/BBC_CPLD_v65.xsvf → vhdl_bbc/BBC_CPLD_v65.xsvf
Wyświetl plik

0
vhdl/RGBtoHDMI.jed → vhdl_bbc/RGBtoHDMI.jed
Wyświetl plik

8
vhdl/RGBtoHDMI.xise → vhdl_bbc/RGBtoHDMI.xise
Wyświetl plik

@ -15,11 +15,11 @@
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="RGBtoHDMI.vhdl" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../vhdl/RGBtoHDMI.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="RGBtoHDMI.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="../vhdl/RGBtoHDMI.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
@ -69,7 +69,7 @@
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SupportAnalog=false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
@ -78,7 +78,7 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|RGBtoHDMI|Behavorial" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../RGBtoHDMI.vhdl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../vhdl/RGBtoHDMI.vhdl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/RGBtoHDMI" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>