kopia lustrzana https://github.com/ArcticSaturn/RFM02
added excel file, added TX via FSK, changed defines
Andre Frantzke
rodzic
89c3146156
commit
eae3fc70e4
42
rfm02.cpp
42
rfm02.cpp
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@ -93,13 +93,48 @@ void RFM02::configureDeviceSettings() {
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}
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// Data via FSK
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/******************************************************************************/
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/* Sending data via the FSK-Pin as Input-Pin */
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/* */
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/* After the PowerAmplifier has turned on ( ea=1 ) from rfm02-module */
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/* comes a clock corresponding to the data-rate set before on nIRQ. */
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/* The data to be transmitted is bitwise set on the FSK-Pin of the */
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/* module, after the falling edge of nIRQ. With the following edge */
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/* of nIRQ this bit is read in and sent out. */
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/* nSEL must be high, SCK low, both all the time */
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/* */
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/* */
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/* TESTED: 28.09.2014 with Deviation +/- 90kHz and 435.000 MHz */
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/* up to 115.000BPS */
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/* */
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/* Support & Copyright: tigarus.programming@web.de */
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/******************************************************************************/
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void RFM02_TX_DataByte_FSK(uint8_t DataByte){
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uint8_t i=8;
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// PowerAmplifier is here already enabled, impulses on nIRQ corresponding to the
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// set data-rate, nSEL is high, SCK is low
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while(i){ // do 8 times..., (any number of bit's will do, also 9 or 121)
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i=i-1;
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digitalWrite(_pinFSK, LOW); //OUT_PORT_REG &= ~FSK; // first set Bitx as '0'
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if( DataByte & BIT7 ) // if not '0' write over with '1'
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//OUT_PORT_REG |= FSK; // ...write '1' if most significant bit is '1'
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digitalWrite(_pinFSK, HIGH); // ...write '1' if most significant bit is '1'
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//while(!(IN_PORT_REG & nIRQ)); // wait for the 0-1-edge of nIRQ, reading in the data
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//while(IN_PORT_REG & nIRQ); // wait for 1-0-edge to send the last bit
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while(!(digitalRead(_pinNIRQ))); // wait for the 0-1-edge of nIRQ, reading in the data
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while((digitalRead(_pinNIRQ))); // wait for the 0-1-edge of nIRQ, reading in the data
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DataByte <<= 1; // shift DataByte one bit left to write the next bit
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}
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}
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/*
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void SendDataSPI(uint8_t data){
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digitalWrite(_pinChipSelect,LOW);
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SPI.transfer(0xC6);
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SPI.transfer(LowByte);
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digitalWrite(_pinChipSelect,HIGH);
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while(i){ // any no of bit's will do, also 9 or 121
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i=i-1;
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@ -113,5 +148,6 @@ void SendDataSPI(uint8_t data){
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data <<= 1; // shift left ( next bit as most significant bit ...)
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} // end while(...)
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digitalWrite(_pinChipSelect,HIGH);
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*/
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}
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2
rfm02.h
2
rfm02.h
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@ -29,7 +29,7 @@ public:
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//private:
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void writeRegister(uint8_t HighByte, uint8_t LowByte);
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void configureDeviceSettings();
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void SendDataSPI(uint8_t data);
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void RFM02_TX_DataByte_FSK(uint8_t DataByte);
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/*
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uint8_t _channel;
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136
rfm02_defines.h
136
rfm02_defines.h
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@ -6,6 +6,13 @@
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* Last changed: 18.09.2014
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*
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* Author: joeder
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*
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*
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* 06.11.2014, ArcticSaturn
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* - added Frequency Deviation Control Bits defines
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* - renamed several name to shorten them
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*
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*
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*/
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@ -19,7 +26,7 @@
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/******************************************************************************/
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/* RF-Config-Register Initvalue: 8080hex -> For 430MHz-Band , b1(0) b0(1) */
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/* */
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/* Bits: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 */
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/* Bits: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 /
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/* 1 0 0 b1 b0 d2 d1 d0 x3 x2 x1 x0 ms m2 m1 m0 */
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/* */
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/* default 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 */
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@ -42,10 +49,18 @@
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/* 0 0 0 0 8.5 pF */
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/* 0 0 0 1 9.0 pF */
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/* 0 0 1 0 9.5 pF */
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/* 0 0 1 1 10 pF */
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/* . . . . */
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/* . . . . 12.5 pF * */
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/* . . . . */
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/* 0 0 1 1 10.0 pF */
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/* 0 1 0 0 10.5 pF */
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/* 0 1 0 1 11.0 pF */
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/* 0 1 1 0 11.5 pF */
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/* 0 1 1 1 12.0 pF */
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/* 1 0 0 0 12.5 pF */
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/* 1 0 0 1 13.0 pF */
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/* 1 0 1 0 13.5 pF */
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/* 1 0 1 1 14.0 pF */
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/* 1 1 0 0 14.5 pF */
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/* 1 1 0 1 15.0 pF */
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/* 1 1 1 0 15.5 pF */
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/* 1 1 1 1 16.0 pF */
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/* */
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/* Frequency of Pin CLK: d2 d1 d0 value */
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@ -71,53 +86,65 @@
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// set: 433MHz, Deviation 90kHz default: CLK 1MHz, Cap 12.0pF, Modularity +180°
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//#define mrc_QuickSet_RFM02_TX() CONFIG_CMD|=FREQ_DEV_90kHz+BAND_SELECT_433MHz
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#define CONFIG_CMD 0x8000
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#define CONFIG_CMD (0x8080) // reset value for Config command
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/* Frequency Deviation Control Bits */
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#define FREQ_DEV0 (0x0001) // Frequency Deviation Control Bit: 0
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#define FREQ_DEV1 (0x0002) // Frequency Deviation Control Bit: 1
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#define FREQ_DEV2 (0x0004) // Frequency Deviation Control Bit: 2
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#define MODPL0 (0x0008) // Modulation Polarity Bit: 0
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#define LOADCAP0 (0x0010) // Crystal Load Cap Bit: 0
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#define LOADCAP1 (0x0020) // Crystal Load Cap Bit: 1
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#define LOADCAP2 (0x0040) // Crystal Load Cap Bit: 2
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#define LOADCAP3 (0x0080) // Crystal Load Cap Bit: 3
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#define CLKFREQ0 (0x0100) // CLK frequency Bit: 0
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#define CLKFREQ1 (0x0200) // CLK frequency Bit: 1
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#define CLKFREQ2 (0x0400) // CLK frequency Bit: 2
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#define FREQBAND0 (0x0800) // Frequency Band Bit: 0
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#define FREQBAND1 (0x1000) // Frequency Band Bit: 1
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/* Frequency Deviation [kHz]: m2 m1 m0 value */
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#define FREQ_DEV_30kHz 0x00 // 0 0 0 0 0 0 0 0
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#define FREQ_DEV_60kHz 0x01
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#define FREQ_DEV_90kHz 0x02
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#define FREQ_DEV_120kHz 0x03
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#define FREQ_DEV_150kHz 0x04
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#define FREQ_DEV_180kHz 0x05
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#define FREQ_DEV_210kHz 0x06 // 0 0 0 0 0 1 1 0
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#define FREQ_DEV_30kHz (0*0x0001u) // Frequency Deviation: 30 kHz
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#define FREQ_DEV_60kHz (1*0x0001u) // Frequency Deviation: 60 kHz
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#define FREQ_DEV_90kHz (2*0x0001u) // Frequency Deviation: 90 kHz
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#define FREQ_DEV_120kHz (3*0x0001u) // Frequency Deviation: 120 kHz
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#define FREQ_DEV_150kHz (4*0x0001u) // Frequency Deviation: 150 kHz
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#define FREQ_DEV_180kHz (5*0x0001u) // Frequency Deviation: 180 kHz
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#define FREQ_DEV_210kHz (6*0x0001u) // Frequency Deviation: 210 kHz
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/* Modulation Polarity: ms value */
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#define MOD_POLTY_180_NEG 0x08 // 0 0 0 0 1 0 0 0
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#define MOD_POLTY_180_POS 0x00
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/* Crystal Load Capacity: x3 x2 x1 x0 value */
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#define CRYSTAL_LD_CAP_08_5PF 0x00 // 8,5pF
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#define CRYSTAL_LD_CAP_09_0PF 0x10 // ...
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#define CRYSTAL_LD_CAP_09_5PF 0x20
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#define CRYSTAL_LD_CAP_10_0PF 0x30
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#define CRYSTAL_LD_CAP_10_5PF 0x40
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#define CRYSTAL_LD_CAP_11_0PF 0x50
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#define CRYSTAL_LD_CAP_11_5PF 0x60
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#define CRYSTAL_LD_CAP_12_0PF 0x70
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#define CRYSTAL_LD_CAP_12_5PF 0x80
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#define CRYSTAL_LD_CAP_13_0PF 0x90
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#define CRYSTAL_LD_CAP_13_5PF 0xA0
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#define CRYSTAL_LD_CAP_14_0PF 0xB0
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#define CRYSTAL_LD_CAP_14_5PF 0xC0
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#define CRYSTAL_LD_CAP_15_0PF 0xD0
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#define CRYSTAL_LD_CAP_15_5PF 0xE0
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#define CRYSTAL_LD_CAP_16_0PF 0xF0
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#define CRYSTAL_LD_CAP_08_5PF 0x0000 // 8,5pF
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#define CRYSTAL_LD_CAP_09_0PF 0x0010 // ...
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#define CRYSTAL_LD_CAP_09_5PF 0x0020
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#define CRYSTAL_LD_CAP_10_0PF 0x0030
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#define CRYSTAL_LD_CAP_10_5PF 0x0040
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#define CRYSTAL_LD_CAP_11_0PF 0x0050
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#define CRYSTAL_LD_CAP_11_5PF 0x0060
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#define CRYSTAL_LD_CAP_12_0PF 0x0070
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#define CRYSTAL_LD_CAP_12_5PF 0x0080
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#define CRYSTAL_LD_CAP_13_0PF 0x0090
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#define CRYSTAL_LD_CAP_13_5PF 0x00A0
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#define CRYSTAL_LD_CAP_14_0PF 0x00B0
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#define CRYSTAL_LD_CAP_14_5PF 0x00C0
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#define CRYSTAL_LD_CAP_15_0PF 0x00D0
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#define CRYSTAL_LD_CAP_15_5PF 0x00E0
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#define CRYSTAL_LD_CAP_16_0PF 0x00F0
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/* Frequency of Pin CLK: d2 d1 d0 value */
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#define CLK_PIN_FREQ_1_00MHZ 0x0000 // 0 0 0 0 0 0 0 0
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#define CLK_PIN_FREQ_1_25MHZ 0x0100
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#define CLK_PIN_FREQ_1_66MHZ 0x0200 // ...
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#define CLK_PIN_FREQ_2_00MHZ 0x0300
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#define CLK_PIN_FREQ_2_50MHZ 0x0400
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#define CLK_PIN_FREQ_3_33MHZ 0x0500
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#define CLK_PIN_FREQ_5_00MHZ 0x0600
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#define CLK_PIN_FREQ_10_00MHZ 0x0700 // 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0
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#define CLK_PIN_FREQ_1_00MHZ 0x0000
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#define CLK_PIN_FREQ_1_25MHZ 0x0100
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#define CLK_PIN_FREQ_1_66MHZ 0x0200
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#define CLK_PIN_FREQ_2_00MHZ 0x0300
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#define CLK_PIN_FREQ_2_50MHZ 0x0400
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#define CLK_PIN_FREQ_3_33MHZ 0x0500
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#define CLK_PIN_FREQ_5_00MHZ 0x0600
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#define CLK_PIN_FREQ_10_00MHZ 0x0700
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/* Band Selection: b1 b0 value ... */
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#define BAND_SELECT_433MHz 0x0800
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#define BAND_SELECT_868MHz 0x1000
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#define BAND_SELECT_915MHz 0x1800
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#define BAND_SELECT_433MHz 0x0800
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#define BAND_SELECT_868MHz 0x1000
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#define BAND_SELECT_915MHz 0x1800
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@ -135,6 +162,8 @@
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/* */
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/* value ranges from 0x0060..0x0F3F */
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/* */
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/* f = carrier frequency */
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/* */
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/* f = 10MHz * C1 * (C2 + F/4000) default: 435 MHz */
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/* */
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/* */
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@ -143,12 +172,14 @@
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// Nothing to do ! leave at 435 MHz
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// Value for frequency must be calculated for the define
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// Value for 439.7575 MHz
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#define RF_FRQUENCY_439_7575_MHZ 0x0F3F // max value
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#define FREQ_430_2400_MHZ 0x0060 // min. value
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#define FREQ_435_0000_MHZ 0x07D0 // default
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#define FREQ_439_7575_MHZ 0x0F3F // max value
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#define RF_FRQUENCY_435_0000_MHZ 0x07D0 // default
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#define FREQ_860_4800_MHZ 0x0060 // min. value
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#define FREQ_868_0000_MHZ 0x0640 // 868.00MHz value
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#define FREQ_879_5150_MHZ 0x0F3F // max. value
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#define RF_FRQUENCY_430_2400_MHZ 0x0060 // min. value
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/******************************************************************************/
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/* Baudrate-Adjust-Register Initvalue: C800hex */
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@ -166,15 +197,14 @@
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/******************************************************************************/
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#define CONFIG_BAUD_RATE_CMD 0xC800
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#define mcr_QuickSet_BaudRate_9600() BAND_SELECT_433MHz|=BAUD_RATE_09_600_BPS
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// Value for baud rate must be calculated for the define
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// Value for 38.400 bps is 7.97988 --> 8
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#define BAUD_RATE_115_000_BPS 0x02
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#define BAUD_RATE_38_400_BPS 0x08
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#define BAUD_RATE_19_200_BPS 0x11
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#define BAUD_RATE_09_600_BPS 0x23
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#define BAUD_RATE_04_800_BPS 0x47
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#define BR_115_000_BPS 0x0002
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#define BR_38_400_BPS 0x0008
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#define BR_19_200_BPS 0x0011
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#define BR_09_600_BPS 0x0023
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#define BR_04_800_BPS 0x0047
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/******************************************************************************/
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