Increase write_delay for Xiegu 6100 to 3ms -- was locking up rig < 3ms

rigs/icom/xiegu.c

@@ -330,7 +330,7 @@ const struct rig_caps x6100_caps =
     RIG_MODEL(RIG_MODEL_X6100),
     .model_name = "X6100",
     .mfg_name =  "Xiegu",
-    .version =  BACKEND_VER ".2",
+    .version =  BACKEND_VER ".3",
     .copyright =  "LGPL",
     .status =  RIG_STATUS_STABLE,
     .rig_type =  RIG_TYPE_TRANSCEIVER,
@@ -343,7 +343,7 @@ const struct rig_caps x6100_caps =
     .serial_stop_bits =  1,
     .serial_parity =  RIG_PARITY_NONE,
     .serial_handshake =  RIG_HANDSHAKE_NONE,
-    .write_delay =  0,
+    .write_delay =  3,
     .post_write_delay =  0,
     .timeout =  1000,
     .retry =  3,