kopia lustrzana https://github.com/F5OEO/PiFmRds
Superior signal purity by modulation fractional PLL
SaucySoliton
rodzic
3a309befa1
commit
65cc5be41d
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@ -11,8 +11,10 @@ This version modulates the PLL instead of the clock divider for superior signal
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TODO list
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watchdog for PLL settings (the GPU changes them sometimes, like brownout)
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( force_turbo=1 may help prevent this)
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measure PLL loop filter response
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It is based on the FM transmitter created by [Oliver Mattos and Oskar Weigl](http://www.icrobotics.co.uk/wiki/index.php/Turning_the_Raspberry_Pi_Into_an_FM_Transmitter), and later adapted to using DMA by [Richard Hirst](https://github.com/richardghirst). Christophe Jacquet adapted it and added the RDS data generator and modulator. The transmitter uses the Raspberry Pi's PWM generator to produce VHF signals.
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327
src/pi_fm_rds.c
327
src/pi_fm_rds.c
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@ -146,7 +146,7 @@
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#define PWM_BASE_OFFSET 0x0020C000
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#define PWM_LEN 0x28
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#define CLK_BASE_OFFSET 0x00101000
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#define CLK_LEN 0xA8
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#define CLK_LEN 0x1300
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#define GPIO_BASE_OFFSET 0x00200000
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#define GPIO_LEN 0x100
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@ -170,9 +170,16 @@
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#define PWMCLK_DIV 41
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#define CM_GP0DIV (0x7e101074)
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#define CM_PLLCFRAC (0x7e102220)
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#define CORECLK_CNTL (0x08/4)
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#define CORECLK_DIV (0x0c/4)
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#define GPCLK_CNTL (0x70/4)
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#define GPCLK_DIV (0x74/4)
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#define GPCLK_DIV (0x74/4)
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#define EMMCCLK_CNTL (0x1C0/4)
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#define EMMCCLK_DIV (0x1C4/4)
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#define PLLC_CTRL (0x1120/4)
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#define PLLC_FRAC (0x1220/4)
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#define PWMCTL_MODE1 (1<<1)
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#define PWMCTL_PWEN1 (1<<0)
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@ -188,9 +195,10 @@
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#define PLLFREQ 500000000. // PLLD is running at 500MHz
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// The deviation specifies how wide the signal is. Use 25.0 for WBFM
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// (broadcast radio) and about 3.5 for NBFM (walkie-talkie style radio)
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#define DEVIATION 25.0
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// The deviation specifies how wide the signal is.
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// Use 75kHz for WBFM (broadcast radio)
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// and about 2.5kHz for NBFM (walkie-talkie style radio)
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#define DEVIATION 75000
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typedef struct {
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@ -226,6 +234,135 @@ struct control_data_s {
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static struct control_data_s *ctl;
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static void
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print_clock_tree(void)
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{
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if( clk_reg==NULL ) return;
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#define PLLA_CTRL (0x1100/4)
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#define PLLA_FRAC (0x1200/4)
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#define PLLA_DSI0 (0x1300/4)
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#define PLLA_CORE (0x1400/4)
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#define PLLA_PER (0x1500/4)
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#define PLLA_CCP2 (0x1600/4)
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#define PLLB_CTRL (0x11e0/4)
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#define PLLB_FRAC (0x12e0/4)
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#define PLLB_ARM (0x13e0/4)
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#define PLLB_SP0 (0x14e0/4)
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#define PLLB_SP1 (0x15e0/4)
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#define PLLB_SP2 (0x16e0/4)
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#define PLLC_CTRL (0x1120/4)
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#define PLLC_FRAC (0x1220/4)
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#define PLLC_CORE2 (0x1320/4)
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#define PLLC_CORE1 (0x1420/4)
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#define PLLC_PER (0x1520/4)
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#define PLLC_CORE0 (0x1620/4)
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#define PLLD_CTRL (0x1140/4)
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#define PLLD_FRAC (0x1240/4)
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#define PLLD_DSI0 (0x1340/4)
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#define PLLD_CORE (0x1440/4)
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#define PLLD_PER (0x1540/4)
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#define PLLD_DSI1 (0x1640/4)
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#define PLLH_CTRL (0x1160/4)
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#define PLLH_FRAC (0x1260/4)
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#define PLLH_AUX (0x1360/4)
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#define PLLH_RCAL (0x1460/4)
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#define PLLH_PIX (0x1560/4)
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#define PLLH_STS (0x1660/4)
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#define XOSC_CTRL (0x1190/4)
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printf("PLLC_DIG0=%08x\n",clk_reg[(0x1020/4)]);
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printf("PLLC_DIG1=%08x\n",clk_reg[(0x1024/4)]);
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printf("PLLC_DIG2=%08x\n",clk_reg[(0x1028/4)]);
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printf("PLLC_DIG3=%08x\n",clk_reg[(0x102c/4)]);
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printf("PLLC_ANA0=%08x\n",clk_reg[(0x1030/4)]);
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printf("PLLC_ANA1=%08x\n",clk_reg[(0x1034/4)]);
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printf("PLLC_ANA2=%08x\n",clk_reg[(0x1038/4)]);
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printf("PLLC_ANA3=%08x\n",clk_reg[(0x103c/4)]);
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printf("PLLC_DIG0R=%08x\n",clk_reg[(0x1820/4)]);
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printf("PLLC_DIG1R=%08x\n",clk_reg[(0x1824/4)]);
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printf("PLLC_DIG2R=%08x\n",clk_reg[(0x1828/4)]);
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printf("PLLC_DIG3R=%08x\n",clk_reg[(0x182c/4)]);
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printf("GNRIC CTL=%08x DIV=%8x ",clk_reg[ 0],clk_reg[ 1]);
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printf("VPU CTL=%08x DIV=%8x\n",clk_reg[ 2],clk_reg[ 3]);
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printf("SYS CTL=%08x DIV=%8x ",clk_reg[ 4],clk_reg[ 5]);
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printf("PERIA CTL=%08x DIV=%8x\n",clk_reg[ 6],clk_reg[ 7]);
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printf("PERII CTL=%08x DIV=%8x ",clk_reg[ 8],clk_reg[ 9]);
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printf("H264 CTL=%08x DIV=%8x\n",clk_reg[10],clk_reg[11]);
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printf("ISP CTL=%08x DIV=%8x ",clk_reg[12],clk_reg[13]);
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printf("V3D CTL=%08x DIV=%8x\n",clk_reg[14],clk_reg[15]);
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printf("CAM0 CTL=%08x DIV=%8x ",clk_reg[16],clk_reg[17]);
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printf("CAM1 CTL=%08x DIV=%8x\n",clk_reg[18],clk_reg[19]);
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printf("CCP2 CTL=%08x DIV=%8x ",clk_reg[20],clk_reg[21]);
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printf("DSI0E CTL=%08x DIV=%8x\n",clk_reg[22],clk_reg[23]);
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printf("DSI0P CTL=%08x DIV=%8x ",clk_reg[24],clk_reg[25]);
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printf("DPI CTL=%08x DIV=%8x\n",clk_reg[26],clk_reg[27]);
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printf("GP0 CTL=%08x DIV=%8x ",clk_reg[28],clk_reg[29]);
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printf("GP1 CTL=%08x DIV=%8x\n",clk_reg[30],clk_reg[31]);
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printf("GP2 CTL=%08x DIV=%8x ",clk_reg[32],clk_reg[33]);
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printf("HSM CTL=%08x DIV=%8x\n",clk_reg[34],clk_reg[35]);
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printf("OTP CTL=%08x DIV=%8x ",clk_reg[36],clk_reg[37]);
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printf("PCM CTL=%08x DIV=%8x\n",clk_reg[38],clk_reg[39]);
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printf("PWM CTL=%08x DIV=%8x ",clk_reg[40],clk_reg[41]);
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printf("SLIM CTL=%08x DIV=%8x\n",clk_reg[42],clk_reg[43]);
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printf("SMI CTL=%08x DIV=%8x ",clk_reg[44],clk_reg[45]);
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printf("SMPS CTL=%08x DIV=%8x\n",clk_reg[46],clk_reg[47]);
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printf("TCNT CTL=%08x DIV=%8x ",clk_reg[48],clk_reg[49]);
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printf("TEC CTL=%08x DIV=%8x\n",clk_reg[50],clk_reg[51]);
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printf("TD0 CTL=%08x DIV=%8x ",clk_reg[52],clk_reg[53]);
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printf("TD1 CTL=%08x DIV=%8x\n",clk_reg[54],clk_reg[55]);
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printf("TSENS CTL=%08x DIV=%8x ",clk_reg[56],clk_reg[57]);
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printf("TIMER CTL=%08x DIV=%8x\n",clk_reg[58],clk_reg[59]);
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printf("UART CTL=%08x DIV=%8x ",clk_reg[60],clk_reg[61]);
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printf("VEC CTL=%08x DIV=%8x\n",clk_reg[62],clk_reg[63]);
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printf("PULSE CTL=%08x DIV=%8x ",clk_reg[100],clk_reg[101]);
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printf("PLLT CTL=%08x DIV=????????\n",clk_reg[76]);
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printf("DSI1E CTL=%08x DIV=%8x ",clk_reg[86],clk_reg[87]);
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printf("DSI1P CTL=%08x DIV=%8x\n",clk_reg[88],clk_reg[89]);
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printf("AVE0 CTL=%08x DIV=%8x\n",clk_reg[90],clk_reg[91]);
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printf("SDC CTL=%08x DIV=%8x ",clk_reg[106],clk_reg[107]);
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printf("ARM CTL=%08x DIV=%8x\n",clk_reg[108],clk_reg[109]);
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printf("AVE0 CTL=%08x DIV=%8x ",clk_reg[110],clk_reg[111]);
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printf("EMMC CTL=%08x DIV=%8x\n",clk_reg[112],clk_reg[113]);
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// Sometimes calculated frequencies are off by a factor of 2
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// ANA1 bit 14 may indicate that a /2 prescaler is active
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printf("PLLA PDIV=%d NDIV=%d FRAC=%d ",(clk_reg[PLLA_CTRL]>>16) ,clk_reg[PLLA_CTRL]&0x3ff, clk_reg[PLLA_FRAC] );
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printf(" %f MHz\n",19.2* ((float)(clk_reg[PLLA_CTRL]&0x3ff) + ((float)clk_reg[PLLA_FRAC])/((float)(1<<20))) );
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printf("DSI0=%d CORE=%d PER=%d CCP2=%d\n\n",clk_reg[PLLA_DSI0],clk_reg[PLLA_CORE],clk_reg[PLLA_PER],clk_reg[PLLA_CCP2]);
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printf("PLLB PDIV=%d NDIV=%d FRAC=%d ",(clk_reg[PLLB_CTRL]>>16) ,clk_reg[PLLB_CTRL]&0x3ff, clk_reg[PLLB_FRAC] );
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printf(" %f MHz\n",19.2* ((float)(clk_reg[PLLB_CTRL]&0x3ff) + ((float)clk_reg[PLLB_FRAC])/((float)(1<<20))) );
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printf("ARM=%d SP0=%d SP1=%d SP2=%d\n\n",clk_reg[PLLB_ARM],clk_reg[PLLB_SP0],clk_reg[PLLB_SP1],clk_reg[PLLB_SP2]);
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printf("PLLC PDIV=%d NDIV=%d FRAC=%d ",(clk_reg[PLLC_CTRL]>>16) ,clk_reg[PLLC_CTRL]&0x3ff, clk_reg[PLLC_FRAC] );
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printf(" %f MHz\n",19.2* ((float)(clk_reg[PLLC_CTRL]&0x3ff) + ((float)clk_reg[PLLC_FRAC])/((float)(1<<20))) );
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printf("CORE2=%d CORE1=%d PER=%d CORE0=%d\n\n",clk_reg[PLLC_CORE2],clk_reg[PLLC_CORE1],clk_reg[PLLC_PER],clk_reg[PLLC_CORE0]);
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printf("PLLD PDIV=%d NDIV=%d FRAC=%d ",(clk_reg[PLLD_CTRL]>>16) ,clk_reg[PLLD_CTRL]&0x3ff, clk_reg[PLLD_FRAC] );
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printf(" %f MHz\n",19.2* ((float)(clk_reg[PLLD_CTRL]&0x3ff) + ((float)clk_reg[PLLD_FRAC])/((float)(1<<20))) );
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printf("DSI0=%d CORE=%d PER=%d DSI1=%d\n\n",clk_reg[PLLD_DSI0],clk_reg[PLLD_CORE],clk_reg[PLLD_PER],clk_reg[PLLD_DSI1]);
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printf("PLLH PDIV=%d NDIV=%d FRAC=%d ",(clk_reg[PLLH_CTRL]>>16) ,clk_reg[PLLH_CTRL]&0x3ff, clk_reg[PLLH_FRAC] );
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printf(" %f MHz\n",19.2* ((float)(clk_reg[PLLH_CTRL]&0x3ff) + ((float)clk_reg[PLLH_FRAC])/((float)(1<<20))) );
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printf("AUX=%d RCAL=%d PIX=%d STS=%d\n\n",clk_reg[PLLH_AUX],clk_reg[PLLH_RCAL],clk_reg[PLLH_PIX],clk_reg[PLLH_STS]);
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}
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static void
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udelay(int us)
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{
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@ -312,7 +449,7 @@ map_peripheral(uint32_t base, uint32_t len)
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#define DATA_SIZE 5000
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int tx(uint32_t carrier_freq, char *audio_file, uint16_t pi, char *ps, char *rt, float ppm, char *control_pipe) {
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int tx(uint32_t carrier_freq, uint32_t divider, char *audio_file, uint16_t pi, char *ps, char *rt, float ppm, char *control_pipe) {
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// Catch all signals possible - it is vital we kill the DMA engine
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// on process exit!
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for (int i = 0; i < 64; i++) {
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@ -349,25 +486,69 @@ int tx(uint32_t carrier_freq, char *audio_file, uint16_t pi, char *ps, char *rt,
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printf("virt_addr = %p\n", mbox.virt_addr);
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uint32_t freq_ctl;
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if( divider ) // PLL modulation
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{
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// switch the core over to PLLA
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clk_reg[CORECLK_DIV] = (0x5a<<24) | (4<<12) ; // core div 4
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udelay(100);
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clk_reg[CORECLK_CNTL] = (0x5a<<24) | (1<<4) | (4); // run, src=PLLA
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// switch the EMMC over to PLLD
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// FIXME should also adjust divider to keep same frequency
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// or possibly not if the gpu decides to change clocks due to low voltage
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// TODO put clocks back to their original state when we are done?
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int clktmp;
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clktmp = clk_reg[EMMCCLK_CNTL];
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clk_reg[EMMCCLK_CNTL] = (0xF0F&clktmp) | (0x5a<<24) ; // clear run
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udelay(100);
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clk_reg[EMMCCLK_CNTL] = (0xF00&clktmp) | (0x5a<<24) | (6); // src=PLLD
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udelay(100);
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clk_reg[EMMCCLK_CNTL] = (0xF00&clktmp) | (0x5a<<24) | (1<<4) | (6); // run , src=PLLD
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// Adjust PLLC frequency
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freq_ctl = (unsigned int)(((carrier_freq*divider)/19.2e6)*((double)(1<<20))) ; // todo PPM
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clk_reg[PLLC_CTRL] = (0x5a<<24) | (0x21<<12) | (freq_ctl>>20 ); // integer part
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freq_ctl&=0xFFFFF;
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clk_reg[PLLC_FRAC] = (0x5a<<24) | (freq_ctl&0xFFFFC) ; // fractional part
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udelay(1000);
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// Program GPCLK integer division
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clktmp = clk_reg[GPCLK_CNTL];
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clk_reg[GPCLK_CNTL] = (0xF0F&clktmp) | (0x5a<<24) ; // clear run
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udelay(100);
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clk_reg[GPCLK_DIV] = (0x5a<<24) | (divider<<12);
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udelay(100);
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clk_reg[GPCLK_CNTL] = (0x5a<<24) | (5); // src=PLLC
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udelay(100);
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clk_reg[GPCLK_CNTL] = (0x5a<<24) | (1<<4) | (5); // run , src=PLLC
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}
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else // MASH modulation
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{
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// Program GPCLK to use MASH setting 1, so fractional dividers work
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clk_reg[GPCLK_CNTL] = 0x5A << 24 | 6; // src 6 = PLLD
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udelay(100);
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clk_reg[GPCLK_CNTL] = 0x5A << 24 | 1 << 9 | 1 << 4 | 6;
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// Calculate the frequency control word
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// The fractional part is stored in the lower 12 bits
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freq_ctl = ((float)(PLLFREQ / carrier_freq)) * ( 1 << 12 ); //PLLD=500MHz
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}
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// GPIO4 needs to be ALT FUNC 0 to output the clock
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gpio_reg[GPFSEL0] = (gpio_reg[GPFSEL0] & ~(7 << 12)) | (4 << 12);
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// Program GPCLK to use MASH setting 1, so fractional dividers work
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clk_reg[GPCLK_CNTL] = 0x5A << 24 | 6;
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udelay(100);
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clk_reg[GPCLK_CNTL] = 0x5A << 24 | 1 << 9 | 1 << 4 | 6;
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ctl = (struct control_data_s *) mbox.virt_addr;
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dma_cb_t *cbp = ctl->cb;
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uint32_t phys_sample_dst = CM_GP0DIV;
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uint32_t phys_sample_dst = divider ? CM_PLLCFRAC : CM_GP0DIV;
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uint32_t phys_pwm_fifo_addr = PWM_PHYS_BASE + 0x18;
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// Calculate the frequency control word
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// The fractional part is stored in the lower 12 bits
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uint32_t freq_ctl = ((float)(PLLFREQ / carrier_freq)) * ( 1 << 12 );
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for (int i = 0; i < NUM_SAMPLES; i++) {
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ctl->sample[i] = 0x5a << 24 | freq_ctl; // Silence
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// Write a frequency sample
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@ -405,12 +586,12 @@ int tx(uint32_t carrier_freq, char *audio_file, uint16_t pi, char *ps, char *rt,
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//
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// So we use the 'ppm' parameter to compensate for the oscillator error
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float divider = (500000./(2*228*(1.+ppm/1.e6)));
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uint32_t idivider = (uint32_t) divider;
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uint32_t fdivider = (uint32_t) ((divider - idivider)*pow(2, 12));
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float srdivider = (500000./(2*228*(1.+ppm/1.e6)));
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uint32_t idivider = (uint32_t) srdivider;
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uint32_t fdivider = (uint32_t) ((srdivider - idivider)*pow(2, 12));
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printf("ppm corr is %.4f, divider is %.4f (%d + %d*2^-12) [nominal 1096.4912].\n",
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ppm, divider, idivider, fdivider);
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ppm, srdivider, idivider, fdivider);
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pwm_reg[PWM_CTL] = 0;
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udelay(10);
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@ -480,6 +661,21 @@ int tx(uint32_t carrier_freq, char *audio_file, uint16_t pi, char *ps, char *rt,
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printf("Starting to transmit on %3.1f MHz.\n", carrier_freq/1e6);
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float deviation_scale_factor;
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if( divider ) // PLL modulation
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{ // note samples are [-10:10]
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deviation_scale_factor= 0.1 * (divider*DEVIATION/ (19.2e6/((double)(1<<20))) ) ; // todo PPM
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}
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else // MASH modulation
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{
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double normdivider=((double)PLLFREQ / (double)carrier_freq) * ( 1 << 12 ); //PLLD=500MHz
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double lowdivider=((double)PLLFREQ / (((double)carrier_freq)+(DEVIATION))) * ( 1 << 12 );
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deviation_scale_factor= 0.1 * (normdivider-lowdivider);
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}
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//printf("deviation_scale_factor = %f \n", deviation_scale_factor);
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for (;;) {
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// Default (varying) PS
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if(varying_ps) {
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@ -505,7 +701,6 @@ int tx(uint32_t carrier_freq, char *audio_file, uint16_t pi, char *ps, char *rt,
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int last_sample = (last_cb - (uint32_t)mbox.virt_addr) / (sizeof(dma_cb_t) * 2);
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int this_sample = (cur_cb - (uint32_t)mbox.virt_addr) / (sizeof(dma_cb_t) * 2);
|
||||
int free_slots = this_sample - last_sample;
|
||||
|
||||
if (free_slots < 0)
|
||||
free_slots += NUM_SAMPLES;
|
||||
|
||||
|
|
@ -519,15 +714,23 @@ int tx(uint32_t carrier_freq, char *audio_file, uint16_t pi, char *ps, char *rt,
|
|||
data_index = 0;
|
||||
}
|
||||
|
||||
float dval = data[data_index] * (DEVIATION / 10.);
|
||||
float dval = data[data_index]*deviation_scale_factor;
|
||||
int intval;
|
||||
if( divider ) // PLL modulation
|
||||
{
|
||||
intval = ( (int)((floor)(dval)) & ~0x3 ) ;
|
||||
// clock settings from boot code seem to always leave 2 lsb clear
|
||||
}
|
||||
else // MASH modulation
|
||||
{
|
||||
intval = (int)((floor)(dval)) ;
|
||||
}
|
||||
data_index++;
|
||||
data_len--;
|
||||
|
||||
int intval = (int)((floor)(dval));
|
||||
//int frac = (int)((dval - (float)intval) * SUBSIZE);
|
||||
|
||||
|
||||
ctl->sample[last_sample++] = (0x5A << 24 | freq_ctl) + intval; //(frac > j ? intval + 1 : intval);
|
||||
ctl->sample[last_sample++] = ( 0x5A << 24 | freq_ctl) + intval;
|
||||
if (last_sample == NUM_SAMPLES)
|
||||
last_sample = 0;
|
||||
|
||||
|
|
@ -547,6 +750,7 @@ int main(int argc, char **argv) {
|
|||
char *ps = NULL;
|
||||
char *rt = "PiFmRds: live FM-RDS transmission from the RaspberryPi";
|
||||
uint16_t pi = 0x1234;
|
||||
uint32_t mash = -1;
|
||||
float ppm = 0;
|
||||
|
||||
|
||||
|
|
@ -580,14 +784,81 @@ int main(int argc, char **argv) {
|
|||
} else if(strcmp("-ctl", arg)==0 && param != NULL) {
|
||||
i++;
|
||||
control_pipe = param;
|
||||
} else if(strcmp("-mash", arg)==0 ) {
|
||||
i++;
|
||||
mash=1;
|
||||
} else {
|
||||
fatal("Unrecognised argument: %s.\n"
|
||||
"Syntax: pi_fm_rds [-freq freq] [-audio file] [-ppm ppm_error] [-pi pi_code]\n"
|
||||
" [-ps ps_text] [-rt rt_text] [-ctl control_pipe]\n", arg);
|
||||
" [-ps ps_text] [-rt rt_text] [-ctl control_pipe] [-mash]\n", arg);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// Choose an integer divider for GPCLK0
|
||||
//
|
||||
// There may be improvements possible to this algorithm.
|
||||
double xtal_freq_recip=1.0/19.2e6; // todo PPM correction
|
||||
int best_divider=0;
|
||||
|
||||
// Optional loop to print tuning solutions for all FM frequencies
|
||||
//for( carrier_freq=76000000 ; carrier_freq<108000000 ; carrier_freq+=100000 )
|
||||
{
|
||||
int solution_count=0;
|
||||
printf("carrier:%3.2f ",carrier_freq/1e6);
|
||||
int divider,min_int_multiplier,max_int_multiplier, fom, int_multiplier, best_fom=0;
|
||||
double frac_multiplier;
|
||||
best_divider=0;
|
||||
for( divider=2;divider<20;divider+=1) // do odd dividers have worse 2nd harmonic?
|
||||
{
|
||||
if( carrier_freq*divider < 760e6 ) continue; // widest accepted frequency range
|
||||
if( carrier_freq*divider > 1300e6 ) break;
|
||||
|
||||
max_int_multiplier=((int)((double)(carrier_freq+100000)*divider*xtal_freq_recip));
|
||||
min_int_multiplier=((int)((double)(carrier_freq-100000)*divider*xtal_freq_recip));
|
||||
if( min_int_multiplier!=max_int_multiplier ) continue; // don't cross integer boundary
|
||||
|
||||
solution_count++; // if we make it here the solution is acceptable,
|
||||
fom=0; // but we want a good solution
|
||||
|
||||
if( carrier_freq*divider > 900e6 ) fom++; // prefer freqs closer to 1000
|
||||
if( carrier_freq*divider < 1100e6 ) fom++;
|
||||
if( carrier_freq*divider > 800e6 ) fom++; // accepted frequency range
|
||||
if( carrier_freq*divider < 1200e6 ) fom++;
|
||||
|
||||
|
||||
frac_multiplier=((double)(carrier_freq)*divider*xtal_freq_recip);
|
||||
int_multiplier = (int) frac_multiplier;
|
||||
frac_multiplier = frac_multiplier - int_multiplier;
|
||||
if( (frac_multiplier>0.2) && (frac_multiplier<0.8) ) fom++; // prefer mulipliers away from integer boundaries
|
||||
|
||||
|
||||
if( divider%2 == 0 ) fom+=2; // prefer even dividers
|
||||
// do odd dividers have worse 2nd harmonic?
|
||||
|
||||
|
||||
//printf(" multiplier:%f divider:%d VCO: %4.1fMHz\n",carrier_freq*divider*xtal_freq_recip,divider,(double)carrier_freq*divider/1e6);
|
||||
|
||||
if( fom > best_fom )
|
||||
{
|
||||
best_fom=fom;
|
||||
best_divider=divider;
|
||||
}
|
||||
}
|
||||
printf(" multiplier:%f divider:%d VCO: %4.1fMHz\n",carrier_freq*best_divider*xtal_freq_recip,best_divider,(double)carrier_freq*best_divider/1e6);
|
||||
|
||||
int errcode = tx(carrier_freq, audio_file, pi, ps, rt, ppm, control_pipe);
|
||||
if( solution_count==0)
|
||||
printf("No tuning solution found. (76.8 and 96.0 are not supported.)\n");
|
||||
|
||||
}// Optional loop to print tuning solutions
|
||||
|
||||
if( best_divider==0) return -1 ;
|
||||
|
||||
if( mash!=-1 )
|
||||
{
|
||||
best_divider=0; // if divider=0, use MASH divider instead of PLL modulation
|
||||
}
|
||||
int errcode = tx(carrier_freq, best_divider, audio_file, pi, ps, rt, ppm, control_pipe);
|
||||
|
||||
terminate(errcode);
|
||||
}
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue